JP2000353947A - Level converting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a level converting device for preventing the rising of an output signal after conversion from becoming dull even when operating level conversion is performed or not. SOLUTION: A signal obtained by logically inverting an input signal S101 of which H level potential is VDDL is connected with the gate of an N type MOS transistor 121, and the input signal S101 is shifted by a level shift part 106, and connected with the gate of a P type MOS transistor 111, and the source of the P type MOS transistor is connected with VDDH. A control signal S105 is inputted to the gate of a P type breakdown voltage protecting MOS transistor 112, and the VDDL is inputted to the gate of an N type breakdown voltage protecting MOS transistor 122. When outputting the H level of an output signal S103 in the VDDH, the control signal S105 to be applied to the gate of the P type breakdown voltage protecting MOS transistor is obtained as a signal generated by a gate voltage generating part 104, and when outputting the H level of the output signal S103 in the VDDL, this signal is obtained as a signal in a ground level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention shares the function of converting a semiconductor internal signal level to a signal level higher than the withstand voltage of a semiconductor element and outputting the same, and the function of outputting the internal signal level within the withstand voltage of the element before conversion. And a semiconductor output circuit.

[0002]

2. Description of the Related Art In recent years, high integration of LSIs has been innovatively advanced by rapid development of miniaturization technology of semiconductor devices.
On the other hand, reduction in breakdown voltage of the semiconductor element due to miniaturization and LS
In order to reduce the power consumption of I, the operating voltage inside the LSI has been reduced.

The maximum operating voltage of an LSI is determined in accordance with a decrease in the breakdown voltage of a semiconductor device, and the level of a logic signal tends to decrease. However, depending on the system environment in which the LSI is placed, the logic signal level of the connection destination component differs,
There may be a disadvantage that a logic signal level higher than the withstand voltage of the SI element is required. In order to solve the inconvenience, when outputting a logic signal to a connection destination having a different logic signal level, the output circuit performs level conversion to match the logic signal potential of the connection destination component. Since an output circuit for converting the level of the logic signal is formed by the same process and library, an intermediate voltage is applied to the gate so that a voltage higher than the breakdown voltage is not applied between the gate and the drain and between the gate and the source of the transistor constituting the output buffer. The structure is provided with a withstand voltage protection transistor to which a potential is applied.

[0004]

However, in the above configuration, when a logic signal is output while maintaining the operating voltage inside the LSI, the gate voltage of the transistor used for withstand voltage protection is an intermediate potential, so that a constant on-state voltage is applied. It has a resistance, so that the rising edge of the signal becomes dull, and the function for level conversion and that for level conversion cannot be shared. For example, the case where the level conversion is not performed in the above configuration circuit is used.

[0005]

According to a first aspect of the present invention, there is provided a level conversion apparatus for receiving a logic signal having an H level as a first potential and an L level as a ground potential. A level shifter that shifts the H level of the logic signal to a second potential; an internal power supply that supplies the first potential for driving the logic signal; and a second power source that drives the level-shifted signal. And a source connected to the output power source, a P-type MOS transistor having a gate connected to the output of the level shift unit, a source connected to the drain of the P-type MOS transistor, and a gate connected to the output power supply. M for P type withstand voltage protection connected to control signal
N-type breakdown voltage protection in which an OS transistor, an output terminal for extracting an output from the drain of the P-type breakdown voltage protection MOS transistor, a drain connected to the drain of the P-type breakdown voltage protection MOS transistor, and a gate connected to the internal power supply An N-type MOS transistor having a drain connected to the source of the N-type breakdown voltage protection MOS transistor, a gate connected to a signal obtained by logically inverting the logic signal, and a source grounded; That is, when the second potential higher than the first potential is supplied to the output power supply and the logic signal is level-shifted to the second potential and output, the mode switching signal is used to output the logic signal.
Is connected to the gate of the P-type withstand voltage protection MOS transistor as the control signal, and the first potential is also supplied to the second mode, that is, the output power supply, and the logic signal is supplied to the output power supply. When the output is performed at the first potential, a switching means for connecting the ground potential as the control signal to the gate of the P-type withstand voltage protection MOS transistor by the mode switching signal is provided.

According to a second aspect of the present invention, there is provided a level conversion device according to the first aspect, wherein the connection means includes a second potential and a second potential which are different from each other. The apparatus further comprises comparing means for comparing a threshold potential indicating that the potential of the first reference voltage approaches the predetermined potential with a predetermined potential, and using a result of the comparison as a mode switching signal.

[0007]

(Embodiment 1) FIG. 1 is a circuit diagram of a level conversion device according to Embodiment 1 of the present invention.
Hereinafter, the configuration will be described.

Reference numeral 100 denotes a level conversion circuit main body. The level conversion circuit 100 outputs the operation mode switching signal S102
To switch the operation mode, the internal signal S10
An output signal S103 higher than (VDDH) or the same (VDDL) level is output. Internal operating voltage is V
DDL and VDDH are properly used.

Reference numeral 101 denotes an input terminal for inputting a signal S101. The level of the amplitude of the signal S101 is VDDL.

Reference numeral 102 denotes an operation mode switching signal input terminal, which is an input terminal for inputting an operation mode switching signal S102. The operation mode switching signal S102 is a signal which becomes H when the level conversion circuit 100 performs the level conversion and becomes L when the level conversion circuit 100 does not perform the level conversion.

Reference numeral 103 denotes an output terminal, and an output signal S10
3 is output. The output signal S103 is input signal S1 according to the mode specified by the operation mode switching signal S102.
01 is converted to VDDH or VD
This is output as DL.

Reference numeral 104 denotes an intermediate potential generating unit, which generates a voltage VD
The voltage DH is divided by the resistors 104a and 104b and converted into a low impedance voltage by the voltage holding circuit 104c to generate the intermediate potential VG2.

An analog switch 105 selects one of the intermediate potential VG2 and the ground potential by an operation mode switching signal S102 and supplies the selected potential to the gate VG of the P-type breakdown voltage protection MOS transistor 112.

A level shift section 106 shifts the level of the input signal S 101 to a signal applied to the gate of the P-type MOS transistor 111. The details thereof are configured as shown by P-type MOS transistors 131 to 134 and N-type MOS transistors 141 to 144.

Reference numeral 111 denotes a P-type MOS transistor.
An N-type MOS transistor 121 and a push-pull type output circuit are formed.

Reference numeral 112 denotes a P-type MOS transistor for withstand voltage protection. When an output S105 of the analog switch 105 is applied to the gate VG, VDDH is applied to the gate of 111.
1 when the level is connected and L level is output to output 103
It has a function of preventing the potential of S105 or lower from propagating to the 12 sources, that is, the drain of 111. Where V
DDH-VG is lower than the element breakdown voltage. That is, the P-type withstand voltage protection MOS transistor 112 functions as a withstand voltage protection transistor that protects the P-type MOS transistor 111 from being damaged by a voltage higher than the element withstand voltage. However, in the mode in which the output signal of VDDL is output to the output 103, if the output of 104 is given to VG, the on-resistance of 112 increases, which causes a problem that the rising of the signal becomes dull. It has both.

Reference numeral 121 denotes an N-type MOS transistor;
A P-type MOS transistor 111 and a push-pull type output circuit are formed.

Reference numeral 122 denotes an N-type withstand voltage protection MOS transistor. When VDDL is applied to the gate, a ground potential is connected to the gate of the N-type MOS transistor 121 to output the output signal S103 at an H level. Has a function of preventing a potential equal to or higher than VDDL from propagating to the source, i.e., the drain of 121. That is, the N-type withstand voltage protection MOS transistor 122 protects the N-type MOS transistor 121 from being damaged by a voltage higher than the withstand voltage of the element.
It functions as a withstand voltage protection transistor.

Incidentally, the gate-drain breakdown voltage and the gate-source breakdown voltage of all the transistors constituting this level conversion circuit are lower than VDDH and higher than VDDL.

The operation of the level conversion device configured as described above will be described. FIG. 2 is a timing chart for explaining the operation of the circuit shown in FIG. 2 (a) to 2
(E) shows the voltage VDD0, the input signal S101, the operation mode switching signal S102, the signal S105 connected to the gate VG, and the output signal S103 shown in FIG. 1, respectively.

At time T1, the input signal S101 becomes 0
(V) changes to VDDL (V), and the output signal S103 changes from 0 (V) to VDDH (V).

At time T2, VDD0 is switched from VDDH to VDDL. This is because the H level of the output signal S103 is set to VDDL and output. As a result, the level of the gate signal S105 generated by dividing the voltage of VDD0 is reduced. However, when the H level of VDDL is output to S103, the gate-source for turning on the P-type breakdown voltage protection MOS transistor 112 is output. The potential difference between them is insufficient, and the P-type withstand voltage protection MOS transistor 112 has a high on-resistance and lowers the rising output current capability.

At time T3, the input signal S101 becomes 0
From (V) to VDDL (V). However, at this time, because of the ON resistance of the P-type withstand voltage protection MOS transistor 112, the rise of the output signal S103 is reduced due to the relationship with the external capacitance generated at the output 103, and the output signal S103 is delayed by ΔT3 to VDDL (V).

At time T4, the mode switching signal S102
To L. The analog switch 105 selects the ground level, and the P-type withstand voltage protection MOS transistor 1
12 is sufficiently reduced.

At time T5, the input signal S101 becomes H. However, the rising of the output signal S103 does not stop because the on-resistance of the P-type breakdown voltage protection MOS transistor 112 is sufficiently reduced.

That is, as described above, by controlling the gate potential of the P-type withstand voltage protection MOS transistor in the level converter, the signal after conversion can be converted regardless of whether the level is converted by the level converter. There is an effect that a signal without dullness can be obtained.

(Embodiment 2) FIG. 3 is a circuit diagram of a level converter according to Embodiment 2 of the present invention. 2, 101 to 106, 111, 121, 122, and 13
1 to 134 and 141 to 144 correspond to those of the first embodiment having the same reference numerals shown in FIG. The difference is that a power supply potential determination circuit 200 is provided. The configuration and effect will be described below. The power supply potential determination circuit 200 has the first variation
The control signal for the analog switch 105 is generated by comparing the voltage obtained by dividing the potential of the second potential with the voltage obtained by dividing the second potential. That is, when the second potential is lower than the threshold, the selection of the analog switch 105 is switched,
A ground potential is supplied to the gate of the P-type breakdown voltage protection MOS transistor 112. That is, the above configuration has an effect that the mode of the level conversion device can be automatically switched without providing a switching control signal from the outside.

[0028]

According to the above configuration, there is an effect that the level shift circuit shares the function of converting the level and the function of not converting the level, and it is possible to output a smooth output signal.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an apparatus according to a first embodiment of the present invention.

FIG. 2 is a timing chart illustrating the operation of the circuit shown in FIG. 1;

FIG. 3 is a circuit diagram of a level conversion device according to a second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Input terminal 102 Operation mode switching signal input terminal 103 Output terminal 104 Intermediate potential generation part 105 Analog switch 106 Level shift part 111 P-type MOS transistor 112 P-type breakdown voltage protection MOS transistor 121 N-type MOS transistor 122 N-type breakdown voltage protection MOS Transistor

Claims (2)

[Claims] A level shifter for inputting a logic signal having an H level as a first potential and an L level as a ground potential, and shifting the H level of the logic signal to a second potential; An internal power supply for supplying the second potential; an output power supply for supplying the second potential; a P-type MOS transistor having a source connected to the output power supply and a gate connected to the output of the level shift unit; P-type withstand voltage protection MOS connected to the drain of a P-type MOS transistor and the gate connected to a control signal
A transistor; an output terminal for extracting an output from the drain of the P-type breakdown voltage protection MOS transistor; and an N-type breakdown voltage protection having a drain connected to the drain of the P-type breakdown voltage protection MOS transistor and a gate connected to the internal power supply. An N-type MOS transistor having a drain connected to the source of the N-type breakdown voltage protection MOS transistor, a gate connected to a signal obtained by logically inverting the logic signal, and a source grounded; When supplying the second potential higher than the first potential to the output power supply and level-shifting the logic signal to the second potential for output, the mode switching signal divides the second potential. Connected to the gate of the P-type breakdown voltage protection MOS transistor as the control signal, When the first potential is also supplied to the output power supply and the logic signal is output at the first potential, the P-type withstand voltage protection MOS transistor uses the mode switching signal to set a ground potential as the control signal. A level conversion device comprising switching means for connecting to a gate. 2. The level conversion device according to claim 1, wherein
The switching means compares the second potential with a threshold potential indicating that the second potential approaches the first potential by a predetermined potential, and uses the comparison result as a mode switching signal. A level conversion device, further comprising: