JP2015195435A - Signal processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the reception of a high common differential signal and a low common differential signal by a common input terminal pair with a small circuit configuration.SOLUTION: An input terminal pair (120, 104) is connected to a voltage/current conversion circuit (108) corresponding to the high common differential signal, and also connected to a voltage/current conversion circuit (112) corresponding to the low common differential signal through a switch circuit (110). The voltage/current conversion circuit (114) converts a differential current signal output from the voltage/current conversion circuits (108, 112) into each voltage signal. The voltage/current conversion circuit (108) is operated at a high power voltage VDDH. The switch circuit (110), the voltage/current conversion circuit (112) and the voltage/current conversion circuit (114) are operated at a low power voltage VDDL.

Description

  The present invention relates to a signal processing apparatus, and relates to a signal processing apparatus that receives and processes a signal input from the outside.

  The imaging apparatus includes an image processing IC that performs specific image processing on an output image signal of the imaging element, and the image processing IC transmits and receives data to and from an external memory and a liquid crystal display panel in addition to the imaging element.

  There are various methods for communication between these individual elements. For example, a source-synchronous signal transmission method that separately transmits a clock and data using a small-amplitude differential signal, or a clock-embedded single transmission method that uses a small-amplitude differential signal (see Patent Document 1). )It has been known. As the former method, LVDS (Low Voltage Differential Signaling) is known.

  For example, image data transmission from the image sensor to the image signal processing IC is about 1 Gbps for LVDS, and about several Gbps for a clock embedded type single transmission method in which the common voltage and the differential amplitude voltage are relatively smaller than LVDS. Can be achieved.

JP 2011-87243 A

  The image signal processing IC is preferably capable of receiving output signals from imaging sensors having different I / F specifications. For this purpose, it is the simplest method to separately provide input terminals having different physical specifications. For example, an input terminal or a dedicated pin for receiving a differential signal with a high common voltage, such as LVDS, and an input terminal or a dedicated pin for receiving high-speed differential serial data with a low common voltage embedded in a clock may be provided independently. . However, in such a configuration in which input terminals corresponding to input signals are individually provided, the number of pins of the image signal processing IC increases. An increase in the number of pins leads to an increase in the area of the image processing IC and an increase in circuit scale. In order to maintain or reduce the number of pins, it is desirable to use dual-purpose pins that can receive signals of different electrical specifications.

  In view of such a demand, the present invention provides a signal processing apparatus capable of inputting a differential signal having a relatively high common voltage such as LVDS and a differential signal having a relatively low common voltage through a common input terminal pair. The purpose is to present.

  The signal processing apparatus according to the present invention includes an input terminal pair to which a high common differential signal and a low common differential signal having different voltage levels are input, and a voltage signal of the high common differential signal input to the input terminal pair. A first voltage / current conversion circuit for converting a current signal into a current signal, the first voltage / current conversion circuit including a first transistor having a withstand voltage to the high common differential signal, and the input terminal A second voltage / current conversion circuit for converting a voltage signal of the low common differential signal input to a pair into a current signal, having a withstand voltage against the low common differential signal, from the first transistor A second voltage / current conversion circuit including a second transistor operating at high speed, and a current / voltage conversion for converting a current signal output from the first and second voltage / current conversion circuits into a voltage signal; A circuit, wherein the second A second current / voltage conversion circuit configured to stop the operation of the second voltage / current conversion circuit during the operation of the first voltage / current conversion circuit. The operation of the first voltage / current conversion circuit is stopped during the operation of the circuit.

  According to the present invention, it is possible to realize a signal processing apparatus with a small area that can receive a plurality of differential signals having different common voltages.

It is a schematic block diagram of the first embodiment of the present invention. 2 is a circuit configuration example of a receiver circuit to which the embodiment shown in FIG. 1 is applied. It is a schematic block diagram of the second embodiment of the present invention. 4 is a circuit configuration example of a receiver circuit to which the embodiment shown in FIG. 3 is applied. It is an eye pattern example with respect to the presence or absence of an offset.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a schematic configuration diagram of an embodiment of a signal processing apparatus according to the present invention. For example, the signal processing apparatus 100 in FIG. 1 can be realized as a part of an image processing circuit for processing an image signal output from an imaging sensor. The signal processing apparatus 100 shown in FIG. 1 has a common input terminal pair, a differential signal having a common voltage such as LVDS and a high differential amplitude level, a common voltage relatively lower than the LVDS, and a differential amplitude level. A differential signal with a small can be input. Hereinafter, the former is referred to as “high common differential signal” and the latter is referred to as “low common differential signal”. For example, an image signal from an imaging sensor composed of a CMOS circuit is input in a differential signal format to an input terminal pair composed of a positive input terminal 102 and a negative input terminal 104. Specifically, the positive voltage of the differential signal is input to the positive input terminal 102 of the input terminal pair, and the negative voltage is input to the negative input terminal 104.

  A termination circuit 106 is connected between the input terminals 102 and 104. The termination circuit 106 is composed of a serially connected resistor and a switch, and the resistance value of this resistor is generally 100 ohms. When a termination resistor is prepared outside the signal processing apparatus 100, the switch of the termination circuit 106 is turned off.

  The input terminal 104 is connected to the negative input terminal of the voltage / current conversion circuit 108, and is connected to the negative input terminal of the voltage / current conversion circuit 112 via the switch 110 a of the switch circuit 110. The input terminal 102 is connected to the positive input terminal of the voltage / current conversion circuit 108, and is connected to the positive input terminal of the voltage / current conversion circuit 112 via the switch 110 b of the switch circuit 110. The differential output of the voltage / current conversion circuit 108 and the differential output of the voltage / current conversion circuit 112 are input to the current / voltage conversion circuit 114. The output of the current / voltage conversion circuit 114 is input to the driver circuit 116, and the output of the driver circuit 116 is connected to the output terminal 120 of the signal processing device 100.

  The voltage / current conversion circuit 108 is driven by the power supply voltage VDDH, and the voltage / current conversion circuit 112, the current / voltage conversion circuit 114, and the driver circuit 116 are driven by the power supply voltage VDDL that is lower than the power supply voltage VDDH. The voltage / current conversion circuit 108 is composed of a high voltage transistor capable of handling a high common differential signal such as an LVDS signal, and the voltage / current conversion circuit 112 is composed of a high speed transistor capable of accommodating a low common differential signal. The The current / voltage conversion circuit 114 and the driver circuit 116 are composed of high-speed transistors.

  A relationship between a general semiconductor process and the breakdown voltage of a transistor will be described. Some transistors with different breakdown voltages are used in the IC manufactured by the CMOS process. For example, in a 40 nm-CMOS process, a high voltage transistor that operates at a power supply voltage of 1.8 V or 3.3 V and a high-speed transistor that operates at a power supply voltage of 1.0 V can be manufactured, that is, can be used. Usually, digital signals are exchanged between an IC and an external module at 1.8V or 3.3V level in many cases. For this reason, the circuit portion directly connected to the IC pin is realized by a high voltage transistor of 1.8V or 3.3V operation, and a circuit portion that requires higher internal high speed operation, such as a logic operation circuit and a flip-flop circuit, etc. Is realized by a high-speed transistor operating at 1.0 V. A voltage level conversion circuit or the like is arranged between circuits having different reference operating voltages.

  A high voltage transistor operating at 1.8 V / 3.3 V has a larger transistor size than a high speed transistor operating at 1.0 V. Therefore, although the input / output unit directly connected to the pin has a withstand voltage, the operation speed is relatively slow and the required circuit area tends to be large. On the other hand, although the circuit portion composed of high-speed transistors operating at 1.0 V has a low withstand voltage, the operation speed is relatively high and the required circuit area can be reduced. The high breakdown voltage transistor is manufactured by, for example, a 0.18 μm-CMOS process or a 0.35 μm-CMOS process, and the high-speed transistor is manufactured by, for example, a process of 40 nm-CMOS or less.

  The control circuit 130 determines whether the differential signal is a high common differential signal or a low common differential signal based on the common-mode voltage and the differential voltage value of the differential signal input to the input terminals 102 and 104. In accordance with the determination result, as will be described later, the control circuit 130 stops the operation of the voltage / current conversion circuit 112 when the voltage / current conversion circuit 108 operates, and the voltage / current conversion circuit when the voltage / current conversion circuit 112 operates. Stop operation 108

  When the differential signal input to the input terminals 102 and 104 is a low common differential signal, the control circuit 130 controls the switches 110a and 110b of the switch circuit 110 to be in an ON state and powers down the voltage / current conversion circuit 108. Control to the state.

  Since the switches 110 a and 110 b of the switch circuit 110 are turned on, the differential signals input to the input terminals 102 and 104 are input to the voltage / current conversion circuit 112. The voltage / current conversion circuit 112 converts the input differential signal from voltage to current and outputs the converted signal. The current / voltage conversion circuit 114 converts the output (current signal) of the voltage / current conversion circuit 112 into a voltage signal. The driver circuit 116 is composed of an inverter, for example. The output of the driver circuit 116 is output from the output terminal 120 to the outside.

  Since the circuits 112 and 114 and the driver circuit 116 are realized by high-speed transistors, for example, high-speed operation of about several Gbps is possible. The control circuit 130 controls the voltage / current conversion circuit 108 to the power down state, so that the output of the voltage / current conversion circuit 108 is in a high impedance state. Therefore, the presence of the voltage / current conversion circuit 108 does not affect the operation of the circuits 112 and 114.

  When a high common differential signal is input to the input terminals 102 and 104, the control circuit 130 turns off the switches 110a and 110b of the switch circuit 110, sets the voltage / current conversion circuit 108 to a power-on state, and sets the voltage / current conversion circuit. 112 is controlled to a power-down state. Since the switch circuit 110 is turned off, the voltage / current conversion circuit 112 is electrically insulated from the input terminals 102 and 104. Further, since the voltage / current conversion circuit 112 is controlled to the power-down state, the output of the voltage / current conversion circuit 112 becomes high impedance.

  In this state, the voltage / current conversion circuit 108 converts the differential voltage signal from the input terminals 102 and 104 into a current signal, and the current / voltage conversion circuit 114 converts the current signal from the voltage / current conversion circuit 108 into a voltage. Convert to signal. The driver circuit 116 operates in the same manner as before.

  In the embodiment shown in FIG. 1, a signal can be appropriately received regardless of whether a high common differential signal or a low common differential signal is input to the input terminals 102 and 104. In the signal processing apparatus 100, it is necessary to provide a voltage / current conversion circuit 108 constituted by high breakdown voltage transistors and a voltage / current conversion circuit 112 constituted by high speed transistors. An increase in area can be minimized.

  FIG. 2 shows a circuit configuration example of a receiver circuit in which the configuration shown in FIG. 1 is realized by a CMOS transistor (FET). In FIG. 2, the transistors surrounded by circles indicate Pch / Nch high-voltage CMOS transistors, and the transistors without circles indicate Pch / Nch high-speed CMOS transistors.

  The receiver circuit 200 includes a positive input terminal 202 corresponding to the input terminal 102 and a negative input terminal 204 corresponding to the input terminal 104. A termination circuit 206 that connects between the positive input terminal 202 and the negative input terminal 204 corresponds to the termination circuit 106. The resistance value of the resistor constituting the termination circuit 206 is generally 100Ω. When a termination resistor exists outside the receiver circuit 200, the switch constituting the termination circuit 206 is turned off. When the termination circuit 206 is made effective, a switch constituting the termination circuit 206 is turned on.

  The circuit 208 is a voltage / current conversion circuit that converts a voltage signal of a high common differential signal such as LVDS into a current signal, and corresponds to the voltage / current conversion circuit 108. The gate of the high voltage transistor constituting the circuit 208 is connected to the positive input terminal 202 and the negative input terminal 204. In FIG. 2, the circuit 208 is a complementary differential circuit using a Pch transistor and an Nch transistor, but this is for wide input common mode voltage range. If there is no such necessity, only one side is provided. But it ’s okay.

  A current source 222 connects the power supply voltage VDDH to the circuit 208, and a current source 224 connects the circuit 208 to GND. When a low common differential signal is input, the current sources 222 and 224 are controlled to be in an off state. As a result, the output of the circuit 208 becomes high impedance. The circuit 226 is a circuit that adds currents of the current outputs of the Pch differential circuit and the Nch differential circuit constituting the circuit 208 in cooperation with the current mirror circuits 228 and 230, and includes a high voltage transistor. The circuit 230 is connected between the circuit 214 corresponding to the current / voltage conversion circuit 114 and GND. In FIG. 2, a high-breakdown-voltage transistor is used for the circuit 230, but the operating voltage range is limited by the power supply voltage VDDL and does not exceed the power supply voltage VDDL.

  The switch circuit 210 corresponds to the switch circuit 110 and is turned off when a high common differential signal is input, and is turned on when a low common differential signal is input. When the switch circuit 210 is turned off, the gates of the transistors forming the circuit 212 corresponding to the voltage / current conversion circuit 112 are electrically separated from the positive input terminal 202 and the negative input terminal 204. A connection point between the switch circuit 210 and the circuit 212 is connected to the GND via the switch circuit 232. Contrary to the switch circuit 210, the switch circuit 232 is turned on when a high common differential signal is input, and is turned off when a low common differential signal is input. That is, at the time of inputting a high common differential signal, the gates of the transistors constituting the circuit 212 are connected to GND.

  A current source 234 connects the power supply voltage VDDL and the circuit 212, and current sources 236 and 238 connect the circuit 212 to GND. When a high common differential signal is input, the current sources 234, 236, and 238 are controlled to be in an off state. As a result, the output of the circuit 212 becomes high impedance.

  The circuit 214 converts a differential current signal into a single current signal, and a bias (Vb) is applied to one gate of the cascade-connected transistors for each current signal. Since the output of the circuit 214 is a current output, the output impedance is very high as it is. In order to operate at high speed, it is necessary to design the operating frequency band of the receiver circuit 200 in a wide band. Therefore, an inverting amplifier circuit 216 having a transimpedance amplifier configuration is connected to the output stage of the circuit 214. The inverting amplifier circuit 216 is composed of, for example, an inverter circuit.

  Since the circuit 216 has a transimpedance circuit configuration, the impedance at the input node of the circuit 216 can be kept low, and as a result, a wide band can be realized. Further, by using a simple circuit such as an inverter for the circuit 216, a wideband transimpedance amplifier can be configured with low power consumption, and the power consumption of the entire receiver circuit 200 can be reduced.

  The buffer 218 has a configuration in which a plurality of inverters are connected in cascade, and outputs a voltage signal output from the circuit 216 to the output terminal 220 in binary.

  When the differential signal input to the input terminals 202 and 204 is a low common differential signal, the switch circuit 210 is turned on, the switch circuit 232 is turned off, and the current sources 222 and 224 are controlled in a power-off state. As a result, an input differential signal is input to the gates of the transistors constituting the circuit 212, and the output of the current mirror circuit 226 is in a high impedance state. Note that the circuits 228 and 230 are also controlled to be in a power-off state. In this state, the differential input circuit 212, the current sources 234, 236, 238, and the circuit 214 constitute a current output type differential amplifier.

  In general, the signal speed of the low common differential signal is faster than the signal speed transmitted by LVDS or the like. Further, since the transimpedance amplifier 216 keeps the impedance of the node of the input section low, the operating frequency of the receiver circuit 200 is dominated by the voltage / current conversion gain of the circuit 208 or 212.

  In the circuit shown in FIG. 2, the amount of current supplied to the current sources 222 and 224 is kept small, and the amount of current supplied to the current sources 234, 236 and 238 is relatively increased. By doing so, it is possible to optimally control the operating frequency band for a relatively low-speed signal such as LVDS and the operating frequency band for a high-speed signal with a low common differential signal.

  Although an embodiment has been described in which there is one high common differential signal processing system and one low common differential signal processing system, one or both may have multiple systems.

  FIG. 3 shows a schematic block diagram of the second embodiment of the present invention. A signal processing device 100a shown in FIG. 3 has a configuration in which an offset adjustment circuit 122 is added to the signal processing device 100 shown in FIG. The same components as those of the signal processing apparatus 100 shown in FIG. 1 are denoted by the same reference numerals, and the description of the same parts is omitted.

  An offset may occur in the output stage of the driver circuit 116 due to transistor device mismatching in the circuits 108, 112, 114, and 116. If there is an offset, the AC timing margin is impaired when data is captured by the clock in the subsequent stage of the signal processing device, but the offset adjustment circuit 122 cancels the offset generated in the circuits 108, 112, 114, 116. I made it.

  The offset adjustment circuit 122 adds the offset current to the differential output of the voltage / current conversion circuits 108 and 112 and supplies the result to the current / voltage conversion circuit 114.

  FIG. 4 shows a circuit configuration example of a receiver circuit in which the configuration shown in FIG. 3 is realized by a CMOS transistor (FET). The same components as those of the receiver circuit 200 shown in FIG. As in FIG. 2, in FIG. 4, the transistors surrounded by circles indicate Pch / Nch high-voltage CMOS transistors, and the transistors not indicated by circles indicate Pch / Nch high-speed CMOS transistors.

  In the receiver circuit 200 shown in FIG. 3, there are a plurality of pairs of circuits that process differential signals. When there is a discrepancy in device characteristics in these paired circuits, or when a deviation occurs between the operating points of the circuits 214 and 216, an offset occurs in the output signal of the output terminal 220. FIG. 5 is an eye pattern example of the output signal of the output terminal 220 of the receiver circuit 200. FIG. 5A shows a case where there is no offset, and FIG. 5B shows a case where there is an offset. In FIG. 5 (a), the data crosses just around the center of the output amplitude, whereas in FIG. 5 (b), the data cross point is shifted from the center. If an offset occurs as shown in FIG. 5B, the AC timing margin when the output signal of the output terminal 220 is captured by a circuit subsequent to the receiver circuit 200 is impaired.

  In order to eliminate or reduce such an offset, an offset adjustment circuit 440 corresponding to the offset adjustment circuit 122 is provided, and switch circuits 442 and 444 and test voltage generation circuits 446 and 448 are provided to determine the offset adjustment amount. The test voltage generation circuit 446 is a circuit that selectively supplies the voltage / current circuit 208 with a voltage corresponding to the common voltage of GND and a high common differential signal. The test voltage generation circuit 448 is a circuit that selectively supplies the voltage / current circuit 212 with a voltage corresponding to the common voltage of GND and the low common differential signal.

  In the receiver circuit 200a shown in FIG. 4, the components different from the receiver circuit 200 shown in FIG. 2 will be described in detail.

  An offset adjustment circuit 440 corresponding to the offset adjustment circuit 122 supplies an offset current between the output of the circuit 206 and the inputs of the circuits 228 and 230, that is, to the circuits 228 and 230. The offset adjustment circuit 440 is a current source output type DAC (Digital-Analogue Converter). The output of the circuit 206 is a differential output, and the balance of the differential signal can be adjusted by adding a current to each current signal.

  The switch circuit 442 is disposed between the input terminals 202 and 204 and the circuit 208, and the output of the test voltage generation circuit 446 is connected to the input of the circuit 208 via the switch circuit 444. Instead of connecting switch circuit 232 to GND, it connects to the output of test voltage generation circuit 448. The switch circuit 442 is turned on when a high common differential signal is input, and is turned off when a low common differential signal is input.

  A control procedure for offset adjustment using the offset adjustment circuit 440 will be described. Calibration for determining an offset adjustment amount by the offset adjustment circuit 440 is performed. First, the switch circuits 210 and 442 are turned off to separate the circuits 208 and 212 from the input terminals 202 and 204.

  In order to calibrate the circuit 108, the switch circuit 232 is turned on, the output voltage of the test voltage generation circuit 448 is set to the GND level, and the current sources 234, 236, and 238 are turned off. That is, the circuit 212 is turned off or hibernated. On the other hand, the switch circuit 444 is turned on, the current sources 222 and 224 are turned on, and the output voltage of the test voltage generation circuit 446 is set to a level close to the common voltage of the high common differential signal.

  In this state, in the ideal state where there is no device mismatching in the differential signal processing system, the Low level and the High level appear on the average almost equal in the binary signal output from the output terminal 220. However, since it actually deviates from the ideal state, it is biased to one of the Low level and the High level.

  Therefore, a value obtained by averaging the binary signal output from the output terminal 220 with, for example, a digital filter is observed, and the average value becomes the center level, that is, the Low level and the High level are equalized. Each current value of the differential output of the offset adjustment circuit 440 is adjusted. Each current value of the differential output of the offset adjustment circuit 440 in which the Low level and the High level are equal is stored in a storage unit (not shown) and is used as an offset adjustment amount (current) for the high common differential signal.

  In order to calibrate the circuit 212, the switch circuit 444 is turned on, the output voltage of the test voltage generation circuit 446 is set to the GND level, and the current sources 222 and 224 are turned off. That is, the circuit 108 is turned off or hibernated. On the other hand, the switch circuit 232 is turned on, the current sources 234, 236 and 238 are turned on, and the output voltage of the test voltage generation circuit 448 is set to a level close to the common voltage of the low common differential signal.

  In this state, each current value of the differential output of the offset adjustment circuit 440 is set so that the average value of the binary signal output from the output terminal 220 becomes the center level, that is, the Low level and the High level are equalized. Adjust. Each current value of the differential output of the offset adjustment circuit 440 in which the Low level and the High level are equal is stored in a storage unit (not shown) and is used as an offset adjustment amount (current) for the low common differential signal.

  The offset adjustment amounts determined in this way are applied when processing a high common differential signal and when processing a low common differential signal, that is, are output from the offset adjustment circuit 440.

  The calibration operation described above may be performed when the entire system including the receiver circuit 200a is activated, or may be performed during a period in which the receiver circuit 200a does not communicate with an external device. Further, during the calibration operation, the outputs of the test voltage generation circuits 446 and 448 may be switched to a plurality of levels, and the final offset adjustment amount may be determined from the offset adjustment amount for each level.

  When the differential signals input to the input terminals 202 and 204 are 8B10B modulated signals, the change in the data string is, on average, the Low level and the High level substantially equal. In this case, the offset adjustment amount can be determined even during processing of differential signals input to the input terminals 202 and 204, that is, while the receiver circuit 200a is communicating with an external device on the input side.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made within the technical scope described in the claims.

Claims (5)

A pair of input terminals to which a high common differential signal and a low common differential signal having different voltage levels are input;
A first voltage / current conversion circuit for converting a voltage signal of the high common differential signal input to the input terminal pair into a current signal, wherein the first transistor has a withstand voltage to the high common differential signal. A first voltage / current conversion circuit configured;
A second voltage / current conversion circuit for converting a voltage signal of the low common differential signal input to the input terminal pair into a current signal, the first voltage / current conversion circuit having a withstand voltage against the low common differential signal; A second voltage / current conversion circuit composed of a second transistor operating at a higher speed than
A current / voltage conversion circuit for converting a current signal output from the first and second voltage / current conversion circuits into a voltage signal, the current / voltage conversion circuit including the second transistor. And
The operation of the second voltage / current conversion circuit is stopped during the operation of the first voltage / current conversion circuit, and the operation of the first voltage / current conversion circuit is performed during the operation of the second voltage / current conversion circuit. A signal processing device characterized by stopping the signal.   The signal processing apparatus according to claim 1, wherein the current / voltage conversion circuit includes a transimpedance amplifier.   The signal processing apparatus according to claim 1, further comprising an offset adjustment circuit that supplies an offset adjustment amount of current to an input of the voltage / current conversion circuit.   The offset adjustment circuit supplies a current of a first offset adjustment amount for adjusting an offset of an output of the first voltage / current conversion circuit during operation of the first voltage / current conversion circuit, and the second voltage / current conversion circuit. 4. The signal processing according to claim 3, wherein a current of a second offset adjustment amount for adjusting an offset of an output of the second voltage / current conversion circuit is supplied during operation of the voltage / current conversion circuit. apparatus. Furthermore,
The first voltage / current circuit is separated from the input terminal pair, and a first voltage / current circuit is selectively supplied with a voltage corresponding to a common voltage of GND and the high common differential signal. A test voltage generating means;
A second voltage / current circuit is separated from the input terminal pair, and a second voltage / current circuit is selectively supplied with a voltage corresponding to a common voltage of GND and the low common differential signal. The signal processing apparatus according to claim 3, further comprising a test voltage generating unit.

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