JP5524268B2 - Word line boost circuit - Google Patents

Description

The present invention relates to a boost circuit, and more particularly to a word line boost circuit.

FIG. 1 is a schematic diagram of a bias during reading of a conventional memory unit. Referring to FIG. 1, a conventional memory unit 100 includes a select transistor MS1 and a memory cell MC1. During a read operation, a word line driver (not shown) provides a selection voltage of -1.2V to the word line WL1, a voltage of 1.8V is applied to the source line SL1, and the selection transistor MS1 is turned on. . Further, voltages of 1.8 V and 0.3 V are applied to the control line CL1 and the bit line BL1, respectively. As described above, the detection circuit of the memory element can determine the state of the memory cell MC1 based on the magnitude of the detection current 101.

Further, prior to the read operation, the word line driver provides an operating voltage of 1.8V to the word line WL1. That is, during the read operation, the word line driver must provide the selection voltage (−1.2 V) lower than the operation voltage (1.8 V) to the word line WL1. Therefore, in actual application, the memory device includes a word line boost circuit, and the word line boost circuit generates a selection voltage in a manner that performs a negative boost. In general, a conventional word line boost circuit detects a change in a column-row address signal through an address transfer detector. When the column-row address signal changes, the booster in the conventional word line boost circuit generates a boost voltage of -1.2V, so the conventional word line boost circuit uses this boost voltage to select the select voltage. Can be generated.

For example, FIG. 2 is a signal waveform diagram of a conventional word line boost circuit. The column-row address signal PA1 has 12 bits, but only the four bits PAY <0> to PAY <3> and the 12th bit PAX <11> before the column-row address signal PA1 are shown in FIG. It is. Furthermore, the five bits before the column-row address signal PA1 are used to indicate the bit line address (BL address), and the remaining seven bits are used to indicate the word line address (WL address). The KICKB indicates a boost clock signal formed by a boost pulse that determines the timing of the boost operation, VBB indicates an output signal of a booster of a conventional word line boost circuit, ENBOOST indicates a signal formed by an enable pulse that determines the timing of the switching operation, and ZWL indicates a signal received by the word line WL1.

As shown in FIG. 2, since the row address of the selected memory unit does not change during the period between the time points t21 and t22, the same word line WL1 is selected. However, even if the row address of the selected memory unit does not change, the column address of the memory unit changes. Therefore, the conventional word line boost circuit continuously performs the boost operation based on the boost pulses P21 to P25. The output signal VBB is switched from 0V to -1.2V by continuously generating an enable pulse for the signal ENBOOST. Therefore, in actual operation, the conventional word line boost circuit has a very high power consumption.

The present invention provides a word line boost circuit including a first address transition detector, a second address transition detector, and a boost operation unit. The first address transition detector generates a first detection pulse that is responsive to changes in the row address signal. The second address transition detector generates a second detection pulse that is responsive to changes in the column address signal. Furthermore, the boost operation unit generates the selection voltage using the boost voltage based on the first detection pulse, and uses the boost voltage based on the delay time between the first detection pulse and the second detection pulse. Decide whether to generate a selection voltage.

In an embodiment of the present invention, the boost operation unit includes a controller, a booster, and a switch element. The controller generates the boost pulse and the enable pulse in order based on the first detection pulse, and determines whether to generate the boost pulse and the enable pulse in order based on the delay time. The booster generates a boost voltage based on the boost pulse. The switch element switches the selection voltage to the boost voltage based on the enable pulse.

In an embodiment of the present invention, when the delay time is longer than a predetermined time, the controller generates a boost pulse and an enable pulse in order. Also, when the delay time is shorter than or equal to the predetermined time, the controller does not generate a boost pulse.

In an embodiment of the present invention, when the delay time is longer than the predetermined time, the boost operating unit uses the boost voltage to generate the selection voltage. Also, when the delay time is shorter than or equal to the predetermined time, the boost operating unit does not regenerate the boost voltage.

The present invention provides a word line boost circuit including a first address transition detector, a second address transition detector, and a boost operation unit. The first address transition detector determines whether to generate a first detection pulse based on the row address signal. The second address transition detector determines whether to generate a second detection pulse based on the column address signal. In addition, the boost operation unit switches the selection voltage to the boost voltage based on the first detection pulse, and switches the selection voltage to the boost voltage based on the delay time between the first detection pulse and the second detection pulse. Decide if.

In an embodiment of the present invention, when the delay time is longer than the predetermined time, the boost operating unit switches the selection voltage to the boost voltage. Also, when the delay time is shorter than or equal to the predetermined time, the boost operating unit stops regeneration of the boost voltage.

The present invention provides a word line boost circuit for boosting a boost voltage in a memory array in which a selected memory cell is designated by a word line address and a bit line address. The word line boost circuit includes a first address transition detector, a second address transition detector, and a boost operation unit. The first address transition detector detects a change in the word line address. The second address transition detector detects a change in the bit line address. The boost operation unit generates a boost clock signal based on detection results of the first address transition detector and the second address transition detector. The boost clock signal is disabled when the selected memory cell is designated with the same word line address.

As described above, according to the present invention, since the boost operation unit selectively performs the boost operation when the column address of the selected memory cell changes, the power consumption of the word line boost circuit can be reduced.

It is a bias schematic diagram during reading of the conventional memory unit. It is a signal waveform diagram of a conventional word line boost circuit. It is a block schematic diagram of a word line boost circuit according to an embodiment of the present invention. 3 is a timing diagram of a word line boost circuit according to an embodiment of the present invention. FIG. It is a block diagram of the boost operation unit which concerns on embodiment of this invention. It is a signal waveform diagram of a boost operation unit. It is a circuit diagram of the booster which concerns on embodiment of this invention. 1 is a partial circuit diagram of a memory element according to an embodiment of the present invention.

FIG. 3 is a block schematic diagram of a word line boost circuit according to an embodiment of the present invention. Referring to FIG. 3, in an actual application, the word line boost circuit 300 is used to provide the selection voltage VBW to the word line driver 301, and the word line driver 301 further receives the operating voltage VPP. As described above, the word line driver 301 can selectively supply the selection voltage VBW or the operation voltage VPP to the word line WL (i) based on the row address signal PAX and the column address signal PAY. The row address signal PAX is used to display a word line address, and the column address signal PAY is used to display a bit line address. A memory cell selected in the memory array is designated by the word line address and the bit line address.

Referring to FIG. 3, the word line boost circuit 300 includes a first address transition detector 310, a second address transition detector 320, and a boost operation unit 330. The first address transition detector 310 and the second address transition detector 320 are electrically connected to the boost operation unit 330.

During operation, the first address transition detector 310 determines whether to generate the first detection pulse ATDX based on the row address signal PAX. For example, when the row address signal PAX changes, the first address transition detector 310 generates a first detection pulse ATDX that is responsive to changes in the row address signal PAX. That is, the first address transition detector 310 detects a change in the word line address. When the row address signal PAX is used to select a different word line, that is, when the word line address changes, the change of the word line address is detected by the first address transition detector 310, and then the first address transition Detector 310 generates a first detection pulse ATDX.

On the other hand, the second address transition detector 320 determines whether or not to generate the second detection pulse ATDY based on the column address signal PAY. For example, when the column address signal PAY changes, the second address transition detector 320 generates the second detection pulse ATDY that reacts to the change of the column address signal PAY. That is, the second address transition detector 320 detects a change in the bit line address. When the column address signal PAY is used to select a different bit line, that is, when the bit line address changes, the change of the bit line address is detected by the second address transition detector 320 and then the second address transition. The detector 320 generates the second detection pulse ATDY.

Further, the boost operation unit 330 generates the selection voltage VBW using the boost voltage based on the first detection pulse ATDX. Further, the boost operation unit 330 performs a boost operation by enabling the boost clock signal and generates a boost voltage. For example, when a word line having a different row address signal PAX is selected, the boost operation unit 330 performs a boost operation with the boost clock signal enabled, and generates a boost voltage. Further, the boost operation unit 330 switches the selection voltage VBW to the boost voltage to provide a selection voltage VBW that is higher or lower than the operation voltage VPP. That is, in one embodiment, when a word line having a different row address signal PAX is selected, the boost operation unit 330 switches the selection voltage VBW to the boost voltage based on the first detection pulse ATDX.

On the other hand, when the row address signal PAX and the column address signal PAY change in order, the boost operation unit 330 selects using the boost voltage based on the delay time between the first detection pulse ATDX and the second detection pulse ATDY. Determine whether to generate voltage VBW. For example, when the column address signal PAY changes after the row address signal PAX changes, that is, when the second detection pulse ATDY is generated after the first detection pulse ATDX, the boost operation unit 330 generates the detection pulses ATDX and ATDY. Calculate the delay time between. That is, the time difference between the pulses ATDX and ATDY is detected.

Further, when the delay time is longer than a predetermined time (eg, 1 μs), the boost operation unit 330 enables the boost clock signal to generate the boost voltage, and generates the selection voltage VBW using the boost voltage. That is, in one embodiment, the boost operation unit 330 switches the selection voltage VBW to the boost voltage. Conversely, if the delay time is shorter than or equal to the predetermined time, the boost operating unit 330 stops using the boost clock signal and stops generating the boost voltage. That is, in an embodiment, the boost operation unit 330 does not switch the selection voltage VBW.

As described above, when a word line having a different row address signal PAX is selected, that is, when the row address of the selected memory unit is changed, the boost operation unit 330 performs a boost operation. However, when a bit line having a different column address signal PAY is selected, that is, when the column address of the selected memory unit is changed, the boost operation unit 330 selectively performs the boost operation. Can reduce the power consumption.

For example, FIG. 4 is a timing diagram of a word line boost circuit according to an embodiment of the present invention. Although the column address signal PAY has five bits, only the four bits PAY <0> to PAY <3> before the column address signal PAY are shown in FIG. The row address signal PAX has seven bits, but only the first bit PAY <0> of the row address signal PAX is shown in FIG. Furthermore, KICKB indicates the boost clock signal formed by the boost pulse that determines the timing of the boost operation, VBB indicates the output signal of the booster of the boost operation unit 330, and ENBOOST is the enable that determines the timing of the switching operation. A signal formed by a pulse is indicated, and ZWL indicates a signal received by the word line WL (i).

As shown in FIG. 4, since the row address signal PAX does not change during the period between the time points t41 and t42, the same word line WL (i) is selected. In addition, since the three bits PAY <0> to PAY <2> before the column address signal PAY change during the period between the time points t41 and t42, the second address transition detector 320 has a plurality of second detections. Pulses ATDY are generated in order. Further, the boost operation unit 330 compares each second detection pulse ATDY with the previous first detection pulse ATDX to obtain a plurality of delay times. If any of the plurality of delay times is smaller than the predetermined time, no boost pulse is generated in the boost clock signal KICKB between time points t41 and t42, so that the booster of the boost operation unit 330 performs the boost operation during this period. Do not do. Further, since no enable signal is generated in the signal ENBOOST between time points t41 and t42, that is, the level of the signal ENBOOST does not change, the boost operation unit 330 does not switch the selection voltage VBW. In this way, the power consumption of the word line boost circuit 300 can be reduced.

Then, the first bit PAX <0> of the row address signal PAX changes at time t42. At that time, the first address transition detector 310 generates a new first detection pulse ATDX, and the boost operation unit 330 generates a boost pulse P41 based on the new first detection pulse ATDX. Therefore, during the period between time points t42 and t43, the booster of the boost operation unit 330 switches the output signal VBB from the ground voltage VSS to VB4 that is boost electricity by performing a negative boost operation based on the boost pulse P41. Further, since the row address signal PAX is not sent to the word line WL (i), the word line driver 310 provides the operation voltage VPP to the word line WL (i).

In order that those skilled in the art may fully understand the spirit of the present invention, the details of the present invention are described below. FIG. 5 is a block diagram of the boost operation unit according to the embodiment of the present invention, and FIG. 6 is a signal waveform diagram of the boost operation unit. A detailed operation procedure of the boost operation unit will be described below with reference to FIGS. 5 and 6.

The boost operation unit 330 further includes a controller 510, a booster 520, and a switch element 530, and the controller 510 includes a counting device 511. Controller 510 is electrically connected to booster 520, and switch element 530 is electrically connected to booster 520 and controller 510. During operation, when the row address signal PAX changes, the controller 510 sequentially generates a boost pulse P41 and an enable pulse P42 based on the first detection pulse ATDX. In FIG. 6, STDX indicates a first detection signal formed by the first detection pulse ATDX, KICKB indicates a boost clock signal formed by the boost pulse P41, and ENBOOST indicates a signal formed by the enable pulse P42. Show.

The booster 520 performs a boost operation based on the boost pulse P41, and generates a boost voltage VB4. The detailed structure of the booster 520 will be further described below. FIG. 7 is a circuit diagram of the booster according to the embodiment of the present invention. Referring to FIG. 7, the booster 520 includes a PMOS (P-channel metal oxide semiconductor) transistor MP71, a PMOS transistor MP72, a capacitor C71 formed by an NMOS (N-channel metal oxide semiconductor) transistor MN71, and an NMOS transistor MN72. Includes a capacitor C72, an inverter 710, and an inverter 720. The sources of the PMOS transistors MP71 and MP72 receive the ground voltage VSS, and the drains of the PMOS transistors MP71 and MP72 are connected to the first ends of the capacitors C71 and C72, respectively.

Further, the gate of the PMOS transistor MP71 is electrically connected to the drain of the PMOS transistor MP72, and the gate of the PMOS transistor MP72 is electrically connected to the drain of the PMOS transistor MP71. The input terminal of the inverter 710 receives the boost clock signal KICKB, and the output terminal of the inverter 710 is electrically connected to the second terminal of the capacitor C71. The input end of the inverter 720 is electrically connected to the output end of the inverter 710, and the output end of the inverter 720 is electrically connected to the second end of the capacitor C72. During operation, when a boost pulse of the boost clock signal KICKB is input, inverters 710 and 720 pull the second ends of capacitors C71 and C72 to different voltage levels, respectively. At that time, the voltage levels at the first ends of the capacitors C71 and C72 change based on this to generate the boost voltage VB4.

Referring to FIG. 6, the booster 520 performs a negative boost operation, so that the output signal VBB of the booster 520 is switched from the ground voltage VSS to the boost voltage VB4. The switch element 530 switches the selection voltage VBW to the boost voltage VB4 based on the enable pulse P42. Thus, the signal ZWLj applied to the word line specified by the row address signal PAX is switched from the operating voltage VPP to the boost voltage VB4 via the word line driver. The signal ZWLi applied to the word line previously designated by the row address signal PAX is switched from the boost voltage VB4 to the operation voltage VPP.

In an embodiment, the switch element 530 further receives a first detection pulse ATDX and a second detection pulse ATDY. As described above, when the controller 510 generates the boost pulse P41 and the enable pulse P42 based on the first detection pulse ATDX, the switch element 530 further switches the first detection pulse before switching the selection voltage VBW to the boost voltage VB4. Based on ATDX, the selection voltage VBW can be switched to the reference voltage VREF. Thus, as shown in FIG. 6, in the process of switching the word line signal ZWLj from the operating voltage VPP to the boost voltage VB4, first, the word line signal ZWLj is switched to the reference voltage VREF having the effect of improving the operability of the memory unit.

On the other hand, when the row address signal PAX and the column address signal PAY change in order, the controller 510 generates the boost pulse P1 and the enable pulse P42 based on the delay time between the first detection pulse ATDX and the second detection pulse ATDY. Determine whether to generate in order. For example, the controller 510 determines the magnitude of the delay time based on the count value generated by the counting device 511. The counting device 511 performs counting again when receiving the first detection pulse ATDX, and generates a count value when receiving the second detection pulse ATDY. Therefore, the count value generated by the counting device 511 is proportional to the delay time.

When the delay time is longer than the predetermined time, the controller 510 generates a boost pulse P41 and resets the enable pulse P42. That is, at this time, in order to enable the controller 510 to use the boost clock signal KICKB, the level of the signal ENBOOST is switched from the low state to the high state, and the enable pulse P42 is formed. If the delay time is shorter than or equal to the predetermined time, the controller 510 does not generate the boost pulse P41 and does not reset the enable pulse P42. That is, at this time, since the controller 510 stops using the boost clock signal KICKB, the level of the signal ENBOOST is maintained high, and the generation of the enable pulse P42 is stopped. Similarly, booster 520 and switch element 530 perform the above-described operation based on boost pulse P41 and enable pulse P42, and switch selection voltage VBW to boost voltage VB4. In one embodiment, when the controller 510 generates the boost pulse P41 and the enable pulse P42 based on the delay time, the switch element 530 outputs the second detection pulse ATDY before switching the selection voltage VBW to the boost voltage VB4. First, the selection voltage VBW can be switched to the reference voltage VREF.

In the above-described embodiment, the power consumption of the word line boost circuit can be reduced by applying the detection pulse generated by the address transition detector to the word line boost circuit. In an actual application, it is possible to prevent erroneous determination of the state of the memory cell by applying the detection pulse generated by the address transition detector and reading the detection current of the memory cell.

For example, FIG. 8 is a partial circuit diagram of a memory device according to an embodiment of the present invention. Referring to FIG. 8, the memory device 800 includes select transistors MS81 to MS82, memory cells MC81 to MC82, NMOS transistors MN81 to MN89, a PMOS transistor MP81, a sensing amplifier 810, and an OP amplifier (operational). amplifier) 820, current source 830, and current source 840. Memory cell MC81 is electrically connected to source line SL8 via selection transistor MS81, and the gates of memory cell MC81 and selection transistor MS81 are connected to control line CL8 and word line WL8, respectively. The memory cell MC82 and the select transistor MS82 have the same connection structure.

Further, the selection transistor MS81, the memory cell MC81, and the NMOS transistors MN81 to MN83 are connected in series, and the selection transistor MS82, the memory cell MC82, and the NMOS transistors MN83 to MN86 are connected in series. As described above, the conduction states of the NMOS transistors MN81 to MN86 are controlled via the four bits PA8 <0> to PA8 <3> before the address signal PA8, so that they are transmitted to different memory cells. Since bit line BL8 is coupled to memory cell MC82, the state of memory cell MC82 can be determined based on the detected current from bit line BL8.

During the process of determining the state of the memory cell MC82, the OP amplifier 820 receives the voltage V81 and stabilizes the voltage at the node N81. As described above, when the bit line BL8 is completely activated, the detection amplifier 810 generates the detection signal S81 based on the detection current from the bit line BL8 and the reference current I81 generated by the current source 830. The state of MC82 is determined. However, when the bit line BL8 is not completely activated, the detection current from the bit line is very small. At this time, if there is a current that is not provided to the bit line BL8, the OP amplifier 820 cannot stabilize the voltage of the node N81, and thus the detection amplifier 810 may generate the error detection signal S81.

Therefore, in order to avoid such a situation, when the bit line BL8 is not completely activated, the transmission gate formed by the NMOS transistor MN89 and the PMOS transistor MP81 is generated by the current source 840 based on the detection pulse ATD8. The precharge current I82 thus provided is temporarily provided to the bit line BL8. The detection pulse ATD8 is a signal generated by an address transition detector (not shown) of the memory element 800. Thus, during the period when the bit line BL8 is not completely activated, the OP amplifier 820 can stabilize the voltage of the node N81 first by using the precharge current I82. In some embodiments, the precharge current I82 generated by the current source 840 is 0.5 times the reference current I81.

As described above, the first address transition detector is used to generate the first detection pulse related to the row address signal, and the second address transition detector is used to generate the second detection pulse related to the column address signal. Generate. Further, the boost operation unit determines whether or not to perform the boost operation based on the delay time between the first detection pulse and the second detection pulse. Therefore, when the column address of the selected memory unit changes, the boost operation unit selectively performs the boost operation, so that the power consumption of the word line boost circuit can be reduced.

As described above, the present invention has been disclosed by the embodiments. However, the present invention is not intended to limit the present invention, and is within the scope of the technical idea of the present invention so that those skilled in the art can easily understand. Therefore, the scope of patent protection should be defined based on the scope of claims and the equivalent area.

Since the word line boost circuit according to the embodiment of the present invention selectively performs the boost operation based on the first detection pulse and the second detection pulse, the power consumption of the circuit can be reduced.

100 conventional memory device 300 word line boost circuit 301 word line driver 310 first address transition detector 320 second address transition detector 330 boost operation unit 510 controller 520 booster 530 switch element 511 counting device 710, 720 inverter 800 memory element 810 Detection amplifier 820 OP amplifier 830, 840 Current source MS1, MS81-MS82 Select transistor MC1, MC81-MC82 Memory cell SL1, SL8 Source line WL1, WL8, WL (i) Word line CL1, CL8 Control line BL1, BL8 Bit line PAY <0> to PAY <3>, PAX <11> Bit KICKB of column-row address signal PA1 Signal VBB formed by boost pulse Booster output signals ZWL, ZWLi, WLj Signals received by the word line P21 to P25, P41 Boost pulses t21, t22, t41, t42, t43 Time VBW selection voltage VPP operation voltage PAX row address signal PAY column address signal ATDX first detection pulse ATDY second detection pulse PAY <0> to PAY <3> 4 bits PAX <0> before column address signal PAY First bit VB4 of row address signal PAX Boost voltage VSS Ground voltage P42 Enable pulse VREF Reference voltage STDX Signal formed by first detection pulse Signals MP71, MP72, MP81 formed by the ENBOOST enable pulse PMOS transistors MN71, MN72, MN81-MN89 NMOS transistors C71, C72 Capacitor PA8 Address signal PA8 <0>- PA8 <3> 4 bits V81 before address signal PA8 Voltage N81 Node S81 Detection signal I81 Reference current ATD8 Detection pulse I82 Precharge current

Claims (18)

A first address transition detector for generating a first detection pulse responsive to a change in a row address signal; a second address transition detector for generating a second detection pulse responsive to a change in a column address signal; and the first detection. Whether to generate a selection voltage using a boost voltage based on a pulse and to generate the selection voltage using the boost voltage based on a delay time between the first detection pulse and the second detection pulse. A word line boost circuit including a boost operation unit that determines whether or not. The boost operation unit generates a boost pulse and an enable pulse in order based on the first detection pulse, and determines whether to generate the boost pulse and the enable pulse in order based on the delay time 2. The word line boost circuit according to claim 1, further comprising: a controller for generating the boost voltage based on the boost pulse; and a switch element for switching the selection voltage to the boost voltage based on the enable pulse. . The word line boost circuit according to claim 2, wherein the switch element switches the selection voltage to a reference voltage based on the first detection pulse or the second detection pulse. When the delay time is longer than a predetermined time, the controller sequentially generates the boost pulse and the enable pulse, and when the delay time is shorter than or equal to the predetermined time, the controller 3. The word line boost circuit according to claim 2, wherein no pulse is generated. The controller includes a counting device that performs re-counting when receiving the first detection pulse and generates a count value when receiving the second detection pulse, and the controller is configured to delay the delay based on the count value. 3. The word line boost circuit according to claim 2, wherein the amount of time is determined. The booster is electrically connected to a first PMOS transistor having a source for receiving a ground voltage, a source for receiving the ground voltage, a gate electrically connected to a drain of the first PMOS transistor, and a gate of the first PMOS transistor A second PMOS transistor having a drain and generating the boost voltage; a first capacitor having a first terminal electrically connected to the drain of the first PMOS transistor; and electrically connected to the drain of the second PMOS transistor. A second capacitor having a first end; an input end for receiving a boost clock signal; a first inverter having an output end electrically connected to a second end of the first capacitor; and the output end of the first inverter. And an input terminal electrically connected to the second connector Word line boost circuit of claim 2 further comprising a second inverter having an electrical output connected to the second end of the capacitor. When the delay time is longer than a predetermined time, the boost operation unit generates the selection voltage using the boost voltage, and when the delay time is shorter than or equal to the predetermined time, the boost operation unit 2. The word line boost circuit of claim 1, wherein the boost voltage is not regenerated. A first address transition detector that determines whether to generate a first detection pulse based on a row address signal, and a second address transition that determines whether to generate a second detection pulse based on a column address signal The selection voltage is switched to the boost voltage based on the detector and the first detection pulse, and the selection voltage is changed to the boost voltage based on the delay time between the first detection pulse and the second detection pulse. A word line boost circuit including a boost operation unit that determines whether to switch. The boost operation unit generates a boost pulse and an enable pulse in order based on the first detection pulse, and determines whether to generate the boost pulse and the enable pulse in order based on the delay time The word line boost circuit according to claim 8, further comprising: a controller that performs the boost pulse generation based on the boost pulse; and a switch element that switches the selection voltage to the boost voltage based on the enable pulse. . The word line boost circuit according to claim 9, wherein the switch element switches the selection voltage to a reference voltage based on the first detection pulse or the second detection pulse. When the delay time is longer than a predetermined time, the controller sequentially generates the boost pulse and the enable pulse, and when the delay time is shorter than or equal to the predetermined time, the controller 10. The word line boost circuit according to claim 9, wherein no pulse is generated. The controller includes a counting device that performs re-counting when receiving the first detection pulse and generates a count value when receiving the second detection pulse, and the controller is configured to delay the delay based on the count value. 10. The word line boost circuit according to claim 9, wherein the time line is determined. The booster is electrically connected to a first PMOS transistor having a source for receiving a ground voltage, a source for receiving the ground voltage, a gate electrically connected to a drain of the first PMOS transistor, and a gate of the first PMOS transistor A second PMOS transistor having a drain and generating the boost voltage; a first capacitor having a first terminal electrically connected to the drain of the first PMOS transistor; and electrically connected to the drain of the second PMOS transistor. A second capacitor having a first end; an input end for receiving a boost clock signal; a first inverter having an output end electrically connected to a second end of the first capacitor; and the output end of the first inverter. And an input terminal electrically connected to the second connector Word line boost circuit of claim 9 further comprising a second inverter having an electrical output connected to the second end of the capacitor. When the delay time is longer than a predetermined time, the boost operation unit switches the selection voltage to the boost voltage, and when the delay time is shorter than or equal to the predetermined time, the boost operation unit 9. The word line boost circuit according to claim 8, wherein regeneration of the boost voltage is stopped. A word line boost circuit used for boosting a boost voltage in a memory array in which a selected memory cell is designated by a word line address and a bit line address, the first address transition detector detecting a change in the word line address A second address transition detector that detects a change in the bit line address; and a boost operation unit that generates a boost clock signal based on detection results of the first address transition detector and the second address transition detector wherein the door, the boost clock signal, Ri Do decommissioning (disable) when the selected memory cell is designated the same word line addresses,
When the change in the word line address is detected, the first address transition detector generates a first detection pulse, and when the change in the bit line address is detected, the second address transition detector Generating a second detection pulse;
The boost operation unit enables the boost clock signal based on the first detection pulse, generates an enable pulse, and delays between the first detection pulse and the second detection pulse. A controller that determines whether to enable the boost clock signal to generate the enable pulse based on time; a booster that generates the boost voltage based on the boost clock signal; and the enable And a switching element that switches a selection voltage applied to the selected memory cell to the boost voltage based on a pulse . The word line boost circuit according to claim 15, wherein the switch element switches the selection voltage to a reference voltage based on the first detection pulse or the second detection pulse. When the delay time is longer than a predetermined time, the controller enables the boost clock signal to generate the enable pulse, and when the delay time is shorter than or equal to the predetermined time 16. The word line boost circuit of claim 15, wherein the controller disables the boost clock signal. The controller includes a counting device that performs re-counting when receiving the first detection pulse and generates a count value when receiving the second detection pulse, and the controller is configured to delay the delay based on the count value. 16. The word line boost circuit of claim 15, wherein the amount of time is determined .

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