JP2013206513A5 - - Google Patents

Description

Then, the first bit PAX <0> of the row address signal PAX changes at time t42. At that time, the first address transition detector 310 generates a new first detection pulse ATDX, and the boost operation unit 330 generates a boost pulse P41 based on the new first detection pulse ATDX. Therefore, during the period between time points t42 and t43, the booster of the boost operation unit 330 switches the output signal VBB from the ground voltage VSS to VB4 that is boost electricity by performing a negative boost operation based on the boost pulse P41. Further, since the row address signal PAX is not sent to the word line WL (i), the word line driver 310 provides the operation voltage VPP to the word line WL (i).

The booster 520 performs a boost operation based on the boost pulse P41, and generates a boost voltage VB4. The detailed structure of the booster 520 will be further described below. FIG. 7 is a circuit diagram of the booster according to the embodiment of the present invention. Referring to FIG. 7, the booster 520 includes a PMOS (P-channel metal oxide semiconductor) transistor MP71, a PMOS transistor MP72, a capacitor C71 formed by an NMOS (N-channel metal oxide semiconductor) transistor MN71, and an NMOS transistor MN72. Includes a capacitor C72, an inverter 710, and an inverter 720. The sources of the PMOS transistors MP71 and MP72 receive the ground voltage VSS, and the drains of the PMOS transistors MP71 and MP72 are connected to the first ends of the capacitors C71 and C72, respectively.

Referring to FIG. 6, the booster 520 performs a negative boost operation, so that the output signal VBB of the booster 520 is switched from the ground voltage VSS to the boost voltage VB4. The switch element 530 switches the selection voltage VBW to the boost voltage VB4 based on the enable pulse P42. Thus, the signal ZWLj applied to the word line specified by the row address signal PAX is switched from the operating voltage VPP to the boost voltage VB4 via the word line driver. The signal ZWLi applied to the word line previously designated by the row address signal PAX is switched from the boost voltage VB4 to the operation voltage VPP.

100 conventional memory device 300 word line boost circuit 301 word line driver 310 first address transition detector 320 second address transition detector 330 boost operation unit 510 controller 520 booster 530 switch element 511 counting device 710, 720 inverter 800 memory element 810 Detection amplifier 820 OP amplifier 830, 840 Current source MS1, MS81-MS82 Select transistor MC1, MC81-MC82 Memory cell SL1, SL8 Source line WL1, WL8, WL (i) Word line CL1, CL8 Control line BL1, BL8 Bit line PAY <0> to PAY <3>, PAX <11> Bit KICKB of column-row address signal PA1 Signal VBB formed by boost pulse Booster output signals ZWL, ZWLi, WLj Signals received by the word line P21 to P25, P41 Boost pulses t21, t22, t41, t42, t43 Time VBW selection voltage VPP operation voltage PAX row address signal PAY column address signal ATDX first detection pulse ATDY second detection pulse PAY <0> to PAY <3> 4 bits PAX <0> before column address signal PAY First bit VB4 of row address signal PAX Boost voltage VSS Ground voltage P42 Enable pulse VREF Reference voltage STDX Signal formed by first detection pulse Signals MP71, MP72, MP81 formed by the ENBOOST enable pulse PMOS transistors MN71, MN72, MN81-MN89 NMOS transistors C71, C72 Capacitor PA8 Address signal PA8 <0>- PA8 <3> 4 bits V81 before address signal PA8 Voltage N81 Node S81 Detection signal I81 Reference current ATD8 Detection pulse I82 Precharge current

Claims (18)

A first address transition detector for generating a first detection pulse responsive to a change in a row address signal; a second address transition detector for generating a second detection pulse responsive to a change in a column address signal; and the first detection. Whether to generate a selection voltage using a boost voltage based on a pulse and to generate the selection voltage using the boost voltage based on a delay time between the first detection pulse and the second detection pulse. A word line boost circuit including a boost operation unit that determines whether or not. The boost operation unit generates a boost pulse and an enable pulse in order based on the first detection pulse, and determines whether to generate the boost pulse and the enable pulse in order based on the delay time 2. The word line boost circuit according to claim 1, further comprising: a controller for generating the boost voltage based on the boost pulse; and a switch element for switching the selection voltage to the boost voltage based on the enable pulse. . The word line boost circuit according to claim 2, wherein the switch element switches the selection voltage to a reference voltage based on the first detection pulse or the second detection pulse. When the delay time is longer than a predetermined time, the controller sequentially generates the boost pulse and the enable pulse, and when the delay time is shorter than or equal to the predetermined time, the controller 3. The word line boost circuit according to claim 2, wherein no pulse is generated. The controller includes a counting device that performs re-counting when receiving the first detection pulse and generates a count value when receiving the second detection pulse, and the controller is configured to delay the delay based on the count value. 3. The word line boost circuit according to claim 2, wherein the amount of time is determined. The booster is electrically connected to a first PMOS transistor having a source for receiving a ground voltage, a source for receiving the ground voltage, a gate electrically connected to a drain of the first PMOS transistor, and a gate of the first PMOS transistor A second PMOS transistor having a drain and generating the boost voltage; a first capacitor having a first terminal electrically connected to the drain of the first PMOS transistor; and electrically connected to the drain of the second PMOS transistor. A second capacitor having a first end; an input end for receiving a boost clock signal; a first inverter having an output end electrically connected to a second end of the first capacitor; and the output end of the first inverter. And an input terminal electrically connected to the second connector Word line boost circuit of claim 2 further comprising a second inverter having an electrical output connected to the second end of the capacitor. When the delay time is longer than a predetermined time, the boost operation unit generates the selection voltage using the boost voltage, and when the delay time is shorter than or equal to the predetermined time, the boost operation unit 2. The word line boost circuit of claim 1, wherein the boost voltage is not regenerated. A first address transition detector that determines whether to generate a first detection pulse based on a row address signal, and a second address transition that determines whether to generate a second detection pulse based on a column address signal The selection voltage is switched to the boost voltage based on the detector and the first detection pulse, and the selection voltage is changed to the boost voltage based on the delay time between the first detection pulse and the second detection pulse. A word line boost circuit including a boost operation unit that determines whether to switch. The boost operation unit generates a boost pulse and an enable pulse in order based on the first detection pulse, and determines whether to generate the boost pulse and the enable pulse in order based on the delay time The word line boost circuit according to claim 8, further comprising: a controller that performs the boost pulse generation based on the boost pulse; and a switch element that switches the selection voltage to the boost voltage based on the enable pulse. . The word line boost circuit according to claim 9, wherein the switch element switches the selection voltage to a reference voltage based on the first detection pulse or the second detection pulse. When the delay time is longer than a predetermined time, the controller sequentially generates the boost pulse and the enable pulse, and when the delay time is shorter than or equal to the predetermined time, the controller 10. The word line boost circuit according to claim 9, wherein no pulse is generated. The controller includes a counting device that performs re-counting when receiving the first detection pulse and generates a count value when receiving the second detection pulse, and the controller is configured to delay the delay based on the count value. 10. The word line boost circuit according to claim 9, wherein the time line is determined. The booster is electrically connected to a first PMOS transistor having a source for receiving a ground voltage, a source for receiving the ground voltage, a gate electrically connected to a drain of the first PMOS transistor, and a gate of the first PMOS transistor A second PMOS transistor having a drain and generating the boost voltage; a first capacitor having a first terminal electrically connected to the drain of the first PMOS transistor; and electrically connected to the drain of the second PMOS transistor. A second capacitor having a first end; an input end for receiving a boost clock signal; a first inverter having an output end electrically connected to a second end of the first capacitor; and the output end of the first inverter. And an input terminal electrically connected to the second connector Word line boost circuit of claim 9 further comprising a second inverter having an electrical output connected to the second end of the capacitor. When the delay time is longer than a predetermined time, the boost operation unit switches the selection voltage to the boost voltage, and when the delay time is shorter than or equal to the predetermined time, the boost operation unit 9. The word line boost circuit according to claim 8, wherein regeneration of the boost voltage is stopped. A word line boost circuit used for boosting a boost voltage in a memory array in which a selected memory cell is designated by a word line address and a bit line address, the first address transition detector detecting a change in the word line address A second address transition detector that detects a change in the bit line address; and a boost operation unit that generates a boost clock signal based on detection results of the first address transition detector and the second address transition detector wherein the door, the boost clock signal, Ri Do decommissioning (disable) when the selected memory cell is designated the same word line addresses,
When the change in the word line address is detected, the first address transition detector generates a first detection pulse, and when the change in the bit line address is detected, the second address transition detector Generating a second detection pulse;
The boost operation unit enables the boost clock signal based on the first detection pulse, generates an enable pulse, and delays between the first detection pulse and the second detection pulse. A controller that determines whether to enable the boost clock signal to generate the enable pulse based on time; a booster that generates the boost voltage based on the boost clock signal; and the enable And a switching element that switches a selection voltage applied to the selected memory cell to the boost voltage based on a pulse . The word line boost circuit according to claim 15, wherein the switch element switches the selection voltage to a reference voltage based on the first detection pulse or the second detection pulse. When the delay time is longer than a predetermined time, the controller enables the boost clock signal to generate the enable pulse, and when the delay time is shorter than or equal to the predetermined time 16. The word line boost circuit of claim 15, wherein the controller disables the boost clock signal. The controller includes a counting device that performs re-counting when receiving the first detection pulse and generates a count value when receiving the second detection pulse, and the controller is configured to delay the delay based on the count value. 16. The word line boost circuit of claim 15, wherein the amount of time is determined .