JP5522079B2 - Write control circuit and semiconductor device - Google Patents

Description

  The present invention relates to a write control circuit and a semiconductor device that control writing to a memory element that is electrically written only once.

  In recent years, in a RAM (Random Access Memory) circuit or the like, electric fuse elements are increasingly used for redundancy processing for relieving defective bits, identification numbers for identifying each chip, and the like.

  The electrical fuse element is a storage element (hereinafter referred to as an OTP (One Time Programming) element) in which writing is performed only once electrically. The electric fuse element is connected to a terminal to which a predetermined write voltage is applied and a write transistor. When a predetermined write voltage is applied and a write transistor such as a WE (Write Enable) signal is instructed to turn on, a current flows through the electric fuse element. The electric fuse element is cut by this current, and a write state is entered.

JP 2009-157981 A JP-A-8-321197

  However, in the OTP element as described above, if any unintended current flows, proper writing is not performed and erroneous writing occurs.

  According to one aspect of the invention, a write control unit that controls writing to a memory element that is electrically written only once according to a write signal that instructs writing to the memory element, a power supply voltage, Alternatively, a write control circuit including a voltage detection unit that causes the write control unit to stop writing to the storage element regardless of the write signal for a certain period when the write voltage supplied to the storage element rises is provided. Is done.

  A storage element that is electrically written only once, and a write transistor that is connected to the storage element and controls whether or not a current caused by a write voltage flows through the storage element in accordance with a control signal; The control signal according to a write signal instructing writing to the storage element is output, a write control unit for controlling writing to the storage element, and a power supply voltage, or a rising time of the write voltage, for a certain period, There is provided a semiconductor device comprising: a voltage detection unit that causes the write control unit to stop writing to the memory element regardless of the write signal.

  According to the disclosed write control circuit and semiconductor device, erroneous writing can be suppressed.

1 is a diagram illustrating an example of a semiconductor device and a write control circuit according to a first embodiment; 6 is a diagram illustrating an example of a semiconductor device and a write control circuit according to a second embodiment; FIG. It is a figure which shows an example of the signal waveform at the time of write-in voltage input. It is a figure which shows an example of the signal waveform at the time of power supply voltage input. It is a figure which shows an example of the semiconductor device and write-in control circuit of 3rd Embodiment. It is a figure which shows an example of the signal waveform at the time of write-in voltage input. It is a figure which shows an example of the signal waveform at the time of power supply voltage input. It is a figure which shows an example of the semiconductor device of 4th Embodiment. It is a figure which shows an example of a fuse block.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In an OTP element that performs electrical writing, if the write transistor is turned on when the signal is unstable, such as when a write voltage or power supply voltage is turned on, an appropriate current does not flow through the electrical fuse element, and overwriting is performed. In addition, there is a possibility of a halfway writing state. In that case, erroneous writing occurs, and the writing quality deteriorates.

The write control circuit and the semiconductor device of the present embodiment suppress such erroneous writing.
In the following, an example in which an electrical fuse element is used as an example of an OTP element that performs electrical writing will be described. However, the present invention is not limited to this. For example, a high voltage is applied to the gate oxide film of a transistor to electrically destroy it. Thus, an OTP element that is in a writing state may be used.

(First embodiment)
FIG. 1 is a diagram illustrating an example of a semiconductor device and a write control circuit according to the first embodiment.
The semiconductor device 1 includes an electric fuse element 2, a write transistor 3, and a write control circuit 10. The write control circuit 10 includes a write control unit 11, a voltage detection unit 12, and a level shifter 13.

  The electrical fuse element 2 and the write transistor 3 are connected, for example, between a terminal VB to which a write voltage is applied from a tester circuit (not shown) and a ground terminal VSS that is a ground potential (reference potential).

  As the electric fuse element 2, an element using a silicide layer formed on a polysilicon layer, a metal fuse, or the like is used. When the electric fuse element 2 has a resistance value of 120Ω and is cut off when a current of 10 mA flows, for example, 2.4 V is applied as a write voltage.

  The write transistor 3 receives a control signal from the write control unit 11 and controls whether or not a current flows to the electric fuse element 2. In the example of FIG. 1, the write transistor 3 is an n-channel MOSFET (Metal-Oxide Semiconductor Field Effect Transistor).

  In the example shown in FIG. 1, one terminal of the electrical fuse element 2 is connected to a terminal VB to which a write voltage is applied, and the other terminal is connected to one input / output terminal (drain) of the write transistor 3. Yes. The other input / output terminal (source) of the write transistor 3 is connected to the ground terminal VSS, and a control signal from the write control unit 11 is input to the control terminal (gate).

  In the write control circuit 10, the write control unit 11 receives a write signal (for example, a write enable signal) input from a tester circuit (not shown) via the terminal WE and boosted by the level shifter 13. Control writing. Then, the write controller 11 controls writing to the electrical fuse element 2 by generating a control signal for turning on or off the write transistor 3 in accordance with the input write signal. The write control unit 11 is driven by a write voltage supplied from the terminal VB. The write controller 11 is also connected to the ground terminal VSS.

  The voltage detection unit 12 is connected to the terminals VB and VDD and the ground terminal VSS, and detects a write voltage and a power supply voltage supplied to the electrical fuse element 2. The voltage detection unit 12 stops writing to the electrical fuse element 2 for a certain period regardless of the write signal input to the write control unit 11 when the power supply voltage or the write voltage rises. Let In the example illustrated in FIG. 1, the voltage detection unit 12 causes the write control unit 11 to fix the control terminal to an L (Low) level potential in order to maintain the write transistor 3 in the off state. (Details will be described later).

The period during which the write transistor 3 is turned off is set according to the period until the write voltage and the power supply voltage become stable at the rise of the power supply voltage.
The level shifter 13 is connected to terminals VB and VDD, a ground terminal VSS, and a terminal WE to which a write signal is input. For example, the level shifter 13 boosts the write signal, which is a pulse signal for a certain period, from the signal level of the power supply voltage (for example, about 1.2 V) to the signal level of the write voltage (for example, about 2.4 V). A thick gate oxide film (for example, about 8 nm) is used for the write transistor 3 to which a relatively high write voltage is applied and the transistor (not shown) in the write controller 11, so that these transistors are sufficiently turned on. Boosting as described above is performed. Note that a thick gate oxide film is also used in the transistor (not shown) in the voltage detector 12.

  The write control circuit 10 as described above can keep the write transistor 3 off for a certain period when the signal at the rise of the write voltage or the power supply voltage is unstable. Can be suppressed.

  For example, if the write signal is boosted in the level shifter 13 when the write voltage is turned on, the write signal may become an unstable signal due to the influence of the unstable write voltage. However, according to the write control circuit 10 and the semiconductor device 1 of the present embodiment, the write transistor 3 can be maintained in the OFF state regardless of the write signal for a certain period when the write voltage is applied. Write by can be suppressed.

Further, writing to the electrical fuse element 2 due to an unstable write voltage when the write voltage is applied is suppressed.
Moreover, even when the boost of the write signal becomes unstable when the power supply voltage is turned on and an unstable write signal is input to the write control unit 11, the write transistor 3 can be maintained in the off state. Thereby, erroneous writing due to a write signal that becomes unstable when the power supply voltage is turned on can be suppressed.

Hereinafter, examples of the write control circuit will be described in more detail as the second and third embodiments.
(Second Embodiment)
FIG. 2 is a diagram illustrating an example of a semiconductor device and a write control circuit according to the second embodiment.

The same elements as those of the semiconductor device 1 of the first embodiment are denoted by the same reference numerals and the description thereof is omitted.
In the semiconductor device 1a of the second embodiment, the write control circuit 10a includes a write control unit 11a and a voltage detection unit 12a.

The write control unit 11a includes an AND circuit 111 and an inverter circuit 112.
The AND circuit 111 outputs an AND logic of the write signal output from the level shifter 13 and the output signal of the voltage detector 12a whose signal level is inverted by the inverter circuit 112. The AND circuit 111 invalidates the write signal output from the level shifter 13 by an H (High) level signal output from the voltage detector 12a when the write voltage or the power supply voltage rises. That is, the AND circuit 111 outputs an L level signal regardless of the write signal.

The AND circuit 111 and the inverter circuit 112 are connected to the terminal VB and the ground terminal VSS, and are driven by the write voltage.
The voltage detector 12a has a series circuit including a capacitor 121, a transistor 122, and a resistor 123 connected between the terminal VB and the ground terminal VSS.

  One terminal of the capacitor 121 is connected to the terminal VB, and the other terminal is connected to one input / output terminal (drain) of the transistor (n-channel MOSFET). The other input / output terminal (source) of the transistor 122 is connected to one end of the resistor 123, and the control terminal (gate) is connected to the terminal VDD. The other end of the resistor 123 is connected to the ground terminal VSS. The potential of the node N1 between the capacitor 121 and the drain of the transistor 122 is input to the inverter circuit 112 of the write control unit 11a as an output signal of the voltage detection unit 12a.

The capacitance value of the capacitor 121 and the resistance value of the resistor 123 are appropriately set according to the period during which the write transistor 3 is desired to be kept off when the write voltage and the power supply voltage are turned on.
Hereinafter, the operation of the semiconductor device 1a according to the second embodiment will be described.

First, the operation when the write voltage is turned on when the power supply voltage supplied from the terminal VDD is already set (in a stable state) will be described.
FIG. 3 is a diagram illustrating an example of a signal waveform when a write voltage is input.

  The vertical axis represents voltage, and the horizontal axis represents time. In the figure, the write voltage supplied from the terminal VB is denoted as VB. Further, the potentials of the nodes N1 and N2 of the semiconductor device 1a shown in FIG. 2 are expressed as N1 and N2, respectively.

  It is assumed that the potential of the node N2 is L level in the initial state. When the input of the write voltage is started at time t1, the potential of the node N1 becomes H level as the write voltage increases. Therefore, the output signal of the inverter circuit 112 becomes L level, the output of the AND circuit 111 becomes L level regardless of the write signal output from the level shifter 13, and the potential of the node N2 is fixed to L level. For this reason, even when the write signal is at the H level, the write transistor 3 remains off, and writing to the electrical fuse element 2 does not occur.

  Since the power supply voltage is already set (H level), the transistor 122 is on. Therefore, the potential of the node N1 decreases according to a time constant determined by the capacitance value of the capacitor 121, the resistance value of the resistor 123, and the like.

  When the potential of the node N1 is equal to or lower than the potential at which the input is determined to be L level by the inverter circuit 112 (determined by the threshold voltage of the transistor of the inverter circuit 112) (time t2), the output of the inverter circuit 112 is set to H level. Invert. As a result, the AND circuit 111 outputs a value corresponding to the write signal output from the level shifter 13. When the write signal is at the H level, the AND circuit 111 outputs an H level control signal, and the potential of the node N2 becomes the H level as shown in FIG. As a result, the write transistor 3 is turned on, a current due to the write voltage flows through the electric fuse element 2, and the cutting is performed.

  As described above, when the write voltage is turned on, the write transistor 3 is maintained in the OFF state regardless of the write signal for a certain period, thereby suppressing writing to the electric fuse element 2 due to an unstable write voltage or write signal. it can. Thereby, erroneous writing can be suppressed.

Next, the operation when the power supply voltage is turned on in the case where the write voltage supplied from the terminal VB has been set (in a stable state) will be described.
FIG. 4 is a diagram illustrating an example of a signal waveform when the power supply voltage is turned on.

  The vertical axis represents voltage, and the horizontal axis represents time. In the figure, the power supply voltage supplied from the terminal VDD is denoted as VDD. Further, the potentials of the nodes N1 and N2 of the semiconductor device 1a shown in FIG. 2 are expressed as N1 and N2, respectively.

  It is assumed that the potential of the node N2 is L level in the initial state. At time t3, the supply of power supply voltage is started, and when the voltage rises to the threshold voltage of the transistor 122 (time t4), the transistor 122 is turned on. Then, the potential of the node N1 decreases according to a time constant determined by the capacitance value of the capacitor 121, the resistance value of the resistor 123, and the like. However, the output signal of the inverter circuit 112 is at the L level until the potential of the node N1 is equal to or lower than the potential at which the input is determined to be the L level in the inverter circuit 112. Therefore, regardless of the write signal output from the level shifter 13, the output of the AND circuit 111 becomes L level, and the potential of the node N2 is fixed at L level. For this reason, even when the write signal is at the H level, the write transistor 3 remains off, and writing to the electrical fuse element 2 does not occur.

  When the potential of node N1 becomes equal to or lower than the potential at which the input is determined to be L level in inverter circuit 112 (time t5), the output of inverter circuit 112 is inverted to H level. As a result, the AND circuit 111 outputs a value corresponding to the write signal output from the level shifter 13. When the write signal is at the H level, the AND circuit 111 outputs an H level control signal, and the potential of the node N2 becomes the H level as shown in FIG. As a result, the write transistor 3 is turned on, and a current due to the write voltage flows to the electric fuse element 2 to be cut.

  As described above, when the power supply voltage is turned on, the write transistor 3 is maintained in the OFF state regardless of the write signal for a certain period, so that even if the write signal becomes unstable during that period, the electric fuse element 2 is supplied. Can be suppressed. Thereby, erroneous writing can be suppressed.

(Third embodiment)
The write control circuit is not limited to the circuit configuration shown in FIG. 2, and may be a circuit as shown below, for example.

FIG. 5 is a diagram illustrating an example of a semiconductor device and a write control circuit according to the third embodiment.
The same elements as those of the semiconductor device 1a of the second embodiment are denoted by the same reference numerals, and description thereof is omitted.

  In the semiconductor device 1b shown in FIG. 5, in the write control circuit 10b, the connection of the resistor 125, the transistor 126, and the capacitor 127 of the voltage detection unit 12b is different from that of the voltage detection unit 12a of the write control circuit 10a of the first embodiment. ing.

  In the write control circuit 10b of the third embodiment, in the voltage detection unit 12b, one end of the resistor 125 is connected to the terminal VB, and the other end is connected to the drain of the transistor 126. The source of the transistor 126 is connected to one terminal of the capacitor 127, and the other terminal of the capacitor 127 is connected to the ground terminal VSS. A terminal VDD is connected to the transistor gate, and a power supply voltage is supplied. The potential of the node N4 between the source of the transistor 126 and the capacitor 127 is input to the write control unit 11b as an output signal of the voltage detection unit 12b.

  The write control unit 11b includes an AND circuit 113, which receives the output signal of the voltage detection unit 12b and the boosted write signal output from the level shifter 13, and inputs the AND logic result to the gate of the write transistor 3. Output as supplied control signal. The AND circuit 113 invalidates the write signal by a signal output from the voltage detection unit 12b during a certain period when the write voltage or the power supply voltage rises. That is, the AND circuit 113 outputs an L level control signal regardless of the write signal.

Hereinafter, the operation of the semiconductor device 1b will be described.
First, the operation when the write voltage is turned on when the power supply voltage supplied from the terminal VDD is already set (in a stable state) will be described.

FIG. 6 is a diagram illustrating an example of a signal waveform when a write voltage is input.
The vertical axis represents voltage, and the horizontal axis represents time. In the figure, the write voltage supplied from the terminal VB is denoted as VB. Further, the potentials of the nodes N2 and N4 of the semiconductor device 1b shown in FIG. 5 are denoted as N2 and N4, respectively.

  It is assumed that the potential of the node N2 is L level in the initial state. At time t10, when the application of the write voltage is started, the transistor 126 is in an on state. Therefore, as the write voltage increases, the potential of the node N4 also increases according to a time constant determined by the capacitor 127, the resistor 125, and the like. start. However, the output signal of the AND circuit 113 remains at the L level until the potential of the node N4 becomes equal to or higher than the potential at which the input is determined to be the H level by the AND circuit 113 (determined by the threshold voltage of the transistor of the AND circuit 113). It is. Therefore, regardless of the write signal output from the level shifter 13, the output of the AND circuit 113 becomes L level, and the potential of the node N2 is fixed at L level. For this reason, even when the write signal is at the H level, the write transistor 3 remains off, and writing to the electrical fuse element 2 does not occur.

  When the potential of the node N4 becomes equal to or higher than the potential at which the input is determined to be H level by the AND circuit 113 (time t11), the AND circuit 113 outputs a value corresponding to the write signal output from the level shifter 13. Become. When the write signal is at the H level, the AND circuit 113 outputs an H level control signal, and the potential of the node N2 becomes the H level as shown in FIG. As a result, the write transistor 3 is turned on, a current due to the write voltage flows through the electric fuse element 2, and the cutting is performed.

  As described above, when the write voltage is turned on, the write transistor 3 is maintained in the OFF state regardless of the write signal for a certain period, thereby suppressing writing to the electric fuse element 2 due to an unstable write voltage or write signal. it can. Thereby, erroneous writing can be suppressed.

Next, the operation when the power supply voltage is turned on in the case where the write voltage supplied from the terminal VB has been set (in a stable state) will be described.
FIG. 7 is a diagram illustrating an example of a signal waveform when the power supply voltage is turned on.

  The vertical axis represents voltage, and the horizontal axis represents time. In the figure, the power supply voltage supplied from the terminal VDD is denoted as VDD. Further, the potentials of the nodes N2 and N4 of the semiconductor device 1b shown in FIG. 5 are denoted as N2 and N4, respectively.

  It is assumed that the potential of the node N2 is L level in the initial state. At time t12, the supply of power supply voltage is started, and when the voltage rises to the threshold voltage of the transistor 126 (time t13), the transistor 126 is turned on. As a result, the potential of the node N4 increases in accordance with a time constant determined by the capacitance value of the capacitor 127, the resistance value of the resistor 125, and the like.

  However, the output signal of the AND circuit 113 is at the L level until the potential of the node N4 becomes equal to or higher than the potential at which the input is determined to be the H level by the AND circuit 113. Therefore, regardless of the write signal output from the level shifter 13, the output of the AND circuit 113 becomes L level, and the potential of the node N2 is fixed at L level. That is, even when the write signal becomes H level, the write transistor 3 remains off, and writing to the electric fuse element 2 does not occur.

  When the potential of the node N4 becomes equal to or higher than the potential at which the input is determined to be H level by the AND circuit 113 (time t14), the AND circuit 113 outputs a value corresponding to the write signal output from the level shifter 13. Become. When the write signal is at the H level, the AND circuit 113 outputs an H level control signal, and the potential of the node N2 becomes the H level as shown in FIG. As a result, the write transistor 3 is turned on, and a current due to the write voltage flows to the electric fuse element 2 to be cut.

  As described above, when the power supply voltage is turned on, the write transistor 3 is maintained in the OFF state regardless of the write signal for a certain period, so that even if the write signal becomes unstable during that period, the electric fuse element 2 is supplied. Can be suppressed. Thereby, erroneous writing can be suppressed.

Hereinafter, as a fourth embodiment, an example will be described in which the write control circuit as described above is applied when, for example, ID (Identification) for identifying a chip is realized.
(Fourth embodiment)
FIG. 8 is a diagram illustrating an example of a semiconductor device according to the fourth embodiment.

  The semiconductor device 50 includes a plurality of fuse blocks 51-1, 51-2, ..., 51-N, AND circuits 52-1, 52-2, ..., 52-N, flip-flops 53-1, 53-2, .... , 53- (N-1).

  A write voltage is supplied from the terminal VB to each of the fuse blocks 51-1 to 51-N. Further, a read signal (sense signal) instructing reading from the fuse blocks 51-1 to 51-N is supplied from the terminal SEN. Further, the write signal supplied from the terminal WE and the enable signal supplied from the terminal EN are input to the AND circuits 52-1 to 52-N, and the outputs of the AND circuits 52-1 to 52-N are the fuse blocks 51-. 1-51-N.

  The flip-flops 53-1 to 53- (N-1) have a function of a shift register that takes in an enable signal and shifts it to a subsequent stage in accordance with a clock signal input from a terminal CLK.

FIG. 9 is a diagram illustrating an example of a fuse block.
An example of the fuse block 51-1 shown in FIG. 8 is shown. The same applies to the other fuse blocks 51-2 to 51-N. The same components as those of the semiconductor device 1a shown in FIG.

The fuse block 51-1 includes a read circuit 511 in addition to the elements of the semiconductor device 1a shown in FIG.
When a sense signal instructing readout is input from the SEN terminal, the readout circuit 511 reads the potential on the cathode side of the electrical fuse element 2 (the potential of the node N3) and outputs it from the output terminal ID [0].

  In the semiconductor device 50 as shown in FIGS. 8 and 9, a fuse block 51-1 that performs writing in accordance with an enable signal, a write signal, and a clock signal while a write voltage is applied to the terminal VB at the time of writing. ~ 51-N is selected and cutting is performed. Thus, for example, the chip ID is programmed depending on which fuse block 51-1 to 51-N is to be cut.

  When a sense signal for reading the written contents of the fuse blocks 51-1 to 51-N is input from the terminal SEN, the state of the electrical fuse element 2 is changed from the read circuit 511 of each fuse block 51-1 to 51-N. The potential of the corresponding node N3 is read out. The read potentials are output terminals ID [0], ID [1],. For example, the chip ID is output from ID [N-1].

  By mounting the write control circuit 10a described in the first embodiment on each of the fuse blocks 51-1 to 51-N of such a semiconductor device 50, it is possible to prevent a chip ID or the like from being erroneously written. can do.

8 illustrates the example in which the write control circuit 10a illustrated in FIG. 2 is applied, the write control circuit 10b illustrated in FIG. 5 may be used.
As described above, one aspect of the write control circuit and the semiconductor device of the present invention has been described based on the embodiment, but these are merely examples, and the present invention is not limited to the above description.

  For example, the write transistor 3 and the transistors 122 and 126 may be p-channel MOSFETs. In that case, the circuit configuration is changed as appropriate. A bipolar transistor may be used instead of the MOSFET.

The following additional notes are further disclosed with respect to the plurality of embodiments described above.
(Additional remark 1) The write control part which controls the writing to the memory | storage element in which writing only once is electrically performed according to the write signal which instruct | indicates the writing to the said memory element,
A voltage detection unit that causes the write control unit to stop writing to the storage element regardless of the write signal at a rising time of a power supply voltage or a write voltage supplied to the storage element;
A write control circuit comprising:

  (Additional remark 2) The said write-control part has a logic circuit which invalidates the said write signal by the signal output from the said voltage detection part at the time of the rise of the said power supply voltage or the said write voltage, It is characterized by the above-mentioned. The write control circuit according to appendix 1.

(Supplementary Note 3) The voltage detection unit includes a series circuit including a resistor, a capacitor, and a transistor to which the power supply voltage is applied to a control terminal, connected between a ground terminal and a terminal to which the write voltage is applied. And
A signal of a node between the transistor and the capacitor is supplied to the write control unit, and writing to the storage element is stopped by the write control unit when the power supply voltage or the write voltage rises. The write control circuit according to appendix 1 or 2.

  (Supplementary note 4) The write signal according to any one of Supplementary notes 1 to 3, wherein the write signal is a signal boosted from a signal level of the power supply voltage to a signal level of the write voltage by a level shifter. Control circuit.

  (Additional remark 5) The said fixed period is set based on the time constant of the said series circuit, and the threshold voltage of the transistor of the said write-control part, The additional description 3 or 4 characterized by the above-mentioned Write control circuit.

(Supplementary Note 6) A storage element that is electrically written only once, and
A write transistor that is connected to the storage element and controls whether or not a current caused by a write voltage flows through the storage element in accordance with a control signal;
A write control unit for controlling the writing to the storage element by outputting the control signal according to a writing signal instructing writing to the storage element;
A voltage detection unit that causes the write control unit to stop writing to the storage element regardless of the write signal for a certain period of time when the power supply voltage or the write voltage rises;
A semiconductor device comprising:

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Electrical fuse element 3 Write transistor 10 Write control circuit 11 Write control part 12 Voltage detection part 13 Level shifter VB, VDD, WE terminal VSS Ground terminal

Claims (4)

A write control unit that controls writing to the storage element that is electrically written only once according to a write signal that instructs writing to the storage element;
A voltage detection unit that causes the write control unit to stop writing to the storage element regardless of the write signal at a rising time of a power supply voltage or a write voltage supplied to the storage element;
A write control circuit comprising:   The write control unit includes a logic circuit that invalidates the write signal by a signal output from the voltage detection unit when the power supply voltage or the write voltage rises. The write control circuit described. The voltage detection unit includes a series circuit including a resistor, a capacitor, and a transistor to which the power supply voltage is applied to a control terminal, connected between a ground terminal and a terminal to which the write voltage is applied,
A signal of a node between the transistor and the capacitor is supplied to the write control unit, and writing to the storage element is stopped by the write control unit when the power supply voltage or the write voltage rises. The write control circuit according to claim 1. A storage element that is electrically written only once;
A write transistor that is connected to the storage element and controls whether or not a current caused by a write voltage flows through the storage element in accordance with a control signal;
A write control unit for controlling the writing to the storage element by outputting the control signal according to a writing signal instructing writing to the storage element;
A voltage detection unit that causes the write control unit to stop writing to the storage element regardless of the write signal for a certain period of time when the power supply voltage or the write voltage rises;
A semiconductor device comprising:

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