JP4964907B2 - Memory controller and decoder - Google Patents

Description

  The present invention relates to a memory controller and a decoder, and more particularly, to a circuit capable of reducing a gate-induced drain leakage current.

  The storage is a kind of storage device and has advantages such as a high access speed and a small volume. Currently, the memory is widely used in various electronic devices. The memory needs to determine an address by a decoder in the process of reading / writing data. A conventional address decoder will be described below.

  FIG. 1 is a circuit diagram of a conventional address decoder. The address decoder 10 includes transistors 11 to 13. The control signal bMWL is used to control whether the transistors 11 and 12 are turned on. Control signal WLRST is used to control whether transistor 13 is conducting. In this way, the signal WL can be controlled.

  The transistor 11 often generates a gate-induced drain leakage (GIDL) current. Since the GIDL current tends to cause a memory operation error, it affects the accuracy of data access.

  An object of the present invention is to provide a memory controller and a decoder capable of reducing the gate-induced drain leakage current in order to solve the above-described problem.

  In order to achieve the aforementioned object, the present invention provides a decoder, which can reduce gate induced drain leakage current.

  In addition, the present invention provides a memory control circuit that limits the amount of gate induced drain leakage current of another transistor by one transistor, thereby reducing the gate induced drain leakage current.

  The present invention provides a decoder including first to fourth transistors. The gate and first end of the first transistor are connected to the first control signal and the first voltage, respectively. The gate and first end of the second transistor are connected to the second control signal and the second end of the first transistor, respectively. The gate, first end and second end of the third transistor are connected to the third control signal, the second end of the second transistor and the second voltage, respectively. The gate, first end and second end of the fourth transistor are connected to the fourth control signal, the second end of the second transistor and the second voltage, respectively. When the first transistor is turned off and the second transistor is turned off, the voltage of the second control signal is smaller than the voltage of the first control signal.

  In one embodiment of the present invention, the first transistor, the second transistor, the third transistor, and the fourth transistor are respectively a P channel field effect transistor, a P channel field effect transistor, an N channel field effect transistor, and an N channel field transistor. It is an effect transistor.

  In one embodiment of the present invention, the decoder further includes a fifth transistor. The gate, first end, and second end of the fifth transistor are connected to the fifth control signal, the second end of the second transistor, and the second voltage, respectively. In another embodiment, the fifth transistor is an N-channel field effect transistor. In another embodiment, the second end of the second transistor may be an output end of the decoder.

  The present invention also provides a memory controller including first and second phase inverters and an output unit. The output unit includes first to third transistors. The first phase inverter can receive the first control signal and generate a second control signal based on the first control signal. The input terminal of the second phase inverter is connected to the output terminal of the first phase inverter, can receive the second control signal, and can output the third control signal based on the second control signal. . The output unit is connected to the output terminal of the second phase inverter. The gate of the first transistor receives the third control signal. The first end of the first transistor is connected to the first voltage. The gate of the second transistor receives the third control signal. The first end of the second transistor is connected to the second end of the first transistor. The gate, the first end, and the second end of the third transistor are connected to the fourth control signal, the second end of the second transistor, and the second voltage, respectively. When the second transistor is turned off and the third transistor is turned off, the voltage of the fourth control signal is greater than the voltage of the third control signal.

  In one embodiment of the present invention, the first transistor, the second transistor, and the third transistor described above are a P-channel field effect transistor, an N-channel field effect transistor, and an N-channel field effect transistor, respectively.

  In one embodiment of the present invention, the storage controller further includes a third phase inverter. The input terminal of the third phase inverter is connected to the output terminal of the first phase inverter, can receive the second control signal, and can output the fifth control signal based on the second control signal. .

  As described above, according to the present invention, the first and second transistors connected in series are arranged in the decoder or the memory controller. When the first transistor is turned off and the second transistor is turned off, the voltage received by the gate of the second transistor is different from the voltage received by the gate of the first transistor. The first transistor can limit the conduction current of the series path, and the second transistor can limit the amount of gate-induced drain leakage current, thereby reducing the leakage current of the series path. .

  The present invention provides a memory controller and decoder that can reduce gate induced drain leakage current.

It is a circuit diagram of a conventional address decoder. FIG. 4 is a circuit diagram of a decoder according to an embodiment of the present invention. It is a figure which shows the mode of the GIDL current of the P channel field effect transistor by one Example of this invention, and its gate voltage. It is a circuit diagram of a memory controller according to an embodiment of the present invention. FIG. 5 is a waveform diagram of the signals in FIGS. 2 and 4. FIG. 6 is a circuit diagram of a decoder according to another embodiment of the present invention.

  Next, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 2 is a circuit diagram of a decoder according to an embodiment of the present invention. The decoder 20 is an address decoder. More specifically, the decoder 20 may be a row decoder or a column decoder. Decoder 20 includes transistors 21-24. In the present embodiment, the transistors 21 to 24 are described by taking, as examples, a P-channel field effect transistor, a P-channel field effect transistor, an N-channel field effect transistor, and an N-channel field effect transistor. Not limited to.

  The gate of transistor 21 receives control signal bMWL, and its potential is relatively high VPP when not selected, and based on this, determines whether transistor 21 is conducting. The gate of transistor 22 receives control signal WLRST and is VINT when its potential is not selected, and based on this, determines whether transistor 22 is conducting. The gate of transistor 23 receives control signal bMWL and determines based on this whether transistor 23 is conducting. The gate of transistor 24 receives control signal WLRST and based on this determines whether transistor 24 is conducting. In this embodiment, the gates of the transistors 21 and 23 receive the same voltage. However, in other embodiments, the gates of the transistors 21 and 23 may receive different voltages. Also, although the gates of transistors 22 and 24 receive the same voltage, in other embodiments, the gates of transistors 22 and 24 may receive different voltages.

  The gate and drain of the transistor 21 are connected to the voltage WLDV and the source of the transistor 22, respectively. The drain of the transistor 22 may be connected to the drains of the transistors 23 and 24 and used as the output terminal of the decoder 20. The sources of the transistors 23 and 24 are connected to the voltage VNN. The bulk voltage of the transistors 21 and 22 may be the voltage VPP. The bulk voltage of the transistors 23 and 24 may be the voltage VNN.

  FIG. 3 is a diagram illustrating a GIDL current and a gate voltage of a P-channel field effect transistor according to an embodiment of the present invention. Please refer to FIG. 2 and FIG. When the transistor 21 is turned off and the transistor 22 is turned off, the voltage of the control signal WLRST is lower than the voltage of the control signal bMWL. For example, the voltage of the control signal bMWL may be the voltage VPP, and the voltage of the control signal WLRST may be the voltage VINT. At this time, the GIDL current of the transistor 21 is I1, and the GIDL current of the transistor 22 is I2, where I2 is smaller than I1. That is, in this embodiment, the conduction current of the transistors 21 and 22 connected in series using the transistor 22 is limited, and the GIDL current is limited using the transistor 22, so that the GIDL current of the decoder 20 can be effectively used. The operation error of the decoder 20 can be prevented.

  Similarly, the above-described method for reducing the GIDL current may be applied to other circuits. For example, FIG. 4 is a circuit diagram of a memory controller according to one embodiment of the present invention, and FIG. 5 is a waveform diagram of the signals of FIGS. Please refer to FIG. 2, FIG. 4 and FIG. The storage control circuit 30 controls the decoder 20. The memory control circuit 30 includes phase inverters 40 and 50 and an output unit 70. The memory control circuit 30 further includes a phase inverter 60. The phase inverter 40 includes transistors 41 and 42. The phase inverter 50 includes transistors 51 and 52. The phase inverter 60 includes transistors 61 and 62. The output unit 70 includes transistors 71 to 73. In the present embodiment, the transistors 41, 51, 61, and 71 are described as examples of P-channel field effect transistors, and the transistors 42, 52, 62, 72, and 73 are described as examples of N-channel field effect transistors.

  The phase inverter 40 receives the control signal MWLRST and generates the control signal MWLRST2 based on the control signal MWLRST, where the phases of the control signal MWLRST2 and the control signal MWLRST are opposite to each other. The input terminal of the phase inverter 50 is connected to the output terminal of the phase inverter 40, receives the control signal MWLRST2, and outputs the control signal MWLRST3 based on the control signal MWLRST3. Here, the control signal MWLRST3 and the control signal MWLRST2 Are opposite to each other. The input terminal of the phase inverter 60 is connected to the output terminal of the phase inverter 40, receives the control signal MWLAST2, and outputs the control signal WLRST based on the control signal MWLAST2, where the control signal WLRST and the control signal MWLRST2 are output. Are opposite to each other.

  Subsequently, the output unit 70 is connected to the output terminal of the phase inverter 50, receives the control signal MWLRSR3, and outputs the voltage WLDV based on this, where the phase of the voltage WLDV and the control signal MWLRST3 is Oppose each other. Note that the transistor 72 and the transistor 73 are connected in series. When the transistor 72 is turned off and the transistor 73 is turned off, the voltage of the control signal MWLRST3 is larger than the voltage of the control signal BNKSEL, so that the off current of the transistor 73 is smaller than the GIDL current of the transistor 21 in FIG. In other words, in this embodiment, the transistor 73 can limit the GIDL current and reduce the GIDL current of the decoder 20 of FIG.

  In addition, although one aspect of the memory controller and the decoder has been described in the above-described embodiments, it will be apparent to those skilled in the art that the designs for the memory controller and the decoder of each manufacturer are different. The application of the invention is not limited to this one aspect. In other words, when two transistors connected in series are turned off, the voltages received by their gates are different from each other, one transistor is used to limit the conduction current, and the other transistor is used to apply GIDL. As long as the current is limited, it falls within the scope of the present invention. Other examples will be given below for those skilled in the art to further understand the spirit of the present invention and implement the present invention.

  Refer to FIG. 2 again. In the embodiment described above, the bulk voltage of the transistors 21 and 22 has been described by taking the voltage VPP as an example, but the present invention is not limited to this.

  Also, the decoder 20 disclosed in FIG. 2 is just a selected embodiment, and in other embodiments, the decoder may include a different number of transistors. For example, FIG. 6 is a circuit diagram of a decoder according to another embodiment of the present invention. Please refer to FIG. 2 and FIG. Decoder 20 'and decoder 20 are similar but the difference is that decoder 20' further includes a plurality of transistors (only transistor 25 is shown here). The gate of transistor 25 receives control signal WLRST1 and determines whether transistor 25 is conductive based on this. In this way, the decoder 20 'has more operating states.

  Therefore, the present invention arranges the first and second transistors connected in series in the decoder or the storage controller. When the first transistor is turned off and the second transistor is turned off, the voltage received by the gate of the second transistor is different from the voltage received by the gate of the first transistor. The first transistor limits the conduction current in the series path, and the second transistor limits the amount of GIDL current, thereby reducing the leakage current in the series path.

  The preferred embodiment of the present invention has been described above, but the present invention is not limited to this embodiment, and all modifications to the present invention are within the scope of the present invention unless departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 10 Address decoder 11-13, 21-25, 41, 42, 51, 52, 61, 62, 71-73 Transistor 20, 20 'Decoder 30 Memory control circuit 40, 50, 60 Phase inverter 70 Output unit bMWL, WLRST1, WLRST2, WLDV, MWLRST, MWLRST2, MWLRST3, BNKSEL Control signal I1, I2 Current VPP, VNN, NODE, VSS, VINT, WL Voltage

Claims (2)

A decoder comprising:
A first transistor having a gate and a first end connected to a first control signal and a first voltage, respectively;
A second transistor having a gate and a first end connected to a second control signal and a second end of the first transistor, respectively;
A third transistor having a gate, a first end and a second end connected to a third control signal, a second end of the second transistor and a second voltage, respectively;
A fourth transistor having a gate, a first end and a second end connected to a fourth control signal, a second end of the second transistor and the second voltage, respectively;
A fifth transistor having a gate, a first end and a second end connected to a fifth control signal, a second end of the second transistor and the second voltage, respectively;
Including
The first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are respectively a P-channel field effect transistor, a P-channel field effect transistor, an N-channel field effect transistor, and an N-channel field effect. A transistor and an N-channel field effect transistor,
When the first transistor is turned off and the second transistor is turned off, the voltage of the second control signal is smaller than the voltage of the first control signal.
Decoder. The second end of the second transistor is an output end of the decoder.
The decoder according to claim 1.

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