JP2013093513A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can inhibit deterioration in a first conductivity type transistor in a standby state.SOLUTION: A semiconductor device comprises: a plurality of cascade connected circuits each including a first conductivity type transistor; and a control circuit connected to connection input terminals connected to another circuit among connection input terminals of the respective plurality of circuits, for supplying, in response to activation of a control signal for controlling a voltage to the connection input terminal, a first voltage to the connection input terminal for causing the first conductivity type transistor to be in a non-conductive state in a circuit that receives a voltage from the connection input terminal.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of suppressing deterioration of a transistor.

  In recent years, gate oxide films of MOS transistors have been made thinner in semiconductor devices.

  However, the thinning of the gate oxide film causes NBTI (Negative Bias Temperature Instability) deterioration in a P-channel MOS transistor (hereinafter referred to as “PMOS transistor”).

  As described in Patent Document 1, the NBTI degradation occurs when the ON voltage “L” is continuously applied to the gate of the PMOS transistor. In the PMOS transistor, the threshold voltage varies due to NBTI degradation.

JP 2006-140284 A

  The inventor has clarified the problem that deterioration (for example, NBTI deterioration) proceeds in a standby state in a circuit having a MOS transistor.

  Here, the standby state is a state in which the power supply is on and the input and output of the circuit having the MOS transistor are fixed to either “H” or “L”, respectively.

  Hereinafter, the problem that the deterioration proceeds in the standby state will be described.

  When a circuit having a PMOS transistor enters a standby state, the levels of various nodes in the circuit are fixed to either “H” or “L”.

  Here, when the standby state continues in a state where the level of the node connected to the gate of the PMOS transistor is fixed to “L”, the NBTI deterioration proceeds in the PMOS transistor.

  In order to prevent NBTI degradation in the standby state, the level of the gate of the PMOS transistor may be set to the off voltage “H” in the standby state.

  However, for example, in a circuit in which a plurality of circuits having PMOS transistors are connected in cascade, for example, in a delay circuit in which five inverter circuits having PMOS transistors are connected in cascade, the level of each node between the inverter circuits in the delay circuit is “H” → “L” → “H” → “L”, or “L” → “H” → “L” → “H”.

  Therefore, in this delay circuit, even if the level of the input terminal of the leading inverter circuit is set to “H” in order to prevent NBTI deterioration in the PMOS transistor in the leading inverter circuit, Inverter circuits whose input terminal level is “L” exist, and NBTI degradation proceeds.

  Thus, there has been a problem that the deterioration of the MOS transistor in which the ON state continues in the standby state proceeds.

The semiconductor device of the present invention is
A plurality of cascaded circuits including transistors of a first conductivity type;
Of the input terminals of the plurality of circuits, connected to a connection input terminal connected to the other circuit, and in response to activation of a control signal for controlling the voltage of the connection input terminal, the connection A control circuit for supplying, to the input terminal, a first voltage that makes the first conductivity type transistor in the circuit receiving voltage from the connection input terminal non-conductive;
Is provided.

  In response to the activation of the control signal, the control circuit turns off the first conductivity type transistor in the circuit that receives the voltage from the connection input terminal. For this reason, for example, in the standby state, the first voltage is supplied to the input terminal of the first circuit among the plurality of cascade-connected circuits and the control signal is activated to The first conductivity type transistors included in each of the circuits can be turned off.

  According to the present invention, it is possible to turn off the first conductivity type transistors included in each of the plurality of circuits in the standby state. Deterioration can be suppressed.

1 is a block diagram illustrating a semiconductor device 100 according to an embodiment of the present invention. 1 is a circuit diagram showing a first embodiment of a deterioration prevention circuit. FIG. 3 is a timing chart for explaining the operation of the deterioration prevention circuit 1; It is the circuit diagram which showed 2nd Embodiment of the deterioration prevention circuit. It is a timing chart for demonstrating operation | movement of the deterioration prevention circuit 1Y.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a semiconductor device 100 according to an embodiment of the present invention. In the present embodiment, a DRAM is used as the semiconductor device 100.

  Semiconductor device 100 includes clock terminals 11a and 11b, a plurality of command terminals 12, a plurality of address terminals 13, a plurality of data input / output terminals 14, and power supply terminals 15a and 15b as external terminals.

  Further, the semiconductor device 100 includes a clock input circuit 21, a fuse (FUSE) 22, a timing generator 23, a DLL circuit 24, a deterioration prevention circuit 25, a command input circuit 31, a command decode circuit 32, and refresh control. Circuit 33, address input circuit 41, address latch circuit 42, mode register 43, deterioration prevention circuit 44, memory cell array 50, row decoder 51, column decoder 52, FIFO circuit 53, and input / output circuit 54 and an internal power generation circuit 61.

  The clock terminal 11a receives an external clock signal CK. Clock terminal 11b receives external clock signal / CK. The external clock signal CK received by the clock terminal 11 a and the external clock signal / CK received by the clock terminal 11 b are supplied to the clock input circuit 21.

  In the present specification, a signal having “/” at the beginning of a signal name means an inverted signal of the corresponding signal or a low active signal. Therefore, external clock signal CK and external clock signal / CK are complementary signals.

  Clock input circuit 21 receives external clock signals CK and / CK and generates internal clock signal ICLK using external clock signals CK and / CK. The clock input circuit 21 supplies the internal clock signal ICLK to the timing generator 23 and the DLL circuit 24.

  The timing generator 23 receives the internal clock signal ICLK and generates a timing signal for specifying various operation timings of the semiconductor device 100 using the internal clock signal ICLK.

  The fuse (FUSE) 22 is set with phase adjustment information indicating the amount of adjustment of the phase of the internal clock signal ICLK. The phase adjustment information is supplied to the DLL circuit 24.

  The DLL circuit 24 generates the input / output clock signal LCLK by shifting the phase of the internal clock signal ICLK by the adjustment amount represented by the phase adjustment information. The DLL circuit 24 outputs the input / output clock signal LCLK to the deterioration prevention circuit 25.

  The deterioration prevention circuit 25 is a circuit that receives the input / output clock signal LCLK and has a function of suppressing NBTI deterioration in the deterioration prevention circuit 25. In the present embodiment, the deterioration prevention circuit 25 has a function of a buffer circuit. The output of the deterioration prevention circuit 25, that is, the input / output clock signal LCLK is supplied to the FIFO circuit 53 and the input / output circuit 54. The FIFO circuit 53 and the input / output circuit 54 will be described later.

  The command terminal 12 receives a command signal. The command signals are, for example, a row address strobe signal / RAS, a column address strobe signal / CAS, and a reset signal / RESET.

  The command input circuit 31 receives a command signal from the command terminal 12 and supplies the command signal to the command decoding circuit 32.

  The command decode circuit 32 receives a command signal. The command decode circuit 32 generates an internal command signal by holding the command signal, decoding the command signal, counting the command signal, and the like. The command decode circuit 32 generates, for example, a refresh command, a write command, a read command, and a STATE (state) signal as internal command signals. The STATE signal is an example of a control signal.

  The refresh control circuit 33 receives a refresh command from the command decode circuit 32. The refresh control circuit 33 supplies a refresh signal to the row decoder 51 when receiving a refresh command.

  The address terminal 13 receives an address signal.

  The address input circuit 41 receives an address signal from the address terminal 13 and supplies the address signal to the address latch circuit 42.

  The address latch circuit 42 receives an address signal from the address input circuit 41. The address latch circuit 42 supplies an address signal to the mode register 43 when setting the mode register 43. The address latch circuit 42 supplies the row address of the address signal to the row decoder 51 and supplies the column address of the address signal to the deterioration prevention circuit 44.

  The mode register 43 is a register in which operation parameters (for example, burst length or CAS latency) of the semiconductor device 100 are set. The mode register 43 receives the internal command signal from the command decode circuit 32 and the address signal from the address latch circuit 42, and sets an operation parameter specified based on the internal command signal and the address signal.

  The deterioration prevention circuit 44 receives the column address from the address latch circuit 42 and adjusts the output timing of the column address, thereby adjusting the difference in output timing between the column address and the internal command signal. The deterioration prevention circuit 44 outputs the column address adjusted for the difference in output timing to the column decoder 52. Further, the deterioration prevention circuit 44 has a function of suppressing the NBTI deterioration in the deterioration prevention circuit 44.

  Memory cell array 50 includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC. Each memory cell MC is specified by a word line WL and a bit line BL.

  The row decoder 51 receives a row address from the address latch circuit 42 and a write command or a read command from the command decode circuit 32. In addition, the row decoder 51 receives a refresh signal from the refresh control circuit 33.

  When the row decoder 51 receives a write command or a read command, the row decoder 51 selects a word line WL corresponding to the address signal from the plurality of word lines WL in the memory cell array 50.

  In the memory cell array 50, a plurality of word lines WL and a plurality of bit lines BL intersect, and memory cells MC are arranged at the intersections. In FIG. 1, only one word line WL, one bit line BL, and one memory cell MC are shown for simplicity of explanation. Each bit line BL is connected to a sense amplifier (not shown) corresponding to its own bit line BL.

  When the row decoder 51 receives the refresh signal, the row decoder 51 selects the word line WL corresponding to the row address from the plurality of word lines WL, and refreshes the memory cell MC corresponding to the selected word line WL. Perform a refresh.

  The column decoder 52 receives the column address from the deterioration prevention circuit 44 and the write command or read command from the command decode circuit 32.

  When the column decoder 52 receives the column address and the write command or the read command, the column decoder 52 selects a sense amplifier corresponding to the column address from the plurality of sense amplifiers.

  During a read operation (when a read command is generated), a memory cell that exists at the intersection of the bit line BL connected to the sense amplifier selected by the column decoder 52 and the word line WL selected by the row decoder 51 Data (read data) in the MC (hereinafter referred to as “selected memory cell”) is amplified by the sense amplifier selected by the column decoder 52, supplied to the FIFO circuit 53, and then supplied to the input / output circuit 54. Is done. On the other hand, at the time of a write operation (when a write command is generated), the sense amplifier selected by the column decoder 52 writes the write data from the FIFO circuit 53 to the selected memory cell.

  The FIFO circuit 53 receives the input / output clock signal LCLK from the deterioration prevention circuit 25, and exchanges read data and write data between the memory cell array 50 and the input / output circuit 54 in synchronization with the input / output clock signal LCLK. I do.

  The data input / output terminal 14 performs output of read data and input of write data. The data input / output terminal 14 is connected to the input / output circuit 54.

  The input / output circuit 54 receives the input / output clock signal LCLK from the deterioration prevention circuit 25 and outputs read data to the data input / output terminal 14 in synchronization with the input / output clock signal LCLK during a read operation.

  The power supply terminal 15a receives the voltage VDD on the high potential side of the power supply voltage. The power supply terminal 15b receives the voltage VSS on the low potential side of the power supply voltage.

  The internal power supply generation circuit 61 receives the voltage VDD from the power supply terminal 15a, receives the voltage VSS from the power supply terminal 15b, and generates internal power supply voltages such as the voltage VPP, the voltage VRERD, and the voltage VPERI.

  In the semiconductor device 100 shown in FIG. 1, a standby state exists.

  In this embodiment, the standby state may be a so-called active standby state from when an active command (row selection) to a read / write command (column selection) is input, or an idle state where no command is input. A state where a specific circuit such as a state or a self-refresh state is in a standby state.

  In the semiconductor device 100 shown in FIG. 1, a deterioration preventing circuit 25 having a function of a buffer circuit for the input / output clock signal LCLK, which is in a standby state in the standby state, an internal command signal and an address signal (row address or column address). The deterioration prevention circuit 44 having the function of a delay circuit for adjusting the difference in output timing with respect to () is exemplified as an example of a circuit having a function for preventing NBTI deterioration in the standby state.

  The NBTI degradation in these circuits greatly affects the control of the semiconductor device 100.

  For example, when the NBTI deterioration occurs in the buffer circuit portion for the input / output clock signal LCLK, that is, the deterioration prevention circuit 25, the operation of the first conductivity type transistor (here, “PMOS transistor”) in the buffer circuit is slow. The second conductivity type transistor (here, “NMOS transistor”) in the buffer circuit operates relatively quickly. For this reason, the duty of the input / output clock signal LCLK is deviated from 50:50, causing a problem in data output in the input / output circuit 54.

  Further, when NBTI deterioration occurs in the delay circuit for adjusting the difference in output timing between the internal command signal and the address signal, that is, the deterioration preventing circuit 44, the output timing between the internal command signal and the address signal is changed. There is a possibility that the difference amount becomes large and the logic cannot be accurately obtained between the internal command signal and the address signal.

  FIG. 2 is a circuit diagram showing a first embodiment of a deterioration preventing circuit that can be used as the deterioration preventing circuit 25 and the deterioration preventing circuit 44.

  In FIG. 2, the deterioration prevention circuit 1 includes a control target circuit 1a and a control circuit 1b.

  The control target circuit 1a includes three inverter circuits 1a1 to 1a3 connected in cascade. The three inverter circuits 1a1 to 1a3 are an example of a plurality of circuits connected in cascade.

  Inverter circuit 1a1 includes a PMOS transistor 1a11 and an NMOS transistor 1a12. The PMOS transistor is an example of a first conductivity type transistor, and the NMOS transistor is an example of a second conductivity type transistor.

  The gate of the PMOS transistor 1a11 and the gate of the NMOS transistor 1a12 are connected to the terminal 1a13. The terminal 1a13 is an input terminal of the control target circuit 1a and an input terminal of the inverter circuit 1a1.

  Inverter circuit 1a2 includes a PMOS transistor 1a21 and an NMOS transistor 1a22. The gate of the PMOS transistor 1a21 and the gate of the NMOS transistor 1a22 are connected to the terminal 1a23. The terminal 1a23 is an input terminal of the inverter circuit 1a2, and is an example of a connection input terminal.

  Inverter circuit 1a3 includes a PMOS transistor 1a31 and an NMOS transistor 1a32. The gate of the PMOS transistor 1a31 and the gate of the NMOS transistor 1a32 are connected to the terminal 1a33. The terminal 1a33 is an input terminal of the inverter circuit 1a3 and is an example of a connection input terminal.

  The control circuit 1b includes an NMOS transistor (source transistor) m0 and PMOS transistors m1 to m3.

  The NMOS transistor m0 is an example of a current control transistor.

  The gate of the NMOS transistor m0 and the gates of the PMOS transistors m1 to m3 are connected to each other and supplied with a STATE signal.

  The sources of the PMOS transistors 1a11, 1a21, 1a31, m1, m2, and m3 are connected to the high potential side of the power supply voltage or the high potential side of the internal power supply voltage.

  The sources of the NMOS transistors 1a12, 1a22, and 1a32 are connected to the drain of the NMOS transistor m0.

  The source of the NMOS transistor m0 is connected to the low potential side of the power supply voltage or the low potential side of the internal power supply voltage.

  The drain of the PMOS transistor 1a11, the drain of the PMOS transistor m1, the drain of the NMOS transistor 1a12, and the terminal 1a23 are connected to each other by a wiring L1.

  The drain of the PMOS transistor 1a21, the drain of the PMOS transistor m2, the drain of the NMOS transistor 1a22, and the terminal 1a33 are connected to each other by a wiring L2.

  The drain of the PMOS transistor 1a31, the drain of the PMOS transistor m3, and the drain of the NMOS transistor 1a32 are connected to each other and function as an output terminal of the control target circuit 1a.

  In the present embodiment, as each transistor in the control target circuit 1a, a MOS transistor in which the threshold voltage (Vt) of the MOS transistor is set lower than the standard (hereinafter referred to as “low Vt (LV) MOS transistor”). Used.

  Specifically, low Vt (LV) PMOS transistors are used as the PMOS transistors 1a11, 1a21, and 1a31, respectively, and low Vt (LV) NMOS transistors are used as the NMOS transistors 1a12, 1a22, and 1a32, respectively.

  In this embodiment, a normal VtNMOS transistor in which the threshold voltage (Vt) of the MOS transistor is set as a standard is used as the NMOS transistor m0.

  In the present embodiment, as the PMOS transistors m1 to m3, normal VtPMOS transistors in which the threshold voltage (Vt) of the MOS transistor is set as a standard are used.

  As described above, in the semiconductor device 100 according to the present embodiment, the plurality of circuits 1a1 to 1a3 including the first conductivity type transistors 1a11, 1a21, and 1a31 and connected in cascade, and the input terminals of the plurality of circuits 1a1 to 1a3, respectively. 1a13, 1a23 and 1a33 are connected to connection input terminals 1a23 and 1a33 connected to other circuit 1a1 or 1a2, and a control signal (STATE signal) for controlling the voltage of connection input terminals 1a23 and 1a33 is activated. Accordingly, the first conductivity type transistor 1a21 in the circuit 1a3 in the circuit 1a3 and the first conductivity type transistor 1a31 in the circuit 1a3 in the circuit 1a2 that receives the voltage from the connection input terminal 1a23 are connected to the connection input terminals 1a23 and 1a33, respectively. First voltage ("H") to turn off And a control circuit 1b supplies.

  In the semiconductor device 100 according to the present embodiment, the first conductivity type transistors 1a11, 1a21, and 1a31 are PMOS transistors.

  In the semiconductor device 100 according to the present embodiment, each of the plurality of circuits 1a1 to 1a3 is an inverter circuit, and each of the inverter circuits 1a1 to 1a3 includes a first conductivity type transistor 1a11, 1a21, or 1a31. Second conductivity type transistor 1a12, 1a22 or 1a32, the first conductivity type transistor and the second conductivity type transistor are connected to each other with the gates connected to each other and the drains connected directly or indirectly to each other. Yes.

  In the semiconductor device 100 according to the present embodiment, the current flowing through the second conductivity type transistors 1a12, 1a22, and 1a32 is suppressed according to the activation of the control signal (STATE signal).

  In the semiconductor device 100 according to the present embodiment, the control circuit 1b includes the current control transistor m0 connected to the respective sources of the second conductivity type transistors 1a12, 1a22, and 1a32. In response to activation of the control signal (STATE signal), the non-conduction state is established.

  Next, the operation of the deterioration preventing circuit 1 will be described.

  FIG. 3 is a timing chart for explaining the operation of the deterioration preventing circuit 1.

  The command decode circuit 32 sets the level of the STATE signal to “H” (inactive state) when outputting an internal command signal indicating a non-standby state such as a read command (READ).

  When the level of the STATE signal is “H”, the NMOS transistor m0 is turned on, and the PMOS transistors m1 to m3 are turned off. For this reason, when the level of the STATE signal is “H”, the control target circuit 1a operates as a circuit in which three inverter circuits are connected in series.

  In the example shown in FIG. 3, when the input / output clock signal LCLK1 is input to the input terminal 1a13 of the inverter circuit 1a1 under the situation where the level of the STATE signal is “H”, the input / output clock signal LCLK1 is Inverted and delayed at 1a1, 1a2, and 1a3, respectively.

  In FIG. 3, the output signal from the inverter circuit 1a1 is shown as an input / output clock signal LCLK2, the output signal from the inverter circuit 1a2 is shown as an input / output clock signal LCLK3, and the output signal from the inverter circuit 1a3 is shown as an input / output clock. This is shown as signal LCLK4. The input / output clock signal LCLK4 is used as an output signal of the control target circuit 1a.

  Further, the command decode circuit 32 sets the level of the STATE signal to “L” (active state) when outputting an internal command signal such as the self-refresh command SREF or the power-down signal PWDN that switches to the standby state.

  When the level of the STATE signal is “L”, the PMOS transistors m1 to m3 are turned on, and the NMOS transistor m0 is turned off. In the present embodiment, when the level of the STATE signal is “L”, “H” is applied to the input terminal of the control target circuit 1a, that is, the input terminal 1a13 of the inverter circuit 1a1.

  Therefore, when the level of the STATE signal is “L” and “H” is applied to the input terminal 1a13, “H” (first voltage) is supplied to the input terminals 1a13, 1a23, and 1a33 (FIG. 3 arrow A1). Therefore, the PMOS transistors 1a11, 1a21 and 1a31 are turned off, and the NBTI deterioration in the PMOS transistors 1a11, 1a21 and 1a31 in the standby state can be prevented.

  When the level of the STATE signal is “L” and “H” is applied to the input terminal 1a13, the NMOS transistors 1a12, 1a22, and 1a32 are turned on, but the NMOS transistor m0 is turned off. It is possible to suppress a through current from flowing through the transistors 1a12, 1a22, and 1a32, and to reduce current consumption in the standby state.

  In this embodiment, in order to suppress the current flowing through the NMOS transistors 1a12, 1a22 and 1a32 during the standby state, the threshold voltage (Vt) of the MOS transistor is not the low Vt (LV) NMOS transistor as the NMOS transistor m0. A normal VtNMOS transistor set to standard is used.

  Further, the command decode circuit 32 sets the level of the STATE signal to “H” (inactive state) when outputting the EXIT signal (internal command signal) for ending the self-refresh operation or the power-down operation. Therefore, the NMOS transistor m0 is turned on, the PMOS transistors m1 to m3 are turned off, and the control target circuit 1a operates as a circuit in which three inverter circuits are connected in series (see arrow A2 in FIG. 3).

  Next, the effect of this embodiment will be described.

  The control circuit 1b is connected to connection input terminals 1a23 and 1a33 connected to other inverter circuits among the input terminals 1a13, 1a23 and 1a33 of the plurality of inverter circuits 1a1, 1a2 and 1a3, and connected to the connection input terminal 1a23. In response to activation of a control signal (STATE signal) for controlling the voltage of 1a33 and 1a33, a first voltage that makes the first conductivity type transistors 1a21 and 1a31 non-conductive at connection input terminals 1a23 and 1a33 Supply.

  For this reason, for example, in the standby state, the first voltage is supplied to the input terminal 1a13 of the first inverter circuit 1a1 among the plurality of inverter circuits 1a1 to 1a3 connected in cascade, and the control signal is activated. Thus, in the standby state, the first conductivity type transistors 1a11, 1a21, and 1a31 included in each of the plurality of inverter circuits 1a1, 1a2, and 1a3 can be turned off. Therefore, it is possible to suppress deterioration in the first conductivity type transistors 1a11, 1a21, and 1a31 in the standby state.

  In the present embodiment, a PMOS transistor is used as the first conductivity type transistor.

  For this reason, it becomes possible to suppress NBTI deterioration in the PMOS transistor in the standby state.

  In this embodiment, each inverter circuit includes a first conductivity type transistor and a second conductivity type transistor, and the gates of the first conductivity type transistor and the second conductivity type transistor are connected to each other, The drains of the conductivity type transistor and the second conductivity type transistor are directly connected to each other.

  For this reason, it is possible to suppress deterioration in the first conductivity type transistor in the inverter circuit in the standby state.

  In the present embodiment, the control circuit 1b suppresses the current flowing through the second conductivity type transistor in response to the activation of the control signal.

  For this reason, when the first conductivity type transistor is in a non-conducting state, the current flowing through the second conductivity type transistor can be suppressed, and current consumption can be reduced.

  In the present embodiment, the control circuit 1b includes a current control transistor m0 connected to each source of the second conductivity type transistor, and the current control transistor m0 is non-conductive in response to activation of the control signal. It becomes a state.

  For this reason, the current flowing through the second conductivity type transistor in each inverter circuit can be suppressed by making one current control transistor m0 nonconductive. Therefore, the structure for suppressing the current flowing through the second conductivity type transistor can be reduced, and the semiconductor device 100 can be downsized.

  In the present embodiment, a normal VtNMOS transistor is used as the current control transistor m0 instead of a low Vt (LV) MOS transistor.

  For this reason, in the situation where the voltage VSS is used as the voltage for making the current control transistor m0 non-conductive, the leakage current generated in the current control transistor m0 is reduced to a low Vt (LV) as the current control transistor m0. It is possible to reduce the leakage current that occurs when a MOS transistor is used.

  FIG. 4 is a circuit diagram showing a second embodiment of the deterioration preventing circuit. In FIG. 4, the same components as those shown in FIG.

  In FIG. 4, the deterioration prevention circuit 1Y includes a control target circuit 1aY and a control circuit 1bY.

  Control target circuit 1aY includes PMOS transistors 1a11, 1a21 and 1a31, and NMOS transistors 1a12, 1a22 and 1a32.

  The PMOS transistor 1a11 and the NMOS transistor 1a12 constitute an inverter 1a1, the PMOS transistor 1a21 and the NMOS transistor 1a22 constitute an inverter 1a2, and the PMOS transistor 1a31 and the NMOS transistor 1a32 constitute an inverter 1a3.

  The control circuit 1bY includes NMOS transistors (source transistors) m0Y to m2Y and NMOS transistors m3Y to m5Y.

  In the present embodiment, low Vt (LV) NMOS transistors are used as the NMOS transistors m0Y to m5Y.

  The NMOS transistors m0Y to m2Y are examples of current control transistors. A STATE_A signal is supplied to each gate of the NMOS transistors m0Y to m2Y. The STATE_A signal is an example of a control signal.

  The NMOS transistor m0Y is provided between the drain of the PMOS transistor 1a11 and the drain of the NMOS transistor 1a12.

  The NMOS transistor m1Y is provided between the drain of the PMOS transistor 1a21 and the drain of the NMOS transistor 1a22.

  The NMOS transistor m2Y is provided between the drain of the PMOS transistor 1a31 and the drain of the NMOS transistor 1a32.

  The NMOS transistors m3Y to m4Y are examples of voltage supply transistors.

  A STATE_B signal is supplied to each gate of the NMOS transistors m3Y to m5Y. The STATE_B signal is an inverted signal of the STATE_A signal. The STATE_A signal and the STATE_B signal are supplied from the command decode circuit 32.

  The sources of the NMOS transistors m3Y, m4Y and m5Y are connected to the high potential side of the power supply voltage or the high potential side of the internal power supply voltage. The drains of the NMOS transistors m3Y, m4Y, and m5Y are connected to terminals N1, N2, and N3, respectively.

  As described above, in the semiconductor device 100 according to the present embodiment, the control circuit 1bY includes the drain of the first conductivity type transistor 1a11, 1a21, or 1a31 in the inverter circuit and the second conductivity type for each of the inverter circuits 1a1, 1a2, and 1a3. Including a plurality of current control transistors m0Y to m2Y provided between the drains of the transistors 1a12, 1a22, and 1a32, and each of the plurality of current control transistors m0Y to m2Y is an activation of a control signal (STATE_A signal). It becomes a non-conducting state according to conversion.

  In the semiconductor device 100 according to the present embodiment, the control circuit 1bY is connected to the connection input terminal 1a23 or 1a33, and the first voltage is applied to the connection input terminal 1a23 or 1a33 in response to the activation of the control signal (STATE_A signal). Voltage supply transistors m3Y and m4Y for supplying ("H"), the first conductivity type transistor is a PMOS transistor, the second conductivity type transistor, the voltage supply transistor, and the plurality of current control transistors are , An NMOS transistor.

  Next, the operation of the deterioration preventing circuit 1Y will be described.

  FIG. 5 is a timing chart for explaining the operation of the deterioration preventing circuit 1Y.

  When the command decode circuit 32 outputs an internal command signal indicating a non-standby state such as a read command (READ), the command decode circuit 32 sets the level of the STATE_A signal to “H” (inactive state) and uses an inverted signal of the STATE_A signal. The level of a certain STATE_B signal is set to “L”.

  When the level of the STATE_A signal is “H”, the NMOS transistors m0Y to m2Y are turned on. When the level of the STATE_A signal is “H”, the level of the STATE_B signal is “L”, so that the NMOS transistors m3Y to m5Y Turns off.

  Therefore, when the STATE_A signal is “H”, the control target circuit 1aY operates as a circuit in which three inverter circuits are connected in series.

  In the example shown in FIG. 5, when the input / output clock signal LCLK5 is input to the input terminal 1a13 in a situation where the level of the STATE_A signal is “H” and the level of the STATE_B signal is “L”, the input / output clock signal is input. Signal LCLK5 is inverted and delayed by inverter circuits 1a1, 1a2, and 1a3, respectively.

  In FIG. 5, the output signal from the inverter circuit 1a1 is shown as an input / output clock signal LCLK6, the output signal from the inverter circuit 1a2 is shown as an input / output clock signal LCLK7, and the output signal from the inverter circuit 1a3 is shown as an input / output clock. This is shown as signal LCLK8. The input / output clock signal LCLK8 is used as an output signal of the control target circuit 1aY.

  When the command decode circuit 32 outputs an internal command signal that switches to the standby state, such as the self-refresh command SREF or the power-down signal PWDN, the level of the STATE_A signal is set to “L” (active state), and the STATE_B signal Set the level to “H”.

  When the level of the STATE_A signal is “L” and the level of the STATE_B signal is “H”, the NMOS transistors m3Y to m5Y are turned on and the NMOS transistors m0Y to m2Y are turned off. In the present embodiment, when the level of the STATE_A signal is “L”, “H” is applied to the input terminal of the control target circuit 1aY, that is, the input terminal 1a13 of the inverter circuit 1a1.

  For this reason, when the level of the STATE_A signal is “L”, the level of the STATE_B signal is “H”, and “H” is applied to the force terminal 1a13, the input terminals 1a13, 1a23, and 1a33 have “H” ( (First voltage) is supplied (see arrow B1 in FIG. 5). Therefore, the PMOS transistors 1a11, 1a21 and 1a31 are turned off, and the NBTI deterioration in the PMOS transistors 1a11, 1a21 and 1a31 in the standby state can be prevented.

  When the level of the STATE_A signal is “L” and the level of the STATE_B signal is “H” and “H” is applied to the input terminal 1a13, the NMOS transistors 1a12, 1a22, and 1a32 are turned on. At this time, since the NMOS transistors m0Y to m2Y are in the off state, it is possible to suppress the through current from flowing through the NMOS transistors 1a12, 1a22, and 1a32, and it is possible to reduce current consumption in the standby state.

  In the deterioration prevention circuit 1Y shown in FIG. 4, low Vt (LV) NMOS transistors are used as the NMOS transistors (source transistors) m0Y to m2Y.

  Therefore, in the present embodiment, as shown in FIG. 5, the negative level voltage VKK (VKK <VSS) is used as the low (“L”) side voltage of the STATE_A signal. Therefore, the leakage current in the NMOS transistors m0Y to m2Y can be suppressed. The negative level voltage VKK is generated by the internal power supply generation circuit 61. In addition, Vds (source-drain voltage) of the second conductivity type transistors (NMOS transistors 1a12 to 1a32) connected in series to any of the NMOS transistors m0Y to m2Y are also suppressed by the NMOS transistors m0Y to m2Y. Therefore, the current consumption in the standby state can be suppressed as a whole.

  In the deterioration preventing circuit 1Y shown in FIG. 4, the first conductivity type transistors (PMOS transistors m1 to m3) used in the control circuit 1b shown in FIG. 2 are replaced with the second conductivity type transistors (NMOS). Transistors m3Y to m5Y). Therefore, when the level of the STATE_A signal is “L”, that is, when the level of the STATE_B signal is “H”, the levels of the terminals N1, N2, and N3 are VDD−Vt (where Vt is NMOS) In this case, the NBTI deterioration can be sufficiently prevented.

  In the deterioration prevention circuit 1Y shown in FIG. 4, the control circuit 1bY includes a drain of the first conductivity type transistor 1a11, 1a21 or 1a31 in the inverter circuit and a second conductivity type transistor for each of the inverter circuits 1a1, 1a2, and 1a3. Including a plurality of current control transistors m0Y to m2Y provided between the drains of 1a12, 1a22, and 1a32. Each of the plurality of current control transistors m0Y to m2Y is used to activate a control signal (STATE_A signal). Accordingly, a non-conduction state is established.

  For this reason, when the first conductivity type transistor is in a non-conducting state, the current flowing through the second conductivity type transistor can be suppressed, and current consumption can be reduced.

  Further, in the deterioration preventing circuit 1Y shown in FIG. 4, the control circuit 1bY is connected to the connection input terminal 1a23 or 1a33, and the first connection is made to the connection input terminal 1a23 or 1a33 in response to the activation of the control signal (STATE_A signal). The first conductivity type transistor is a PMOS transistor, the second conductivity type transistor, the voltage supply transistor, and a plurality of current control transistors are included. The transistor is an NMOS transistor.

  For this reason, all the transistors in the deterioration preventing circuit 1Y can be made to be low Vt (LV) MOS transistors.

  In each of the above embodiments, the number of cascade-connected inverter circuits is 3, but the number of cascade-connected inverter circuits may be an integer of 2 or more.

  In each of the above embodiments, a plurality of inverter circuits are used as the plurality of cascade-connected circuits. However, the plurality of cascade-connected circuits is not limited to the plurality of inverter circuits, and each of them is a first conductivity type. A plurality of circuits including these transistors may be used.

  In each of the above embodiments, a PMOS transistor is used as the first conductivity type transistor, but an NMOS transistor may be used as the first conductivity type transistor. In this case, the first voltage supplied from the control circuit to the connection input terminal is “L”. In this case, it becomes possible to suppress the PBTI deterioration in the NMOS transistor. In this case, the second conductivity type transistor is a PMOS transistor.

  In each of the above embodiments, the semiconductor device 100 is not limited to the DRAM and can be changed as appropriate.

  In each embodiment described above, the illustrated configuration is merely an example, and the present invention is not limited to the configuration.

DESCRIPTION OF SYMBOLS 100 Semiconductor device 11a, 11b Clock terminal 12 Command terminal 13 Address terminal 14 Data input / output terminal 15a, 15b Power supply terminal 21 Clock input circuit 22 FUSE
23 Timing Generator 24 DLL Circuit 25 Degradation Prevention Circuit 31 Command Input Circuit 32 Command Decode Circuit 33 Refresh Control Circuit 41 Address Input Circuit 42 Address Latch Circuit 43 Mode Register 44 Degradation Prevention Circuit 50 Memory Cell Array 51 Row Decoder 52 Column Decoder 53 FIFO Circuit 54 Input / output circuit 61 Internal power generation circuit BL Bit line WL Word line MC Memory cell 1, 1Y Deterioration prevention circuit 1a, 1aY Control target circuit 1a1-1a3 Inverter circuit 1a11, 1a21, 1a31, m1-m3 PMOS transistors 1a12, 1a22, 1a32 , M0, m0Y to m5Y NMOS transistors

Claims (7)

A plurality of cascaded circuits including transistors of a first conductivity type;
Of the input terminals of the plurality of circuits, connected to a connection input terminal connected to the other circuit, and in response to activation of a control signal for controlling the voltage of the connection input terminal, the connection A control circuit for supplying, to the input terminal, a first voltage that makes the first conductivity type transistor in the circuit receiving voltage from the connection input terminal non-conductive;
A semiconductor device comprising: The semiconductor device according to claim 1,
The semiconductor device, wherein the first conductivity type transistor is a P-channel MOS transistor. The semiconductor device according to claim 1 or 2,
Each of the plurality of circuits is an inverter circuit,
The inverter circuit includes a first conductivity type transistor and a second conductivity type transistor, wherein the first conductivity type transistor and the second conductivity type transistor have gates connected to each other and drains to each other. A semiconductor device connected directly or indirectly. The semiconductor device according to claim 3.
The control circuit is a semiconductor device that suppresses a current flowing through the second conductivity type transistor in response to activation of the control signal. The semiconductor device according to claim 4,
The control circuit includes a current control transistor connected to each source of the second conductivity type transistor;
The semiconductor device, wherein the current control transistor is turned off in response to activation of the control signal. The semiconductor device according to claim 4,
The control circuit includes, for each inverter circuit, a plurality of current control transistors provided between a drain of the first conductivity type transistor and a drain of the second conductivity type transistor in the inverter circuit. ,
Each of the plurality of current control transistors is in a non-conductive state in response to the activation of the control signal. The semiconductor device according to claim 6.
The control circuit includes:
A voltage supply transistor connected to the connection input terminal and supplying the first voltage to the connection input terminal in response to activation of the control signal;
The first conductivity type transistor is a P-channel MOS transistor,
The semiconductor device, wherein the second conductivity type transistor, the voltage supply transistor, and the plurality of current control transistors are N-channel MOS transistors.

Images