JP5515270B2 - Heat treatment method and heat treatment apparatus for silicon wafer, and silicon wafer - Google Patents

Description

  The present invention relates to a heat treatment method and a heat treatment apparatus for a silicon wafer, and more particularly to a heat treatment method and a heat treatment apparatus for a silicon wafer capable of suppressing deformation and strength reduction of the silicon wafer. The present invention also relates to a silicon wafer subjected to such heat treatment.

  A silicon wafer used for manufacturing an IC device is manufactured by slicing a silicon single crystal ingot pulled up by the Czochralski method (CZ method) or the like, and performing mirror processing or the like.

  However, immediately after being pulled up by the CZ method (as-grown), the silicon single crystal contains crystal growth introduction defects (grown-in defects), and if such defects exist on the surface layer of the silicon wafer, the IC device May not work properly. One of the grown-in defects is COP (Crystal Originated Particle). COP is a regular octahedron cavity defect, which deteriorates oxide film breakdown voltage characteristics and device characteristics. Therefore, it is necessary to remove COP at least from the device formation region. In order to remove COP, it is necessary to heat treat (anneal) the silicon wafer under conditions that cause the oxygen concentration to become unsaturated. By performing such high-temperature heat treatment, COP in the range of about 20 μm from the surface of the silicon wafer disappears, so that a defect-free layer can be formed on the surface layer portion of the silicon wafer.

  Such high-temperature heat treatment is performed by loading a boat holding a plurality of silicon wafers into a furnace tube and heating it to a temperature of 1100 ° C. or higher. At this time, since the silicon wafer is supported by the support pins provided on the boat, the back surface of the silicon wafer is slightly damaged at the contact portion with the support pins, and scratches are generated. Since the scratches generated in this manner reduce the strength of the silicon wafer, it is desirable to perform the heat treatment under conditions where the scratches are as small as possible.

  In addition, dislocation clusters are generated in the part where the scratch is generated. The dislocation clusters themselves on the back surface of the silicon wafer are not actually harmful, but when a strong thermal stress is applied to the dislocation clusters by the heat treatment, the dislocation clusters expand and become slip dislocations. Slip dislocation gradually extends during heat treatment.

  In particular, in a large-diameter silicon wafer having a diameter of 300 mm that has been widely used in recent years, the stress due to its own weight is large, so that the extension of slip dislocation is remarkable as compared with a small-diameter silicon wafer. Of course, in a silicon wafer having a larger diameter such as 450 mm in diameter, extension of slip dislocation due to its own weight becomes more remarkable.

  When slip dislocations are formed on the back surface of the silicon wafer in this way, the strength of the silicon wafer is further reduced, or the silicon wafer is warped. Further, slip dislocation also causes a leakage current in the IC device, which causes a problem of reducing the yield of the IC device. For this reason, it is important in the heat treatment process to minimize the scratch that becomes the starting point of slip dislocation.

  In addition, during the device process, a rapid heating / cooling heat treatment (flash lamp annealing (FLA) processing or laser spike annealing (LSA) processing) that applies a very high stress load to the silicon wafer may be introduced. In other words, if the LSI design rule is reduced, the conditions required for forming the ultra-shallow junction in the CMOS diffusion region become more severe, and therefore it is required to perform annealing at a higher temperature and in a shorter time. For this reason, unlike the conventional rapid thermal annealing (RTA), an annealing time of several seconds is not allowed, and FLA and LSA having a shorter heating time are frequently used. Annealing with a short heating time also increases the stress load on the silicon wafer, so if there is a flaw in the silicon wafer, there is a high possibility that the flaw will start during processing and the silicon wafer will break. That is, scratches that did not cause a problem in annealing by resistance heating or RTA cause a serious problem in a silicon wafer subjected to FLA or LSA. For these reasons, in recent years when FLA and LSA are performed, it is particularly desirable to produce a silicon wafer with few scratches.

  A major cause of scratches caused by heat treatment is that the silicon wafer is deformed by a temperature difference that occurs in the plane of the silicon wafer or in the vertical direction (thickness direction). When the silicon wafer is deformed, the support pins provided on the boat and the silicon wafer are rubbed with each other, and physical damage caused thereby causes scratches on the silicon wafer.

As methods for suppressing the occurrence of scratches due to heat treatment, methods described in Patent Documents 1 and 2 are known. Patent Document 1 describes a method in which a heater is divided into zones and thereby the temperature gradient is controlled. Patent Document 2 describes that an elastic body having a hollow portion is used as a support portion of a boat.
JP 2006-100303 A No. 2004-001835

  However, the method described in Patent Document 1 has a problem that the structure and control of the heater are complicated. Further, the method described in Patent Document 2 has a problem that a special boat must be used.

  Accordingly, an object of the present invention is to provide a heat treatment method and a heat treatment apparatus capable of suppressing generation of scratches on a silicon wafer without using a complicated heater or a special boat.

  Another object of the present invention is to provide a silicon wafer in which a decrease in strength is suppressed by performing such heat treatment.

  The silicon wafer heat treatment method according to the present invention includes an annealing process in which a boat holding a silicon wafer is loaded into a furnace core tube, and the silicon wafer is heat-treated at a temperature of 1100 ° C. or more. A temperature lowering process for lowering the temperature of the wafer to 500 ° C. or less; and an unloading process for removing the boat from the core tube after the temperature lowering process. In the unloading process, the boat take-off speed is 45 cm / min or less. It is characterized by doing. In addition, the silicon wafer according to the present invention is characterized by being subjected to such heat treatment.

  In addition, a silicon wafer heat treatment apparatus according to the present invention includes a core tube, a heater for heating the core tube, a load / unload mechanism for loading and unloading a boat capable of holding the silicon wafer into the core tube, and the output of the heater. And a temperature control unit that controls the temperature of the silicon wafer by adjusting the temperature, the temperature control unit heat-treats the silicon wafer at a temperature of 1100 ° C. or higher, then lowers the temperature of the silicon wafer to 500 ° C. or lower, and loads The / unload mechanism is characterized in that after the temperature of the silicon wafer is lowered to 500 ° C. or less, the boat is taken out from the core tube at a speed of 45 cm / min or less.

According to the present invention, the temperature of the silicon wafer is lowered to 500 ° C. or less in the furnace core tube, and the boat take-off speed during unloading is set to 45 cm / min or less. Therefore, the cooling rate of the silicon wafer during unloading is moderate. . As a result, the temperature difference that occurs in the plane of the silicon wafer and in the vertical direction (thickness direction) is reduced, so that deformation of the silicon wafer is suppressed, and physical damage due to the support pins provided on the boat is reduced. Therefore, it is possible to suppress damage to the silicon wafer caused by the heat treatment without using a complicated heater or a special boat. Specifically, the maximum size of the scratch at the contact portion with the support pin can be 100 μm or less, and the number of scratches of 10 μm or more can be 50 or less per 1 mm ² .

  In the present invention, it is preferable that the boat take-off speed is 5 cm / min or more in the unloading step. This is because if the boat take-out speed is less than 5 cm / min, the productivity is reduced to a degree that cannot be ignored. On the other hand, if the boat take-out speed is 5 cm / min or more, the productivity is not significantly reduced.

  In the present invention, it is preferable to lower the temperature of the silicon wafer at a temperature lowering rate of 8 ° C./min or less in a temperature range where the temperature of the silicon wafer decreases from 900 ° C. to 500 ° C. According to this, since the temperature difference generated in the silicon wafer becomes smaller, it becomes possible to more effectively suppress the scratch on the silicon wafer caused by the heat treatment.

  In this case, it is more preferable to lower the temperature of the silicon wafer at a rate of 2 ° C./min or more in a temperature range where the temperature of the silicon wafer is lowered from 900 ° C. to 500 ° C. This is because if the rate of temperature decrease is less than 2 ° C./min, the productivity is reduced to a degree that cannot be ignored. On the other hand, if the rate of temperature decrease is 2 ° C./min or more, the productivity will not be significantly reduced.

  In the present invention, it is preferable to lower the temperature of the silicon wafer to 490 ° C. or lower in the temperature lowering step. According to this, since the temperature difference generated in the silicon wafer becomes smaller, it becomes possible to more effectively suppress the scratch on the silicon wafer caused by the heat treatment.

  In this case, it is more preferable to lower the temperature of the silicon wafer to 490 ° C. or lower and 200 ° C. or higher in the temperature lowering step. This is because if the temperature is lowered to below 200 ° C., it takes time to reheat the core tube, and the productivity is reduced to a degree that cannot be ignored. On the other hand, if the temperature of the silicon wafer in the temperature lowering process is set to 490 ° C. or lower and 200 ° C. or higher, the productivity is not significantly reduced.

  As described above, according to the present invention, it is possible to suppress the generation of scratches on the silicon wafer without using a complicated heater or a special boat. Therefore, it is possible to provide a silicon wafer with high strength at a low cost.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic diagram showing the structure of a heat treatment apparatus according to a preferred embodiment of the present invention.

  The heat treatment apparatus 10 according to the present embodiment is a so-called vertical furnace, and as shown in FIG. 1, a core tube 11, a heater 12 that heats the core tube 11, and a load that loads and unloads a boat 20 on the core tube 11. / An unload mechanism 13 and a temperature adjustment unit 14 that adjusts the temperature by controlling the heater 12 are provided.

  The core tube 11 has a cylindrical shape whose upper end is closed and whose lower end is opened, and the boat 20 is loaded or unloaded from the opened lower end side. A shutter 11 a is provided on the opened lower end side, and the shutter 11 a is opened when the boat 20 is loaded or unloaded on the core tube 11. Although not particularly limited, quartz or silicon carbide (SIC) is used as the material of the core tube 11.

  The boat 20 is a holding member for holding a plurality of silicon wafers 30 and is inserted into or discharged from the core tube 11 by the load / unload mechanism 13. Although not particularly limited, quartz or silicon carbide (SIC) is also used as the material of the boat 20. The boat 20 is provided with support pins, and the silicon wafer 30 is supported by the support pins.

  The heater 12 is provided over the entire outer periphery of the core tube 11 so that the silicon wafer 30 accommodated in the core tube 11 can be heated evenly. The output of the heater 12 is adjusted by the temperature adjustment unit 14.

Oxygen gas is supplied to the inside of the core tube 11 through the gas introduction port 15, whereby the inside of the core tube 11 is maintained in a predetermined oxygen atmosphere. Further, the oxygen gas inside the core tube 11 is discharged through the gas discharge port 16, whereby the inside of the core tube 11 is maintained at a predetermined pressure. The interior of the core tube 11 is adjusted to an atmosphere in which the oxygen concentration becomes unsaturated. When heat treatment is performed under such conditions, the oxide film (SiO ₂ ) constituting the inner wall of the COP contained in the silicon wafer 30 is dissolved, and interstitial silicon generated by thermal oxidation diffuses into the silicon wafer. Then, the COP is embedded. As a result, COP in the range of about 20 μm from the surface of the silicon wafer disappears, so that a defect-free layer is formed on the surface layer portion of the silicon wafer.

  FIG. 2 is a schematic diagram for explaining a contact position between the silicon wafer 30 and the support pins.

  As shown in FIG. 2, the support pins 21 are in contact at three locations in the vicinity of the outer periphery of the back surface 31 of the silicon wafer 30. For this reason, when deformation occurs in the silicon wafer 30, rubbing occurs between the back surface 31 of the silicon wafer 30 and the support pins 21, and scratches are generated due to physical damage caused thereby. Such a flaw becomes more prominent when the silicon wafer 30 has a large diameter of 300 mm or more because stress due to its own weight is large. The mechanical strength of the silicon wafer 30 decreases as the scratch increases. Further, since a dislocation cluster is generated in the scratched portion, it becomes a starting point of slip dislocation.

  FIG. 3 is a flowchart for explaining a heat treatment method using the heat treatment apparatus 10.

  First, after raising the temperature of the core tube 11 to a predetermined temperature using the heater 12, the shutter 11a is opened, and the boat 20 holding the silicon wafer 30 is loaded onto the core tube 11 (step S1: loading process). The boat 20 is loaded by the load / unload mechanism 13. Although not particularly limited, the temperature of the core tube 11 at the time of loading is preferably about 700 ° C. Oxygen gas is supplied to the core tube 11 loaded with the boat 20 through the gas introduction port 15 to maintain an atmosphere in which the oxygen concentration becomes unsaturated.

  Next, the output of the heater 12 is increased under the control of the temperature adjusting unit 14, and the silicon wafer 30 is heated to a temperature of 1100 ° C. or higher and lower than the melting point of silicon (step S2: temperature raising step). Then, annealing is performed by maintaining this state for about 1 hour (step S3: annealing step). Thereby, the COP existing on the surface layer of the silicon wafer 30 disappears, and a defect-free layer is formed on the surface layer portion of the silicon wafer. The temperature of the silicon wafer 30 during the annealing step is not particularly limited as long as it is 1100 ° C. or higher and lower than the melting point of silicon, but is preferably about 1200 ° C. This is because COP cannot be sufficiently removed at a temperature below 1100 ° C., and the silicon wafer 30 is melted at a temperature exceeding the melting point. If the temperature is set to about 1200 ° C., COP can be removed most efficiently.

  Moreover, about the temperature increase rate in a temperature rising process (step S2), it is preferable to set to 1 degreeC / min or more and 10 degrees C / min or less. This is because if the rate of temperature increase is less than 1 ° C./min, the time required for temperature increase becomes too long, and the productivity decreases to a degree that cannot be ignored, and the rate of temperature increase exceeds 10 ° C./min. This is because the temperature difference that occurs in the surface of the silicon wafer 30 and in the vertical direction (thickness direction) becomes large, and there is a possibility that a large scratch may occur on the back surface 31 of the silicon wafer 30.

  After performing the annealing process (step S3), the output of the heater 12 is lowered by the control of the temperature adjusting unit 14, and the temperature of the silicon wafer 30 is lowered to 500 ° C. or lower (step S4: temperature lowering process). The reason why the temperature of the silicon wafer 30 is lowered to 500 ° C. or less in the core tube 11 is that when the silicon wafer 30 exceeding 500 ° C. is taken out of the core tube 11, the back surface 31 of the silicon wafer 30 is drastically lowered. This is because large scratches are generated.

  More preferably, the temperature of the silicon wafer 30 is lowered to 490 ° C. or lower and 200 ° C. or higher inside the core tube 11. This is because if the silicon wafer 30 is taken out after being lowered to 490 ° C. or less, the temperature drop when taken out from the core tube 11 becomes more gradual, so that the scratches generated on the back surface 31 of the silicon wafer 30 are more effectively suppressed. Because it is done. On the other hand, if the temperature is lowered to less than 200 ° C., it takes time to reheat the core tube 11, and the productivity is reduced to a degree that cannot be ignored. On the other hand, if the temperature of the silicon wafer in the temperature lowering step is 490 ° C. or lower and 200 ° C. or higher, scratches can be effectively suppressed without causing a significant decrease in productivity.

  In the temperature lowering step (step S4), it is preferable to lower the temperature of the silicon wafer 30 at a temperature lowering rate of 10 ° C./min or lower and 2 ° C./min or higher in a temperature range where the temperature of the silicon wafer 30 decreases from 900 ° C. to 500 ° C. It is particularly preferable to lower the temperature at a temperature lowering rate of 2 ° C./min or less. This is because it is necessary to set the rate of temperature decrease to about 1 ° C./min in order to prevent the extension of slip dislocation in the temperature region exceeding 900 ° C., whereas such a problem occurs in the temperature region below 900 ° C. Although the temperature drop rate can be increased because it disappears, if the temperature drop rate exceeds 10 ° C./min, the temperature difference that occurs in the surface and in the vertical direction (thickness direction) of the silicon wafer 30 increases, and the effect of suppressing scratches is increased. It is because there is a possibility that it will fade. On the other hand, if the rate of temperature decrease is less than 2 ° C./min, the time required for temperature decrease becomes too long, and the productivity is lowered to an extent that cannot be ignored. Further, if the boat 20 is taken out from the core tube 11 in a temperature region exceeding 500 ° C., the temperature difference generated in the vertical direction (thickness direction) of the silicon wafer 30 becomes large.

  After the temperature of the silicon wafer 30 is lowered to 500 ° C. or lower in this manner, the boat 20 is taken out from the core tube 11 (step S5: unload process). At this time, the take-out speed of the boat 20 needs to be 45 cm / min or less. This is because, when the boat 20 is taken out at a speed exceeding 45 cm / min, the temperature of the silicon wafer 30 is rapidly lowered during unloading, so that a large scratch is generated on the back surface 31 of the silicon wafer 30. On the other hand, when the boat 20 is taken out at a speed of 45 cm / min or less, the cooling rate of the silicon wafer during unloading becomes moderate. Since the boat 20 moves in the thickness direction of the silicon wafer 30 at the time of unloading, if the boat 20 is taken out at the above speed, the temperature difference generated in the plane of the silicon wafer 30 and in the vertical direction (thickness direction) is reduced. The deformation of the silicon wafer 30 is suppressed, and physical damage due to the support pins 21 provided on the boat 20 is reduced.

  The take-out speed of the boat 20 is preferably 5 cm / min or more. This is because when the boat take-out speed is less than 5 cm / min, the temperature drop of the silicon wafer 30 becomes more gradual, but as a result of the take-out speed being too slow, productivity is reduced to a degree that cannot be ignored. On the other hand, if the boat take-out speed is 5 cm / min or more, the productivity is not significantly reduced.

Thus, according to the present embodiment, the temperature drop rate in the temperature drop process (step S4), the temperature of the silicon wafer at the start of the unload process (step S5), and further, the boat 20 in the unload process (step S5). Since the take-out speed is optimized, the deformation of the silicon wafer is suppressed, and physical damage caused by the support pins 21 provided on the boat 20 is reduced. Thereby, it is possible to effectively suppress the generation of scratches on the silicon wafer 30 without using a complicated heater or a special boat. Specifically, it is possible to set the maximum size of a scratch at the contact portion with the support pin 21 to 100 μm or less and the number of scratches of 10 μm or more to 50 or less per 1 mm ² .

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, these are also included in the present invention.

  For example, in the above embodiment, a so-called vertical furnace is used as the heat treatment apparatus 10, but the present invention is not limited to this, and a horizontal furnace may be used. Even in the horizontal furnace, the boat 20 moves in the thickness direction of the silicon wafer 30 during unloading. Therefore, as in the case of using the vertical furnace, in the plane of the silicon wafer 30 and in the vertical direction (thickness direction). The generated temperature difference can be reduced.

  Moreover, in the said embodiment, although heat processing for removing COP was demonstrated to the example, the heat processing used as the object of this invention is not limited to this, Other heat processing, for example, on the surface of the silicon wafer 30, is demonstrated. It is also possible to apply to heat treatment for forming an epitaxial layer. Further, the heat treatment may be performed on a defect-free wafer that is substantially free of crystal defects such as COP in an as-grown state. Furthermore, the present invention can be applied to heat treatment included in the IC device manufacturing process.

As a silicon wafer for evaluation, a plurality of p ^- silicon wafers having a diameter of 200 mm, an oxygen concentration [Oi] of 12 to 15 × 10 ¹⁷ atoms / cm ³ and a resistivity of 10 Ω · cm were prepared, and the heat treatment apparatus shown in FIG. Heat treatment was performed using an apparatus having a structure similar to that in FIG. The heat treatment was performed according to the flowchart shown in FIG. 3, and the introduced gas was oxygen.

  The heat treatment conditions were common to all silicon wafers for evaluation in the loading process (step S1), the temperature raising process (step S2), and the annealing process (step S3). Specifically, the temperature of the core tube before loading is set to 500 ° C., the boat insertion speed in the loading step is set to 10 cm / min, the heating rate in the heating step is set to 10 ° C./min, and the annealing step is 1200 ° C. This was carried out by holding at 2 ° C for 2 hours.

  On the other hand, the temperature drop rate in the temperature lowering step (step S4), the temperature of the silicon wafer at the start of the unloading step (step S5) (starting temperature of taking out), and the boat takeout speed in the unloading step (step S5) are evaluated. Different for each silicon wafer. Table 1 shows the temperature drop rate, the extraction start temperature, and the extraction speed for each sample.

Thus, after heat-processing with respect to all the silicon wafers, when the back surface of the silicon wafer was confirmed with the optical microscope, generation | occurrence | production of a crack was recognized by the contact part with a support pin in any silicon wafer. The size of the largest scratch and the number of scratches of 10 μm or more per 1 mm ² were measured. The measurement was performed on 10 silicon wafers in any of the examples and the comparative examples, and the average value was taken as the measured values (maximum scratches and the number of scratches) of the examples or comparative examples. The results are shown in Table 1. As shown in Table 1, in each of Examples 1 to 9, the maximum scratch was 100 μm or less, and the number of scratches was 50 or less. On the other hand, in Comparative Examples 1 to 4, the maximum scratch was more than 100 μm and the number of scratches was more than 50. Further, none of the silicon wafers had COP in the range of 20 μm from the surface.

  Next, in order to evaluate the strength reduction due to scratches, the breaking load of the silicon wafer was measured by a three-point bending test method. In the three-point bending test, as shown in FIG. 4A which is a side view and FIG. 4B which is a top view, two support bars 41 and 42 and one punch 43 which are parallel to each other are used. The back surface 31 side of the silicon wafer 30 was supported by the support rods 41 and 42, and the front surface 32 side was pressed by the punch 43. The support bars 41 and 42 were set at positions passing through a point 70 mm away from the center of the silicon wafer. On the other hand, the punch 43 was set at a portion passing through the center of the silicon wafer and the upper portion of the scratch 33. The descending speed of the punch 43 was set to 5 mm / min.

  The measurement was performed on 10 silicon wafers in any of the examples and comparative examples, and the average value was taken as the measured value (destructive load average value) of the example or comparative example. The results are shown in Table 1.

  As shown in Table 1, in the sample of Comparative Example 1 as a reference (temperature decrease rate: 10 ° C./min, extraction start temperature: 500 ° C., extraction speed: 50 cm / min), the average value of 10 silicon wafers is 260.5N.

  On the other hand, in the sample of Example 1, which has a slower take-out speed than Comparative Example 1, the average value of 10 silicon wafers was 321.8 N, and the strength was greatly improved. Further, in Examples 2 and 3 where the take-out speed was slower than that of Example 1, the average values of 10 silicon wafers were 363.2N and 405.1N, respectively, and the strength was further improved. Thereby, it was confirmed that intensity | strength is improved, so that taking-out speed is slow. Further, as shown in Table 1, it was confirmed that the slower the take-off speed, the shorter the maximum scratch and the fewer the number of scratches.

  Further, in the samples of Examples 4 to 6 having a lower temperature lowering rate than Example 1, the average values of the 10 silicon wafers were 343.5N, 360.4N, and 389.8N, respectively, and the strength was further improved. . Thereby, it was confirmed that intensity | strength is improved, so that a temperature-fall rate is small. In addition, as shown in Table 1, it was confirmed that the smaller the temperature drop rate, the shorter the maximum scratch and the number of scratches decreased. On the other hand, although the temperature drop rate is slower than that of Example 1 (8 ° C./min), in the sample of Comparative Example 2 where the take-out speed is 50 cm / min, the average value of 10 silicon wafers is 311.8 N. The strength as high as Example 1 was not obtained. Thus, it was confirmed that a higher strength can be obtained by lowering the take-off speed than simply lowering the temperature lowering rate.

  Further, in the samples of Examples 7 to 9 having a lower extraction start temperature than that of Example 1, the average values of 10 silicon wafers were 339.9N, 372.3N, and 394.6N, respectively, and the strength was further improved. It was. Thereby, it was confirmed that intensity | strength is improved, so that extraction start temperature is low. Further, as shown in Table 1, it was confirmed that the lower the take-off start temperature, the shorter the maximum scratches and the fewer the number of scratches. On the other hand, although the extraction start temperature is lower than that of Example 1 (490 ° C.), in the sample of Comparative Example 3 where the extraction speed is 50 cm / min, the average value of 10 silicon wafers is 316.7 N. A strength as high as 1 was not obtained. Thus, it was confirmed that a higher strength can be obtained by lowering the extraction speed than simply lowering the extraction start temperature.

  Further, the removal speed is the same as in Example 1, but in the sample of Comparative Example 4 where the extraction start temperature is high (510 ° C.), the average value of 10 silicon wafers is 299.6 N. Also decreased in strength. Thus, it was confirmed that even when the take-out speed was 45 cm / min, sufficient strength could not be obtained if the take-out start temperature was high.

It is a schematic diagram which shows the structure of the heat processing apparatus 10 by preferable embodiment of this invention. 4 is a schematic diagram for explaining a contact position between a silicon wafer 30 and a support pin 21. FIG. 3 is a flowchart for explaining a heat treatment method using the heat treatment apparatus 10; It is a figure for demonstrating a three-point bending test method, (a) is a side view, (b) is a top view.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Heat processing apparatus 11 Furnace core tube 11a Shutter 12 Heater 13 Load / unload mechanism 14 Temperature control part 15 Gas inlet 16 Gas outlet 20 Boat 21 Support pin 30 Silicon wafer 31 The back surface of a silicon wafer 32 The surface of a silicon wafer 33 Scratch 41, 42 support rod 43 punch

Claims (3)

An annealing step of loading a boat holding a silicon wafer into a furnace tube and heat-treating the silicon wafer at a temperature of 1100 ° C. or higher;
A temperature lowering step of lowering the temperature of the silicon wafer to 450 ° C. or higher and 500 ° C. or lower in the furnace tube after performing the annealing step;
An unloading step of removing the boat from the core tube after performing the temperature lowering step,
In the temperature lowering step, the temperature of the silicon wafer is lowered at a temperature falling rate of 4 ° C./min or more and 10 ° C./min or less in a temperature range in which the temperature of the silicon wafer decreases from 900 ° C. to 500 ° C.,
In the unloading step, the silicon wafer heat treatment method is characterized in that the boat take-out speed is 35 cm / min or more and 45 cm / min or less. 2. The silicon wafer heat treatment method according to claim 1 , wherein in the temperature lowering step, the temperature of the silicon wafer is decreased to 490 [deg.] C. or lower. A core tube, a heater for heating the core tube, a load / unload mechanism for loading and unloading a boat capable of holding a silicon wafer to the core tube, and adjusting the output of the heater to adjust the output of the silicon wafer. A temperature control unit for controlling the temperature,
In the temperature range where the temperature of the silicon wafer decreases from 900 ° C. to 500 ° C. after the heat treatment of the silicon wafer at a temperature of 1100 ° C. or more, the temperature control unit is 4 ° C./min or more and 10 ° C./min or less. The temperature of the silicon wafer is lowered to 450 ° C. or higher and 500 ° C. or lower by lowering the temperature at a temperature lowering rate ,
The load / unload mechanism takes out the boat from the core tube at a speed of 35 cm / min or more and 45 cm / min or less after the temperature of the silicon wafer is lowered to 450 ° C. or more and 500 ° C. or less. Heat treatment equipment for silicon wafers.

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