JP5515231B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a method for manufacturing a semiconductor integrated circuit device in which one electrode of a capacitor used in an oscillation circuit or the like is used as the same metal material as a gate electrode.

As the degree of integration increases, passive elements such as capacitive elements and resistive elements are formed on the element isolation region of the semiconductor integrated circuit device. In addition, the thickness of a LOCOS (Local Oxidation of Silicon) film used for the element isolation region may be reduced by etching or the like in order to adjust parasitic capacitance or reduce a step. In this case, it is known that the thickness of the LOCOS film is adjusted in a step immediately before forming a conductive layer such as an electrode or a wiring disposed thereon.
In recent years, semiconductor integrated circuit devices have been multilayered, and a capacitor of a polysilicon / interlayer insulating film / polysilicon structure is used. Patent Document 1 discloses a structure in which an upper electrode layer of a capacitor is formed using the same conductive layer as a gate electrode of a transistor, and a lower electrode layer is formed using another level of conductive layer. In this case, an etching process for adjusting the thickness of the LOCOS film is performed between the formation process of the upper electrode layer and the lower electrode layer.

8 to 10 are process cross-sectional views illustrating a conventional method for manufacturing a semiconductor integrated circuit device in which a capacitor element is formed on an element isolation region. In this capacitive element, a metal electrode such as molybdenum is used for the upper electrode and polysilicon is used for the lower electrode, and the metal layer constituting the upper electrode also constitutes the gate of the transistor.
First, the main surface of the silicon semiconductor substrate 101 is oxidized to form a LOCOS film 102 that is an element isolation region (FIG. 8A). A polysilicon film 104 is deposited on the main surface of the semiconductor substrate 101 and the LOCOS film 102 by, for example, a CVD (Chemical Vapor Deposition) method (FIG. 8B). Thereafter, the polysilicon film 104 is etched to form a lower electrode 104a on the LOCOS film 102 (FIG. 8C). Next, a predetermined region on the surface of the LOCOS film 102 where the lower electrode 104a is not formed is thinned by wet etching or the like. This thinned area is called a film thickness adjusting unit 103. The film thickness adjusting portion 103 is over-etched by wet etching, and an over-etching portion 103a extending under the lower electrode 104a is added (FIG. 9A).

Next, an interlayer insulating film 105 such as a silicon oxide film is coated on the semiconductor substrate 101, the LOCOS film 102 including the film thickness adjusting portion 103 and the overetching portion 103a, and the lower electrode 104a by, for example, a CVD method ( FIG. 9B). Thereafter, a metal film 106 such as molybdenum is deposited on the interlayer insulating film 105 by sputtering or the like (FIG. 9B). Then, the metal film 106 is patterned to form the upper electrode 106a made of a metal such as molybdenum on the lower electrode 104a with the interlayer insulating film 105 interposed therebetween. In this manner, a capacitive element composed of the lower electrode / interlayer insulating film / upper electrode is formed on the LOCOS film 102 (FIG. 10).
JP 2001-250869 A

In a semiconductor integrated circuit device having such a LOCOS film thickness adjusting step, when the upper electrode and the lower electrode are both made of polysilicon as in Patent Document 1, this is not a big problem. When incorporated in the semiconductor integrated circuit device described, the transistor has a metal gate, and the upper electrode is made of the same metal layer as the gate, the following problems arise.
That is, the etching performed to adjust the film thickness after the formation of the lower electrode causes the etching to wrap around under the polysilicon lower electrode end (this is called over-etching), so that the subsequent metal layer During sputtering and subsequent patterning, there arises a problem of a residue at an etching wrap-around portion (over-etched portion).
The residue 106b (see FIG. 10) appears particularly prominently in the etching progress portion (over-etched portion) 103a. This is due to the shape of this over-etched portion, and the problem is that the metal crystal grows abnormally in that portion during sputtering. In normal growth, for example, a metal crystal made of molybdenum grows in a columnar shape. However, the etching rate is slow because the crystal is not standing in a columnar shape in the base portion having large irregularities such as the over-etched portion. Accordingly, a residue remains.

  The present invention has been made in order to solve the above-described problems, and in a method of manufacturing a semiconductor integrated circuit device for adjusting the film thickness of a LOCOS film, there is no depression due to etching wrapping, and therefore, an etching residue of a metal layer is generated. Provided is a method for forming a capacitor element with a small amount.

The method for manufacturing a semiconductor integrated circuit device according to the present invention includes a step of selectively oxidizing a main surface of a semiconductor substrate to form a LOCOS film as an element isolation region on the semiconductor substrate, and etching the LOCOS film to form the LOCOS film. A film thickness adjusting step , a step of forming a polysilicon film on the main surface of the semiconductor substrate so as to cover the LOCOS film after the film thickness adjusting step, and patterning the polysilicon film to at least partly Forming a lower electrode disposed on the LOCOS film, forming an interlayer insulating film on the main surface of the semiconductor substrate so as to cover the lower electrode, and forming a metal film on the interlayer insulating film process and, by patterning the metal film and forming an upper electrode via the interlayer insulating film on the lower electrode, the film thickness adjustment of the LOCOS film Wherein except for the portion that will form the lower electrode, and has no depression by diffraction of the etching in the patterning of the metal film, it is characterized in that an etching remaining generate less capacitive element of said metal film.

A transistor may be formed in the element region partitioned by the element isolation region, and the gate electrode of the transistor may be formed in the same step as the step of forming the upper electrode. The side surface of the lower electrode may be inclined in a tapered shape. The lower electrode, the interlayer insulating film, and the upper electrode may be at least partially formed in the element region.

  According to the present invention, by performing the LOCOS film thickness adjustment process before the etching process of the polysilicon film for the lower electrode, a capacitor element free from the depression due to the etching wrapping and hence with little occurrence of etching residue of the metal layer is obtained. I can do it.

  Hereinafter, embodiments of the invention will be described with reference to examples.

First, Embodiment 1 will be described with reference to FIGS.
1 to 4 are process cross-sectional views illustrating a method for manufacturing a semiconductor integrated circuit device having a capacitive element, and FIG. 5 is a circuit diagram illustrating an example of an oscillation circuit in which the capacitive element is used. For example, a silicon oxide film (SiO2) is formed on the main surface of the P-type silicon semiconductor substrate 1 by a thermal oxidation method. A silicon nitride film (Si3 N4) is deposited on the silicon oxide film by CVD. Next, a photoresist (positive) is applied on the silicon nitride film. Thereafter, the photoresist is irradiated with light through a photomask 7 such as a glass mask (exposure process, FIG. 1A). The photoresist is removed leaving the shaded part. The remaining light-shielded portion becomes a resist mask 8 (development process, FIG. 1B). Using the resist mask 8 as a mask, the silicon nitride film is etched using an etching gas (etching process, FIG. 1C) to form a nitride film mask 9 (etching process, FIG. 2A).

Thereafter, impurity ions such as boron (B) ions can be doped to selectively form channel stoppers in the surface region to be an element region of the semiconductor substrate 1. Next, the surface of the semiconductor substrate 1 is selectively oxidized using the nitride film mask 9 as a mask. Since the silicon nitride film has oxidation resistance, only the portion not covered with the nitride film mask 9 is oxidized (selective oxidation step, FIG. 2A). When the selective oxidation is completed, the nitride film mask 9 is removed. As a result, a LOCOS film 2 that is an element isolation region is formed on the main surface of the semiconductor substrate 1. A region partitioned by the element isolation region is an element region 11 where a transistor or the like is formed (mask removal process, FIG. 2B).
Next, a process for forming a capacitive element on the LOCOS film will be described. 3 to 4 show a region A including an element isolation region in which the capacitor element of the semiconductor substrate shown in FIG. 2B is formed and a peripheral device region. In this capacitive element, a metal electrode made of molybdenum is used for the upper electrode and polysilicon is used for the lower electrode, and the metal layer constituting the upper electrode also constitutes the gate of the transistor. As a metal used for the metal electrode, tungsten, titanium, or the like can be used in addition to molybdenum.

As shown in FIG. 2B, a LOCOS film 2 as an element isolation region is formed on the main surface of the silicon semiconductor substrate 1. A predetermined region on the surface of the LOCOS film 2 is thinned by wet etching or the like, for example, about 38 nm. This thinned region is called a film thickness adjusting unit 3 (FIG. 3A). Next, a polysilicon film 4 having a film thickness of, for example, 300 nm is deposited on the main surface of the semiconductor substrate 1 and the LOCOS film 2 by the CVD method (FIG. 3B). Thereafter, the polysilicon film 4 is etched to form a lower electrode 4 a in a region other than the film thickness adjusting portion 3 on the LOCOS film 102. The side surface of the lower electrode 4a is tapered. This shape is employed to improve the adherence of the film deposited on the lower electrode (FIG. 3C).
Next, an interlayer insulating film 5 such as a silicon oxide film having a film thickness of, for example, 20 nm is formed on the semiconductor substrate 1 and on the LOCOS film 2 including the film thickness adjusting unit 3 and the lower electrode 4a by, for example, a CVD method. Cover (FIG. 4 (a)). Thereafter, a metal film 6 having a film thickness of, for example, 200 nm is deposited on the interlayer insulating film 3 by sputtering or the like (FIG. 4B).

Sputtering is a method of depositing a film of metal or the like on a substance, and unlike plating, it is performed in a vacuum without using chemicals. A sample for depositing a film on the surface and a target of a raw material such as a metal are arranged close to each other in a sputtering apparatus. A voltage is applied between the sample and the target in a vacuum state in the sputtering apparatus. Electrons and ions move at high speed between them, and the ions collide with the target. Electrons and ions that move at high speed collide with gas molecules, repel the electrons of the molecules, and become ions. The ions that collide with the target repel the target particles, and the repelled particles collide with the sample and adhere to form a film.
Next, the metal film 6 is patterned to form an upper electrode 6a made of a metal such as molybdenum on the lower electrode 4a with the interlayer insulating film 5 interposed therebetween. In this way, the capacitive element 10 composed of the lower electrode 4a / interlayer insulating film 5 / upper electrode 6a is formed on the LOCOS film 2 (FIG. 4C). It is also used for a metal gate of a transistor formed in the element region.

  The capacitive element formed as described above is used, for example, in the oscillation control circuit and the oscillation circuit shown in FIG. In the figure, reference numeral 13 denotes a P-channel MOS transistor and reference numeral 14 denotes an N-channel MOS transistor, which constitutes a CMOS inverter B. The source of the P channel MOS transistor 13 is connected to a positive power supply line (not shown), and the source of the N channel MOS transistor 14 is connected to a ground line (not shown). Reference numeral 15 denotes a first resistor connected in parallel to the CMOS inverter B, and reference numeral 16 denotes a second resistor connected in parallel to the P-channel MOS transistor 13. In this case, the output terminal of the CMOS inverter B and the positive power supply line It is a pull-up resistor connected between them. The resistance value of the pull-up resistor 16 is preferably a value sufficiently larger than the on-resistance of the P-channel MOS transistor 13 and the N-channel MOS transistor 14 and sufficiently smaller than the off-resistance (for example, 10 kilohms). The oscillation control circuit A is configured by the CMOS inverter B and the first and second resistors 15 and 16.

  The oscillation control circuit A is an integrated circuit formed on a single semiconductor substrate such as silicon. Reference numeral 17 denotes a crystal resonator which is connected in parallel to the CMOS inverter B and the first resistor 15 by external connection terminals 18 and 19 of the integrated circuit. Reference numerals 10 and 12 denote capacitive elements provided on the semiconductor substrate. The capacitor element 10 is formed by the manufacturing process shown in FIGS.

In this embodiment, the LOCOS film thickness adjusting step is performed before the etching process of the polysilicon film for the lower electrode, so that there is no depression due to the wraparound of the etching, and as a result, the generation of the etching residue of the metal layer is small. Can be obtained on the element isolation region. In the above-described embodiment, the example in which the film thickness adjustment of the LOCOS film is performed in a limited range so as to exclude the capacity formation scheduled portion . When the film thickness is adjusted with respect to the entire LOCOS film, the capacitance portion approaches the semiconductor substrate by the adjusted film thickness, so there is a concern about a change in parasitic capacitance.

Next, Embodiment 2 will be described with reference to FIGS.
FIG. 6 is a cross-sectional view of a semiconductor integrated circuit device having a capacitive element, and FIG. 7 is a circuit diagram showing an example of an oscillation circuit in which the capacitive element is used. This embodiment is characterized in that capacitive elements are formed in both the element region and the element isolation region.
As shown in FIG. 6, a part of the element region 31a provided in the semiconductor substrate 21 such as silicon and a part of the element isolation region 22 around the element region 31a includes a PN junction diode 29 on the surface region of the semiconductor substrate 21 and the semiconductor thereon. A capacitive element 28 is formed on the substrate 21, and a MOS transistor 30 is formed in the element region 31b.

  The element region 31 a provided with the PN junction diode 29 is partitioned into a LOCOS film (element isolation region) 22. The LOCOS film 22 is formed by the steps shown in FIGS. 1 to 4 described in the first embodiment. The capacitive element 28 is not formed on the film thickness adjusting unit 23 that adjusts the parasitic capacitance and the like formed in this process. The PN junction diode 29 is composed of a high-concentration P-type diffusion region 21a and a high-concentration N-type diffusion region 21b thereon, and a PN junction is constituted by both diffusion regions. A silicon oxide film 27a is formed on the surface of the N-type diffusion region 21b. A lower electrode 24a made of polysilicon is formed on the silicon oxide film 27a and on a region other than the film thickness adjusting portion 23 of the LOCOS film 23 around the silicon oxide film 27a. An interlayer insulating film 25 such as a silicon oxide film is formed on the lower electrode 24a. An upper electrode 26a made of a metal layer such as molybdenum is formed on the lower electrode 24a with an interlayer insulating film 25 interposed therebetween. Thus, the capacitive element 28 composed of the lower electrode / interlayer insulating film / upper electrode is formed.

  A source / drain region 20 is formed in the element region 31b, and a metal gate 26b is formed on the source / drain region 20 via a gate insulating film 27b. The metal gate 26b is formed in the same process as that of the upper electrode 26a, and the NMOS transistor 30 configured by the source / drain regions, the gate insulating film, and the metal gate is obtained.

The semiconductor integrated circuit device shown in FIG. 6 is used, for example, in the oscillation circuit shown in FIG. The oscillation circuit is provided with terminals 32 and 33 for externally attaching the crystal resonator 31, an amplifying inverter 34 and a feedback resistor 35, and a DC blocking capacitor element between the input terminal of the inverter 34 and the terminal 32. A capacitor 28 having a molybdenum electrode (26a in FIG. 6) and a polysilicon electrode (24a in FIG. 2) is provided, and a damping resistor 36 connected in series between the output terminal of the inverter 34 and the terminal 33 and a direct current blocking circuit are provided. A capacitor 37 which is a capacitive element is provided. The molybdenum electrode of the capacitor 28 is located on the inverter 34 side, and the polysilicon electrode is located on the terminal 32 side.
Between the terminal 32 and the capacitor 28, the cathode side of a PN junction diode 29, which is an oscillation frequency control variable capacitor, is connected. The cathode side (21b in FIG. 6) of the PN junction diode 29 is connected to a control voltage terminal 41 for inputting an external voltage for frequency control through a load resistor 43, and the anode side (21a in FIG. 6) is grounded (21a). VSS potential). Similarly, a cathode side of a PN junction diode 38 which is a variable capacitance element for oscillation frequency control is connected between the terminal 33 and the capacitor 37. The cathode side of the PN junction diode 38 is also connected to a control voltage terminal 41 for inputting an external voltage for frequency control via a load resistor 40, and the anode side is grounded (VSS potential).

The cathode of the PN junction diode 29 is connected to the collector terminal of an NPN snapback transistor 42 for protecting against breakdown voltage, and the emitter terminal of the snapback transistor 42 is connected to the anode of the PN junction diode 29. The gate terminal and the emitter terminal of the snapback transistor 42 are grounded (VSS potential). The cathode of the PN junction diode 38 is connected to the collector terminal of an NPN snapback transistor 39 for protection against breakdown voltage, and the emitter terminal of the snapback transistor 39 is connected to the anode of the PN junction diode 38. The gate terminal and the emitter terminal of the snapback transistor 39 are grounded (VSS potential).
The NMOS transistor 30 formed in the element region 31b shown in FIG. 6 is used as a transistor constituting the inverter 34 of the oscillation circuit of FIG. The formation of the gate constituting the NMOS transistor 30 is performed in the same process as the upper electrode 26a constituting the capacitive element 28.

  In this embodiment, the LOCOS film thickness adjusting step is performed before the etching process of the polysilicon film for the lower electrode, so that there is no depression due to the wraparound of the etching, and as a result, the generation of the etching residue of the metal layer is small. Can be obtained on the element isolation region and the element region.

FIG. 6 is a process cross-sectional view illustrating a method for manufacturing a semiconductor integrated circuit device having a capacitor element according to the first embodiment. FIG. 6 is a process cross-sectional view illustrating a method for manufacturing a semiconductor integrated circuit device having a capacitor element according to the first embodiment. FIG. 6 is a process cross-sectional view illustrating a method for manufacturing a semiconductor integrated circuit device having a capacitor element according to the first embodiment. FIG. 6 is a process cross-sectional view illustrating a method for manufacturing a semiconductor integrated circuit device having a capacitor element according to the first embodiment. FIG. 3 is a circuit diagram illustrating an oscillation circuit in which the capacitive element of Example 1 is used. FIG. 6 is a cross-sectional view of a semiconductor integrated circuit device having a capacitive element according to a second embodiment. FIG. 6 is a circuit diagram showing an oscillation circuit in which the capacitor element of Example 2 is used. FIG. 10 is a process cross-sectional view illustrating a method for manufacturing a semiconductor integrated circuit device in which a capacitor element is formed on a conventional element isolation region. FIG. 10 is a process cross-sectional view illustrating a method for manufacturing a semiconductor integrated circuit device in which a capacitor element is formed on a conventional element isolation region. FIG. 10 is a process cross-sectional view illustrating a method for manufacturing a semiconductor integrated circuit device in which a capacitor element is formed on a conventional element isolation region.

Explanation of symbols

1, 21 ... Semiconductor substrate 2, 22 ... LOCOS film (element isolation region)
3, 23... Thickness adjuster 4... Polysilicon film 4 a, 24 a .. Lower electrode 5, 25 .. Interlayer insulating film 6 .. Metal film 6 a, 26 a. .... Photomask 8 ... Photoresist 9 ... Nitride film mask 10, 12 ... Capacitance element 11, 31a, 31b ... Element region 13, 14 ... MOS transistor 15, 16, 35, 36 , 40, 43... Resistors 17, 31... Crystal resonator 18, 19, 32, 33, 41... Terminal 20... Source / drain region 21a... P-type diffusion region 21b. N-type diffusion region 26b ... Metal gate 27a ... Field oxide film 27b ... Gate insulating film 28 ... Capacitance element (capacitor)
29, 38 ... PN junction diode 30 ... MOS transistor 34 ... Inverter 37 ... Capacitor 39, 42 ... Snapback transistor

Claims (4)

Forming a LOCOS film semiconductor substrate main surface selectively oxidized to a said semiconductor substrate in the element isolation region, a step of the film thickness adjustment of the LOCOS film by etching the LOCOS film, the thickness After the adjustment step, a step of forming a polysilicon film on the main surface of the semiconductor substrate so as to cover the LOCOS film, and patterning the polysilicon film to form a lower electrode at least partially disposed on the LOCOS film. A step of forming an interlayer insulating film on the main surface of the semiconductor substrate so as to cover the lower electrode, a step of forming a metal film on the interlayer insulating film, and patterning the metal film to and a step of forming an upper electrode via the interlayer insulating film on the lower electrode, the film thickness adjustment of the LOCOS film except for the portion that will form the lower electrode And, wherein the metal film without recesses due to diffraction of the etching in the patterning of the method of manufacturing a semiconductor integrated circuit device, which comprises forming an etching remaining generate less capacitive element of said metal film. 2. The semiconductor integrated circuit according to claim 1, wherein a transistor is formed in an element region partitioned by the element isolation region, and a gate electrode of the transistor is formed in the same step as the step of forming the upper electrode. Device manufacturing method. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a side surface of the lower electrode is inclined in a tapered shape. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein at least a part of the lower electrode, the interlayer insulating film, and the upper electrode is formed in the element region. .

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