JP5513052B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device that supplies a drain signal to two pixel columns from a single drain signal line.

  A liquid crystal display device that supplies a drain signal from one drain signal line to two pixel columns is disclosed in, for example, Patent Document 1 below.

  In such a liquid crystal display device, among the pixels arranged in a matrix, in the pixel group of each pixel arranged in the row direction, every other pixel (for example, an odd-numbered pixel) is arranged as the pixel. A gate selected by a gate signal line (sometimes referred to as a first gate signal line) formed on one side of the group and another pixel (even-numbered pixel) formed on the other side of the pixel group It is selected by a signal line (sometimes referred to as a second gate signal line).

  Further, the drain signal line is disposed so as to run between the adjacent odd-numbered pixels and the even-numbered pixels, and is not disposed between the adjacent even-numbered pixels and odd-numbered pixels. It has become. Each of the drain signal lines supplies a video signal to the odd-numbered pixels adjacent to the drain signal line when the odd-numbered pixels are selected by the first gate signal line, and is even-numbered by the second gate signal line. When the second pixel is selected, a video signal is supplied to even-numbered pixels adjacent to the drain signal line. That is, a single drain signal line can supply a video signal to each of two pixels arranged on both sides of the drain signal line.

  Therefore, the liquid crystal display device having such a configuration has an effect that the number of drain signal lines for supplying a video signal to each pixel can be halved compared to the conventional one.

  As a technique related to the present invention, for example, there is Patent Document 2 below. In Patent Document 2, a pair of drain signal lines run on both sides of a pixel, and the pixel electrode formed on the pixel region of the insulating film formed by covering these drain signal lines is viewed in a plan view. Thus, there is described a configuration in which each side on the drain signal line side is formed so as to overlap the drain signal line.

JP-A-2-42220 Japanese Patent Laid-Open No. 62-223727

  Note that in the liquid crystal display device disclosed in Patent Document 1, a pixel electrode made of a light-transmitting conductive film is formed on a substrate on which a gate signal line and a drain signal line are formed (sometimes referred to as a first substrate). Thus, a so-called vertical electric field structure is formed in which a counter electrode made of a light-transmitting conductive film is formed on a substrate (sometimes referred to as a second substrate) opposed to the first substrate.

  In such a vertical electric field type liquid crystal display device, it has been found that when the aperture ratio of each pixel is to be improved, there is a limit to the improvement of the aperture ratio. That is, as described above, in the pixels arranged in the row direction, for example, a drain signal line is not formed between adjacent even-numbered pixels and odd-numbered pixels. Therefore, a black matrix (light-shielding film) is formed on the second substrate side in order to shield light between the adjacent even-numbered pixels and odd-numbered pixels, but the even-numbered pixels and odd-numbered pixels are formed. The width of the black matrix corresponding to the gap with the pixel must be increased. In addition, when the second substrate is opposed to the first substrate, it is necessary to allow a margin for the width of the black matrix in consideration of misalignment between them. For this reason, the aperture ratio of each pixel is limited by the black matrix.

  An object of the present invention is to provide a liquid crystal display device having an improved aperture ratio.

  The liquid crystal display device of the present invention includes a storage line that forms a capacitive element between the pixel electrode and the storage line is arranged at a location on the side where the drain signal line of each pixel is not arranged. The storage line is configured to have the function of a light shielding film. In addition, a capacitor element is formed by using the storage line newly formed in this manner, thereby reducing the area occupied by the capacitor element conventionally provided, and as a result, the pixel area is enlarged and the aperture ratio is increased. It is intended to improve.

  The configuration of the present invention can be as follows, for example.

( 1 ) The liquid crystal display device of the present invention includes a thin film transistor controlled by a signal from a gate signal line, a drain signal line for supplying a video signal, a pixel electrode to which a video signal from the drain signal line is supplied, A liquid crystal display device comprising: a capacitor element formed between the pixel electrode and a storage line; and an intermediate electrode extending from a source electrode of the thin film transistor and electrically connecting the pixel electrode and the thin film transistor. And
The first pixel and the second pixel are repeatedly arranged in this order in the first direction to form a pixel group,
A first gate signal line and a second gate signal line are disposed across the pixel group, the thin film transistor of the first pixel is controlled by a scanning signal from the first gate signal line, and the thin film transistor of the second pixel Is controlled by a scanning signal from the second gate signal line,
The drain signal line, the first pixel and the a plurality of arranged so as to sandwich the second pixel, each pixel electrode in the video signal of the first pixel and the second pixel positioned at both sides of the drain signal lines Supply
The storage line is electrically connected to the first storage line adjacent to the first gate signal line, the second storage line adjacent to the second gate signal line, and the first storage line and the second storage line. A third storage line connected between the first pixel and the second pixel, wherein the drain signal line is connected and the drain signal line does not travel;
The intermediate electrode of the first pixel includes a first extension portion of the first pixel extending along the third storage line to a middle portion of the first pixel, and a first extension portion of the first pixel. A second extending portion of a second pixel connected and extending along the first storage line,
The intermediate electrode of the second pixel includes a first extension portion of the second pixel extending along the third storage line to a middle portion of the second pixel, and a first extension portion of the second pixel. And a second extending portion of the first pixel connected and extending along the second storage line.

( 2 ) The liquid crystal display device of the present invention is characterized in that, in ( 1 ), the pixel electrode has a portion where a side adjacent to the drain signal line overlaps the drain signal line.

( 3 ) In the liquid crystal display device of the present invention, in any one of ( 1 ) and ( 2 ), a protective film made of an organic insulating film is formed on the substrate so as to cover the thin film transistor, and the pixel electrode is protected It is formed on the upper surface of the film.

( 4 ) In the liquid crystal display device of the present invention, in ( 1 ), a pixel group in which the first pixel and the second pixel are repeatedly arranged in this order is defined as a first pixel group, and is adjacent to the first pixel group. When the other pixel group arranged in the second pixel group is the second pixel group, the second pixel group is arranged so as to be shifted by a half pitch of the pixel with respect to the first pixel group,
The drain signal line is formed with a bent portion in a region between the first pixel group and the second pixel group.

  The above-described configuration is merely an example, and the present invention can be modified as appropriate without departing from the technical idea. Further, examples of the configuration of the present invention other than the above-described configuration will be clarified from the entire description of the present specification or the drawings.

  The liquid crystal display device thus configured can improve the aperture ratio.

  Other effects of the present invention will become apparent from the description of the entire specification.

It is a top view of the pixel which shows Example 1 of the liquid crystal display device of this invention. 1 is an equivalent circuit diagram of a pixel showing Embodiment 1 of a liquid crystal display device of the present invention. It is sectional drawing in the III-III line of FIG. It is sectional drawing in the IV-IV line of FIG. It is a top view of the pixel which shows Example 2 of the liquid crystal display device of this invention. It is sectional drawing in the VI-VI line of FIG. It is sectional drawing of the pixel which shows Example 2 of the liquid crystal display device of this invention.

  Embodiments of the present invention will be described with reference to the drawings. In each drawing and each example, the same or similar components are denoted by the same reference numerals and description thereof is omitted.

  FIG. 1 is a plan view showing Example 1 of a pixel of a liquid crystal display device of the present invention. FIG. 1 shows pixels formed on the liquid crystal side surface of one of the pair of substrates (first substrate SUB1) that are opposed to each other with the liquid crystal interposed therebetween. 3 shows a cross-sectional view taken along line III-III in FIG. 1 together with the other substrate (second substrate SUB2), and FIG. 4 shows a cross-sectional view taken along line IV-IV in FIG. It is shown together with the substrate SUB2).

  FIG. 1 shows a pixel group (first pixel group PG1) arranged in the row direction (x direction in the figure) among a plurality of pixels arranged in a matrix in the image display area. This first pixel group For example, four adjacent pixels of PG1 are shown. For convenience of explanation, these pixels will be referred to as the first pixel PIX1 or the second pixel PIX2, and will be described separately. This is because the first pixel PIX1 and the second pixel PIX2 have the same configuration, but are symmetrically arranged in the horizontal direction. For example, the four pixels shown in FIG. 1 are arranged in the order of the first pixel PIX1, the second pixel PIX2, the first pixel PIX1, and the second pixel PIX2 from the left to the right in the figure, and the following is repeated in this order. Are arranged.

  Here, prior to the description of FIG. 1, an outline of an equivalent circuit drawn in association with FIG. 1 will be described with reference to FIG. However, in FIG. 2, in addition to the pixel group (first pixel group PG1) composed of four pixels arranged in the row direction (x direction in the drawing), 4 arranged in the column direction (y direction in the drawing). A pixel group composed of individual pixels (second pixel group PG2) is also drawn. In FIG. 2, the first pixel group PG1 includes a first gate signal line GL (indicated by reference numeral GL1 in the figure) and a second gate signal line GL (running in the x direction in the figure) with the first pixel group PG1 in between. (Indicated by reference numeral GL2 in the figure). The thin film transistor TFT (indicated by reference numeral TFT1 in the figure) of the first pixel PIX1 is controlled by a scanning signal from the first gate signal line GL1, and the thin film transistor TFT (indicated by reference numeral TFT2 in the figure) of the second pixel PIX2 It is controlled by a scanning signal from the gate signal line GL2. Thus, the thin film transistor TFT1 of the first pixel PIX1 is disposed adjacent to the first gate signal line GL1 side, and the thin film transistor TFT2 of the second pixel PIX2 is disposed adjacent to the second gate signal line GL2 side. It has become. Further, a drain signal line DL runs between the first pixel PIX1, the first pixel PIX1, and the second pixel PIX2 adjacent in the (−) x direction in the drawing, and the video signal from the drain signal line DL is In the first pixel PIX1, the pixel electrode PX is supplied through the thin film transistor TFT1, and in the second pixel PIX2, the pixel electrode PX is supplied through the thin film transistor TFT2.

  Further, in the first pixel group PGL1, a first storage line STL (indicated by reference sign STL1 in the drawing) adjacent to the first gate signal line GL1 and extending along the first gate signal line GL1, and a second gate A second storage line STL (indicated by reference sign STL2 in the drawing) adjacent to the signal line GL2 and extending along the second gate signal line GL2 is disposed. The first storage line STL1 forms a capacitive element CP (indicated by reference numeral CP1 in the figure) between the first pixel PIX1 and the pixel electrode PX, and forms a capacitive element between the pixel electrode PX in the second pixel PIX2. CP (indicated by reference numeral CP2 in the figure) is formed. Therefore, conventionally, the capacitive element CP1 of the first pixel PIX1 is formed in the formation region of the first storage line STL1 in the first pixel PIX1, and the capacitive element CP2 of the second pixel PIX2 is formed in the second pixel PIX2. The second storage line STL2 is formed in the formation region. However, in this embodiment, although not shown in FIG. 2, the capacitive elements CP1 and CP2 are formed in regions other than those described above. A detailed configuration thereof will be described later. Further, in this embodiment, the first pixel PIX1, the first pixel PIX1, and the second pixel PIX2 adjacent in the (+) x direction in the drawing run, and the first storage line STL1 and the second storage A third storage line STL (indicated by symbol STL3 in the figure) that is electrically connected to the line STL2 is newly provided. The effect of the third storage line STL3 will be described later.

  The second pixel group PG2 is arranged in the column direction (y direction in the figure) with respect to the first pixel group PG1 configured as described above. The first pixel PX1 and the second pixel PX2 in the second pixel group PG2 have the same configuration as the first pixel PX1 and the second pixel PX2 in the first pixel group PG1, respectively. Further, in this embodiment, the second pixel group PIX2 is arranged so as to be shifted from the first pixel group PIX1 by a half pitch portion of the pixel in the (−) x direction in the drawing. Therefore, the drain signal line DL in the first pixel group PIX1 is connected to the corresponding drain signal line DL and the bent portion BD in the second pixel group PG2 in the region between the first pixel group PG1 and the second pixel group PG2, respectively. Connected. Although not shown, the pixel group arranged adjacent to the upper side of the drawing with respect to the first pixel group PG1 is also shifted by a half pitch of the pixel in the (−) x direction in the drawing. Yes. However, it is not always necessary to dispose the pixel groups so that the drain signal line DL may be formed in a straight line without having the bent portion BD.

  Returning to FIG. 1, on the liquid crystal side surface (front surface) of the first substrate SUB1 (see FIGS. 3 and 4), the first gate signal line GL1, the second gate signal line GL2, the first storage line STL1, the second A storage line STL2 and a third storage line STL3 are formed. The first gate signal line GL1, the second gate signal line GL2, the first storage line STL1, the second storage line STL2, and the third storage line STL3 are made of a light-shielding material such as metal, and are formed simultaneously, for example. It is like that.

  The first gate signal line GL1 is formed with a protrusion that protrudes toward the center of the pixel in the region of the first pixel PIX1, and this protrusion constitutes the gate electrode GT of the thin film transistor TFT1 in the first pixel PIX1. Yes. Similarly, the second gate signal line GL2 is formed with a protrusion protruding toward the center of the pixel in the region of the second pixel PIX2, and this protrusion forms the gate electrode GT of the thin film transistor TFT2 in the second pixel PIX2. It has become.

  The first storage line STL1 has a portion that is wide in the region of the first pixel PIX1, and constitutes one electrode of the capacitive element CP1 in the first pixel PIX1. Similarly, the second storage line STL2 has a portion that is formed wide in the region of the second pixel PIX2, and constitutes one electrode of the capacitive element CP2 in the second pixel PIX2.

  Here, a third storage line STL3 is formed between the first pixel PIX1, the first pixel PIX1, and the second pixel PIX2 adjacent in the (+) x direction in the drawing. The third storage line STL3 is formed in a portion where a drain signal line DL, which will be described later, does not travel, and is electrically connected to the first storage line STL1 and the second storage line STL2. Accordingly, in the first pixel PIX1, the drain signal line DL is positioned on the left side in the drawing, and the third storage line STL3 is positioned on the right side in the drawing. In the second pixel PIX2, the drain signal line DL is positioned on the left side in the drawing. The drain signal line DL is positioned on the right side of the third storage line STL3 in the drawing.

  The surface of the first substrate SUB1 is covered with the first gate signal line GL1, the second gate signal line GL2, the first storage line STL1, the second storage line STL2, and the third storage line STL3, for example, from a silicon oxide film. An insulating film GI (see FIGS. 3 and 4) is formed. This insulating film GI functions as a gate insulating film in a region where a thin film transistor TFT described later is formed.

  An island-shaped semiconductor layer AS made of, for example, amorphous silicon is formed on the upper surface of the insulating film GI and in a portion overlapping with the gate electrode GT. The semiconductor layer AS is a semiconductor layer of a MIS (Metal Insulator Semiconductor) type thin film transistor TFT, and a drain electrode DT and a source electrode ST which are disposed to face each other are formed on the upper surface thereof. In the first pixel PIX1, a part of the drain signal line DL that extends between the first pixel PIX1, the first pixel PIX1, and the second pixel PIX2 adjacent in the (−) x direction in the drawing is extended. Thus, the drain electrode DT of the thin film transistor TFT1 is configured. In this case, also in the second pixel PIX2, a part of the drain signal line DL is extended to constitute the drain electrode DT of the thin film transistor TFT2. In the second pixel PIX2, a part of the drain signal line DL extending between the second pixel PIX2, the second pixel PIX2, and the first pixel PIX1 adjacent in the (+) x direction in the drawing is extended. Thus, the drain electrode DT of the thin film transistor TFT2 is configured. In this case, also in the first pixel PIX1, a part of the drain signal line DL is extended to constitute the drain electrode DT of the thin film transistor TFT1.

  The source electrodes ST of the thin film transistor TFT1 of the first pixel PIX1 and the thin film transistor TFT2 of the second pixel PIX2 are formed at the same time when the drain signal line DL is formed, for example. In the first pixel PIX1, the source electrode ST has an extending portion MT (indicated by reference numeral MT1 in the drawing) extending to the pixel region side, and this extending portion MT1 is formed adjacent to the thin film transistor TFT1. The first storage line STL1 is overlapped with the first storage line STL1. The overlapping part of the extension part MT1 of the source electrode ST and the first storage line STL1 constitutes a capacitor. Similarly, in the second pixel PIX2, the source electrode ST has an extending portion MT (indicated by reference numeral MT2 in the drawing) extending to the pixel region side, and this extending portion MT2 is adjacent to the thin film transistor TFT2. The second storage line STL2 is formed so as to overlap with the second storage line STL2. The overlapping part of the extension part MT2 of the source electrode ST and the second storage line STL2 constitutes a capacitor. In this specification, for convenience of later explanation, the extension portions MT of the source electrode ST are respectively named intermediate electrodes MT. The source electrode ST is electrically connected to a pixel electrode PX described later via the intermediate electrode MT.

  Here, the intermediate electrode MT is formed to include not only a portion overlapping the storage line STL but also an extending portion extending to a hatched region in the drawing as shown in FIG. That is, in the case of the first pixel PIX1, the intermediate electrode MT1 formed so as to overlap the first storage line STL1 first extends in the vicinity of the third storage line STL3 along the traveling direction of the third storage line STL3. A first extending part EX1 (indicated by reference numeral EX11 in the figure) is provided. The first extension portion EX11 extends with a relatively narrow width. Further, the side of the first extension part EX11 on the third storage line STL3 side partially overlaps the third storage line STL3, and a gap is formed between the first extension part EX11 and the third storage line STL3. There is no such thing. The reason why the first extending portion EX11 has a narrow width is that it is not avoided that the first extending portion EX11 having a light shielding function is formed in a wide area in the pixel region. The first extending portion EX11 includes a second extending portion EX12 that is bent in a direction intersecting the traveling direction of the third storage line STL3 at the extending end in the traveling direction of the third storage line STL3. The second extension part EX2 (indicated by reference numeral EX12 in the drawing) is formed so as to overlap with the second storage line STL2 formed in the region of the first pixel PIX1. Similarly, in the case of the second pixel PIX2, the intermediate electrode MT2 formed so as to overlap the second storage line STL2 is first in the vicinity of the third storage line STL3, along the traveling direction of the third storage line STL3. A first extending portion EX2 (indicated by symbol EX21 in the figure) is provided. The first extension portion EX21 extends with a relatively narrow width. Further, the side of the first extension part EX21 on the third storage line STL3 side partially overlaps the third storage line STL3, and a gap is formed between the first extension part EX21 and the third storage line STL3. There is no such thing. The first extension portion EX21 is a second extension portion EX2 (indicated by symbol EX22 in the drawing) that bends in a direction intersecting the traveling direction of the third storage line STL3 at the extending end in the traveling direction of the third storage line STL3. ). The second extension part EX22 is formed so as to overlap with the first storage line STL1 formed in the region of the second pixel PIX2.

  In such a configuration, for example, in the first pixel PIX1, by providing the first extension part EX11 and the second extension part EX12 in the intermediate electrode MT1, the second storage can be provided between the third storage line STL3 and the second storage line STL3. A new capacitance can be formed between the line STL1. In this case, the first extending portion EX11 and the second extending portion EX12 need only be formed so as to overlap the storage line STL, and can be formed while greatly reducing the aperture ratio of the pixel. In this way, the capacitance formed between the first storage line STL1 in the first pixel PIX1 can be reduced by the amount that the capacitance is increased by forming the first extension portion EX11 and the second extension portion EX12. The area of the capacitive element in this portion can be reduced. Therefore, the aperture ratio of the first pixel PIX1 can be improved. The same applies to the second pixel PIX2.

  The capacitive element CP in each pixel is formed between the storage line STL and the intermediate electrode MT, and is also formed in an overlapping portion between the intermediate electrode MT and a pixel electrode PX described later. .

  The surface of the first substrate SUB1 is covered with the drain signal line DL and the thin film transistor TFT, and a protective film made of a sequential laminate of an inorganic protective film PAS1 made of, for example, a silicon nitride film and an organic protective film PAS2 made of, for example, a resin film. A PAS (see FIGS. 3 and 4) is formed. The protective film PAS avoids direct contact of the liquid crystal with the thin film transistor TFT, and prevents characteristic deterioration of the thin film transistor TFT.

  In each region of the first pixel PIX1 and the second pixel PIX2 on the upper surface of the protective film PAS, a pixel electrode PX made of, for example, a light-transmitting conductive film made of ITO (Indium Tin Oxide) is formed. These pixel electrodes PX are electrically connected to the intermediate electrode MT through through holes TH formed in the protective film PAS in each pixel. The pixel electrode PX is formed in the vicinity of the through hole TH so as to overlap with the intermediate electrode MT with a relatively large area, and constitutes a capacitor using the protective film PAS as a dielectric film, and this capacitor is also the capacitor. It is a capacity constituting the element CP.

  Further, as shown in FIG. 1, the pixel electrode PX has a pair of sides in a direction intersecting the traveling direction of the gate signal line GL, and one side overlaps the drain signal line DL (or the storage line STL). And the other side is formed so as to have a portion overlapping the storage line STL (or drain signal line DL). For example, when taking the first pixel PIX1 as an example, the left side SD (indicated by the symbol SD1 in the figure) of the pixel electrode PX is superimposed on the drain signal line DL disposed adjacent to the side SD1. The side SD on the right side of the drawing (indicated by the symbol SDr in the drawing) overlaps the third storage line STL3 arranged adjacent to this side. The pixel electrode PX overlaps the drain signal line DL with a certain length along the traveling direction of the drain signal line DL, and the pixel electrode PX overlaps the third storage line STL3. A certain length is made along. Since the pixel electrode PX is disposed with the organic protective film PAS2 interposed between the drain signal line DL and the third storage line STL3, the capacitance between the drain signal line DL and the third storage line STL3. Can be made small. This means that the pixel electrodes PX in the adjacent pixels can be arranged close to each other above the drain signal line DL or the third storage line STL3. For this reason, the pixel electrode PX can secure the maximum area in each pixel region. A region between pixels adjacent in the running direction of the gate signal line GL can be shielded by the drain signal line DL and the third storage line STL3. An alignment film is formed on the surface of the first substrate SUB1 on which the pixel electrode PX is formed so as to cover the pixel electrode PX, but this alignment film is omitted in FIGS. .

Further, as shown in FIGS. 3 and 4, on the liquid crystal side surface of the second substrate SUB2 disposed opposite to the first substrate SUB1 via the liquid crystal LC, a black matrix (light shielding film) BM, a color filter CF, A planarizing film OC, for example, a counter electrode CT made of an ITO film is formed. An alignment film is formed on the surface of the second substrate SUB2 on which the counter electrode CT is formed so as to cover the counter electrode CT, but this alignment film is omitted in FIGS. . Here, as shown in FIG. 4, the black matrix (light-shielding film) BM is also formed, for example, in a region between pixels adjacent in the running direction of the gate signal line GL. In this case, as described above, the drain signal line DL and the storage line STL formed on the first substrate SUB1 side also have the function of a light shielding film in the region. Each side of the pixel electrode PX that intersects the running direction of the gate signal line GL is formed so as to overlap the drain signal line DL or the storage line STL. From this, the black matrix (light-shielding film) BM formed on the second substrate SUB2 side can be formed in cooperation with the drain signal line DL and the storage line STL. Therefore, the width Wb of the black matrix (light shielding film) BM can be made smaller than, for example, the width Ws of the third storage line STL. Similarly, the width of the black matrix (light shielding film) on the drain signal line DL can be made smaller than the width of the drain signal line DL. Thus, the aperture ratio in each pixel can be greatly improved.

  FIG. 5 is a diagram showing Example 2 of the pixel configuration in the image display region of the liquid crystal display device of the present invention, and is a plan view corresponding to FIG.

  In FIG. 5, the configuration different from that in FIG. 1 is in the intermediate electrode MT, and other configurations are the same as those in FIG. That is, in the first pixel PIX1, the intermediate electrode MT1 formed so as to overlap the first storage line STL1 first extends along the traveling direction of the third storage line STL3 in the vicinity of the third storage line STL3. The first extending portion EX11 is provided. And this 1st extension part EX11 has a termination | terminus in the y direction in the figure, for example in the middle part of the 1st pixel PIX. The first extension portion EX11 extends with a relatively narrow width, and the side on the third storage line STL3 side partially overlaps the third storage line STL3, and is between the third storage line STL3. The fact that there is no gap is the same as in the case shown in FIG. Further, the intermediate electrode MT1 has a second extending portion EX12 formed so as to overlap with the first storage line STL1 extending in the second pixel PIX2 adjacent in the (+) x direction in the drawing. Is formed. Similarly, in the second pixel PIX2, the intermediate electrode MT2 formed so as to overlap the second storage line STL2 first extends in the vicinity of the third storage line STL3 along the traveling direction of the third storage line STL3. A first extending portion EX21 is provided. The first extending portion EX21 has a terminal end when it reaches, for example, the middle portion of the second pixel PIX in the (−) y direction in the drawing. The first extension portion EX21 extends with a relatively narrow width, and the side on the third storage line STL3 side partially overlaps the third storage line STL3, and between the third storage line STL3. No gap is formed. Further, the intermediate electrode MT2 has a second extension portion EX22 formed so as to overlap the second storage line STL1 extending in the first pixel PIX1 adjacent in the (−) x direction in the drawing. Is formed.

  Even in such a configuration, for example, in the first pixel PIX1, by providing the first extension portion EX11 and the second extension portion EX12 in the intermediate electrode MT1, the gap between the third storage line STL3 and each of the first extension portions EX11 and EX12 is provided. A new capacitor can be formed between the first storage line STL1 formed in the adjacent second pixel PIX2. In this case, the first extending portion EX11 and the second extending portion EX12 need only be formed so as to overlap the storage line STL, and can be formed while greatly reducing the aperture ratio of the pixel. Thus, the capacitance formed with the first storage line STL1 in the first pixel PIX1 can be reduced by the amount increased by the formation of the first extension portion EX11 and the second extension portion EX12. The area of the capacitive element in the portion can be reduced. Therefore, the aperture ratio of the first pixel PIX1 can be improved.

  In FIG. 5, the first extension portion EX1 of the intermediate electrode MT formed so as to overlap the third storage line STL3 is configured to be formed up to the middle portion of the pixel. In this case, the first extension part EX11 of the intermediate electrode MT1 in the first pixel PIX1 and the first extension part EX21 of the intermediate electrode MT2 in the second pixel PIX2 are back-to-back above the third storage line STL3. Since the arrangement (parallel arrangement) does not occur, the area overlapping the third storage line STL3 can be increased (the width of the first extension portion EX1 can be increased). However, the present invention is not limited to this, and the first extension portion of the intermediate electrode MT is extended so as to be close to the second storage line STL2 in the first pixel PIX1, and the first storage line in the second pixel PIX2. You may make it extend so that it may adjoin to STL1.

  In both the first and second embodiments described above, the protective film PAS is configured by laminating the organic protective film PAS2 on the inorganic protective film PAS1. However, the protective film PAS may be configured only by the inorganic protective film PAS1 without forming the organic protective film PAS2.

  Here, in the case of Example 1 and Example 2, as shown in FIG. 6 which is a cross-sectional view taken along the line VI-VI in FIG. 1, the pixel electrode PX on the first pixel PIX1 side and the second electrode are connected to the drain signal line DL. The pixel electrode PX on the pixel PIX2 side can be sufficiently overlapped. This is because it is not necessary to consider the capacitance generated between the drain signal line DL and the pixel electrode PX due to the formation of the organic protective film PAS2.

  However, when the protective film PAS is composed only of the inorganic protective film PAS1, as shown in FIG. 7 corresponding to FIG. 6, the pixel electrode PX on the first pixel PIX1 side and the pixel electrode PX on the second pixel PIX2 side are shown. May be difficult to be formed so as to overlap with the drain signal line DL, and must be formed slightly apart from the drain signal line DL in plan view. As a result, the aperture ratio of the pixel is slightly reduced. However, the above-described effect of the intermediate electrode MT can greatly improve the aperture ratio of the pixel regardless of the presence or absence of the organic protective film PAS2. Therefore, the present invention can be applied even in a configuration in which the organic protective film PAS2 is not formed.

  The present invention has been described using the embodiments. However, the configurations described in the embodiments so far are only examples, and the present invention can be appropriately changed without departing from the technical idea. Further, the configurations described in the respective embodiments may be used in combination as long as they do not contradict each other.

SUB1, SUB2 ... Substrate, PIX1 ... First pixel, PIX2 ... Second pixel, PG1 ... First pixel group, PG2 ... Second pixel group, GL1 ... First gate signal line, GL2 ... First 2 gate signal lines, DL... Drain signal line, BD ....... bent portion, STL1... First storage line, STL2... Second storage line, STL3. , DT ... Drain electrode, ST ... Source electrode, CP, CP1, CP2 ... Capacitance element, MT, MT1, MT2 ... Intermediate electrode, EX1, EX11, EX 21 ... First extension part, EX2, EX 12 , EX 22, second extension, GI, insulating film, PAS, protective film, PAS 1, inorganic insulating film, PAS 2, organic insulating film, TH, through hole, PX, pixel electrode , BM: Black matrix (light shielding film), CF: Color filter, OC: Flattening film, CT: Counter electrode.

Claims (4)

A thin film transistor controlled by a signal from a gate signal line, a drain signal line for supplying a video signal, a pixel electrode to which a video signal from the drain signal line is supplied, and formed between the pixel electrode and the storage line A liquid crystal display device comprising a capacitive element and an intermediate electrode extending from a source electrode of the thin film transistor and electrically connecting the pixel electrode and the thin film transistor,
The first pixel and the second pixel are repeatedly arranged in this order in the first direction to form a pixel group,
A first gate signal line and a second gate signal line are disposed across the pixel group, the thin film transistor of the first pixel is controlled by a scanning signal from the first gate signal line, and the thin film transistor of the second pixel Is controlled by a scanning signal from the second gate signal line,
The drain signal line, the first pixel and the a plurality of arranged so as to sandwich the second pixel, each pixel electrode in the video signal of the first pixel and the second pixel positioned at both sides of the drain signal lines Supply
The storage line is electrically connected to the first storage line adjacent to the first gate signal line, the second storage line adjacent to the second gate signal line, and the first storage line and the second storage line. A third storage line connected between the first pixel and the second pixel, wherein the drain signal line is connected and the drain signal line does not travel;
The intermediate electrode of the first pixel includes a first extension portion of the first pixel extending along the third storage line to a middle portion of the first pixel, and a first extension portion of the first pixel. A second extending portion of a second pixel connected and extending along the first storage line,
The intermediate electrode of the second pixel includes a first extension portion of the second pixel extending along the third storage line to a middle portion of the second pixel, and a first extension portion of the second pixel. A liquid crystal display device comprising: a second extending portion of a first pixel connected and extending along the second storage line. The liquid crystal display device according to claim 1 , wherein the pixel electrode has a portion in which a side adjacent to the drain signal line overlaps the drain signal line. On the substrate, a protective film made of an organic insulating film to cover the thin film transistor is formed, the pixel electrode according to claim 1, 2, characterized in that formed on the upper surface of the protective film Liquid crystal display device. A first pixel group in which the first pixel and the second pixel are repeatedly arranged in this order along the first direction; and a first pixel group arranged adjacent to the first pixel group in a direction intersecting the first direction. A second pixel group, and the second pixel group is arranged to be shifted by a half pitch of the pixel with respect to the first pixel group,
2. The liquid crystal display device according to claim 1 , wherein the drain signal line has a bent portion in a region between the first pixel group and the second pixel group.

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