JP5502360B2 - Zinc oxide based semiconductor device and method for manufacturing the same - Google Patents

Description

  The present invention relates to a method for manufacturing a zinc oxide (ZnO) based semiconductor device, and more particularly to a ZnO based compound semiconductor device in which a contact electrode having high adhesion and good ohmic contact is formed, and a method for manufacturing the same.

  Zinc oxide (ZnO) is a direct transition type semiconductor having a band gap energy of 3.37 eV at room temperature, and is expected as a material for optical elements in the blue or ultraviolet region. In particular, the exciton binding energy is 60 meV and the refractive index n = 2.0, which is very suitable for a semiconductor light emitting device. Further, the present invention can be widely applied not only to light emitting elements and light receiving elements but also to electronic devices such as surface acoustic wave (SAW) devices and piezoelectric elements. In addition, the raw material is inexpensive and harmless to the environment and the human body.

  It is generally known that oxide crystals and metals have poor adhesion and are easy to peel off. That is, for semiconductors that do not contain oxygen (for example, AlGaAs, InAlGaP, InGaN, etc.), adhesion to electrode metals and adhesion were not a major problem. However, a ZnO-based semiconductor that is a metal oxide has particularly poor adhesion to metal materials such as gold (Au), silver (Ag), rhodium (Rh), platinum (Pt), and palladium (Pd). Accordingly, there has been a problem that these metal electrodes formed on the ZnO film are peeled off in the process of producing the p-type electrode (for example, Patent Document 1 and Patent Document 2).

  Further, when heat treatment (alloying, sintering, etc.) is performed after the electrode is formed in order to reduce the contact resistance between the p-type Zn oxide layer and the electrode (improvement of ohmic contact), peeling of the electrode becomes remarkable. There's a problem. As described above, the electrode of a semiconductor element such as a semiconductor light emitting element is subjected to heat stress or external resistance in various manufacturing processes such as a heat treatment process for reducing contact resistance, a die bonding process, a wire bonding process, or a resin sealing process. Stress. Further, various stresses are applied even after manufacturing. For example, thermal stress is applied in an element sealing step or a step of bonding to a circuit board. Further, mechanical stress due to the sealing resin is also applied in the sealing process. Furthermore, it receives various stresses due to heat and stress even during use of the semiconductor element. For example, when a semiconductor light emitting device or the like is used for a vehicle such as an automobile, the interior temperature of the automobile, the engine room temperature, heat shock due to day and night or seasonal fluctuations, exposure to ultraviolet rays due to sunlight, moisture and atmospheric gases (for example, sulfide It is subject to various stresses such as heat and stress due to corrosion by substances, chlorine, ozone). Therefore, it is important to form an electrode having high peel strength against various stresses in order to secure device performance, manufacturing yield, and reliability.

  On the other hand, since ZnO-based compounds are wide band gap semiconductors, metal materials with good ohmic properties that can be used as p-type electrodes are limited. Therefore, it is extremely important to realize a ZnO-based semiconductor element that a good low-resistance ohmic contact can be obtained and the formation of a metal electrode with high adhesion is achieved.

JP 2003-110142 A JP 2004-207440 A

  However, until now, sufficient studies have not been made on the formation of contact electrodes having good ohmic contact and high adhesiveness with respect to ZnO-based compound semiconductor crystals.

  The present invention relates to a method of forming a contact electrode having high adhesion without causing peeling of the electrode of such a p-type ZnO-based compound semiconductor and having good ohmic contact, a ZnO-based compound semiconductor device having the electrode formed thereon, and It is in providing the manufacturing method. In addition, a ZnO-based compound semiconductor device having high performance, high manufacturing yield and reliability, and a method for manufacturing the same, maintaining high adhesion and device operating characteristics against stress due to heat and stress in the manufacturing process and use environment. It is to provide.

The manufacturing method of the present invention is a method of manufacturing a zinc oxide (ZnO) based semiconductor element having at least a p-type ZnO based semiconductor layer,
the p-type ZnO based semiconductor layer, a first metal layer forming step of forming a first metal layer consisting of at least one Ni (nickel) and Cu (copper) in an island-like or mesh,
Following the first metal layer forming step, heat treatment is performed on the first metal layer and the p-type ZnO-based semiconductor layer in a reducing atmosphere to leave a metal phase layer on the surface of the first metal layer, and p A heat treatment step of forming a mixed layer composed of an element of the p-type ZnO-based semiconductor layer and an element of the first metal layer at the interface between the type-ZnO-based semiconductor layer and the first metal layer;
After the heat treatment step, a second metal layer made of at least one of Pt (platinum), Rh (rhodium), Pd (palladium), and Ir (iridium) is formed into the first metal layer and the first metal layer. And a second metal layer forming step of covering the p-type ZnO-based semiconductor layer exposed from the opening.

Furthermore, the ZnO-based semiconductor element of the present invention is a ZnO-based semiconductor element having at least a p-type ZnO-based semiconductor layer,
A first metal layer formed in an island-like or net-like on at least one from it ,, p-type ZnO based semiconductor layer of Ni and Cu,
A second metal layer made of at least one of Pt, Rh, Pd, and Ir, and formed to cover the first metal layer and the p-type ZnO-based semiconductor layer exposed from the opening of the first metal layer; And a metal layer,
The first metal layer is formed on the surface side of the first metal layer at the interface between the metal phase of the element of the first metal layer and the p-type ZnO-based semiconductor layer and the first metal layer. And a mixed layer made of the element of the p-type ZnO-based semiconductor layer and the element of the first metal layer.

Furthermore, the forming method of the present invention is a method for forming a contact electrode of a p-type ZnO-based semiconductor,
the p-type ZnO based semiconductor layer, a first metal layer forming step of forming a first metal layer consisting of at least one of Ni and Cu in an island-like or mesh,
Following the first metal layer forming step, heat treatment is performed on the first metal layer and the p-type ZnO-based semiconductor layer in a reducing atmosphere to leave a metal phase layer on the surface of the first metal layer, and p A heat treatment step of forming a mixed layer composed of an element of the p-type ZnO-based semiconductor layer and an element of the first metal layer at the interface between the type-ZnO-based semiconductor layer and the first metal layer;
After the heat treatment step , the p-type ZnO-based material in which the second metal layer made of at least one of Pt, Rh, Pd, and Ir is exposed from the opening of the first metal layer and the first metal layer. And a second metal layer forming step for forming the semiconductor layer so as to cover the semiconductor layer.

  The first metal layer may have an average layer thickness within a range of 3 nm to 15 nm.

The reducing atmosphere may be a nitrogen gas atmosphere mixed with hydrogen gas .

  In addition, the temperature of the heat treatment can be in the range of 350 ° C. to 450 ° C.

It is a flowchart which shows the procedure of the manufacturing method of the semiconductor element by this invention. It is sectional drawing which shows the board | substrate with an LED device layer in which the zinc oxide type compound semiconductor layer was grown on the ZnO board | substrate. It is sectional drawing which shows the outline | summary of the manufacturing process of an LED element. It is sectional drawing for demonstrating the detail of the formation process of a p side electrode. It is the top view of the manufactured LED element, and sectional drawing in the AA shown in a top view. The threshold voltage of the VI characteristic of LED by Example 1, and LED of the comparative examples 1 and 2 and the evaluation result of peeling of the p side electrode are shown. It is a figure which illustrates typically the effect of the heat processing in the case of forming the electrode metal of the 1st p electrode layer on a ZnO system crystal layer, and has shown the contact portion expanded. It is a typical partial enlarged view for explaining in detail the mixed region formed at the interface between the ZnO-based crystal layer and the first p-electrode layer. It is sectional drawing which expands and shows the contact part of the p side electrode in the boundary part W (FIG.3 (c)) of a translucent electrode and a p side electrode. It is the top view of the LED element which is Example 2, and sectional drawing in the AA line shown to a top view. 6 is an enlarged cross-sectional view schematically showing a configuration of a p-side electrode of an LED element according to Example 2. FIG. It is the top view of the LED element which is Example 3, and sectional drawing in the AA line shown to a top view. 6 is an enlarged cross-sectional view schematically showing a configuration of a p-side electrode of an LED element according to Example 3. FIG.

  In the following, a method for forming a crystal layer of a ZnO-based compound semiconductor on a zinc oxide (ZnO) substrate, forming a metal electrode on the crystal stack, and a method for manufacturing a semiconductor element with the electrode formed will be described with reference to the drawings. Will be described in detail. Further, a case where a semiconductor layer used for manufacturing a semiconductor light emitting element (LED: Light Emitting Diode) is grown as the semiconductor crystal laminate will be described as an example.

  A method for manufacturing a semiconductor light emitting device according to the present invention will be described in detail with reference to the flowchart shown in FIG. FIG. 2 is a cross-sectional view showing a substrate 17 with an LED device layer in which a zinc oxide-based compound semiconductor layer (hereinafter referred to as a ZnO-based crystal layer or a ZnO-based semiconductor layer) is grown on a ZnO substrate 10.

Using a RS-MBE (radical source molecular beam growth) apparatus, ZnO-based compound semiconductor crystal layers were sequentially stacked on the substrate 10 (FIG. 1, step S11). Zinc (Zn), magnesium (Mg), and gallium (Ga), which are metal materials, were irradiated with a Knudsen cell and supplied to the substrate 10. Oxygen (O) and nitrogen (N) as gas materials were irradiated (supplied) as oxygen radicals (denoted as O ^* ) and nitrogen radicals (denoted as N ^* ) in an RF radical generator. The substrate 10 was heated with a resistance heater.

  The substrate 10 is made of a ZnO single crystal whose principal surface is the {0001} plane of the wurtzite structure, and has a thickness of, for example, 500 micrometers (μm). More specifically, a ZnO-based crystal layer was grown on the substrate 10 using the Zn polar plane (+ c plane) as a crystal growth plane.

  As shown in FIG. 2, first, a buffer layer 11, which is a ZnO layer having a thickness of 30 nm, was grown on the + c plane of the ZnO substrate 10. The buffer layer 11 is a so-called low temperature growth buffer layer, and the growth temperature (Tg) was 300 ° C. Further, after the growth of the buffer layer 11, a heat treatment (annealing) at a temperature T = 900 ° C. for 5 minutes (min) was performed.

Next, the first n-type ZnO-based crystal layer 12A and the second n-type ZnO-based crystal layer 12B were sequentially grown on the buffer layer 11 at a growth temperature Tg = 900 ° C. The first n-type ZnO-based crystal layer 12A is a ZnO layer having a thickness of 300 nanometers (nm) and a gallium (Ga) concentration of 3 × 10 ¹⁸ cm ⁻³ , and the second n-type ZnO-based crystal. The layer 12B was a Mg _0.2 Zn _0.8 O layer having a thickness of 50 nm and a Ga concentration of 3 × 10 ¹⁸ cm ⁻³ .

  A light emitting layer 13 was grown on the second n-type ZnO-based crystal layer 12B at a growth temperature Tg = 900 ° C. The light emitting layer 13 was an undoped ZnO layer having a thickness of 30 nm.

Next, the first p-type ZnO-based crystal layer 14A and the second p-type ZnO-based crystal layer 14B were sequentially grown on the light-emitting layer 13 at a growth temperature Tg = 700 ° C. The first p-type ZnO-based crystal layer 14A was a Mg _0.2 Zn _0.8 O layer having a thickness of 30 nm and a nitrogen (N) concentration of 1 × 10 ²⁰ cm ⁻³ . The second p-type ZnO-based crystal layer 14B was a ZnO layer having a thickness of 100 nm and a nitrogen concentration of 1 × 10 ²⁰ cm ⁻³ .

  In the following, a layer composed of the first n-type ZnO-based crystal layer 12A and the second n-type ZnO-based crystal layer 12B is referred to as an n-type ZnO-based crystal layer 12 and a first p-type ZnO-based crystal layer 14A. The layer composed of the second p-type ZnO-based crystal layer 14B is also referred to as a p-type ZnO-based crystal layer 14. In addition, a laminated structure including the n-type ZnO-based crystal layer 12, the light emitting layer 13, and the p-type ZnO-based crystal layer 14 is referred to as a device layer (LED device layer) 15. In addition, although the case where each of the n-type ZnO-based crystal layer 12 and the p-type ZnO-based crystal layer 14 includes a plurality of crystal layers having different compositions and thicknesses is illustrated, each may be a single layer. In this way, a device layer (LED device layer) 15 composed of the n-type ZnO-based crystal layer 12, the light emitting layer 13, and the p-type ZnO-based crystal layer 14 was formed (FIG. 1, step S11).

  Here, the device layer refers to a layer composed of a semiconductor to be included for the semiconductor element to perform its function. For example, a simple transistor includes a structural layer formed by a pn junction of an n-type semiconductor, a p-type semiconductor, and an n-type semiconductor (or a p-type semiconductor, an n-type semiconductor, and a p-type semiconductor).

  In addition, a semiconductor structure layer that includes a p-type semiconductor layer, a light-emitting layer, and an n-type semiconductor layer (or a p-type semiconductor layer and an n-type semiconductor layer) and that emits light by recombination of injected carriers, It is called a light emitting device layer. In particular, in the case of an LED, it is also referred to as an LED device layer.

  Note that the crystal growth method is not limited to the RS-MBE method. That is, a growth method such as a MOCVD (Metal Organic Chemical Vapor Deposition) method or a PLD (pulse laser deposition) method may be used.

In addition, the configuration of the buffer layer 11, the n-type ZnO-based crystal layer 12, the light-emitting layer 13, and the p-type ZnO-based crystal layer 14, or the first n-type ZnO-based crystal layer 12A and the second n-type ZnO-based crystal layer. 12B, the configuration of the first p-type ZnO-based crystal layer 14A and the second p-type ZnO-based crystal layer 14B, that is, the composition, layer thickness, dopant concentration, etc. of these layers are generally used for device manufacturing. It's okay. For example, the buffer layer 11 may be a Mg _x Zn _{(1-x) 2} O (0 ≦ x <0.43) layer that is a ZnO-based crystal containing, for example, magnesium (Mg). The buffer layer 11 is an n-type Mg _x Zn _(1-x) O (0 ≦ x <0.43) layer doped with an impurity (for example, Ga) and having a thickness of several nm to several μm, for example. be able to. The n-type ZnO-based crystal layer 12 has an n-type thickness of about 10 nm to several μm doped with impurities (for example, Ga) within a concentration range of about 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ^−3, for example. Type Mg _x Zn _(1-x) O (0 ≦ x <0.43) layer. The light emitting layer 14B is an SQW (single quantum well) layer comprising a quantum well layer and a barrier layer each having a thickness of several nanometers, or an MQW (multiple quantum well) layer having a plurality of quantum well layers and barrier layers, or a single layer. An Mg _x Zn _(1-x) O (0 ≦ x <0.43) layer having a composition can be used.

The p-type ZnO-based crystal layer 14 may be a p-type Mg _x Zn _(1-x) O (0 ≦ x <0.43) layer. The p-type ZnO-based crystal layer 14 is, for example, p-type Mg _x Zn _{(1-x) 2} O having a thickness of several tens of nm to several μm doped with N (nitrogen) at a concentration of about 1 × 10 ²⁰ cm ^−3. (0 ≦ x <0.43) layer.

As described above, these compositions, layer thicknesses, dopant concentrations, and the like are merely examples, and can be appropriately selected so as to obtain necessary device characteristics.
[Configuration and formation of p-side electrode]
Next, a ZnO-based compound semiconductor element (LED) was fabricated using the thus-formed substrate with an LED device layer (hereinafter, also simply referred to as a substrate with a device layer) 17. FIG. 3 is a cross-sectional view showing an outline of the manufacturing process of the LED element. 4A to 4C are cross-sectional views for explaining details of the p-side electrode forming step, and FIGS. 5A and 5B are top views of the manufactured LED element 30. FIG. Sectional drawing in the AA line is shown, respectively.

  First, a p-side electrode was formed on the p-type ZnO-based crystal layer 14 of the substrate 17 with a device layer. More specifically, a resist mask having an opening in the shape of the translucent electrode 21 (see FIG. 5A and a top view) was formed using a photolithography technique. More specifically, the translucent electrode 21 has a rectangular shape, and a contact region having a circular shape (diameter: 100 μm) at the center for ohmic contact between a p-side electrode 22 and a p-type ZnO-based crystal layer 14 described later. The resist was patterned so that (CR) was formed. In the present example, the translucent electrode 21 was formed in a square shape of 270 μm (D3), each side being approximately 15 μm smaller than the square element partition size having a side of D2 (300 μm) (FIG. 5). . The element was formed in a square shape having a side of 400 μm (D1) and a thickness of 200 μm as described later.

  Next, Ni (nickel) and Au (gold) were sequentially deposited at a thickness of 5 nm and 30 nm, respectively, by electron beam (EB) deposition to form a Ni / Au layer (FIG. 3A). For example, a structure in which Ni is stacked as the first layer and Au is stacked as the second layer is referred to as a Ni / Au layer, and the same applies to the following. Then, the Ni / Au layer other than the mask opening was removed by a lift-off method (FIG. 3B).

Next, the Ni / Au layer was subjected to a transparent treatment using a RTA (rapid thermal annealer) apparatus under the conditions of 450 ° C. and 30 seconds (seconds). Nitrogen gas containing 20% oxygen was used as the atmospheric gas. Through this step, Ni in the Ni / Au layer is oxidized to nickel oxide (NiO, Ni ₂ O), and the translucent electrode 21 is made translucent.

  Next, a p-side electrode 22 composed of three p-electrode layers was formed (FIG. 3C). In the following description, these layers will be referred to as first, second, and third p-electrode layers 23, 24, and 25, respectively.

  First, a metal mask opened in the shape of the p-side electrode 22 (see FIG. 5A, circular in this embodiment) was set in a metal mask cell. Next, the substrate was set so that the center of the mask opening coincided with the center of the translucent electrode 21 formed by the above process. Then, as schematically shown in FIG. 4A, Ni (nickel) as an electrode metal of the first p-electrode layer 23 (contact electrode) is formed in an island shape or a mesh shape on the p-type ZnO-based crystal layer 14. It formed so that it might exist (step S12 of FIG. 1).

As a method for forming the island-like or network-like metal layer (Ni layer), a resistance heating vapor deposition method capable of forming a vapor deposition metal particle size relatively large was used. Furthermore, reducing gas (H ₂ ) is introduced into the vapor deposition chamber with an MFC (mass flow controller) or the like, and the vapor deposition pressure is slightly increased (about 10 times the normal operating pressure, 1 × 10 ⁻⁴ Pa (pascal)). ) To increase the particle size of the deposited metal. The average layer thickness of the island-like or network-like metal thus formed was 10 nm, and the particle size was within a range of variation of about φ10 nm to φ100 nm. Separately, a vapor deposition film was deposited on the sapphire substrate by the above method, the electrical resistance of the deposited vapor deposition film was measured, and vapor deposition was performed using a non-conducting or high resistance region (vapor deposition conditions). .

  Next, the metal mask cell on which the substrate was set was set in an RTA apparatus, nitrogen gas mixed with 3% of hydrogen gas was supplied as an atmosphere gas, and heat treatment (annealing) was performed at 400 ° C. for 1 second in a reducing atmosphere ( FIG. 1, step S13). Thereby, the first p-electrode layer 23 was formed.

  Next, again, the metal mask cell is set in the EB vapor deposition apparatus, Pt (platinum) is vapor-deposited as a barrier metal with a thickness of 100 nm, the second p electrode layer 24 is formed, and the second p electrode layer 24 is formed. Then, Au (gold) as a connection electrode (pad electrode) metal was vapor-deposited with a thickness of 1000 nm to form a third p-electrode layer 25 (FIGS. 4B and 4C, step S14 in FIG. 1). . Thus, the p-side electrode 22 composed of the first, second and third p-electrode layers 23, 24, 25 was formed.

  As described above, in the first p-electrode layer 23, the electrode metal (Ni) is formed in an island shape or a mesh shape. That is, the island-shaped or network-shaped metal (Ni) layer is formed to have the opening OP. Then, by the vapor deposition of the second p-electrode layer 24, the island-shaped or network-shaped first p-electrode layer 23 (Ni layer) is included in the second p-electrode layer 24, that is, embedded. Is formed. In other words, the entire surface of the first p-electrode layer 23 (Ni layer) is covered with the second p-electrode layer 24. Further, in a portion where the metal (Ni) of the first p electrode layer 23 is not formed on the p-type ZnO-based crystal layer 14 (that is, the opening OP), the metal (Pt of the second p electrode layer 24). ) Is in direct contact with and covers the p-type ZnO-based crystal layer 14. That is, the second p electrode layer 24 is formed so as to cover the p-type ZnO-based semiconductor layer exposed from the opening OP of the first p-electrode layer 23 (exposed portion of the p-type ZnO-based semiconductor layer). Has been.

  Next, on the surface side where the p-side electrode 22 was formed, a resist mask having an opening in the shape of an element section (a square having a side D2; FIG. 5) was formed using a photolithography technique. Etching was performed to a depth at which a part of the n-type ZnO-based crystal layer 12 was partially removed by wet etching to form an element partition groove (G) (FIG. 3D).

  The surface side on which the p-side electrode 22 was formed was affixed to a support, and the back surface of the device layer-equipped substrate 17 was ground and mirror-polished so that the thickness was about 200 μm. Next, by photolithography and EB vapor deposition, Ti and Au are vapor-deposited at a thickness of 100 nm and 1000 nm, respectively, on the back surface of the substrate 17 with the device layer (Ti / Au = 100 nm / 1000 nm), and have the same shape as the element section. An n-side electrode 28 was formed (step S15 in FIG. 1, FIG. 3D). A Ti / Rh / Au layer can be used as the ohmic electrode metal layer of the n-side electrode 28. For example, the thicknesses of these layers are Ti / Rh / Au = 3 to 30 nm / 50 to 100 nm / 500 to 1000 nm, or Ti / Rh / Au = 10 nm / 80 nm / 1000 nm. Alternatively, a Ti / Al / Au layer can be used as the n-side ohmic electrode metal layer. For example, the thickness of each layer is Ti / Al / Au = 3 to 30 nm / 50 to 100 nm / 500 to 1000 nm, or Ti / Al / Au = 10 nm / 80 nm / 1000 nm.

  The device layer-equipped substrate 17 on which the formation of the n-side electrode 28 has been completed was scribed and braked along the element partitioning grooves (G), and separated into individual semiconductor light emitting elements (LEDs) (see FIG. 1). Step S16). FIGS. 5A and 5B are a top view and a cross-sectional view of the semiconductor light emitting device (LED) manufactured as described above. In addition, the arrow in a figure has shown the light extraction direction.

[Evaluation of electrical characteristics and adhesion]
The electrical characteristics and adhesiveness of the semiconductor light emitting device (LED) manufactured according to Example 1 described above were evaluated in comparison with the comparative example. Specifically, the ohmic characteristics of the LED of Example 1 and the LEDs of Comparative Examples 1 and 2 are evaluated based on the threshold voltage of the VI characteristic, and whether or not electrode peeling occurs at the time of wire bonding with respect to the adhesive strength of the p-side electrode. It was evaluated by. In addition, assuming a thermal history associated with device mounting, a heat treatment of nitrogen gas atmosphere, 350 ° C., 15 seconds was added to the devices of Example 1 and Comparative Examples 1 and 2, and then the same evaluation as described above was performed. . Note that the number of samples in Example 1 and Comparative Examples 1 and 2 was 25, and evaluation was performed using a total of 75 samples.

(Comparative Example 1 and Comparative Example 2)
In the LED of Comparative Example 1, Ni was used as the first p electrode layer, and Au (gold) was used as the second p electrode layer. More specifically, Ni / Au was vapor-deposited at a thickness of 30 nm / 1000 nm, respectively, by electron beam (EB) vapor deposition to form a p-side electrode. Note that the first and second p-electrode layers were not annealed. Points other than the configuration and formation method of the p-side electrode are the same as in the case of Example 1. That is, the configuration of the semiconductor crystal layer, the translucent electrode, the n-side electrode, and other element forming methods are the same as those in the first embodiment.

In the LED of Comparative Example 2, Ni was used as the first p electrode layer. That is, Ni was formed with a thickness of 30 nm by electron beam evaporation. Then, after vapor deposition, annealing was performed at 450 ° C. for 1 minute in nitrogen gas (oxygen atmosphere or oxidizing gas atmosphere) mixed with 20% oxygen gas by an RTA apparatus. That is, the first p-electrode layer including the surface portion was formed as nickel oxide (NiO + Ni ₂ O) by such annealing.

  After annealing, Au was deposited as a second p-electrode layer with a thickness of 1000 nm by electron beam evaporation to form a p-side electrode. Note that points other than the configuration and formation method of the p-side electrode are the same as in the case of Example 1.

(Evaluation results)
FIG. 6 collectively shows the threshold voltage of the VI characteristics of the LED according to Example 1 and the LEDs of Comparative Examples 1 and 2 and the evaluation results of the p-side electrode peeling. In addition, assuming a thermal history after element manufacture, for example, a thermal process accompanying element mounting such as solder reflow (temperature: about 230 ° C. to 270 ° C.) or Au / Sn bonding (temperature: about 300 to 350 ° C.) in die bonding, The evaluation results of the threshold voltage and electrode peeling after applying heat treatment at 350 ° C. for 15 seconds to the manufactured element are also shown.

  The rise of the VI curve of the LED of Example 1 was steep, the threshold voltage (VT) was low, and good diode characteristics and ohmic contact were obtained. Specifically, as shown in FIG. 6, the threshold voltage VT of the sample of Example 1 was as low as 3.3V to 3.6V. It was also found that stable characteristics can be obtained without change even after the heat treatment of the element.

  On the other hand, the threshold voltage VT of the sample of Comparative Example 1 was as high as 4.2 V to 5.3 V, and the variation (dispersion) of the threshold voltage value was large. Furthermore, after the element heat treatment, there were many samples that could not be measured (opened) due to electrode peeling. Even for the samples that could be measured, the threshold voltage VT was as high as about 5.8V. Further, the sample of Comparative Example 2 was the same as the sample of Comparative Example 1, and the threshold voltage VT was as high as 3.6 V to 4.8 V, and the variation in value was large. Even after the heat treatment of the element, there were many samples that could not be measured (opened) due to the occurrence of electrode peeling.

  As an evaluation of electrode adhesion, the samples of Example 1, Comparative Example 1, and Comparative Example 2 were die-bonded to the stem with an Ag (silver) paste, and then Au wire bonding was performed. All the samples of Example 1 were free from electrode peeling and wire bonding was possible. In some samples, bonding failure occurred, but not due to electrode adhesion, but due to die bonding position failure. In addition, wire bonding was possible without problems even after the heat treatment of the element.

  In the samples of Comparative Examples 1 and 2, electrode peeling occurred with considerable frequency during wire bonding. Moreover, the peeling variation between sample lots was large, and the yield was good with a yield of 60% to 70%, and the yield was poor with a yield of about 20% to 30%. Further, after the heat treatment, many spontaneous peeling of electrodes and peeling during bonding occurred, and the yield was about 5 to 10%.

  From the above evaluation, it was demonstrated that the electrode structure and the electrode manufacturing method of Example 1 have excellent ohmic characteristics as an electrode for a ZnO-based semiconductor element, as well as high electrode adhesion and adhesion strength. In addition, it was demonstrated that excellent characteristics were maintained even in the heat process after the device was manufactured, and that the heat resistance was also excellent.

[Examination of improvement of ohmic characteristics and adhesion]
In this example, the point that the ohmic characteristics and adhesiveness of the p-side electrode were greatly improved was examined. The mechanism for improving these characteristics will be described in detail below with reference to the drawings.

  7A and 7B, the electrode metal (Ni) of the first p electrode layer 23 is deposited on the p-type ZnO-based crystal layer 14 in an island shape or a mesh shape, and heat treatment (annealing) is performed. It is a figure explaining the effect in the case typically, and has expanded and showed the contact part of the p-type ZnO type | system | group crystal layer 14 and an electrode metal. FIG. 7C is a cross-sectional view when the second p-electrode layer 24 and the third p-electrode layer 25 are formed on the first p-electrode layer 23 after annealing.

  As shown in FIG. 7A, in the first embodiment, in the formation of the first p-electrode layer 23, Ni (nickel), which is a metal that is easily oxidized, is used as the electrode metal, and the p-type ZnO-based crystal layer 14 is used. It deposited in the shape of islands or meshes by evaporation. After vapor deposition, island-like or network-like metal (Ni) is in contact with the p-type ZnO-based crystal layer 14. As described above, the metal (Pt) of the second p-electrode layer 24 is in direct contact with the p-type ZnO-based crystal layer 14 in the opening OP of the island-shaped or network-shaped metal layer.

  In the following, for ease of explanation and ease of understanding, the island-shaped or mesh-shaped metal (Ni) is an island shape, that is, an electrode metal (Ni) island (island) IS. Although the case will be described, the same applies to the case where a plurality of islands IS are combined to form a network, or the case where the islands and the network are mixed.

  In this example, after depositing Ni, annealing was performed in a reducing atmosphere (oxygen-free atmosphere). By such annealing, as shown in FIG. 7B, these atoms are in various states at the interface (IF) between the p-type ZnO-based crystal layer 14 and the island IS (Ni) of the first p electrode layer 23. It is considered that a bonded and mixed region (hereinafter referred to as a mixed region) 23A was formed. In addition, a pure metal layer (Ni layer) 23B remains on a portion other than the mixed region 23A of the island IS, that is, on the surface of the island IS.

  More specifically, in annealing in a reducing atmosphere (or oxygen-free atmosphere or non-oxidizing atmosphere), oxygen (O) is supplied only from a ZnO-based crystal (p-type ZnO-based crystal layer 14). Therefore, annealing causes interdiffusion of atoms present at the interface. Further, the easily oxidized metal (Ni) changes from the metal layer to the oxide layer continuously in accordance with the amount of oxygen diffusing from the interface. That is, a double-sided layer capable of forming a metal bond with a metal and a covalent bond with an oxide is formed. Specifically, oxygen (O) atoms in the ZnO-based crystal move into Ni deposited on the ZnO-based crystal, and the movement of Ni atoms into the ZnO-based crystal is promoted. As a result, a mixed region 23A in which Zn, Ni, and O are mixed and combined in various states is formed in the interface (IF) region between the p-type ZnO-based crystal layer 14 and the island IS.

FIG. 8 is a partially enlarged cross-sectional view schematically showing the interface region of the island IS between the p-type ZnO-based crystal layer 14 and the first p-electrode layer 23 after annealing. The mixed region 23A will be described in more detail. As shown in FIG. 8, the mixed region 23A is composed of a mixed crystal phase (ZnO) mainly composed of ZnO and NiO sequentially from the ZnO crystal (p-type ZnO-based crystal layer 14) side. -O-Ni) and a mixed region 23A2 mainly composed of layers of ZnO, NiO phase and Ni metal phase (NiO, Ni ₂ O + Ni metal). The thickness of the mixed region 23A is estimated to be several monolayers (atomic layers) to about ten or more monolayers in view of the average layer thickness and particle size (island diameter) of the deposited Ni layer. These regions are not completely separated, and it is considered that the state and thickness of these regions differ depending on annealing conditions such as temperature.

  Furthermore, as another viewpoint, in the process of such interface oxidation, there is no change in the number of atoms in the interface region, and the volume change is small. Therefore, the internal strain of the mixed region itself is small, and further, since the Ni vapor deposition layer is island-like or network-like, the volume change and the stress change are also small, so there is no opening and the p-type ZnO-based crystal layer 14 Compared with the case where it is in the form of a layer covering the whole, the effect of preventing peeling is great. Further, since it is a mixed region of a relatively hard oxide and a relatively soft metal, even if a volume change occurs, the stress is absorbed.

  Further, as described above, under the annealing conditions according to this example, the surface of the island-like or network-like vapor-deposited layer has no supply or movement of oxygen (O) from the atmosphere gas and ZnO crystal, and is pure. A single layer (Ni metal layer) 23B of a metal phase made of metal (Ni) remains.

  FIG. 9 is an enlarged cross-sectional view showing the contact portion of the p-side electrode 22 in the boundary portion W (FIG. 3C, FIG. 5B) between the translucent electrode 21 and the p-side electrode 22. A mixed region 23A is formed at the interface portion between the p-type ZnO-based crystal layer 14 and the first p-electrode layer 23 (island IS), and a metal layer is formed on the surface portion of the island IS of the first p-electrode layer 23. (Ni layer) 23B remains. A second p electrode layer 24 is formed as a barrier metal (Pt or the like) on the first p electrode layer (Ni layer) 23B, and a connection electrode (pad electrode) is formed on the second p electrode layer 24. ), A third p-electrode layer 25 is formed.

  According to the present invention, the p-side electrode 22 having extremely excellent adhesion and adhesion can be obtained from the following various points.

  First, as described above, the single phase layer 23B of the metal phase remains on the surface portion of the vapor deposition layer, so that the adhesion and adhesion of the second p-electrode layer 24 to the barrier metal are extremely excellent. Furthermore, since a mixed region is formed at the interface (IF) between the p-type ZnO-based crystal layer 14 and the island-shaped or network-shaped first p-electrode layer 23, the p-type ZnO-based crystal layer 14 and the first p-type ZnO-based crystal layer 14 High adhesion and adhesion strength can be obtained even between the p electrode layers 23. In other words, the first p-electrode layer 23 is bonded to the p-type ZnO-based crystal layer 14 as an oxide crystal and is bonded to the second p-electrode layer 24 as a metal, that is, oxidation. The structure has high adhesion to both the object and the metal.

  In addition, good adhesion between the second p-electrode layer 24 and the p-type ZnO-based crystal layer 14 can be obtained via the first p-electrode layer 23. More specifically, the second p electrode layer 24 (barrier metal) has a structure in contact with the p-type ZnO-based crystal layer 14 in the opening OP of the first p electrode layer 23 (Ni layer). Compared with the case where the barrier metal is formed on the entire surface of the p-type ZnO-based crystal layer 14, the peeling stress is diffused. That is, when the second p-electrode layer (barrier metal) is formed on the entire surface of the p-type ZnO-based crystal layer 14, stress concentration tends to occur, but the first p-electrode layer 23 has an island shape or a mesh shape. Therefore, the stress is diffused and peeling is difficult to occur. Further, even if a small peeling occurs at a part of the second p electrode layer 24, the peeling is prevented from being derived therefrom. That is, the separation of the second p-electrode layer 24 from the p-type ZnO-based crystal layer 14 in the opening OP propagates laterally on the surface of the p-type ZnO-based crystal layer 14 from the portion where the separation occurs. This is because the propagation of delamination is stopped by the first p-electrode layer 23 (island IS) in the shape of a mesh or mesh.

  The area occupancy (or coverage) of the first p-electrode layer 23 on the p-type ZnO-based crystal layer 14 is preferably in the range of 20 to 80%. If it is less than 20%, the adhesion strength of the electrode is low and it is easy to peel off. If the area occupancy exceeds 80%, the first p-electrode layer 23 is oxidized in the heat application step after electrode formation, the adhesion is reduced, and it is easy to peel off. Further, the area occupation ratio is more preferably in the range of 30 to 70%.

  From the viewpoint of contact resistance, the area occupancy is preferably in the range of 30 to 60%. The contact resistance of the first p electrode layer 23 varies somewhat depending on the degree of heat treatment in a reducing atmosphere, but the contact resistance of the second p electrode layer 24 is stable. Therefore, it is preferable that the area of the second p-electrode layer 24 is wide as long as the adhesion does not decrease.

  According to the present invention, the p-side electrode 22 having not only excellent adhesiveness but also extremely excellent ohmic characteristics can be obtained from the following points.

  That is, since a mixed region is formed at the interface between the p-type ZnO-based crystal layer 14 and the first p-electrode layer 23, excellent ohmic characteristics are exhibited at the interface. Further, since a barrier metal (Pt or the like) that exhibits good ohmic characteristics with respect to the p-type ZnO-based crystal layer 14 is used as the second p-electrode layer 24, the opening of the first p-electrode layer 23 is also used. Good ohmic characteristics can be obtained. Therefore, ohmic contact between the p-type ZnO-based crystal layer 14 and the first p-electrode layer 23, and the p-type ZnO-based crystal layer 14 and the second p-electrode at the opening of the first p-electrode layer 23. Due to the effect of both contact with the layer 24 (barrier metal), the p-side electrode 22 exhibits excellent ohmic characteristics.

  Furthermore, according to the present invention, the first p electrode layer 23 is formed so as to be embedded in the second p electrode layer 24. That is, the second p electrode layer 24 covers the entire surface of the island-shaped or network-shaped first p electrode layer 23, and a p-type ZnO-based crystal is formed in the opening of the first p electrode layer 23. Layer 14 is coated. Therefore, the total area where the second p-electrode layer 24 is in contact with the first p-electrode layer 23 and the p-type ZnO-based crystal layer 14 is larger than the formation area (planar area) of the p-side electrode 22. large. With this configuration, the adhesion and adhesion of the p-side electrode 22 are excellent, and the contact resistance of the p-side electrode 22 is small.

[P-side electrode formation conditions]
(Material of first p-electrode layer)
For the first p-electrode layer 23, it is necessary to use a metal having ohmic contact with the p-type ZnO-based crystal. In the present invention, in order to form a metal oxide between the first p-electrode layer and the p-type ZnO-based crystal layer, it is necessary to form an ohmic junction between the electrode metal oxide and the p-type ZnO-based crystal layer. NiO is known as such a p-type oxide crystal, but based on a so-called 3d transition element, for example, an oxide of Cu (copper), Al (aluminum), Ca (calcium), Sr (strontium). Oxides contained in these materials also become p-type. Accordingly, Ni or Cu, or an alloy of Ni or Cu and Al, Ca, Sr, or the like can be used as the first p electrode layer. That is, a metal or alloy containing at least one of Ni and Cu can be used as the contact metal.

(Layer thickness of the first p-electrode layer)
The first p electrode layer may be formed so that the electrode layer has an island shape or a mesh shape. More specifically, it may be formed to have an island shape with an average layer thickness of 3 nm to 15 nm and a particle size of φ10 nm to φ100 nm, or a network shape in which islands are combined.

  Moreover, since the mixed region is not formed in the deposited electrode layer (first p-electrode layer) and the oxide crystal layer and the metal layer are in contact with each other, if the deposited layer is too thick, it is easy to peel off. . The average layer thickness of the first p-electrode layer is more preferably 10 nm or less.

(Atmospheric gas in annealing of first p-electrode layer)
The present invention utilizes the property that a metal (Ni, Cu, or Al or Ca or Sr compound of Ni or Cu) that is easily oxidized binds to O (oxygen) that is a constituent element of the p-type ZnO-based crystal layer, and p Only the interface region between the type ZnO-based crystal layer 14 and the first p-electrode layer 23 is oxidized by oxygen (O) supplied from the ZnO-based crystal layer 14 so that the metal layer remains on the surface layer. A heat treatment atmosphere gas was selected. Therefore, the annealing may be performed in an oxygen-free atmosphere or a non-oxidizing atmosphere. Further, it is more preferable to mix H ₂ (hydrogen), which is a reducing gas, in order to keep the surface layer of the first p electrode layer 23 in a better metallic state.

In the first embodiment described above, 3% of the reducing gas H ₂ (hydrogen) gas is mixed with the so-called inert gas N ₂ (nitrogen) gas as the atmosphere gas in the annealing of the first p-electrode layer 23. Nitrogen gas was used. By using a reducing atmosphere in which a small amount (> 0%) of H ₂ gas is mixed, the surface of the first p-electrode layer 23 is maintained in a metallic state, and the adhesiveness of the first p-electrode layer 24 is improved. On the other hand, an H ₂ concentration exceeding 10% is not preferable because O (oxygen) escape from the surface of the ZnO-based crystal layer increases and a surface absorption layer is easily formed. Therefore, the H ₂ gas concentration is preferably 0.05% to 10%, and more preferably 0.05% to 3%.

As the inert gas, He (helium), Ar (argon), or the like can be used in addition to N ₂ (nitrogen). As the reducing gas, N ₂ H ₄ (hydrazine) or the like can be used in addition to H ₂ (hydrogen). However, when a reducing gas is used, care must be taken so that the heat treatment temperature is lowered and the p-type ZnO-based crystal layer is not altered. Furthermore, although it is possible even in a vacuum, it is necessary to sufficiently dehydrate the inner wall of the heat treatment container.

  Note that the formation conditions of the first p-electrode layer 23 vary depending on the metal used, the constituent elements and composition of the p-type ZnO-based crystal layer 14, the annealing temperature, and the time. It only has to be selected.

(Annealing temperature)
As for the annealing temperature, it is difficult to form a mixed crystal layer (mixed region) at a temperature lower than about 350 ° C. Further, a high temperature of about 500 ° C. or higher is not suitable because the metal (Ni) of the first p-electrode layer 23 is dissolved in the ZnO-based crystal layer 14 and mixed into the surface layer. Therefore, the annealing temperature needs to be in the range of 350 ° C to 500 ° C. In order to prevent solid solution in the heating step in the mounting step or the like after the device is manufactured, the temperature is more preferably in the range of 350 ° C to 450 ° C.

(Material of second p-electrode layer)
As described above, the second p electrode layer 24 needs to be a metal that does not form a solid solution with the metal (Ni or the like) of the first p electrode layer 23. This is because even if the metal is a solid, it may be dissolved at a low temperature (less than a few hundred degrees). In particular, since the average thickness of the first p-electrode layer 23 is as thin as about 3 nm to 15 nm, the mixed region disappears due to solid solution with the first p-electrode layer 23, the adhesiveness decreases, and the electrode peels off. It is because it becomes easy. Further, even when the third p electrode layer 25 such as a connection electrode (or pad electrode) is provided on the second p electrode layer 24, it is preferable that the metal is not dissolved in the third p electrode layer 25. .

  Furthermore, it is necessary to use a material that can make ohmic contact with the p-type ZnO-based crystal layer 14 for the second p-electrode layer 24.

  Therefore, as the second p electrode layer 24, a transition metal group VIII, which is a metal having ohmic contact with a p-type ZnO-based crystal, in particular, Pt (platinum), Rh (rhodium), Pd (palladium), Ir (iridium) or the like can be used.

  In addition, the semiconductor element receives various thermal histories after mounting the element, such as by mounting on the substrate. At this time, the electrode is exposed to oxidative stress. As described above, by using an oxidation-resistant (non-oxidizing) metal such as Pt, Rh, Pd, and Ir for the second p electrode layer 24, the entire first p electrode layer 23 is embedded. Further, it is possible to prevent the mixed region of the first p-electrode layer 23 from disappearing due to external oxidation, the adhesiveness is lowered, and the electrode is easily peeled off.

  The second p-electrode layer 24 (barrier layer) may have a multilayer structure. For example, a metal having a non-solid solution relationship with the first p electrode layer 23 and a metal having a non-solid solution relationship with the third p electrode layer 25 may be formed in combination. In addition, the metal used for the barrier layer is often hard, and if it is formed thick, when it is heated, strain stress due to the difference in thermal expansion coefficient from that of the p-type ZnO-based crystal layer may occur, leading to electrode peeling. Therefore, the barrier layer can be prevented by stacking multiple layers and sandwiching a soft metal (such as Au) between them.

(Material of third p-electrode layer)
The material of the third p electrode layer 25 may be Al (aluminum) in addition to Au (gold). Usually, since the wire is Au (gold), Au is optimal as the bonding pad layer material. On the other hand, Al (aluminum) is a highly reflective material that reflects to the near ultraviolet, and is a suitable material for suppressing light absorption by the electrodes.

(Annealing process timing)
In the first embodiment, the annealing step for forming the mixed region is performed after the formation of the first p electrode layer 23. However, after the formation of the second p electrode layer 24 (barrier layer), or the third p electrode layer. You may implement after formation of 25 (pad electrode layer).

  However, when the mixed region is formed, the bonding state of the crystal changes due to the movement (diffusion) of O (oxygen) atoms, and a distortion is generated not less than spatially. Therefore, since the metal layer is thin after the formation of the first p-electrode layer 23, the distortion is easily relieved, so that the adhesive force and adhesion force of the mixed region are not weakened. Therefore, it is most effective to perform the annealing process after the first p electrode layer 23 is deposited, rather than when the second p electrode layer 24 or the third p electrode layer 25 is formed.

  FIGS. 10A and 10B respectively show a top view of the LED element 40 according to the second embodiment and a cross-sectional view taken along the line AA of FIG. 10A.

  Although the LED element 40 of Example 2 is different from Example 1 in that a mesh-shaped electrode structure is adopted, the other configurations are the same as those of the LED element 30 of Example 1. That is, the device layer 15 including the buffer layer 11, the n-type ZnO-based crystal layer 12, the light emitting layer 13, and the p-type ZnO-based crystal layer 14 was formed on the ZnO substrate 10.

  A p-side electrode 42 was formed on the p-type ZnO-based crystal layer 14 using the thus formed substrate with a device layer. The p-side electrode 42 is composed of a mesh-shaped p-side electrode 42A and a circular (100 μm diameter) p-side electrode 42B for wire bonding disposed in the center of the element. As shown in FIG. 11, the p-side electrode 42 includes first, second and third p-electrode layers 43, 44 and 45.

  Below, the formation process of the p side electrode 42 is demonstrated in detail. A resist mask having openings corresponding to the mesh-shaped p-side electrode 42A and the circular p-side electrode 42B was formed on the p-type ZnO-based crystal layer 14 by using a photolithography technique. Next, the metal of the first p-electrode layer 43 was deposited so as to have an island shape or a mesh shape. More specifically, Ni was deposited in an island shape with an average layer thickness of 10 nm by electron beam deposition. The particle size was within the range of φ10 nm to φ100 nm distribution. Thereafter, Ni other than the mask opening was removed by a lift-off method.

  Next, the substrate was set with an RTA apparatus, nitrogen gas mixed with 3% of hydrogen gas was supplied as an atmosphere gas, and annealing was performed at 400 ° C. for 10 seconds in a reducing atmosphere. Thereby, the first p-electrode layer 43 was formed. As in the first embodiment, as shown in FIG. 11, a mixed region 43A is formed at the interface between the p-type ZnO-based crystal layer 14 and the deposited metal (Ni) island by such annealing, A first p-electrode layer 43 in which a pure metal layer (Ni layer) 43B remained was formed.

  Next, Pt (barrier metal) and Au were vapor-deposited to a thickness of 100 nm and 1000 nm, respectively, by electron beam vapor deposition to form a second p-electrode layer 44 and a third p-electrode layer 45, respectively.

  After forming the p-side electrode 42, the back surface of the device layer-attached substrate 17 was polished to form the n-side electrode 28. The device layer-equipped substrate 17 in which the formation of the n-side electrode 28 was completed was separated into individual semiconductor light emitting elements (LEDs) by scribing and breaking.

  As described in detail in Example 1, a mixed region is formed at the interface between the p-type ZnO-based crystal layer 14 and the p-side electrode 42, and a metal phase layer (Ni) is formed on the surface of the first p-electrode layer 43. Layer) remains, it has high ohmic properties and high electrode adhesion and adhesion strength. Furthermore, since the second p electrode layer 24 (a barrier metal such as Pt) is in direct contact with the p-type ZnO-based crystal layer 14 in the opening of the first p electrode layer 43, ohmic contact and adhesion Also, an excellent p-side electrode 42 is formed.

  According to the second embodiment, since the mesh-shaped p-side electrode 42 is formed over the light extraction surface, an electrode with even lower resistance and excellent ohmic characteristics is realized. In addition, since the current injected from the p-side electrode 42B is diffused throughout the light emitting layer 13, the current injection into the light emitting layer 13 can be uniformly and highly efficient. Furthermore, it has excellent electrode adhesion and adhesion strength. The width of each line of the mesh may be set as appropriate in consideration of (external) light extraction efficiency, contact resistance, electrode adhesion strength, and the like.

  12A and 12B show a top view of the LED element 50 according to the third embodiment and a cross-sectional view taken along the line AA in FIG. 12A, respectively.

  The LED element 50 of the third embodiment is different from the first embodiment in that it adopts a flip chip type structure and a light reflecting structure in which the n-side electrode side is a light extraction surface, but other configurations are the same as in the first embodiment. This is the same as the LED element 30 of FIG. That is, the device layer 15 including the buffer layer 11, the n-type ZnO-based crystal layer 12, the light emitting layer 13, and the p-type ZnO-based crystal layer 14 was formed on the ZnO substrate 10.

  A p-side electrode 52 was formed on the p-type ZnO-based crystal layer 14 using the thus formed substrate with a device layer. The element section size is the same as that of the first embodiment (see FIG. 5). As shown in FIG. 12, in this embodiment, the p-side electrode 52 has a square element section size having a side of D2 (300 μm). Each side was formed in a square shape of 270 μm (D3), which is slightly smaller than each side and approximately 15 μm on each side.

  FIG. 13 is a cross-sectional view showing the configuration of the p-side electrode 52. The p-side electrode 52 includes first, second, and third p-electrode layers 53, 54, 55, and a reflective layer 57A and a reflective protective layer 57B formed between the second and third p-electrode layers 54, 55. It consists of and. More specifically, a reflective layer 57A made of a highly reflective metal such as Ag (silver) is formed on the second p-electrode layer 53 in order to reflect the radiated light from the light emitting layer 13, and the reflective layer 57A and the first A protective layer 57B of barrier metal (Pt or the like) is formed between the third p electrode layer 55 and the p electrode layer 55.

  For example, as the second p electrode layer 54 (barrier metal layer), the reflective layer 57A, the protective layer 57B, and the third p electrode layer 55 (pad electrode), Rh (rhodium) / Ag (silver) / Rh (rhodium), respectively. ) / Au (gold) were stacked at a thickness of 30 nm / 100 nm / 60 nm / 1000 nm, respectively, to form a p-side electrode. In addition to Ag, the reflective layer 57A can also have a high reflectance with Al (aluminum), Rh (rhodium), or the like. Since Rh also has a function as a barrier layer, the layer structure can be simplified by using Rh for the second p-electrode layer (barrier layer) or the like.

  In Example 3, Ni was vapor-deposited as the first p-electrode layer 53 in an island shape or network shape having an average layer thickness of 10 nm. The particle size was within the range of φ10 nm to φ100 nm distribution. Further, the points of annealing at 400 ° C. for 10 seconds in a reducing atmosphere and the point that the second p-electrode layer 54 (barrier metal layer) and the like are formed after the annealing are the same as in the first and second embodiments. . Accordingly, as shown in FIG. 13, a mixed region 53A is formed in the interface region between the p-type ZnO-based crystal layer 14 and the deposited metal (Ni) island by such annealing, and a pure metal layer (Ni) is formed on the surface. The first p-electrode layer 53 with the layer 53B remaining is the same as in the first and second embodiments.

  After forming the p-side electrode 52, the back surface of the substrate 17 with the device layer was polished to form the n-side electrode 58. The device layer-equipped substrate 17 in which the formation of the n-side electrode 58 was completed was separated into individual semiconductor light emitting elements (LEDs) by scribing and breaking.

  According to the third embodiment, since the p-side electrode 52 is formed over the entire surface of the p-type ZnO-based crystal layer 14, an electrode with even lower resistance and excellent ohmic characteristics is realized. In addition, since the current injected from the p-side electrode 52 is diffused throughout the light emitting layer 13, the current injection into the light emitting layer 13 can be uniformly and highly efficient. Furthermore, it has excellent electrode adhesion and adhesion strength.

  In the above embodiment, the LED has been described as an example of the semiconductor element, but the present invention can also be applied to a semiconductor element such as a semiconductor laser or other electronic device.

  Further, the above-described embodiments can be applied in appropriate combination. In Examples 1 and 2, for example, a reflective layer and a protective layer may be appropriately formed between the second p-electrode layer and the third p-electrode layer.

  As described above in detail, according to the present invention, a method for forming a contact electrode having excellent ohmic characteristics and high electrode adhesion and adhesion strength, a ZnO-based compound semiconductor element on which the electrode is formed, and A manufacturing method thereof can be provided.

DESCRIPTION OF SYMBOLS 10 Substrate 12 n-type ZnO-based crystal layer 13 Light-emitting layer 14 p-type ZnO-based crystal layer 15 Device layer 21 Translucent electrode 22 p-side electrode 23 First p-electrode layer 23A Mixed region 23B Metal layer 24 Second p-electrode Layer 25 third p-electrode layer 28 n-side electrode

Claims (11)

A method of manufacturing a zinc oxide (ZnO) based semiconductor element having at least a p-type ZnO based semiconductor layer,
The p-type ZnO based semiconductor layer, a first metal layer forming step of forming a first metal layer consisting of at least one Ni (nickel) and Cu (copper) in an island-like or mesh,
Following the first metal layer forming step, heat treatment is performed on the first metal layer and the p-type ZnO-based semiconductor layer in a reducing atmosphere to leave a metal phase layer on the surface of the first metal layer. And a heat treatment step of forming a mixed layer composed of the elements of the p-type ZnO-based semiconductor layer and the elements of the first metal layer at the interface between the p-type ZnO-based semiconductor layer and the first metal layer;
After the heat treatment step, a second metal layer made of at least one of Pt (platinum), Rh (rhodium), Pd (palladium), and Ir (iridium) is formed on the first metal layer and the first metal layer. And a second metal layer forming step of covering the p-type ZnO-based semiconductor layer exposed from the opening of the metal layer. The manufacturing method according to claim 1, wherein the reducing atmosphere is a nitrogen gas atmosphere mixed with hydrogen gas . The manufacturing method according to claim 1 or 2 , wherein the temperature of the heat treatment is within a range of 350 ° C to 450 ° C. The first metal layer, 3 nm to method according to any one of claims 1 to 3, characterized in that it has an average layer thickness in the range of 15 nm. The area occupation ratio of the first metal layer on the p-type ZnO-based semiconductor layer on which the first metal layer or the second metal layer is formed is 20 to 80%. Item 5. The production method according to any one of Items 1 to 4 . The ZnO-based semiconductor device manufacturing method according to any one of claims 1 to 5, characterized in that a light emitting diode (LED) including an n-type ZnO based semiconductor layer and the light emitting layer. A ZnO-based semiconductor element having at least a p-type ZnO-based semiconductor layer,
Ni becomes at least one of (nickel) and Cu (copper), a first metal layer formed in an island shape or a mesh shape on the p-type ZnO based semiconductor layer,
The p-type made of at least one metal of Pt (platinum), Rh (rhodium), Pd (palladium), and Ir (iridium) and exposed from the openings of the first metal layer and the first metal layer A second metal layer formed so as to cover the ZnO-based semiconductor layer,
The first metal layer includes a metal phase layer of an element of the first metal layer , the p-type ZnO-based semiconductor layer, and the first metal formed on a surface side of the first metal layer. A ZnO-based semiconductor device comprising: a mixed layer formed at an interface between layers and made of an element of the p-type ZnO-based semiconductor layer and an element of the first metal layer. The ZnO-based semiconductor element according to claim 7 , wherein the first metal layer is formed by heat treatment under a reducing atmosphere . A method for forming a contact electrode of a p-type ZnO-based semiconductor,
The p-type ZnO based semiconductor layer, a first metal layer forming step of forming a first metal layer consisting of at least one Ni (nickel) and Cu (copper) in an island-like or mesh,
Following the first metal layer forming step, heat treatment is performed on the first metal layer and the p-type ZnO-based semiconductor layer in a reducing atmosphere to leave a metal phase layer on the surface of the first metal layer. And a heat treatment step of forming a mixed layer composed of the elements of the p-type ZnO-based semiconductor layer and the elements of the first metal layer at the interface between the p-type ZnO-based semiconductor layer and the first metal layer;
After the heat treatment step, a second metal layer made of at least one of Pt (platinum), Rh (rhodium), Pd (palladium), and Ir (iridium) is formed on the first metal layer and the first metal layer. A second metal layer forming step of forming so as to cover the p-type ZnO-based semiconductor layer exposed from the opening of the metal layer;
A forming method characterized by comprising: The forming method according to claim 9 , wherein the reducing atmosphere is a nitrogen gas atmosphere mixed with hydrogen gas . A method according to claim 1 0, wherein the process temperature of the heat treatment is in the range of 350 ° C. to 450 ° C..

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