JP5499702B2 - Protection circuit, battery protection device, battery pack, and mode switching method - Google Patents

Description

  The present invention relates to a protection circuit that is supplied with power from a secondary battery and protects the secondary battery. Moreover, it is related with a battery protection apparatus provided with this protection circuit. Moreover, it is related with a battery pack provided with this battery protection apparatus. The present invention also relates to a mode switching method for switching the operation mode of the protection circuit.

  In recent years, secondary batteries such as lithium-ion batteries have been miniaturized, and the battery capacity has been reduced by the size reduction. Therefore, when using a secondary battery with a reduced size, the secondary battery is likely to be over-discharged as compared with the conventional case only with the current consumption of the IC. As a result, for example, the secondary battery may be completely discharged when it is in stock after the product is shipped, and recharging may be required at the time of purchase.

  As a conventional technique capable of solving this point, a battery pack having a built-in operation mode switching circuit for switching between a normal operation mode and a low power consumption mode and having a communication terminal with an electric device to be mounted is known (for example, (See Patent Document 1). This battery pack detects the low power consumption mode transition command input from the communication terminal, and the operation mode is set to the low power consumption mode when the potential of the communication terminal is held at “Low” for longer than a predetermined time. To switch to.

Japanese Patent Laid-Open No. 2002-300731

  However, in the case of a configuration in which no communication terminal exists, the disclosed technique of Patent Document 1 cannot switch the operation mode to the low power consumption mode, and thus cannot prevent the secondary battery from being overdischarged in the storage state.

  Therefore, an object of the present invention is to provide a protection circuit, a battery protection device, a battery pack, and a mode switching method that can prevent overdischarge of a secondary battery in a storage state even without a communication terminal.

In order to achieve the above object, a protection circuit according to the present invention comprises:
A protection circuit that receives power from a secondary battery and protects the secondary battery,
Based on a mode switching signal given to a power supply terminal for supplying power from the secondary battery to an external load, comprising mode switching means for switching the operation mode of the protection circuit to a low power consumption mode ,
The mode switching means switches to a low power consumption mode according to a time during which an abnormal current flowing through the power supply terminal flows as the mode switching signal .

In order to achieve the above object, the battery protection device according to the present invention includes:
A protection circuit including the mode switching unit and a blocking unit that blocks a power supply path between the power supply terminal and the secondary battery based on an output signal of the circuit.

In order to achieve the above object, the battery pack according to the present invention includes:
The battery protection device provided with the blocking means and the secondary battery are incorporated.

In order to achieve the above object, a mode switching method according to the present invention includes:
Based on a mode switching signal supplied to a power supply terminal for supplying power from the secondary battery to the external load, the operation mode of the protection circuit that is supplied with power from the secondary battery and protects the secondary battery is switched to the low power consumption mode. A mode switching method ,
The mode switching signal is switched to the low power consumption mode according to the time during which an abnormal current flowing through the power supply terminal flows.

  According to the present invention, even if there is no communication terminal, overdischarge of the secondary battery in the storage state can be prevented.

1 is a configuration diagram of a protection IC 90, a protection module circuit 80, and a battery pack 100 according to an embodiment of the present invention. It is the figure which showed the fall of the voltage P- between negative terminals by charge overcurrent Icharge. It is the figure which showed the transfer mode with respect to charge pulse width tIchg. It is a time chart in case charging overcurrent flows. It is the flowchart which showed the operation | movement flow of protection IC90 when a charge overcurrent flows. It is the figure which showed the raise of the negative side terminal voltage P- by the discharge overcurrent Idischarge. It is the figure which showed the transfer mode with respect to discharge pulse width tIdis. It is the flowchart which showed the operation | movement flow of protection IC90 when the discharge overcurrent flows.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. 1 is a configuration diagram of a protection IC 90, a protection module circuit 80, and a battery pack 100 according to an embodiment of the present invention. The battery pack 100 is a module component that incorporates a protection module circuit 80 that is a battery protection device that protects the secondary battery 200 such as a lithium ion battery or a nickel metal hydride battery together with the secondary battery 200. The protection module circuit 80 includes a power supply path 9 (9a, 9) between the input / output terminals 5 and 6 to which the external load 300 and / or the inspection apparatus 400 can be connected and the terminals 3 and 4 to which both electrodes of the secondary battery 200 can be connected. 9b) includes FETs 1 and 2 that switch between conduction and cutoff, and a protection IC 90 that controls the switching operation of FETs 1 and 2. The input / output terminals 5 and 6 are power supply terminals for supplying power from the secondary battery 200 to the external load 300.

  The battery pack 100 is built in or externally attached to the external load 300. The external load 300 is, for example, an electronic device or an electric device that can be carried by a person. Specific examples include a communication terminal device having a wireless communication function such as a player such as music and video, a headset, and a mobile phone, an information terminal device such as a PDA and a mobile personal computer, a camera, and a game machine.

  The FETs 1 and 2 are switching elements connected in series so that switching of conduction / cutoff of the negative power supply path 9b between the negative electrode side terminal 4 and the negative input / output terminal 6 of the secondary battery 200 is possible. . The FET 1 is a first blocking unit that blocks the power supply path 9, and the FET 2 is a second blocking unit that blocks the power supply path 9. More specifically, the FET 1 is a first switching unit that can switch off / conduction of the charging current of the secondary battery 200 that flows in the charging direction through the power supply path 9, and the FET 2 moves the charging / discharging path 9 in the discharging direction. It is the 2nd switching means which can switch interruption | blocking / conduction of the discharge current of the flowing secondary battery 200. FIG. Charging of the secondary battery 200 is permitted when the charge control FET 1 is in the on state, and charging of the secondary battery 200 is prohibited in the off state. Further, when the discharge control FET 2 is in the on state, the secondary battery 200 is allowed to discharge, and when the discharge control FET 2 is in the off state, the secondary battery 200 is prohibited from discharging.

  The FETs 1 and 2 are, for example, MOSFETs having parasitic diodes. The FET 1 is arranged between the negative terminal 4 and the negative input / output terminal 6 in such a direction that the forward direction of the parasitic diode 1a becomes the discharge direction of the secondary battery 200, and the FET 2 is the forward direction of the parasitic diode 2a. Is arranged between the negative electrode side terminal 4 and the negative side input / output terminal 6 in the direction in which the secondary battery 200 is charged. The FETs 1 and 2 may be replaced with a bipolar transistor in which a diode is formed between the collector and emitter in the illustrated direction, or may be replaced with a semiconductor element such as an IGBT.

  The protection IC 90 is an integrated circuit that receives power from the secondary battery 200 and protects the secondary battery 200. For example, the protection IC 90 protects the secondary battery 200 from overcharge (overcharge protection operation), protects the secondary battery 200 from overdischarge (overdischarge protection operation), and charges the secondary battery 200. A charge overcurrent protection operation for preventing an overcurrent from flowing in the direction and a discharge overcurrent protection operation for preventing an overcurrent from flowing in the direction of discharging the secondary battery 200 are performed. These protection operations are performed when predetermined operating conditions for each protection operation are satisfied.

  For example, the protection IC 90 turns off the FET 1 when the operating condition of the overcharge protection operation of the secondary battery 200 is established. Thereby, it is possible to prevent the secondary battery 200 from being overcharged regardless of the on / off state of the FET 2.

  Specifically, the detector 21 of the protection IC 90 monitors the battery voltage (cell voltage) of the secondary battery 200 by detecting the voltage between the VDD terminal and the VSS terminal of the protection IC 90. The VDD terminal is connected to the positive power supply path 9a between the positive input / output terminal 5 and the positive terminal 3 of the secondary battery 200, and to the resistor R1 connected to the positive power supply path 9a and the negative power supply path 9b. The connection is made via a connection point with the capacitor C1. The VSS terminal is connected to the negative power supply path 9b. The cell voltage corresponds to the terminal voltage of the positive terminal 3 detected on the basis of the negative terminal 4 (in other words, the terminal voltage of the VDD terminal detected on the basis of the VSS terminal). The detector 21 detects an overcharge of the secondary battery 200 by detecting a cell voltage equal to or higher than a predetermined overcharge detection voltage, and outputs an overcharge detection signal. The charge control logic circuit 25 that has detected the overcharge detection signal waits for the delay time generated by the oscillator 22 and the counter 23 to elapse, and then outputs an “L” level signal from the Cout terminal of the protection IC 90. The charge control FET 1 is turned off. Thereby, it can prevent that the secondary battery 200 is overcharged. The delay time generated by the oscillator 22 and the counter 23 is a time after the detector 21 detects a cell voltage that is equal to or higher than a predetermined overcharge detection voltage.

  For example, the protection IC 90 turns off the FET 2 when the operating condition of the overdischarge protection operation of the secondary battery 200 is satisfied. Thereby, it is possible to prevent the secondary battery 200 from being overdischarged regardless of the on / off state of the FET 1.

  Specifically, the detector 21 of the protection IC 90 monitors the battery voltage (cell voltage) of the secondary battery 200 by detecting the voltage between the VDD terminal and the VSS terminal of the protection IC 90. The detector 21 detects an overdischarge of the secondary battery 200 by detecting a cell voltage equal to or lower than a predetermined overdischarge detection voltage, and outputs an overdischarge detection signal. The discharge control logic circuit 24 that has detected the overdischarge detection signal waits for the delay time generated by the oscillator 22 and the counter 23 to pass, and then outputs an “L” level signal from the Dout terminal of the protection IC 90. The discharge control FET 2 is turned off. Thereby, it is possible to prevent the secondary battery 200 from being overdischarged. Note that the delay time generated by the oscillator 22 and the counter 23 is a time after the detector 21 detects a cell voltage equal to or lower than a predetermined overdischarge detection voltage.

  Further, the protection IC turns off the FET 1 when, for example, the operating condition of the charge overcurrent protection operation of the secondary battery 200 is established. Thereby, it is possible to prevent an overcurrent (charging overcurrent) in the direction of charging the secondary battery 200 from flowing regardless of the on / off state of the FET 2.

  Specifically, the detector 21 of the protection IC 90 detects the voltage between the V− terminal and the VSS terminal of the protection IC 90, thereby detecting the voltage between the negative input / output terminal 6 and the negative terminal 4. A certain negative terminal voltage P- is monitored. The V-terminal is connected to a negative power supply path 9b between the charge control FET 1 and the negative input / output terminal 6 via a resistor R2. The negative terminal voltage P− corresponds to the terminal voltage of the negative input / output terminal 6 detected on the basis of the negative terminal 4 (in other words, the terminal voltage of the V− terminal detected on the basis of the VSS terminal). . The detector 21 detects an abnormal current flowing through the negative input / output terminal 6 by detecting a negative terminal voltage P− that is a predetermined first threshold voltage or lower than the charge overcurrent detection voltage Vth1 (see FIG. 2). As a charging overcurrent is detected, a charging overcurrent detection signal is output. The charge control logic circuit 25 that has detected the charge overcurrent detection signal waits for the delay time t2 generated by the oscillator 22 and the counter 23 to pass (see FIG. 3), and then goes to the “L” level from the Cout terminal of the protection IC 90. By outputting a signal, the charging control FET 1 is turned off. As a result, the operation mode of the protection IC 90 shifts to a charge overcurrent prevention mode in which the charge control FET 1 is turned off as an abnormal current prevention mode for preventing an abnormal current from flowing through the power supply path 9 (see FIG. 3). ), Charging overcurrent can be prevented from flowing through the secondary battery 200. The delay time t2 is a time after the detector 21 detects a negative terminal voltage P− that is equal to or lower than a predetermined charging overcurrent detection voltage Vth1. The charge pulse width tIchg and the standby mode shown in FIGS. 2 and 3 will be described later.

  Here, in the state where the charge control FET 1 is at least on, the negative terminal voltage P− decreases due to the flow of the charge current for charging the secondary battery 200 due to the on resistance of the charge control FET 1. This is because a voltage drop occurs. Further, if the discharge control FET 2 is on, the negative terminal voltage P− decreases including the voltage drop due to the on-resistance of the discharge control FET 2, and if the discharge control FET 2 is off, the discharge control FET 2 is discharged. The voltage P- between the negative terminals decreases including the voltage drop due to the parasitic diode 2a of the control FET2.

  For example, the protection IC 90 turns off the FET 2 when the operating condition of the discharge overcurrent protection operation of the secondary battery 200 is established. Thereby, it is possible to prevent an overcurrent (discharge overcurrent) in the direction of discharging the secondary battery 200 from flowing regardless of the on / off state of the FET 1.

  Specifically, the detector 21 of the protection IC 90 detects the voltage between the V− terminal and the VSS terminal of the protection IC 90, thereby detecting the voltage between the negative input / output terminal 6 and the negative terminal 4. A certain negative terminal voltage P- is monitored. The detector 21 detects a discharge overcurrent as an abnormal current flowing through the negative input / output terminal 6 by detecting a negative terminal voltage P− that is equal to or higher than a predetermined discharge overcurrent detection voltage Vth2 (see FIG. 6). As a result, a discharge overcurrent detection signal is output. The discharge control logic circuit 24 that has detected the discharge overcurrent detection signal waits for the elapse of the delay time t4 generated by the oscillator 22 and the counter 23 (see FIG. 7), and then goes “L” level from the Dout terminal of the protection IC 90. By outputting a signal, the discharge control FET 2 is turned off. Thereby, the operation mode of the protection IC 90 shifts to the discharge overcurrent prevention mode in which the discharge control FET 2 is turned off as the abnormal current prevention mode for preventing the abnormal current from flowing through the power supply path 9 (see FIG. 7). ), A discharge overcurrent can be prevented from flowing through the secondary battery 200. The delay time generated by the oscillator 22 and the counter 23 is a time after the detector 21 detects the negative terminal voltage P− that is equal to or higher than a predetermined discharge overcurrent detection voltage. The discharge pulse width tIdis and the standby mode shown in FIGS. 6 and 7 will be described later.

  Here, when the discharge control FET 2 is at least on, the negative terminal voltage P− rises due to the flow of the discharge current that discharges the secondary battery 200 due to the on-resistance of the discharge control FET 2. This is because a voltage rise occurs. If the charge control FET 1 is on, the negative terminal voltage P− increases including the voltage increase due to the on-resistance of the charge control FET 1, and if the charge control FET 1 is off, the charge control FET 1 is charged. The negative terminal voltage P− rises including the voltage rise due to the parasitic diode 1a of the control FET1.

  Furthermore, the protection IC 90 sets the operation mode of the protection IC 90 to the low power consumption mode (based on a mode switching signal given to the negative input / output terminal 6 that is a power supply terminal for supplying power from the secondary battery 200 to the external load 300. Mode switching means for switching to the standby mode). The protection IC 90 includes a detector 21, a discharge control logic circuit 24, a standby pulse detection circuit 29, a standby determination circuit 30, and a standby signal generation circuit 31 as main components of mode switching means.

  The standby pulse detection circuit 29 detects a standby pulse output from the inspection device 400 that inspects the battery pack 100 before shipment as a mode switching signal given to the negative input / output terminal 6. The standby pulse is a pulse signal generated by a charging current that lowers the negative terminal voltage P− to the charging overcurrent detection voltage Vth1 or less. The pulse width of the standby pulse is determined in advance.

  The standby determination circuit 30 determines whether or not to shift the operation mode of the protection IC 90 from the normal operation mode to the standby mode based on the standby pulse detected by the standby pulse detection circuit 29.

  When the standby determination circuit 30 determines that the operation mode of the protection IC 90 shifts from the normal operation mode to the standby mode, the standby signal generation circuit 31 generates a standby signal for suppressing a current flowing in a part of the protection IC 90. Output. Thereby, the electric current supplied to the said one part circuit can be suppressed.

  FIG. 2 is a diagram showing a decrease in the negative terminal voltage P− due to the charge overcurrent Icharge. The standby pulse detection circuit 29 detects the time (charge pulse width tIchg) during which the charging overcurrent detected by the detector 21 as an abnormal current flowing through the negative input / output terminal 6 is applied to the negative input / output terminal 6. Time detection means. The charging pulse width tIchg corresponds to the time during which the negative terminal voltage P− that is equal to or lower than the charging overcurrent detection voltage Vth1 is generated.

  FIG. 3 is a diagram showing a transition mode with respect to the charging pulse width tIchg. The operation mode of the protection IC 90 changes according to the charging pulse width tIchg. When the charge pulse width tIchg is less than the standby permission time t1, which is a predetermined first threshold time, the operation mode of the protection IC 90 remains the default normal mode and does not shift to the standby mode or the charge overcurrent prevention mode. Thereby, it is possible to prevent malfunctions due to instantaneous pulses such as noise.

  The standby pulse detection circuit 29 sets a permission flag when it detects a charging pulse width tIchg that is longer than the standby permission time t1. Even after the permission flag is set, the counter 23 continues to count the delay time t2, and when the count up to the delay time t2, the charge overcurrent detected by the detector 21 is a negative input / output terminal. 6, the operation mode of the protection IC 90 shifts from the normal mode to the standby mode. If the charge overcurrent detected by the detector 21 is applied to the negative input / output terminal 6, The operation mode shifts from the normal mode to the above-described charge overcurrent prevention mode.

  That is, the pulse width of the standby pulse output from the inspection apparatus 400 is set in advance to be longer than the standby permission time t1 and less than the delay time t2. As a result, it is possible to prevent the standby pulse from being erroneously determined as noise, and to prevent transition to the charge overcurrent prevention mode due to application of the standby pulse.

  When the standby determination circuit 30 counts up to the delay time t2, the operation mode of the protection IC 90 is detected by detecting that the charging overcurrent detected by the detector 21 is not applied to the negative input / output terminal 6. Is determined to enter standby mode. The standby determination circuit 30 that has determined to shift to the standby mode outputs a standby mode shift determination signal. The discharge control logic circuit 24 that has detected the standby mode transition determination signal outputs an “L” level signal from the Dout terminal of the protection IC 90 to turn off the discharge control FET 2 and turn on the transistor 26. The V− terminal of the protection IC 90 is pulled up to the VDD voltage (the voltage at the VDD terminal). By pulling up the V-terminal, the voltage of the V-terminal is raised to a predetermined voltage. The standby signal generation circuit 31 that has detected the pull-up of the V-terminal cuts the current path of some circuits such as the reference power supply bias circuit 28 and the detector 21 for generating the reference voltage of the circuit in the protection IC 90. . By pulling up the V− terminal to the VDD terminal and cutting the current path of some internal circuits of the protection IC 90, it is possible to suppress the capacity of the secondary battery 200 from being consumed by the protection IC 90. Therefore, the secondary battery 200 can be reliably prevented from being overdischarged, and the secondary battery 200 can be prevented from being overdischarged in a stored state.

  FIG. 5 is a flowchart showing an operation flow of the protection IC 90 when a charge overcurrent flows. In the normal mode (step S10), when the negative terminal voltage P− equal to or lower than the charge overcurrent detection voltage Vth1 is detected by the detector 21, the counter 23 starts counting the charge pulse width tIchg (step S12).

  In step S10, the negative terminal voltage P− below the charging overcurrent detection voltage Vth1 is detected during the period from the detection of the negative terminal voltage P− below the charging overcurrent detection voltage Vth1 once by the detector 21 to the standby permission time t1. If P- is no longer detected by the detector 21, the normal mode is maintained assuming that an instantaneous pulse such as noise is detected (steps S14 and S16). This operation is shown in period A in FIG.

  On the other hand, the negative terminal between the charging overcurrent detection voltage Vth1 and the negative terminal voltage P− below the charging overcurrent detection voltage Vth1 is detected by the detector 21 until the standby permission time t1 in step S10. If the inter-voltage P− continues to be detected by the detector 21, the standby pulse detection circuit 29 sets a permission flag (steps S14, S16, S18).

  When the count of the charging pulse width tIchg by the counter 23 reaches the delay time t2 (step S20), if the negative terminal voltage P− below the charging overcurrent detection voltage Vth1 is detected by the detector 21 (step S22). The charge control logic circuit 25 outputs an “L” level signal from the Cout terminal of the protection IC 90 (step S24). As a result, the operation mode of the protection IC 90 shifts to the charge overcurrent prevention mode in which the charge control FET 1 is turned off. This operation is shown in periods F and G in FIG.

  On the other hand, when the count of the charging pulse width tIchg by the counter 23 reaches the delay time t2 (step S20), if the negative terminal voltage P− below the charging overcurrent detection voltage Vth1 is not detected by the detector 21, The standby determination circuit 30 determines to shift to the standby mode, and a standby mode shift determination signal is output (step S22). The discharge control logic circuit 24 that has detected the standby mode transition determination signal outputs the “L” level signal from the Dout terminal of the protection IC 90, thereby turning off the discharge control FET 2 (step S26), and turning on the transistor 26. By turning on, the V-terminal of the protection IC 90 is pulled up to the VDD voltage (the voltage at the VDD terminal) (step S28). The standby signal generating circuit 31 that has detected the pull-up of the V-terminal outputs a standby signal (step S30), thereby cutting the current paths of some circuits such as the reference power supply bias circuit 28 and the detector 21 (step S30). Step S32). As a result, the operation mode of the protection IC 90 shifts to the standby mode in which the discharge control FET 2 is turned off. This operation is shown in periods C, D, and E in FIG.

  In the above-described FIGS. 2 to 5, the example in which the inspection apparatus 400 shifts to the standby mode by applying the charging overcurrent is shown. However, the inspection apparatus 400 shifts to the standby mode by applying the discharge overcurrent. May be.

  The standby pulse in this case is a pulse signal by a discharge current that raises the negative terminal voltage P− to the discharge overcurrent detection voltage Vth2 or more. The pulse width of the standby pulse is determined in advance. For example, the inspection apparatus 400 applies a discharge overcurrent by short-circuiting the input / output terminals 5 and 6 with a low resistance.

  FIG. 6 is a diagram showing an increase in the negative terminal voltage P− due to the discharge overcurrent Idischarge. The standby pulse detection circuit 29 detects the time (discharge pulse width tIdis) during which the discharge overcurrent detected by the detector 21 as an abnormal current flowing through the negative input / output terminal 6 is applied to the negative input / output terminal 6. Time detection means. The discharge pulse width tIdis corresponds to the time during which the negative terminal voltage P− that is equal to or higher than the discharge overcurrent detection voltage Vth2 is generated.

  FIG. 7 is a diagram showing a transition mode with respect to the discharge pulse width tIdis. The operation mode of the protection IC 90 changes according to the discharge pulse width tIdis. When the discharge pulse width tIdis is less than the standby permission time t3 that is a predetermined third threshold time, the operation mode of the protection IC 90 remains the default normal mode and does not shift to the standby mode or the discharge overcurrent prevention mode. Thereby, it is possible to prevent malfunctions due to instantaneous pulses such as noise.

  When the standby pulse detection circuit 29 detects a discharge pulse width tIdis equal to or longer than the standby permission time t3, it sets a permission flag. Even after the permission flag is set, the counter 23 continues to count the delay time t4. At the time when the counter 23 counts up to the delay time t4, the discharge overcurrent detected by the detector 21 is the negative input / output terminal. 6, the operation mode of the protection IC 90 shifts from the normal mode to the standby mode. If the discharge overcurrent detected by the detector 21 is applied to the negative input / output terminal 6, The operation mode shifts from the normal mode to the above-described discharge overcurrent prevention mode.

  That is, the pulse width of the standby pulse output from the inspection apparatus 400 is set to be equal to or greater than the standby permission time t3 and less than the delay time t4. As a result, it is possible to prevent the standby pulse from being erroneously determined as noise, and to prevent transition to the discharge overcurrent prevention mode due to application of the standby pulse.

  By detecting that the discharge overcurrent detected by the detector 21 is not applied to the negative input / output terminal 6 when the standby determination circuit 30 counts up to the delay time t4, the operation mode of the protection IC 90 Is determined to enter standby mode. The standby determination circuit 30 that has determined to shift to the standby mode outputs a standby mode shift determination signal. The discharge control logic circuit 24 that has detected the standby mode transition determination signal outputs an “L” level signal from the Dout terminal of the protection IC 90 to turn off the discharge control FET 2 and turn on the transistor 26. The V− terminal of the protection IC 90 is pulled up to the VDD voltage (the voltage at the VDD terminal). By pulling up the V-terminal, the voltage of the V-terminal is raised to a predetermined voltage. The standby signal generation circuit 31 that has detected the pull-up of the V-terminal cuts the current path of some circuits such as the reference power supply bias circuit 28 and the detector 21 for generating the reference voltage of the circuit in the protection IC 90. . By pulling up the V− terminal to the VDD terminal and cutting the current path of some internal circuits of the protection IC 90, it is possible to suppress the capacity of the secondary battery 200 from being consumed by the protection IC 90. Therefore, the secondary battery 200 can be reliably prevented from being overdischarged, and the secondary battery 200 can be prevented from being overdischarged in a stored state.

  FIG. 8 is a flowchart showing an operation flow of the protection IC 90 when a discharge overcurrent flows. In the normal mode (step S40), when the negative terminal voltage P− equal to or higher than the discharge overcurrent detection voltage Vth2 is detected by the detector 21, the counter 23 starts to count the charging pulse width tIdis (step S42).

  In step S40, the negative terminal voltage P- equal to or higher than the discharge overcurrent detection voltage Vth2 after the negative terminal voltage P- equal to or higher than the discharge overcurrent detection voltage Vth2 is once detected by the detector 21 until the standby permission time t3. If P- is no longer detected by the detector 21, the normal mode is maintained assuming that an instantaneous pulse such as noise has been detected (steps S44 and S46).

  On the other hand, in step S40, the negative-side terminal voltage P− greater than or equal to the discharge overcurrent detection voltage Vth2 is detected, and the negative-side terminal voltage greater than or equal to the discharge overcurrent detection voltage Vth2 is detected during the period from when the detector 21 detects the negative terminal voltage P− If the inter-voltage P− continues to be detected by the detector 21, the standby pulse detection circuit 29 sets a permission flag (steps S44, S46, S48).

  When the count of the discharge pulse width tIdis by the counter 23 reaches the delay time t4 (step S50), if the negative terminal voltage P− equal to or higher than the discharge overcurrent detection voltage Vth2 is detected by the detector 21 (step S52). The discharge control logic circuit 24 outputs an “L” level signal from the Dout terminal of the protection IC 90 (step S54). As a result, the operation mode of the protection IC 90 shifts to the discharge overcurrent prevention mode in which the discharge control FET 2 is turned off.

  On the other hand, when the count of the discharge pulse width tIdis by the counter 23 reaches the delay time t4 (step S50), if the detector 21 does not detect the negative terminal voltage P− that is equal to or higher than the discharge overcurrent detection voltage Vth2, The standby determination circuit 30 determines to shift to the standby mode, and a standby mode shift determination signal is output (step S52). The discharge control logic circuit 24 that has detected the standby mode transition determination signal outputs a “L” level signal from the Dout terminal of the protection IC 90, thereby turning off the discharge control FET 2 (step S56) and turning on the transistor 26. By turning on, the V-terminal of the protection IC 90 is pulled up to the VDD voltage (the voltage at the VDD terminal) (step S58). The standby signal generation circuit 31 that has detected the pull-up of the V− terminal outputs a standby signal (step S60), thereby cutting the current paths of some circuits such as the reference power supply bias circuit 28 and the detector 21 (step S60). Step S62). As a result, the operation mode of the protection IC 90 shifts to the standby mode in which the discharge control FET 2 is turned off.

  As described above, according to the above-described embodiment, the secondary battery 200 can be reliably prevented from being overdischarged, the secondary battery 200 can be prevented from being overdischarged in a storage state, and used by an actual user. The need for recharging at the time or immediately before shipment from the factory can be eliminated.

  In addition, as a protection function for secondary batteries such as lithium ion batteries in recent years in terms of safety, a function of prohibiting charging (0V charging prohibition) is required for a battery that has dropped below a certain voltage. Even in the case of a battery pack equipped with this function (the same applies to a protection circuit and a battery protection device), according to the above-described embodiment, even if it is not an overdischarge level but a normal battery voltage state, a certain voltage or less Therefore, it is possible to forcibly shift to the standby mode before dropping the battery pack, so that it is possible to eliminate the disposal of the battery pack that has fallen below a certain voltage or the re-shipment after recharging at the factory.

  In addition, since the standby mode can be set at the time of shipment from the factory, the battery pack can be stored in stock for a long time, and the cost of disposal and recharging can be suppressed. The same applies to the protection circuit and the battery protection device.

  Further, since the discharge control FET 2 is turned off in the standby mode, discharge via the load is prohibited. Therefore, even if the power supply terminal (input / output terminal) is accidentally shorted at the time of factory shipment or the like, current can be prevented from flowing, and safety is improved.

  In actual use by the user, the charger can be used by releasing the standby mode by connecting the charger to the power supply terminal (input / output terminal).

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the above-described embodiments, and various modifications, improvements, and modifications can be made to the above-described embodiments without departing from the scope of the present invention. Substitutions can be added.

  For example, FETs 1 and 2 may replace the arrangement positions shown in FIG.

  Further, the above-described threshold value may be provided to the temperature detection terminal and the time-short terminal (DS terminal) of the protection IC 90, and the mode switching signal as described above may be applied to shift to the standby mode.

1 FEt for charge control
1a Parasitic diode 2 Discharge control FET
2a Parasitic diode 3 Positive side terminal 4 Negative side terminal 5 Positive side input / output terminal 6 Negative side input / output terminal 9a Positive side power supply path 9b Negative side power supply path 80 Protection module circuit 90 Protection IC
100 Battery pack 200 Secondary battery 300 External load 400 Inspection device

Claims (8)

A protection circuit that receives power from a secondary battery and protects the secondary battery,
Based on a mode switching signal given to a power supply terminal for supplying power from the secondary battery to an external load, comprising mode switching means for switching the operation mode of the protection circuit to a low power consumption mode ,
The protection circuit according to claim 1, wherein the mode switching means switches to a low power consumption mode according to a time during which an abnormal current flowing through the power supply terminal flows as the mode switching signal . It said mode switching means, when the time is less than the predetermined value, switching to the low power consumption mode, the protection circuit according to claim 1. The protection circuit according to claim 2 , wherein when the time is equal to or greater than a predetermined value, the operation mode of the protection circuit is switched to an abnormal current prevention mode. The protection circuit according to claim 1, wherein the abnormal current is a charge overcurrent. The protection circuit according to claim 1, wherein the abnormal current is a discharge overcurrent. A protection circuit according to any one of claims 1 to 5 ;
A battery protection device comprising: a blocking unit that blocks a power supply path between the power supply terminal and the secondary battery based on an output signal of the circuit. A battery pack including the battery protection device according to claim 6 and the secondary battery. Based on a mode switching signal supplied to a power supply terminal for supplying power from the secondary battery to the external load, the operation mode of the protection circuit that is supplied with power from the secondary battery and protects the secondary battery is switched to the low power consumption mode. A mode switching method ,
A mode switching method for switching to a low power consumption mode according to a time during which an abnormal current flowing through the power supply terminal flows as the mode switching signal.

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