JP5498973B2 - Multilayer ceramic capacitor and method for manufacturing multilayer ceramic capacitor - Google Patents
Multilayer ceramic capacitor and method for manufacturing multilayer ceramic capacitor Download PDFInfo
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Description
本発明は、積層セラミックコンデンサ及びその製造方法に関する。 The present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same.
積層セラミックコンデンサは、携帯機器、通信機器等の各種電子機器に用いられている。積層セラミックコンデンサは、セラミック誘電体層と内部電極層とが交互に積層され、内部電極層の静電容量形成部から交互に異なる端面に露出するように引出された引出部を有するセラミック積層体と、セラミック積層体の各内部電極層の引出部が露出している端面に形成された外部電極とを備えてなるものが一般的である。外部電極は、下地金属と、該下地金属の表層に形成されたメッキ層とからなる。製造工程の簡略化、内部電極と下地金属との接続の信頼性等の要請から、未焼成のセラミック積層体と、未焼成の下地金属とを同時焼成することが行われている。 Multilayer ceramic capacitors are used in various electronic devices such as portable devices and communication devices. The multilayer ceramic capacitor includes a ceramic multilayer body having lead portions that are alternately laminated with ceramic dielectric layers and internal electrode layers, and are drawn out from the capacitance forming portions of the internal electrode layers so as to be exposed to different end faces. In general, the ceramic laminate is provided with an external electrode formed on the end face where the lead portion of each internal electrode layer is exposed. The external electrode includes a base metal and a plating layer formed on the surface layer of the base metal. In view of the demands for simplification of the manufacturing process, reliability of connection between the internal electrodes and the base metal, etc., the unfired ceramic laminate and the unfired base metal are simultaneously fired.
ところで、携帯機器、通信機器等の電子機器において、近年小型化が求められており、これらの電子機器に搭載される電子部品においても小型化が求められているが、積層セラミックコンデンサを小型化するに伴い、セラミック積層体と下地金属との接触面積が減少して、セラミック積層体と下地金属との接着強度が低下する傾向にあった。 By the way, in recent years, electronic devices such as portable devices and communication devices have been required to be downsized, and electronic components mounted on these electronic devices are also required to be downsized. As a result, the contact area between the ceramic laminate and the base metal decreased, and the adhesive strength between the ceramic laminate and the base metal tended to decrease.
特許文献１には、セラミック誘電体層中に、誘電体セラミックにＭｇ化合物が添加され、セラミック誘電体層と内部電極層とを交互に積層したチップ状セラミック積層体（素体）とＮｉ外部電極の境界面に（Ｎｉ、Ｍｇ）化合物の酸化層を有する積層セラミックコンデンサが開示されている。 Patent Document 1 discloses a chip-like ceramic laminate (element body) in which an Mg compound is added to a dielectric ceramic in a ceramic dielectric layer, and ceramic dielectric layers and internal electrode layers are alternately laminated, and a Ni external electrode. A multilayer ceramic capacitor having an oxide layer of a (Ni, Mg) compound on the boundary surface is disclosed.
下地金属の表面にメッキ処理する際において、積層セラミックコンデンサを小型化するに伴い、小型化になった分だけ、短い距離にてセラミック積層体の内部に侵入し易くなる。メッキ液がセラミック積層体の内部に侵入すると、短絡等が発生して所望の電気特性が得られ難くなる。 When plating the surface of the base metal, as the monolithic ceramic capacitor is miniaturized, it becomes easier to enter the ceramic laminate at a short distance by the miniaturization. If the plating solution enters the inside of the ceramic laminate, a short circuit or the like occurs, making it difficult to obtain desired electrical characteristics.
特許文献１の積層セラミックコンデンサは、セラミック積層体とＮｉ外部電極の境界面に、（Ｎｉ、Ｍｇ）化合物の酸化層を有することにより、両者の接合強度を向上させたものである。この接着強度は、セラミック積層体の面と、Ｎｉ外部電極の面に関したものであり、メッキ液の侵入を抑制することについては、特許文献１では検討されていない。接続強度は、セラミック積層体の面と、Ｎｉ外部電極の面とが部分的であっても、強固に接続されていれば（すなわち、すべての面にて、隙間なくつながっていなくても良い）よいのに対し、メッキ液の侵入を抑制するには、一部でも接続していない部分があれば、その部分からメッキ液が侵入してしまう。 The multilayer ceramic capacitor disclosed in Patent Document 1 has an (Ni, Mg) compound oxide layer at the interface between the ceramic laminate and the Ni external electrode, thereby improving the bonding strength between the two. This adhesive strength relates to the surface of the ceramic laminate and the surface of the Ni external electrode, and it has not been studied in Patent Document 1 to suppress the penetration of the plating solution. As for the connection strength, even if the surface of the ceramic laminate and the surface of the Ni external electrode are partial, it is only required to be firmly connected (that is, all surfaces need not be connected without a gap). On the other hand, in order to suppress the penetration of the plating solution, if there is a part that is not connected at all, the plating solution enters from that part.
よって、本発明の目的は、電気特性に優れた積層セラミックコンデンサを歩留まり良く製造可能な積層セラミックコンデンサ及びその製造方法を提供することにある。 Therefore, an object of the present invention is to provide a multilayer ceramic capacitor capable of manufacturing a multilayer ceramic capacitor having excellent electrical characteristics with a high yield and a method for manufacturing the same.
本発明の積層セラミックコンデンサは、セラミック誘電体層と内部電極層とが交互に積層され、前記内部電極層が交互に異なる端面に露出するように形成されたセラミック積層体と、前記セラミック積層体の内部電極層が露出している端面に形成された外部電極とを備えた積層セラミックコンデンサにおいて、前記外部電極は、前記セラミック積層体と同時焼成して形成される金属からなる下地金属と、該下地金属を被覆するメッキ層とからなり、前記下地金属の周縁が、Ｍｇの酸化物と、Ｎｉ及び／又はその酸化物とを含む縁取層で縁取りされて、該縁取層と前記セラミック積層体とが接続されていることを特徴とする。 The multilayer ceramic capacitor of the present invention includes a ceramic multilayer body in which ceramic dielectric layers and internal electrode layers are alternately stacked, and the internal electrode layers are alternately exposed on different end faces; In the multilayer ceramic capacitor comprising an external electrode formed on an end surface where the internal electrode layer is exposed, the external electrode includes a base metal made of a metal formed by simultaneous firing with the ceramic laminate, and the base And a peripheral layer of the base metal is bordered by a border layer containing Mg oxide and Ni and / or oxide thereof, and the border layer and the ceramic laminate are formed. It is connected.
本発明の積層セラミックコンデンサは、前記下地金属が、Ｎｉであることが好ましい。 In the multilayer ceramic capacitor of the present invention, the base metal is preferably Ni.
また、本発明の積層セラミックコンデンサの製造方法は、セラミック誘電体層と内部電極層とが交互に積層され、前記内部電極層が交互に異なる端面に露出するように形成されたセラミック積層体と、前記セラミック積層体の内部電極層が露出している端面に形成された外部電極とを備えた積層セラミックコンデンサの製造方法であって、セラミック粉末を少なくとも含有するセラミックスラリーを塗布してグリーンシートを形成する工程と、前記グリーンシートの表面に第１導体ペーストを印刷して未焼成内部電極層を形成する工程と、未焼成内部電極層が形成されたグリーンシートを積層し、圧着して未焼成セラミック積層体を製造する工程と、前記未焼成セラミック積層体をカットする工程と、カットした未焼成セラミック積層体の前記未焼成内部電極層が露出した端面に、Ｎｉ金属を少なくとも含有する第２導電ペーストを塗布して未焼成下地金属を形成する工程と、前記未焼成下地金属の周縁に、Ｍｇ化合物を含有する縁取層形成用ペーストを塗布し、前記未焼成セラミック積層体と前記未焼成下地金属とを同時焼成する工程と、前記未焼成下地金属を焼成して得られた下地金属の表面をメッキする工程と、を含むことを特徴とする。 Further, in the method for manufacturing a multilayer ceramic capacitor of the present invention, the ceramic dielectric layers and the internal electrode layers are alternately laminated, and the ceramic laminate formed so that the internal electrode layers are alternately exposed on different end faces; A method of manufacturing a multilayer ceramic capacitor comprising an external electrode formed on an end face where an internal electrode layer of the ceramic laminate is exposed, and forming a green sheet by applying a ceramic slurry containing at least ceramic powder A step of printing a first conductive paste on the surface of the green sheet to form an unfired internal electrode layer, and laminating and pressing the green sheet on which the unfired internal electrode layer is formed to form an unfired ceramic. A step of manufacturing a laminate, a step of cutting the green ceramic laminate, and a front of the cut green ceramic laminate A step of applying a second conductive paste containing at least Ni metal to the end face where the unfired internal electrode layer is exposed to form an unfired base metal, and an edge containing Mg compound at the periphery of the unfired base metal Applying a layer forming paste, simultaneously firing the unfired ceramic laminate and the unfired base metal, and plating the surface of the base metal obtained by firing the unfired base metal; It is characterized by including.
本発明の積層セラミックコンデンサは、下地金属の周縁が縁取層で縁取りされてセラミック積層体に接続している。縁取層と下地金属は、両者の構成成分どうしが相互に拡散しあって強固に接合している。特に下地金属としてＮｉを用いた場合、同種の材料どうしなので、両者がより強固に接合する。また、縁取層とセラミック誘電体層は、いずれも酸化物を含む組成物であるので、両者の構成成分どうしが相互に拡散しあって強固に接合している。このように、下地金属の周縁が、縁取層を介してセラミック積層体に強固に接合している。また、縁取層の熱膨張係数は、下地金属とセラミック誘電体層との中間程度であり、縁取層によって、下地金属とセラミック誘電体層との熱膨張係数の差によって生じる応力が緩和され、セラミック誘電体層にクラックが入り難い。このため、本発明の積層セラミックコンデンサは、下地金属の周縁が、セラミック積層体とが隙間なく接続しており、これによってメッキ液の内部への侵入を抑制して絶縁抵抗を維持でき、不良品の発生が少なく歩留まりが良い。 In the multilayer ceramic capacitor of the present invention, the periphery of the base metal is bordered by a border layer and connected to the ceramic laminate. The border layer and the base metal are firmly bonded to each other because their constituent components diffuse to each other. In particular, when Ni is used as the base metal, since the same kind of materials are used, both are bonded more firmly. Further, since the border layer and the ceramic dielectric layer are both compositions containing oxides, the constituent components of both are diffused to each other and are firmly bonded. Thus, the periphery of the base metal is firmly bonded to the ceramic laminate through the border layer. In addition, the thermal expansion coefficient of the border layer is about the middle between the base metal and the ceramic dielectric layer, and the border layer alleviates the stress caused by the difference in the thermal expansion coefficient between the base metal and the ceramic dielectric layer. The dielectric layer is difficult to crack. For this reason, the multilayer ceramic capacitor of the present invention has the periphery of the base metal connected to the ceramic multilayer body without any gaps, thereby suppressing the penetration of the plating solution into the interior and maintaining the insulation resistance. Yield is good.
そして、本発明の積層セラミックコンデンサの製造方法によれば、未焼成下地金属の周縁にＭｇ化合物を含有する縁取層形成用ペーストを塗布して、未焼成セラミック積層体と未焼成下地金属とを同時焼成するので、下地金属の周縁が、Ｍｇの酸化物と、Ｎｉ及び／又はその酸化物とを含む縁取層で縁取りされて、縁取層とセラミック積層体とが接続された積層セラミックコンデンサを製造することができる。 According to the method for manufacturing a multilayer ceramic capacitor of the present invention, a paste for forming an edge layer containing an Mg compound is applied to the periphery of the unfired base metal, and the unfired ceramic laminate and the unfired base metal are simultaneously applied. Since the firing is performed, the peripheral edge of the base metal is edged with an edge layer containing Mg oxide and Ni and / or oxides thereof, and a multilayer ceramic capacitor in which the edge layer and the ceramic laminate are connected is manufactured. be able to.
本発明の積層セラミックコンデンサについて、図１〜４を用いて説明する。図１は、本発明の積層セラミックコンデンサの斜視図であり、図２は、セラミック積層体３の分解斜視図であり、図３は、図１のＡ−Ａ線に沿った断面図であり、図４は、図１の平面図である。 The multilayer ceramic capacitor of the present invention will be described with reference to FIGS. 1 is a perspective view of a multilayer ceramic capacitor of the present invention, FIG. 2 is an exploded perspective view of a ceramic multilayer body 3, and FIG. 3 is a cross-sectional view taken along line AA in FIG. FIG. 4 is a plan view of FIG.
本発明の積層セラミックコンデンサ１０は、セラミック誘電体層１と内部電極層２とが交互に積層され、内部電極層２が交互に異なる端面に露出するように形成されたセラミック積層体３と、セラミック積層体３の内部電極層２が露出している端面に形成された一対の外部電極４，４とを備えている。 The multilayer ceramic capacitor 10 of the present invention includes a ceramic laminate 3 in which ceramic dielectric layers 1 and internal electrode layers 2 are alternately stacked, and the internal electrode layers 2 are alternately exposed on different end faces. It has a pair of external electrodes 4 and 4 formed on the end face where the internal electrode layer 2 of the laminate 3 is exposed.
セラミック誘電体層１は、セラミックペーストをグリーンシート化して焼成したセラミック焼結体から構成される。セラミックペーストとしては、ＢａＴｉＯ３、ＣａＴｉＯ３、ＳｒＴｉＯ３等のセラミック粉末を主原料とし、これに、Ｓｍ、Ｅｕ、Ｇｄ、Ｔｂ、Ｄｙ、Ｈｏ、Ｅｒ、Ｔｍ、Ｙｂ、Ｙ等の希土類金属酸化物、Ｖ、Ｃｒ及びＭｎ等の遷移金属酸化物、ＳｉＯ２等のガラス成分、ＭｇＯ、ＭｇＣＯ３等のＭｇ化合物を添加物として混合したセラミック組成物に、ポリビニルアルコール樹脂、ポリビニルブチラール樹脂等のバインダーと、トルエン等の溶剤と、その他助剤を添加してペースト化したもの等が挙げられる。セラミック組成物は、ＢａＴｉＯ３（チタン酸バリウム）を例として主成分としたものが挙げられる。他にペロブスカイト構造を形成するＢａ１-ｘ−ｙＣａＸＳｒｙＴｉ１−ＺＺｒｚＯ３(０≦Ｘ≦１，０≦ｙ≦１，０≦ｚ≦１)で表されるセラミックスを用いても良い。 The ceramic dielectric layer 1 is formed of a ceramic sintered body obtained by firing a ceramic paste into a green sheet. As ceramic paste, ceramic powder such as BaTiO 3 , CaTiO 3 , SrTiO 3, etc. is used as a main raw material, and rare earth metal oxides such as Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Y, etc. , V, transition metal oxides such as Cr and Mn, glass component such as SiO 2, MgO, the ceramic composition mixed as additives a Mg compound such as MgCO 3, polyvinyl alcohol resin, and a binder such as polyvinyl butyral resin , A solvent such as toluene, and other pastes added with auxiliary agents. Examples of the ceramic composition include those containing BaTiO 3 (barium titanate) as an example as a main component. Ceramics represented by Ba 1-x-y Ca X Sr y Ti 1-Z Zr z O 3 forming the other perovskite structure (0 ≦ X ≦ 1,0 ≦ y ≦ 1,0 ≦ z ≦ 1) It may be used.
内部電極層２は、導体ペーストの薄膜を焼結した金属薄膜からなる。導体ペーストは、導電材料となる導電性金属と、バインダーと、溶剤と、必要に応じてその他助剤とを含んでいる。導電性金属としては、Ｎｉ、Ｃｕ、Ａｇ、Ｐｄ等が挙げられ、後述する下地金属５との同時焼成が容易であるという理由からＮｉ、Ｃｕが好ましい。バインダー、溶剤は、上記したセラミックペーストと同様のものを使用できる。 The internal electrode layer 2 is made of a metal thin film obtained by sintering a thin film of conductive paste. The conductive paste contains a conductive metal serving as a conductive material, a binder, a solvent, and other auxiliary agents as necessary. Examples of the conductive metal include Ni, Cu, Ag, and Pd. Ni and Cu are preferable because they can be easily fired simultaneously with the base metal 5 described later. As the binder and solvent, the same ceramic paste as described above can be used.
外部電極４は、下地金属５と、該下地金属５の表面を被覆するメッキ層６とで構成される。 The external electrode 4 includes a base metal 5 and a plating layer 6 that covers the surface of the base metal 5.
下地金属５は、導体ペーストの薄膜を焼結した金属薄膜からなる。導体ペーストに含まれる導電性金属は、セラミック積層体３と同時焼成して形成される金属であり、例えば、Ｎｉが挙げられる。 The base metal 5 is a metal thin film obtained by sintering a thin film of a conductor paste. The conductive metal contained in the conductor paste is a metal formed by simultaneous firing with the ceramic laminate 3, and examples thereof include Ni.
図３，４を合わせて参照すると、下地金属５の周縁５ａが、Ｍｇの酸化物と、Ｎｉ及び／又はその酸化物とを含む縁取層７で縁取りされて、最外層のセラミック誘電体層１に接続している。縁取層７の幅Ｗは、１〜５０μｍが好ましく、１〜５μｍがより好ましい。縁取層７の幅が５０μｍを超えると、画像認識等で、外部電極と縁取層７とが誤認識されるおそれがあり、更には、メッキ付き性が低下する傾向にある。縁取層７の幅Ｗが１μｍ未満であると、下地金属５とセラミック誘電体層１との接着性が不十分な場合があり、メッキ処理時などにおいて外部から下地金属５の端部に応力が加わると、下地金属５がセラミック誘電体層１から剥離する可能性がある。なお、縁取層７は、セラミック誘電体層１の表面であって、下地電極５の端部（周縁）にて、Ｍｇの酸化物と、Ｎｉ及び／又はその酸化物とを含む部位である。縁取層７が、Ｍｇの酸化物と、Ｎｉ及び／又はその酸化物とを含むものであるかどうかは、縁取層７を元素分析することにより確認できる（Ｍｇ、Ｎｉ、Ｏが同時に検出される）。 3 and 4 together, the peripheral edge 5a of the base metal 5 is bordered by a border layer 7 containing an oxide of Mg and Ni and / or its oxide, so that the outermost ceramic dielectric layer 1 is formed. Connected to. The width W of the border layer 7 is preferably 1 to 50 μm, and more preferably 1 to 5 μm. If the width of the border layer 7 exceeds 50 μm, the external electrode and the border layer 7 may be erroneously recognized by image recognition or the like, and further, the plating property tends to be lowered. If the width W of the border layer 7 is less than 1 μm, the adhesion between the base metal 5 and the ceramic dielectric layer 1 may be insufficient, and stress may be applied to the end of the base metal 5 from the outside during plating or the like. If applied, the base metal 5 may be peeled off from the ceramic dielectric layer 1. The border layer 7 is a part of the surface of the ceramic dielectric layer 1 and containing Mg oxide and Ni and / or oxide thereof at the end (periphery) of the base electrode 5. Whether or not the border layer 7 includes Mg oxide and Ni and / or oxides thereof can be confirmed by elemental analysis of the border layer 7 (Mg, Ni, and O are simultaneously detected).
メッキ層６は、Ｎｉ、Ｃｕ及びこれらの合金からなる第１メッキ層６ａと、該第１メッキ層６ａ上に形成された、Ｓｎ及び／又はＳｎ合金からなる第２メッキ層６ｂとで構成されることが好ましい。第１メッキ層６ａによって、下地金属５と第２メッキ層６ｂとの接着性が向上し、第２メッキ層６ｂによって、半田濡れ性が向上する。 The plating layer 6 includes a first plating layer 6a made of Ni, Cu, and an alloy thereof, and a second plating layer 6b made of Sn and / or an Sn alloy formed on the first plating layer 6a. It is preferable. The adhesion between the base metal 5 and the second plating layer 6b is improved by the first plating layer 6a, and the solder wettability is improved by the second plating layer 6b.
次に、本発明の積層セラミックコンデンサの製造方法の一例について以下説明する。 Next, an example of a method for manufacturing the multilayer ceramic capacitor of the present invention will be described below.
まず、従来公知の方法で形成されたＢａＴｉＯ３粉末等のセラミック粉末と、必要に応じてその他の添加物粉末を適宜の量加え、バインダー及び溶剤を加えて、ボールミルなどで混合攪拌してセラミックスラリーを調製する。その他添加物粉末としては、ＭｇＯ、ＭｇＣＯ３などのＭｇ化合物が好ましい。Ｍｇ化合物は、セラミック粉末１００ｍｏｌに対し０．４〜１．４ｍｏｌ含有することが好ましい。 First, a ceramic slurry such as BaTiO 3 powder formed by a conventionally known method and other additive powders as appropriate are added in an appropriate amount, a binder and a solvent are added, and the mixture is mixed and stirred by a ball mill or the like to be a ceramic slurry. To prepare. Other additive powders are preferably Mg compounds such as MgO and MgCO 3 . The Mg compound is preferably contained in an amount of 0.4 to 1.4 mol with respect to 100 mol of the ceramic powder.
次に、ドクターブレード法等の従来公知の方法により、セラミックスラリーをＰＥＴフィルム等の長尺のベースフィルムに流し、その厚みをドクターブレードとの隙間で調整し、乾燥して、所定厚みのグリーンシートを作製する。 Next, the ceramic slurry is poured into a long base film such as a PET film by a conventionally known method such as a doctor blade method, the thickness is adjusted with a gap between the doctor blade and dried, and then a green sheet having a predetermined thickness is obtained. Is made.
次に、グリーンシート上に、スクリーン印刷法等の従来公知の方法により、内部電極形成用導電ペーストを塗布し、未焼成内部電極層を所定パターンで形成する。 Next, a conductive paste for forming an internal electrode is applied on the green sheet by a conventionally known method such as a screen printing method, and an unfired internal electrode layer is formed in a predetermined pattern.
次に、未焼成内部電極層を形成したグリーンシートを所定の単位寸法でカットしてベースフィルムから取り出し、取り出されたグリーンシートを必要枚数積層し、静水圧プレス機等により圧着成型して未焼成セラミック積層体を作製する。 Next, the green sheet on which the unfired internal electrode layer has been formed is cut out with a predetermined unit size and taken out from the base film, the required number of the taken green sheets are stacked, and then pressure-molded by an isostatic press or the like to be unfired A ceramic laminate is produced.
次に、圧着後の未焼成セラミック積層体を、回転ブレードや昇降ブレード等のブレードでカットして、個々のチップ状未焼成セラミック積層体とする。このチップ状未焼成セラミック積層体の相対する面には未焼成内部電極層の端縁が交互に露出している。 Next, the unfired ceramic laminate after the press bonding is cut with a blade such as a rotary blade or a lifting blade to obtain individual chip-like unfired ceramic laminates. Edges of the unfired internal electrode layers are alternately exposed on the opposing surfaces of the chip-like unfired ceramic laminate.
次に、チップ状未焼成セラミック積層体の未焼成内部電極層が露出した端面に、Ｎｉ金属を少なくとも含有する下地金属形成用導電ペーストを、ローラ塗布法やディップ法等の公知の方法で塗布して、未焼成下地金属を形成する。 Next, a conductive paste for forming a base metal containing at least Ni metal is applied to the end face where the unfired internal electrode layer of the chip-like unfired ceramic laminate is exposed by a known method such as a roller coating method or a dipping method. Thus, an unfired base metal is formed.
次に、チップ状未焼成セラミック積層体の最外層の表層であって、未焼成下地金属の周縁に沿って、ＭｇＯ、ＭｇＣＯ３等のＭｇ化合物を含有する縁取層形成用導電ペーストを塗布する。なお、縁取層形成用導電ペーストの塗布量や、縁取層形成用導電ペーストの中のＭｇＯ粉末の比率をかえることで、焼成後の縁取層７の幅Ｗを調整することができる。 Next, a border layer forming conductive paste containing an Mg compound such as MgO or MgCO 3 is applied along the periphery of the unfired base metal, which is the outermost surface layer of the chip-like unfired ceramic laminate. In addition, the width W of the bordering layer 7 after baking can be adjusted by changing the coating amount of the bordering layer forming conductive paste and the ratio of the MgO powder in the bordering layer forming conductive paste.
そして、脱バインダー炉に投入し、好ましくはＮ２雰囲気で脱バインダー処理した後、焼成炉に投入して、所定の温度及び時間等の条件下で焼成して、チップ状未焼成セラミック積層体と未焼成下地金属とを同時焼成する。焼成温度は、１１５０〜１４００℃が好ましい。焼成時の酸素分圧Ｏ２濃度は６．２×１０−４Ｐａ以下が好ましい。Ｏ２濃度が６．２×１０−４Ｐａよりも大きい場合には、下地金属の酸化が全体的に進んでしまい、次の工程のメッキ付き性が悪くなる。 And after putting into a debinding furnace, preferably after debinding treatment in an N 2 atmosphere, it is put into a firing furnace and fired under conditions such as a predetermined temperature and time, and a chip-like unfired ceramic laminate and Simultaneous firing with the unfired base metal. The firing temperature is preferably 1150 to 1400 ° C. The oxygen partial pressure O 2 concentration during firing is preferably 6.2 × 10 −4 Pa or less. When the O 2 concentration is higher than 6.2 × 10 −4 Pa, the oxidation of the base metal proceeds as a whole, and the plating property in the next step is deteriorated.
次に、未焼成下地金属を焼成して得られた下地金属５の表面を、Ｎｉ、Ｃｕ及びこれらの合金でメッキして第１メッキ層６ａを形成して、第２メッキ層６ａのメッキ付け性を向上させる。その後、第１メッキ層６ａ上に、Ｓｎ及び／又はＳｎ合金でメッキして第２メッキ層６ｂを形成する。メッキ方法としては特に限定はなく、バレルメッキなど従来公知の方法が挙げられる。 Next, the surface of the base metal 5 obtained by firing the unfired base metal is plated with Ni, Cu, and alloys thereof to form the first plating layer 6a, and the second plating layer 6a is plated. Improve sexiness. Thereafter, the second plating layer 6b is formed on the first plating layer 6a by plating with Sn and / or an Sn alloy. The plating method is not particularly limited, and a conventionally known method such as barrel plating can be used.
このようにして、図１〜４に示す本発明の積層セラミックコンデンサ１０が得られる。この積層セラミックコンデンサ１０は、下地金属５の周縁が縁取層７で縁取りされてセラミック誘電体層１に接続している。縁取層７と下地金属５は、相溶性が良好で、両者の構成成分どうしが相互に拡散しあって強固に接合している。また、縁取層７とセラミック誘電体層１は、いずれも酸化物を含む組成物であるので、両者の構成成分どうしが相互に拡散しあって強固に接合している。また、ＢａＴｉＯ３を主成分とするセラミック誘電体層１の熱膨張係数は約１０〜１２×１０−６℃−１であり、Ｎｉ金属からなる下地金属５の熱膨張係数は約１４〜１６×１０−６℃−１であり、セラミック誘電体層１と下地金属５は、熱膨張係数が異なる材料で構成されていることから、従来では、未焼成セラミック積層体と、未焼成下地金属とを同時焼成すると、セラミック誘電体層１の下地金属５の周縁と接する部分を起点にして、セラミック誘電体層１にクラックが発生したり、下地金属５がセラミック誘電体層１からはがれることがあった。この積層セラミックコンデンサは、下地金属５の周縁が縁取層７で縁取りされてセラミック誘電体層１に接続しており、縁取層７の熱膨張係数は約１１〜１４×１０−６℃−１であることから、縁取層７によって、下地金属５とセラミック誘電体層１との熱膨張係数の差によって生じる応力が緩和され、セラミック誘電体層１にクラックが入り難い。また、下地金属５がセラミック誘電体層１からはがれ難く、下地金属５とセラミック誘電体層１とがほぼ隙間なく接続している。 In this way, the multilayer ceramic capacitor 10 of the present invention shown in FIGS. In this multilayer ceramic capacitor 10, the periphery of the base metal 5 is bordered by a border layer 7 and connected to the ceramic dielectric layer 1. The border layer 7 and the base metal 5 have good compatibility, and the constituent components of both are diffused to each other and bonded firmly. Further, since the border layer 7 and the ceramic dielectric layer 1 are both compositions containing oxides, the constituent components of the two diffuse mutually and are firmly bonded. Further, the thermal expansion coefficient of the ceramic dielectric layer 1 mainly composed of BaTiO 3 is about 10 to 12 × 10 −6 ° C.− 1 , and the thermal expansion coefficient of the base metal 5 made of Ni metal is about 14 to 16 ×. Since it is 10 <-6> (degreeC) -1 and the ceramic dielectric material layer 1 and the base metal 5 are comprised by the material from which a thermal expansion coefficient differs, conventionally, an unfired ceramic laminated body and an unfired base metal are used. When fired at the same time, cracks may occur in the ceramic dielectric layer 1 starting from the portion of the ceramic dielectric layer 1 in contact with the periphery of the base metal 5, or the base metal 5 may peel off from the ceramic dielectric layer 1. . In this multilayer ceramic capacitor, the periphery of the base metal 5 is bordered by a border layer 7 and connected to the ceramic dielectric layer 1, and the thermal expansion coefficient of the border layer 7 is about 11 to 14 × 10 −6 ° C. −1 . For this reason, the border layer 7 relieves stress caused by the difference in thermal expansion coefficient between the base metal 5 and the ceramic dielectric layer 1, and the ceramic dielectric layer 1 is difficult to crack. Further, the base metal 5 is difficult to peel off from the ceramic dielectric layer 1, and the base metal 5 and the ceramic dielectric layer 1 are connected with almost no gap.
このため、本発明の積層セラミックコンデンサは、メッキ液の内部への侵入を抑制でき、これによって電気特性（絶縁抵抗）のバラつきや低下を抑えることができ、不良品の発生率が極めて低く、歩留まりがよい。 For this reason, the multilayer ceramic capacitor of the present invention can suppress the penetration of the plating solution into the interior, thereby suppressing variation and decrease in electrical characteristics (insulation resistance), and the occurrence rate of defective products is extremely low, yield. Is good.
つまり、本発明では、積層セラミックコンデンサにて、セラミック誘電体と、下地電極との縁部に着目したものである。積層セラミックコンデンサの製造工程において、セラミック積層体と下地電極とを同時焼成すると、下地電極の縁部にてセラミック誘電体と、下地電極との熱膨張差により密着性が悪くなること（クラック、はがれ）、その後のメッキ処理工程において、セラミック積層体と下地金属との界面において、両者が接続していない部分があると、その部分からメッキ液が侵入すること、との観点から、下地金属の周縁をセラミック積層体に隙間なく接続することにより、メッキ液の侵入による絶縁抵抗を維持できる効果が得られている。 That is, the present invention focuses on the edge of the ceramic dielectric and the base electrode in the multilayer ceramic capacitor. In the manufacturing process of a multilayer ceramic capacitor, if the ceramic laminate and the base electrode are fired simultaneously, the adhesion of the ceramic dielectric and the base electrode at the edge of the base electrode may deteriorate due to the difference in thermal expansion (crack, peeling). ) In the subsequent plating treatment step, if there is a portion where the two are not connected at the interface between the ceramic laminate and the base metal, the periphery of the base metal from the viewpoint that the plating solution enters from that portion. By connecting to the ceramic laminate without any gap, an effect of maintaining the insulation resistance due to the penetration of the plating solution is obtained.
以下の実施例、比較例で使用したセラミックスラリー、内部電極形成用導電ペースト、外部部電極形成用導電ペースト、縁取層形成用導電ペーストは以下である。 The ceramic slurry, internal electrode forming conductive paste, external electrode forming conductive paste, and bordering layer forming conductive paste used in the following Examples and Comparative Examples are as follows.
・セラミックスラリー１
アルコキシド法にて作製した平均粒径０．１５μｍのＢａＴｉＯ３粉末を用い、ＢａＴｉＯ３１００ｍｏｌに対し、Ｈｏ２Ｏ３１．０ｍｏｌ、ＭｇＯ０．４ｍｏｌ、ＭｎＯ０．１ｍｏｌ、ＳｉＯ２１．５ｍｏｌの割合にて、トルエン中で混合し、ブチラール樹脂を添加してセラミックスラリーを作製した。
・ Ceramic slurry 1
Using BaTiO 3 powder with an average particle size of 0.15 μm produced by the alkoxide method, with respect to 100 mol of BaTiO 3 , Ho 2 O 3 1.0 mol, MgO 0.4 mol, MnO 0.1 mol, SiO 2 1.5 mol The mixture was mixed in toluene, butyral resin was added to prepare a ceramic slurry.
・セラミックスラリー２
アルコキシド法にて作製した平均粒径０．１５μｍのＢａＴｉＯ３粉末を用い、ＢａＴｉＯ３１００ｍｏｌに対し、Ｈｏ２Ｏ３１．０ｍｏｌ、ＭｇＯ１．０ｍｏｌ、ＭｎＯ０．１ｍｏｌ、ＳｉＯ２１．５ｍｏｌの割合にて、トルエン中で混合し、ブチラール樹脂を添加してセラミックスラリーを作製した。
・ Ceramic slurry 2
Using BaTiO 3 powder having an average particle size of 0.15 μm prepared by the alkoxide method, with respect to 100 mol of BaTiO 3 , Ho 2 O 3 1.0 mol, MgO 1.0 mol, MnO 0.1 mol, SiO 2 1.5 mol The mixture was mixed in toluene, butyral resin was added to prepare a ceramic slurry.
・内部電極形成用導電ペースト
平均粒径０．２μｍのＮｉ粉末に、共材としてＢａＴｉＯ３粉末とエチルセルロース及びターピネオールを加えて混合し、内部電極形成用導電ペーストを作製した。
· The Ni powder of the internal electrode-forming conductive paste average particle size 0.2 [mu] m, and mixed by adding BaTiO 3 powder and ethyl cellulose and terpineol as a common material, to prepare an internal electrode-forming conductive paste.
・下地金属形成用導電ペースト
平均粒径０．５μｍのＮｉ粉末に、エチルセルロースとブチルカルビトールを加えて混合し、下地金属形成用導電ペーストを作製した。
-Conductive paste for forming a base metal An electrically conductive paste for forming a base metal was prepared by adding ethyl cellulose and butyl carbitol to Ni powder having an average particle size of 0.5 µm and mixing them.
・縁取層形成用導電ペースト
平均粒径０．２μｍのＭｇＯ粉末に、エチルセルロースとブチルカルビトールを加えて混合し、縁取層形成用導電ペーストを作製した。
-Conductive paste for bordering layer formation Ethylcellulose and butyl carbitol were added to and mixed with MgO powder having an average particle size of 0.2 µm to prepare a conductive paste for bordering layer formation.
（実施例１）
セラミックスラリー１を、ＰＥＴフィルム上にドクターブレード法により塗布して厚さ３μｍグリーンシートを形成した。次に、このグリーンシート上に、スクリーン印刷法により、内部電極形成用導電ペーストを塗布して、未焼成内部電極層を形成した。次に、未焼成内部電極層を形成したグリーンシートを４８０層積層し、静水圧プレス機により圧着成型した後、焼成後に１．０ｍｍ×０．５ｍｍの大きさになるように切断分割して、チップ状未焼成セラミック積層体を作製した。次に、チップ状未焼成セラミック積層体の未焼成内部電極層が露出した端面に、下地金属形成用導電ペーストを、ローラ塗布して、未焼成下地金属を形成した。次に、チップ状未焼成セラミック積層体の最外層の表層であって、未焼成下地金属の周縁に沿って、縁取層形成用導電ペーストを塗布した。そして、脱バインダー炉に投入し、Ｎ２雰囲気で１２６０℃、２時間加熱して脱バインダー処理した後、焼成炉に投入して、焼成雰囲気中の酸素分圧（Ｏ２濃度）を６．２×１０−４Ｐａの条件にて、１２６０℃で２時間保持して焼成を行なった。その後、再酸化を目的とした再酸化処理を１０００℃／１ｈ、３０Ｐａで実施した後、バレルメッキ法により、Ｃｕメッキ、Ｓｎ−Ｚｎメッキの順にメッキ層を施して、実施例１の積層セラミックコンデンサを得た。
Example 1
Ceramic slurry 1 was applied onto a PET film by a doctor blade method to form a green sheet having a thickness of 3 μm. Next, a conductive paste for forming an internal electrode was applied on the green sheet by screen printing to form an unfired internal electrode layer. Next, 480 layers of green sheets on which an unfired internal electrode layer was formed were laminated, pressure-molded with an isostatic press, and then cut and divided to have a size of 1.0 mm × 0.5 mm after firing, A chip-shaped unfired ceramic laminate was produced. Next, a base metal-forming conductive paste was applied onto the end surface of the chip-like unfired ceramic laminate exposed from the unfired internal electrode layer, to form an unfired base metal. Next, a conductive paste for forming an edge layer was applied along the outer periphery of the chip-shaped unfired ceramic laminate and along the periphery of the unfired base metal. Then, it was put into a debinding furnace, heated at 1260 ° C. for 2 hours in an N 2 atmosphere, and then subjected to a debinding process, and then put into a firing furnace to set the oxygen partial pressure (O 2 concentration) in the firing atmosphere to 6.2. Firing was performed at 1260 ° C. for 2 hours under the condition of × 10 −4 Pa. Then, after re-oxidation treatment for the purpose of re-oxidation was performed at 1000 ° C./1 h, 30 Pa, plating layers were applied in the order of Cu plating and Sn—Zn plating by barrel plating, and the multilayer ceramic capacitor of Example 1 Got.
この積層セラミックコンデンサの図１の平面方向から見た写真（１２０倍拡大）を図５に示す。また、図５の範囲ａの部分の電子顕微鏡写真（６００倍拡大）を図６に示す。また、図６の範囲ｂの部分の元素分析結果を図７に示す。
図５〜７に示されるように、この積層セラミックコンデンサは、下地金属の周縁が、Ｍｇの酸化物と、Ｎｉ及び／又はその酸化物とを含む縁取層で縁取りされていた。
また、この積層セラミックコンデンサについて、ＤＣ２５Ｖを印加して１分後、絶縁抵抗試験を行い、抵抗値が１０ＭΩ以上のものを合格とし、抵抗値が１０ＭΩ未満のものを不合格としたところ、試験数１００個中、不合格数は０個であった。結果を表１に記す。
FIG. 5 shows a photograph of the multilayer ceramic capacitor as viewed from the plane direction of FIG. FIG. 6 shows an electron micrograph (enlarged 600 times) of the range a in FIG. In addition, FIG. 7 shows the elemental analysis results in the range b of FIG.
As shown in FIGS. 5 to 7, in this multilayer ceramic capacitor, the periphery of the base metal was bordered by a border layer containing Mg oxide and Ni and / or oxides thereof.
In addition, with respect to this multilayer ceramic capacitor, an insulation resistance test was conducted 1 minute after applying DC25V, and a resistance value of 10 MΩ or more was accepted and a resistance value of less than 10 MΩ was rejected. Out of 100, the number of rejects was zero. The results are shown in Table 1.
（実施例２）
実施例１において、セラミックスラリー１の代わりにセラミックスラリー２を用いた以外は、実施例１と同様にしてチップ状未焼成セラミック積層体を作製し、その最外層の表層であって、未焼成下地金属の周縁に沿って、縁取層形成用導電ペーストを塗布した。そして、脱バインダー炉に投入し、Ｎ２雰囲気で１２６０℃、２時間加熱して脱バインダー処理した後、焼成炉に投入して、焼成雰囲気中の酸素分圧（Ｏ２濃度）を３．０×１０−４Ｐａの条件にて、１２６０℃で２時間保持して焼成を行なった。その後、再酸化を目的とした再酸化処理を１０００℃／１ｈ、３０Ｐａで実施した後、バレルメッキ法により、Ｃｕメッキ、Ｓｎ−Ｚｎメッキの順にメッキ層を施して、実施例２の積層セラミックコンデンサを得た。
この積層セラミックコンデンサは、下地金属の周縁が、Ｍｇの酸化物と、Ｎｉ及び／又はその酸化物とを含む縁取層で縁取りされていた。
また、実施例１と同様にして絶縁抵抗試験を行ったところ、試験数１００個中、不合格数は０個であった。結果を表１に記す。
(Example 2)
In Example 1, a chip-like unfired ceramic laminate was prepared in the same manner as in Example 1 except that ceramic slurry 2 was used instead of ceramic slurry 1, and was the outermost surface layer of the unfired substrate. A conductive paste for forming a border layer was applied along the periphery of the metal. And after putting into a debinding furnace and heating at 1260 ° C. for 2 hours in an N 2 atmosphere and debinding, it is put into a baking furnace and an oxygen partial pressure (O 2 concentration) in the baking atmosphere is set to 3.0. Firing was performed at 1260 ° C. for 2 hours under the condition of × 10 −4 Pa. Then, after re-oxidation treatment for the purpose of re-oxidation was performed at 1000 ° C./1 h and 30 Pa, a plating layer was applied in the order of Cu plating and Sn—Zn plating by barrel plating, and the multilayer ceramic capacitor of Example 2 Got.
In this multilayer ceramic capacitor, the periphery of the base metal was bordered by a border layer containing an oxide of Mg and Ni and / or the oxide thereof.
Moreover, when the insulation resistance test was conducted in the same manner as in Example 1, the number of failures was 0 out of 100. The results are shown in Table 1.
（比較例１）
実施例１において、縁取層形成用導電ペーストを使用しなかった以外は実施例１と同様にして積層セラミックコンデンサを得た。この積層セラミックコンデンサは、縁取層が形成されていなかった。また、実施例１と同様にして絶縁抵抗試験を行ったところ、試験数１００個中、不合格数は４個であった。結果を表１に記す。
(Comparative Example 1)
In Example 1, a multilayer ceramic capacitor was obtained in the same manner as in Example 1 except that the conductive paste for forming the border layer was not used. In this multilayer ceramic capacitor, the border layer was not formed. Moreover, when the insulation resistance test was conducted in the same manner as in Example 1, the number of failures was 4 out of 100 tests. The results are shown in Table 1.
（比較例２）
実施例２において、縁取層形成用導電ペーストを使用しなかった以外は実施例２と同様にして積層セラミックコンデンサを得た。この積層セラミックコンデンサは、縁取層が形成されていなかった。また、実施例１と同様にして絶縁抵抗試験を行ったところ、試験数１００個中、不合格数は４個であった。結果を表１に記す。
(Comparative Example 2)
In Example 2, a multilayer ceramic capacitor was obtained in the same manner as Example 2 except that the conductive paste for forming the border layer was not used. In this multilayer ceramic capacitor, the border layer was not formed. Moreover, when the insulation resistance test was conducted in the same manner as in Example 1, the number of failures was 4 out of 100 tests. The results are shown in Table 1.
１：セラミック誘電体層
２：内部電極層
３：セラミック積層体
４：外部電極
５：下地金属
６：メッキ層
６ａ：第１メッキ層
６ｂ：第２メッキ層
７：縁取層
1: Ceramic dielectric layer 2: Internal electrode layer 3: Ceramic laminate 4: External electrode 5: Base metal 6: Plating layer 6a: First plating layer 6b: Second plating layer 7: Border layer
Claims (3)
前記外部電極は、前記セラミック積層体と同時焼成して形成される金属からなる下地金属と、該下地金属を被覆するメッキ層とからなり、
前記下地金属の周縁が、Ｍｇの酸化物と、Ｎｉ及び／又はその酸化物とを含む縁取層で縁取りされて、該縁取層と前記セラミック積層体とが接続されていることを特徴とする積層セラミックコンデンサ。 Ceramic dielectric layers and internal electrode layers are alternately laminated, the ceramic laminate formed such that the internal electrode layers are alternately exposed at different end faces, and the internal electrode layers of the ceramic laminate are exposed In the multilayer ceramic capacitor provided with the external electrode formed on the end face,
The external electrode is composed of a base metal made of metal formed by simultaneous firing with the ceramic laminate, and a plating layer covering the base metal,
Laminate characterized in that a peripheral edge of the base metal is bordered by a border layer containing Mg oxide and Ni and / or oxide thereof, and the border layer and the ceramic laminate are connected. Ceramic capacitor.
セラミック粉末を少なくとも含有するセラミックスラリーを塗布してグリーンシートを形成する工程と、
前記グリーンシートの表面に第１導体ペーストを印刷して未焼成内部電極層を形成する工程と、
未焼成内部電極層が形成されたグリーンシートを積層し、圧着して未焼成セラミック積層体を製造する工程と、
前記未焼成セラミック積層体をカットする工程と、
カットした未焼成セラミック積層体の前記未焼成内部電極層が露出した端面に、Ｎｉ金属を少なくとも含有する第２導電ペーストを塗布して未焼成下地金属を形成する工程と、
前記未焼成下地金属の周縁に、Ｍｇ化合物を含有する縁取層形成用ペーストを塗布し、前記未焼成セラミック積層体と前記未焼成下地金属とを同時焼成する工程と、
前記未焼成下地金属を焼成して得られた下地金属の表面をメッキする工程と、を含むことを特徴とする積層セラミックコンデンサの製造方法。 Ceramic dielectric layers and internal electrode layers are alternately laminated, the ceramic laminate formed such that the internal electrode layers are alternately exposed at different end faces, and the internal electrode layers of the ceramic laminate are exposed A method for producing a multilayer ceramic capacitor comprising an external electrode formed on an end face,
Applying a ceramic slurry containing at least a ceramic powder to form a green sheet;
Printing a first conductive paste on the surface of the green sheet to form an unfired internal electrode layer;
Laminating a green sheet on which an unfired internal electrode layer has been formed, press-bonding, and manufacturing an unfired ceramic laminate,
Cutting the green ceramic laminate;
Applying a second conductive paste containing at least Ni metal to an end face where the unfired internal electrode layer of the cut unfired ceramic laminate is exposed to form an unfired base metal;
Applying a border layer forming paste containing Mg compound to the periphery of the unfired base metal, and simultaneously firing the unfired ceramic laminate and the unfired base metal;
And a step of plating the surface of the base metal obtained by firing the unfired base metal.
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