JP5491333B2 - 集積回路の設計のためのデバイスミスマッチのモデリングおよびシミュレーティング - Google Patents

集積回路の設計のためのデバイスミスマッチのモデリングおよびシミュレーティング Download PDF

Info

Publication number
JP5491333B2
JP5491333B2 JP2010205642A JP2010205642A JP5491333B2 JP 5491333 B2 JP5491333 B2 JP 5491333B2 JP 2010205642 A JP2010205642 A JP 2010205642A JP 2010205642 A JP2010205642 A JP 2010205642A JP 5491333 B2 JP5491333 B2 JP 5491333B2
Authority
JP
Japan
Prior art keywords
layout
devices
matching
computer
style
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2010205642A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011081786A5 (enExample
JP2011081786A (ja
Inventor
ジェイ，オリオーダン ドナルド
アーサー，シャルデンブランド
ジョン，オドノヴァン
Original Assignee
ケイデンス デザイン システムズ， インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ケイデンス デザイン システムズ， インコーポレイテッド filed Critical ケイデンス デザイン システムズ， インコーポレイテッド
Publication of JP2011081786A publication Critical patent/JP2011081786A/ja
Publication of JP2011081786A5 publication Critical patent/JP2011081786A5/ja
Application granted granted Critical
Publication of JP5491333B2 publication Critical patent/JP5491333B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/08—Probabilistic or stochastic CAD
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2010205642A 2009-09-17 2010-09-14 集積回路の設計のためのデバイスミスマッチのモデリングおよびシミュレーティング Expired - Fee Related JP5491333B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/561,801 US8176463B2 (en) 2009-09-17 2009-09-17 Modeling and simulating device mismatch for designing integrated circuits
US12/561,801 2009-09-17

Publications (3)

Publication Number Publication Date
JP2011081786A JP2011081786A (ja) 2011-04-21
JP2011081786A5 JP2011081786A5 (enExample) 2013-10-24
JP5491333B2 true JP5491333B2 (ja) 2014-05-14

Family

ID=43432014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010205642A Expired - Fee Related JP5491333B2 (ja) 2009-09-17 2010-09-14 集積回路の設計のためのデバイスミスマッチのモデリングおよびシミュレーティング

Country Status (3)

Country Link
US (1) US8176463B2 (enExample)
EP (1) EP2306348A1 (enExample)
JP (1) JP5491333B2 (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8645901B2 (en) * 2009-12-01 2014-02-04 Cadence Design Systems, Inc. Visualization and information display for shapes in displayed graphical images based on a cursor
TWI476619B (zh) * 2011-12-01 2015-03-11 Ncku Res & Dev Foundation 類比積體電路布局的電阻匹配方法
KR101502103B1 (ko) * 2013-01-30 2015-03-12 삼성전자 주식회사 자기공명영상장치 및 자화강조영상법
EP2762910A1 (en) 2013-01-30 2014-08-06 Samsung Electronics Co., Ltd Susceptibility-weighted magnetic resonance imaging
US9922146B2 (en) 2013-03-21 2018-03-20 Nxp Usa, Inc. Tool apparatus, method and computer program for designing an integrated circuit
US9255962B2 (en) 2013-08-15 2016-02-09 GlobalFoundries, Inc. Determining intra-die variation of an integrated circuit
CN104715094A (zh) * 2013-12-17 2015-06-17 北京华大九天软件有限公司 一种自动生成匹配器件方法
US9679094B2 (en) 2015-04-29 2017-06-13 International Business Machines Corporation Determining correlation coefficient(s) among different field effect transistor types and/or among different electrical parameter types
US20170046470A1 (en) * 2015-08-14 2017-02-16 Globalfoundries Inc. Process design kit for efficient and accurate mismatch simulation of analog circuits
US10216887B1 (en) 2015-12-18 2019-02-26 Cadence Design Systems, Inc. Methods, systems, and computer program products for implementing an electronic design with time varying resistors in power gating analysis
US10162931B2 (en) * 2017-03-28 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Method of forming serpentine resistor
US10262092B1 (en) * 2017-05-08 2019-04-16 Cadence Design Systems, Inc. Interactive platform to predict mismatch variation and contribution when adjusting component parameters
DE102017213583A1 (de) * 2017-08-04 2019-02-07 Siemens Aktiengesellschaft Verfahren zur Produktionsplanung
US10467370B1 (en) 2017-09-30 2019-11-05 Cadence Design Systems, Inc. Methods, systems, and computer program product for implementing a net as a transmission line model in a schematic driven extracted view for an electronic design
US10558780B1 (en) 2017-09-30 2020-02-11 Cadence Design Systems, Inc. Methods, systems, and computer program product for implementing schematic driven extracted views for an electronic design
US10678978B1 (en) * 2017-09-30 2020-06-09 Cadence Design Systems, Inc. Methods, systems, and computer program product for binding and back annotating an electronic design with a schematic driven extracted view
CN108256219B (zh) * 2018-01-18 2021-08-06 上海华虹宏力半导体制造有限公司 一种mos晶体管的器件失配模型的修正方法及系统
US10916042B2 (en) * 2019-03-12 2021-02-09 DecisionNext, Inc. Methods and devices for capturing heuristic information via a relationship tool
CN109933946B (zh) * 2019-03-29 2023-08-18 上海华力集成电路制造有限公司 一种半导体器件的分析方法
US10997333B1 (en) 2019-12-05 2021-05-04 Cadence Design Systems, Inc. Methods, systems, and computer program product for characterizing an electronic design with a schematic driven extracted view
TWI717302B (zh) * 2020-07-30 2021-01-21 頂極科技股份有限公司 半導體製程零配件的質變檢測系統及方法
US11361142B2 (en) * 2020-08-31 2022-06-14 Siemens Industry Software Inc. Estimating integrated circuit yield from modeled response to scaling of distribution samples
US20230195984A1 (en) * 2021-12-22 2023-06-22 Texas Instruments Incorporated Method for timing signoff in mixed-transistor designs
GB2620947B (en) * 2022-07-26 2025-02-19 Agile Analog Ltd Analogue circuit design

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7418683B1 (en) * 2005-09-21 2008-08-26 Cadence Design Systems, Inc Constraint assistant for circuit design

Also Published As

Publication number Publication date
US8176463B2 (en) 2012-05-08
EP2306348A1 (en) 2011-04-06
JP2011081786A (ja) 2011-04-21
US20110066997A1 (en) 2011-03-17

Similar Documents

Publication Publication Date Title
JP5491333B2 (ja) 集積回路の設計のためのデバイスミスマッチのモデリングおよびシミュレーティング
US8117576B2 (en) Method for using an equivalence checker to reduce verification effort in a system having analog blocks
US9223925B2 (en) Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awareness
US6292766B1 (en) Simulation tool input file generator for interface circuitry
US6286126B1 (en) Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits using best and worst case delay models for nets therein
JP2810341B2 (ja) 超ｌｓｉ回路のパワーネットワークの分析装置及び分析方法
US6289412B1 (en) Layout synopsizing process for efficient layout parasitic extraction and circuit simulation in post-layout verification
US5790835A (en) Practical distributed transmission line analysis
US8806414B2 (en) Method and system for layout parasitic estimation
KR101000544B1 (ko) 집적회로에서 여파된 상호접속에 대한 배선 기생 추출
US20150269297A1 (en) Methods for reducing post layout circuit simulation results
US20070094622A1 (en) Methods, Apparatus and Computer Program Products for Generating Selective Netlists that Include Interconnection Influences at Pre-Layout and Post-Layout Design Stages
US7434183B2 (en) Method and system for validating a hierarchical simulation database
US7340697B2 (en) Integrated computer-aided circuit design kit facilitating verification of designs across different process technologies
KR100895260B1 (ko) 회로 모델 축소 해석 방법
TWI775299B (zh) 在電子設計自動化平台上進行電壓規則檢查的電腦實施方法
US6230302B1 (en) Method and system for performing timing analysis on an integrated circuit design
US7900174B2 (en) Method and system for characterizing an integrated circuit design
US8091052B2 (en) Optimization of post-layout arrays of cells for accelerated transistor level simulation
US8813004B1 (en) Analog fault visualization system and method for circuit designs
US7036096B1 (en) Estimating capacitances using information including feature sizes extracted from a netlist
US6272665B1 (en) Method and tool for automatically generating engineering change order
US8316336B1 (en) Method and mechanism for modeling interconnect structures for integrated circuits
US20050138587A1 (en) Analysis of congestion attributed to component placement in an integrated circuit topology floor-plan
US20110078649A1 (en) Wafer layout assisting method and system

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130909

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130909

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20131226

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140128

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140227

R150 Certificate of patent or registration of utility model

Ref document number: 5491333

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees