JP5488445B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device, and in particular, in each pixel, a positive-polarity video signal and a negative-polarity video signal are separately sampled and held in two holding capacitors, and then those holding voltages are alternately applied to the pixel electrodes. The present invention relates to a liquid crystal display device in which a display element is AC driven.

  In recent years, a liquid crystal display device of LCOS (Liquid Crystal on Silicon) type is often used as a central part for projecting images in projector devices and projection televisions. As this LCOS type liquid crystal display device, the present applicant has first made a plurality of sets of data lines including two data lines (column signal lines) and a plurality of gate lines (row scanning lines). Pixels are arranged in a matrix at each intersection, and positive and negative video signals are sampled and held separately in two holding capacitors at each pixel, and then the holding voltages are alternately applied to the pixel electrodes. A liquid crystal display device is proposed in which the liquid crystal display element is AC-driven by applying the voltage to the liquid crystal display (see, for example, Patent Document 1).

  FIG. 5 shows an equivalent circuit diagram of an example of one pixel of the liquid crystal display device. In the figure, one pixel has pixel selection transistors Tr1 and Tr2 for writing a positive-polarity video signal and a negative-polarity video signal, and two independent holdings that hold video signal voltages of respective polarities in parallel. Capacitors Cs1 and Cs2, transistors Tr3 to Tr7, and a liquid crystal display element LC are included. The liquid crystal display element LC has a well-known structure in which a liquid crystal layer (display body) LCM is sandwiched between a pixel electrode PE and a common electrode CE arranged to face each other.

  The pixel selection transistors Tr1 and Tr2 are N-channel MOS field effect transistors (hereinafter referred to as NMOS transistors). The source follower transistors Tr3 and Tr4, the switching transistors Tr5 and Tr6, and the transistor Tr7 are P A channel MOS field effect transistor (hereinafter referred to as a PMOS transistor). The transistors Tr3 and Tr7 and the transistors Tr4 and Tr7 constitute a so-called source follower buffer. The transistors Tr3 and Tr4 function as a source follower transistor, and the transistor Tr7 functions as a constant current source load. The input resistance of the source follower buffer of the MOS transistor is almost infinite, and the charges accumulated in the holding capacitors Cs1 and Cs2 are held without leakage until a signal is newly written after one vertical scanning period.

  The pixel portion data lines are composed of a pair of positive data lines Di + and negative data lines Di− for each pixel, and video signals having different polarities sampled by a data line driving circuit (not shown). Is supplied. The drain terminals of the pixel selection NMOS transistors Tr1 and Tr2 are connected to the positive polarity data line Di + and the negative polarity data line Di-, respectively, and the gate terminals are connected to the row scanning line (gate line) Gj for the same row. Has been. The wirings S + and S− are wirings for gate control signals, and are connected to the gates of the PMOS transistors Tr5 and Tr6, respectively. Further, the row scanning line Gj is commonly connected to the transistors Tr1 and Tr2 of a plurality of pixels in the same row.

  In addition, the constant current load PMOS transistor Tr7 has a configuration in which the wiring B is commonly connected in the row direction for the same row pixel in the row direction, and bias control of the constant current load is possible. When the constant current load transistor Tr7 is configured by a PMOS transistor, as shown in FIG. 5, the drain terminal as the current supply terminal and the back gate (configured by the N well) are both VDD. Therefore, normally, both are connected and the voltage is supplied by the same wiring.

  Next, an outline of the AC drive control of the pixel will be described with reference to the timing chart of FIG. 6B shows a vertical synchronization signal VD which is a reference for vertical scanning of the video signal, and FIG. 6C shows a wiring B applied to the gate of the constant current load PMOS transistor Tr7 in the pixel of FIG. The load characteristic control signal is shown. FIG. 6D shows a gate control signal of the wiring S + applied to the gate of the switching PMOS transistor Tr5 for transferring the positive side drive voltage in the pixel, and FIG. 6E shows the negative electrode in the pixel. 5 shows signal waveforms of a gate control signal of the wiring S− applied to the gate of the switching PMOS transistor Tr6 that transfers the active side drive voltage.

  In FIG. 5, during the period when the gate control signal of the wiring S + shown in FIG. 6D is at a high level, the positive polarity side switching PMOS transistor Tr5 is turned on, and the load characteristic control signal supplied to the wiring B during this period As shown in FIG. 6C, when the level is low, the source follower buffer becomes active, and the pixel electrode PE node is charged to the positive video signal level. When the potential of the pixel electrode PE is fully charged, when the load characteristic control signal of the wiring B is set to high level and the gate control signal of the wiring S + is switched to low level at that time, the pixel electrode PE becomes floating, and a positive drive voltage is held in the liquid crystal capacitor.

  On the other hand, the negative side switching PMOS transistor Tr6 is turned on while the gate control signal of the wiring S- shown in FIG. 6E is at a high level, and the load characteristic control signal supplied to the wiring B during this period is shown in FIG. When it is at a low level as shown in (C), the source follower buffer becomes active, and the pixel electrode PE node is charged to a negative video signal level. When the potential of the pixel electrode PE is fully charged, the load characteristic control signal of the wiring B is set to the high level, and the gate control signal of the wiring S- is switched to the low level at that time. PE becomes floating, and the negative drive voltage is held in the liquid crystal capacitor.

  Hereinafter, in synchronization with the switching for turning on the switching PMOS transistors Tr5 and Tr6 alternately, the operation of intermittently making the PMOS transistor Tr7 active in response to the load characteristic control signal of the wiring B is repeated. A driving voltage VPE converted into an alternating current by each of the positive and negative video signals is applied to the LC pixel electrode PE as shown in FIG. The pixel shown in FIG. 5 does not directly transfer the retained charge to the pixel electrode PE, but supplies the voltage via the source follower buffer. Therefore, it is possible to realize driving without attenuation of the voltage level.

  Further, Vcom shown in FIG. 6G represents a voltage applied to the common electrode CE formed on the counter substrate of the liquid crystal display device. The substantial AC drive voltage of the liquid crystal layer LCM is a difference voltage between the applied voltage Vcom of the common electrode CE and the applied voltage of the pixel electrode PE. As shown in FIG. 6H, the applied voltage Vcom of the common electrode CE is inverted in synchronization with pixel polarity switching with respect to a reference level substantially equal to the inversion reference level Vc of the pixel electrode potential.

  Further, the positive and negative video signal voltages sampled and held in the holding capacitors Cs1 and Cs2, respectively, are read out through the high-input-resistance source follower PMOS transistors Tr3 and Tr4, as shown in FIG. As shown in (E), the pixel electrodes PE are alternately selected by the switching PMOS transistors Tr5 and Tr6 which are turned on by the gate control signals alternately supplied to the wirings S + and S-, and have the positive and negative polarities. Is applied as the drive voltage VPE shown in FIG. In the pixel shown in FIG. 5, once the positive and negative video signal voltages are written to the holding capacitors Cs1 and Cs2 once in one vertical scanning period (one frame), the video signal voltage of the next frame is obtained. The video signal voltage can be read from the holding capacitors Cs1 and Cs2 any number of times during one frame period until it is held, and the liquid crystal display element LC can be AC driven by alternately switching the PMOS transistors Tr5 and Tr6. Therefore, the pixel shown in FIG. 5 can AC drive the liquid crystal display element LC at a high driving frequency without any restriction on the vertical scanning frequency independently of the video signal writing cycle.

  This AC drive frequency can be freely set in the inversion control cycle in the pixel circuit, regardless of the vertical scanning frequency. For example, it is assumed that the vertical scanning frequency is 60 Hz used for a general television image signal, and the configuration is composed of 1125 lines of full periodic high-definition vertical scanning lines. If the polarity of the pixel circuit is switched at a cycle of about 15 line periods, the AC drive frequency of the liquid crystal display element is 2.25 kHz (= 60 (Hz) × 1125 ÷ (15 × 2)), which is a conventional liquid crystal display. Compared with the apparatus, the liquid crystal driving frequency can be dramatically increased. As a result, image sticking can be prevented, and deterioration in display quality such as reliability, stability, and spots can be greatly improved as compared with the case where the AC drive frequency of the liquid crystal display element is low.

  Note that the constant current load PMOS transistor Tr7 of the source follower buffer is not always active in consideration of the current consumption in the liquid crystal display device, and is limited in the conduction period of the switching PMOS transistors Tr5 and Tr6. Only controlled to be active. For example, even if the steady source follower circuit current per pixel circuit is a minute current of 1 μA, a large amount of current is consumed under the condition that all pixels of the liquid crystal display device constantly consume current. For example, in a liquid crystal display device with 2 million pixels of full high vision, the current consumption is estimated to reach 2A.

  Therefore, in the pixel shown in FIG. 5, the low level period of the load characteristic control signal that becomes the gate bias of the constant current load PMOS transistor Tr7 is limited only to the transition period of the pixel voltage polarity switching, and the pixel electrode voltage VPE reaches the target level. Immediately after being discharged, the current of the source follower buffer is stopped immediately by setting it to a high level. Therefore, it is possible to suppress a substantial current consumption even though the configuration includes a buffer for all pixels. In FIG. 6A, the source follower buffer is turned on and current is supplied during the period when the load characteristic control signal is inputted via the wiring B as the gate bias of the constant current load PMOS transistor Tr7. Since it is consumed, the power supply potential VDD whose potential is changed will be described later.

JP 2009-223289 A

  As described above, in the conventional liquid crystal display device, the low level period of the load characteristic control signal of the wiring B which is the gate bias of the PMOS transistor Tr7 for constant current load is set as the transition period (wirings S + and S +) of the pixel voltage polarity switching. -Within the low level period of each gate control signal, and immediately after the pixel electrode voltage VPE is charged / discharged to the target level, the load characteristic control signal is immediately set to high level to stop the source follower buffer current. I am letting. However, in the case of full high-definition, it is necessary to pass a current corresponding to 1980 pixels in one line through the source follower buffer during the low level period of the load characteristic control signal. Therefore, in the above conventional liquid crystal display device, about 2 mA per line. Consume.

  On the other hand, a load characteristic control signal (gate bias) is supplied to the gate of the constant current load PMOS transistor Tr7 through a wiring B from a current mirror circuit (not shown). Here, since the current mirror circuit has a function of copying a current, for example, when a current of 1 μA is to be copied, the current is 1 μA between the source and drain of the current copy source transistor in the current mirror circuit. Only flows. The transistor of the current copy source has a gate and a drain connected, and the capacitance of the wiring B with a constant current of 1 μA until the load characteristic control signal serving as a gate bias reaches a predetermined voltage (a voltage for copying 1 μA). Since it must be charged, it takes time for the potential of the wiring B to reach a predetermined voltage, and it is necessary to lengthen the low level period of the load characteristic control signal.

  For example, the capacity of the wiring B in full high vision includes a parasitic capacity between the wirings and a gate MOS capacity of 1980 pixels in the horizontal direction, and is about 3 pF in total. The gate bias for passing 1 μA of the PMOS transistor is about 4.3 V, and charging this with 1 μA requires 3.6 μsec. Therefore, considering the time until the wiring B settles at a normal potential, the low level period of the load characteristic control signal needs to be set to about 100 lines. For this reason, a current of about 200 mA (= 2 mA × 100) flows from the power supply VDD to the GND during the low level period of the load characteristic control signal. Therefore, assuming that the wiring resistance of the power supply is 5Ω, a voltage drop of 1V occurs during the low level period of the load characteristic control signal.

  In the conventional liquid crystal display device, the data lines Di + and Di- formed on the first metal have a parasitic capacitance via the N well (substrate) of the PMOS transistor, the field oxide film and the first interlayer film, and the parasitic capacitance is obtained. Due to the crosstalk due to the capacitance, the potentials of the data lines Di + and Di− in the column direction are fluctuated due to the above-described voltage drop of 1 V during the low level period of the load characteristic control signal (for example, 0.1 V). Therefore, the signal voltage written in the holding capacitors Cs1 and Cs2 when the source follower buffer is operating, and the signal voltage written in the holding capacitors Cs1 and Cs2 when the source follower buffer is not operating The signal potential will be different. In this case, when a solid picture is displayed, as shown in FIG. 6A, the power supply potential VDD periodically fluctuates, and the line that is scanned when the VDD drops and the VDD drops. When this is not the case, a horizontal band is generated between the line being scanned and flicker and burn-in occur.

  The present invention has been made in view of the above points, and paying attention to the fact that the well has the largest parasitic capacitance of the data lines Di + and Di− related to the characteristic deterioration, so that the well voltage does not fluctuate. Thus, an object of the present invention is to provide a liquid crystal display device that can prevent occurrence of a horizontal band, flicker, and burn-in on a display screen.

In order to achieve the above object, the liquid crystal display device of the present invention has a plurality of data lines provided at intersections where a plurality of sets of data lines and a plurality of row scanning lines intersect each other. Each of the pixels
A display element in which a liquid crystal layer is sandwiched between an opposing pixel electrode and a common electrode, and a positive video signal supplied via one data line of a set of two data lines are sampled and fixed. The first sampling and holding means for holding in the first holding capacitor for the period and the negative polarity having the opposite polarity to the positive video signal supplied through the other data line of the set of two data lines Second sampling and holding means for sampling the video signal and holding it in the second holding capacitor for a certain period of time, first and second source follower transistors, and a first holding input through the first source follower transistors The positive video signal voltage held in the capacitor and the negative video signal voltage held in the second holding capacitor inputted through the second source follower transistor are shorter than the vertical scanning period. A drain is connected to a common connection point between the pixel electrode and the first and second switching transistors, and the first and second switching transistors that are alternately applied to the pixel electrode by switching at a constant cycle. A constant current load transistor that operates as a constant current load of the first and second source follower transistors when a first power supply voltage is applied to a current supply terminal;
A first power supply for applying a first power supply voltage to the first current supply terminal, have a second power source for applying a second power supply voltage to each well of the transistor in the pixel, the same one line In the constant current load transistors in each of the plurality of pixels, the gate length of the current reference source transistor and the current output side transistor are equal to each other, and the ratio of the gate width of the current reference source transistor to the current output side transistor Each of the current output side transistors of the current mirror circuit having a function of flowing the current flowing through the current reference source transistor to the current output side transistor, and the current mirror circuit is connected to the current reference source transistor. The first power supply voltage is applied to the second current supply terminal from the first power supply, and the source of the transistor supplies the third current through the resistor. The gate of the current reference transistor is connected to the connection point between the source and resistance of the transistor in the source follower circuit connected to the child, and the drain of the current reference transistor is the gate of the transistor in the source follower circuit. The first power supply voltage is applied from the first power supply to the first to third current supply terminals .

  In order to achieve the above object, in the liquid crystal display device of the present invention, the constant current load transistor and the first and second source follower transistors are configured by P-channel MOS transistors. The first power supply voltage applied to the first current supply terminal from the power supply, and the N-wells of the constant current load transistor and the first and second source follower transistors from the second power supply different from the first power supply The second power supply voltage applied to the terminal has the same voltage value.

  According to the present invention, since the well voltage of the transistor in the pixel can be fixed, it is possible to eliminate the influence of the voltage drop on the potential of the data line in the column direction in which crosstalk due to the parasitic capacitance between the transistor well and the wiring is noticeable. It is possible to prevent the occurrence of horizontal bands on the display screen, flicker, and burn-in.

It is an equivalent circuit diagram of one pixel of one embodiment of the liquid crystal display device of the present invention. It is sectional drawing of one pixel of one Embodiment of the liquid crystal display device of this invention. FIG. 3 is a circuit diagram of an example of one pixel and a current generation circuit in an embodiment of the liquid crystal display device of the present invention. FIG. 11 is a circuit diagram of another example of one pixel and a current generating circuit in one embodiment of the liquid crystal display device of the present invention. It is an equivalent circuit diagram of an example of one pixel of the liquid crystal display device which the present applicant disclosed previously. 6 is a timing chart for explaining the operation of FIG. 5. It is a figure which shows the relationship between the positive polarity video signal supplied to the liquid crystal display device of this invention, and a negative polarity video signal.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows an equivalent circuit diagram of one pixel of an embodiment of a liquid crystal display device according to the present invention. In the figure, the same components as those in FIG. As in the liquid crystal display device described in Patent Document 1, the liquid crystal display device of this embodiment includes a plurality of sets of data lines including a set of two data lines (column signal lines) and a plurality of gate lines ( The pixels are arranged in a matrix at each intersection with the row scanning line), and the positive video signal and the negative video signal are separately sampled and held in the two holding capacitors at each pixel, and then held. This is a liquid crystal display device in which a voltage is alternately applied to the pixel electrode to drive the liquid crystal display element in an alternating current, but the configuration of the pixel is different from that of the liquid crystal display device described in Patent Document 1, and is represented by the equivalent circuit shown in FIG. It is supposed to be configured.

  That is, the pixel 10 shown in FIG. 1 is a pixel in the j-th row and i-th column, and a set of two data lines (column signal lines) Di + and Di- in the i-th column and a gate line (row scanning line) in the j-th row. ) A constant current load PMOS transistor Tr10, which is provided at the intersection with Gj and forms a source follower buffer together with the source follower PMOS transistors Tr3 and Tr4 shown in FIG. A power supply voltage VD2 applied to the terminal X and a power supply voltage VDD applied to the N well terminal which is each back gate of the PMOS transistor Tr10 and other PMOS transistors in the pixel 10 are applied from different power sources, and This is characterized by the same voltage (for example, 5.5 V).

  In FIG. 1, pixel selection NMOS transistors Tr1 and Tr2 have drain terminals connected to a positive data line Di + and a negative data line Di-, respectively, and gate terminals connected to a row scanning line (gate line) for the same row. ) Connected to Gj. The source terminals of the NMOS transistors Tr1 and Tr2 are respectively connected to the connection points between the one ends of the positive polarity holding capacitor Cs1 and the negative polarity holding capacitor Cs2 and the gate terminals of the source follower PMOS transistors Tr3 and Tr4. ing. The source terminals of the PMOS transistors Tr3 and Tr4 are connected to the drain terminals of the switching PMOS transistors Tr5 and Tr6.

  The source terminals of the switching PMOS transistors Tr5 and Tr6 are connected in common to the pixel electrode PE of the liquid crystal display element LC and the drain terminal of the constant current load PMOS transistor Tr10. In the PMOS transistor Tr10, the voltage VD2 is applied to the source terminal via the current supply terminal X, and the back gate has the same voltage value (for example, 5.5 V) as the voltage VD2, but the voltage VDD from another power source is applied. Is applied. This voltage VDD is also applied in common to the back gates of the other PMOS transistors Tr3, Tr4, Tr5, Tr6. The positive polarity gate control signal wiring S + is connected to the gate terminal of the switching PMOS transistor Tr5, and the negative polarity gate control signal wiring S- is connected to the gate terminal of the switching PMOS transistor Tr6.

  The basic operation itself of the pixel 10 of the present embodiment is the same as the operation of the pixel of the conventional liquid crystal display device described together with the timing charts shown in FIGS. That is, when the row selection signal of one vertical scanning period supplied to the pixel 10 via the row scanning line Gj becomes high level for a predetermined period, the NMOS transistors Tr1 and Tr2 are simultaneously turned on for the predetermined period, respectively. A positive video signal input via the data line Di + is sampled by the NMOS transistor Tr1 and held in the holding capacitor Cs1. In parallel with this, a negative polarity video signal having the same video information as the positive polarity video signal but having a reverse polarity is input via the negative polarity data line Di-, and is sampled by the NMOS transistor Tr2 to be stored. Held at Cs2.

  FIG. 7 shows the black level of the positive video signal a input through the positive data line Di + and written to the pixel and the black level of the negative video signal b input through the negative data line Di− and written to the pixel. To the white level. The positive-polarity video signal a is the black level of the minimum gradation when the level is minimum, and the white level of the maximum gradation when the level is maximum, whereas the negative-polarity video signal b is the maximum level when the level is minimum. The white level of the tone, the black level of the minimum gradation when the level is the maximum. The positive polarity video signal a and the negative polarity video signal b have opposite polarities, and their inversion centers are indicated by c.

  The positive and negative video signal voltages sampled and held in the holding capacitors Cs1 and Cs2, respectively, are read out through the high-input-resistance source follower PMOS transistors Tr3 and Tr4, and alternately supplied to the wirings S + and S-. Are alternately selected at a predetermined cycle shorter than the vertical scanning cycle by the switching PMOS transistors Tr5 and Tr6 which are turned on by the gate control signal supplied to the pixel electrode PE and applied to the pixel electrode PE as a drive voltage.

  Next, a cross section of the structure of the pixel 10 of the present embodiment will be described. FIG. 2 is a sectional view of one pixel of an embodiment of the liquid crystal display device according to the present invention. In the figure, the same components as those in FIG.

  In FIG. 2, a constant current load PMOS transistor 102 and a switching PMOS transistor 103 are formed on an N well 101 formed on a silicon substrate 100, and the field oxide film 104 is divided between them. The constant current load PMOS transistor 102 corresponds to the PMOS transistor Tr10 in FIG. 1, and the PMOS transistor 103 corresponds to the PMOS transistor Tr5 (or Tr6) in FIG.

  The source region of the constant current load PMOS transistor 102 is connected to the source of a copy destination transistor of a current mirror circuit (not shown) using the first metal electrode 105 formed through the first interlayer film 107 as a current supply terminal X, and the voltage VD2 Is supplied. The N well electrode 106 formed in the N well 101 is electrically connected to an N well terminal 109 formed through the first interlayer film 107 and the second interlayer film 108 and supplied with the power supply voltage VDD. Has been.

  The first metal formed on the first interlayer film 107 is covered with the second interlayer film 108, the second metal 110 formed on the second interlayer film 108 is covered with the third interlayer film 111, and the third The third metal 112 formed on the interlayer film 111 is covered with the fourth interlayer film 113, and the pixel electrode PE is formed on the fourth interlayer film 113 as the fourth metal. The third metal 112 is formed as a light shielding film.

  The drain region of the constant current load PMOS transistor 102 and the source region of the switching PMOS transistor 103 are formed through the first interlayer film 107, the second interlayer film 108, the third interlayer film 111, and the fourth interlayer film 113. The electrode 114 is electrically connected to the pixel electrode PE. A liquid crystal layer LCM and a common electrode CE are respectively stacked on the pixel electrode (fourth metal) PE. The common electrode CE is a transparent electrode that is formed to be opposed to the pixel electrode (fourth metal) PE. Light from a backlight (not shown) is transmitted through the common electrode CE and the liquid crystal layer LCM, is incident on the pixel electrode (fourth metal) PE, and is reflected.

  Thus, as shown in the equivalent circuit diagram of FIG. 1 and the cross-sectional view of FIG. 2, the pixel 10 includes the power source of the voltage VD2 supplied to the current supply terminal X of the constant current load PMOS transistor Tr10, the PMOS transistor Tr3, The power supply of the power supply voltage VDD supplied to the N well terminal 109 which is the back gate of Tr4, Tr5, Tr6 and Tr10 is a separate power supply. However, both voltages VD2 and VDD are 5.5V. That is, in the pixel 10 of the present embodiment, the PMOS transistor Tr10 has the same power supply voltage VDD supplied to the N well terminal 109 of the back gate and the voltage VD2 supplied to the source terminal thereof through the current supply terminal X. Although it is a voltage, by using a separate power source, the N-well voltage can be prevented from being affected by the potential fluctuation of the current supply terminal X.

  As a result, in the pixel 10, when a current flows through the source follower buffer, the terminal where the voltage drop is observed is only the current supply terminal X, and the influence of the voltage drop on the N well terminal 109 of the PMOS transistors Tr3, Tr4, Tr5, and Tr6. Since the N-well voltage can be fixed without affecting the voltage, the influence of the above-described voltage drop on the potentials of the data lines Di + and Di- in the column direction in which crosstalk due to parasitic capacitance between the N-well and the wiring of the PMOS transistor appears remarkably. This can eliminate the occurrence of horizontal bands on the display screen, flicker, and burn-in.

  Next, a circuit of each example of one pixel and a current generation circuit in one embodiment of the liquid crystal display device according to the present invention will be described.

  FIG. 3 is a circuit diagram showing an example of one pixel and a current generating circuit in one embodiment of the liquid crystal display device according to the present invention. In the figure, the same components as those in FIG. In FIG. 3, PIX in the pixel 10 is a pixel electrode wiring PIX of the liquid crystal display element LC. Further, the gate and drain of the PMOS transistor Tr11, the drain of the PMOS transistor Tr12, and the source of the NMOS transistor Tr13 are equal to the number of pixels in one horizontal line via the wiring B of the load characteristic control signal (full HD video). In this case, it is commonly connected to the pixel 10 of 1980 pixels). The gates of the PMOS transistors Tr12 and Tr13 are connected to the input terminal of the control signal CC1. A terminal Y connected to the source of the PMOS transistor Tr11 is a current supply terminal of the current mirror circuit, which, together with the current supply terminal X connected to the source of the constant current load transistor Tr10, is a back gate (N well) of the PMOS transistor. The power supply voltage VD2 (here, 5.5V) is supplied from a power supply different from the power supply of the power supply voltage VDD (here, 5.5V). The constant current load transistor Tr10 constitutes a current output side transistor of a current mirror circuit as will be described later.

  The NMOS transistor Tr14 has a drain connected to the drain of the PMOS transistor Tr13, and a gate connected to each gate and each drain of the PMOS transistor Tr15 and NMOS transistor Tr16 in the current generation circuit 20. The current generation circuit 20 includes the PMOS transistor Tr15 and the NMOS transistor Tr16, and a resistor R1 connected to the source of the PMOS transistor Tr15. The gates and drains of the PMOS transistor Tr15 and the NMOS transistor Tr16 are commonly connected to the gate of each NMOS transistor Tr14 connected to the pixel 10 for each line by the number of pixels in the vertical direction (1080 pixels in the case of full high vision). Has been.

  The NMOS transistors Tr14 and Tr16 constitute a current mirror circuit, and the current created by the current creation circuit 20 that is the current supply source is copied to the NMOS transistor Tr14. When the current reference source Tr16 and the current copy side Tr14 have the same gate length and gate width, the same current value is copied. When the gate lengths of the current reference source Tr16 and the current copy side Tr14 are the same, and the gate widths of the Tr16 and Tr14 are changed, the current is copied to the Tr14 in the ratio of the gate width.

  When the control signal CC1 is at a high level, the PMOS transistor Tr12 is turned off and the NMOS transistor Tr13 is turned on. As a result, all the current mirror circuits are turned on, the current flowing between the source and drain of the NMOS transistor Tr14 is supplied from the voltage VD2 applied to the current supply terminal Y, and the current flowing in the PMOS transistor Tr14 is PMOS It is equal to the current flowing through the transistor Tr11.

  The PMOS transistor Tr11 and the constant current load PMOS transistor Tr10 also constitute a current mirror circuit in which Tr11 is a current reference source transistor and Tr10 is a current output side transistor. The current flowing through the PMOS transistor Tr11 of the current mirror circuit is Copied to the constant current load PMOS transistor Tr10 of each pixel 10 on the same line. Again, if the current reference source Tr11 and the current copy side Tr10 have the same gate length and gate width, the same current value is copied. When the gate lengths of the current reference source Tr11 and the current copy side Tr10 are the same and the gate widths of the Tr11 and Tr10 are changed, the current is copied to the Tr10 in the ratio of the gate width.

  On the other hand, when the control signal CC1 is at a low level, the NMOS transistor Tr13 is turned off and the current mirror circuit is disconnected. At the same time, since the NMOS transistor Tr12 is turned on, the potential of the wiring B is raised to VDD (= VD2 = 5.5V). As a result, the PMOS transistor Tr11 is turned off, and the plurality of pixels 10 in the same one line are turned on. Each constant current load PMOS transistor Tr10 is turned off.

  As described above, since VD2 is applied to the current supply terminals X and Y from a power source different from the power source that applies VDD to the N well terminal that is the back gate of the PMOS transistors Tr3 to Tr6, Tr11, Tr12, and Tr15, When the current is supplied to the source follower buffer in the pixel 10 by turning off the transistor Tr10, only the current supply terminal X has a voltage drop, and as described above, the potential with respect to the potentials of the data lines Di + and Di- The influence of the voltage drop can be eliminated.

  In this embodiment, when all the current mirror circuits are in the on state, the current created by the current creating circuit 20 is copied to the NMOS transistor Tr14, and the current having the same value as the current flowing through the NMOS transistor Tr14 is The current flowing through the transistor Tr11 and the current flowing through the PMOS transistor Tr11 is used as a reference source current of the current mirror circuit, and the current flowing through the PMOS transistors Tr10 in the plurality of pixels 10 in one line, which is the output current of the same current mirror circuit, respectively. It can be the same value as the current of the reference source.

  Note that the power supply potentials VDD and VD2 are the same 5.5 V, but the power supply is supplied as a separate power supply from the outside of the panel. In the system, the board that drives the panel may take two systems from the same power supply. However, as in this embodiment, the panel has two power supplies so that the above horizontal band, flicker, burn-in, etc. Improved.

  FIG. 4 is a circuit diagram showing another example of one pixel and a current generating circuit in one embodiment of the liquid crystal display device according to the present invention. In the figure, the same components as those in FIGS. 1 and 3 are denoted by the same reference numerals, and the description thereof is omitted. In the embodiment shown in FIG. 4, the voltage generated by the current mirror circuit is supplied to the gate of each constant current load PMOS transistor Tr10 in the plurality of pixels 10 of the same one line via the wiring B, and the PMOS The transistor Tr10 is characterized in that the rise of the gate bias is speeded up using a source follower circuit.

  In FIG. 4, the PMOS transistor Tr17 and the resistor R2 connected between the source and the current supply terminal Z constitute a source follower circuit. A power supply voltage VD2 is applied to the current supply terminal Z. A connection point between the source of the PMOS transistor Tr17 and the resistor R2 is connected to the wiring B and the gate of the PMOS transistor Tr11. The gate and drain of the PMOS transistor Tr11 are not connected unlike FIG. 3, and the drain of the PMOS transistor Tr11 is connected to the gate of the PMOS transistor Tr17, the drain of the PMOS transistor Tr13, and the source of the NMOS transistor Tr12. .

  In the circuit of FIG. 4 having such a configuration, when the control signal CC1 is at a high level, the NMOS transistor Tr13 is turned on and the PMOS transistor Tr12 is turned off, and the current mirror circuit having the source follower configuration operates. When the control signal CC1 is at a low level, the NMOS transistor Tr13 is turned off and the PMOS transistor Tr12 is turned on. Therefore, the wiring B is charged to the power supply potential VD2 by the resistor R2, and the PMOS transistor Tr17 is turned off. Each PMOS transistor Tr10 in the pixel 10 is turned off.

  In the embodiment shown in FIG. 4, the power supply voltage VD2 is applied to the current supply terminal X of the constant current load PMOS transistor Tr10, the current supply terminal Y of the PMOS transistor Tr11 of the current mirror circuit, and the current supply terminal Z of the source follower circuit. It is set as the structure to apply. This power supply voltage VD2 has the same voltage value (for example, 5.5 V) as VDD supplied from a power supply different from the power supply of the applied voltage VDD of the N well that is the back gate of the PMOS transistor. As a result, when a current is passed through the source follower circuit, VD2 is the only terminal at which a voltage drop is seen, and does not affect the back gate (N well terminal) of the PMOS transistor. The influence of the above voltage drop on the potentials of the data lines Di + and Di− in the column direction where crosstalk due to the parasitic capacitance is noticeable can be eliminated, and the occurrence of horizontal bands, flicker and burn-in on the display screen can be eliminated. Can be prevented.

  Further, according to the present embodiment, even when a voltage drop due to the current flowing through the source follower circuit occurs, the PMOS transistors Tr11 and Tr10, the resistor R2, and the PMOS transistor Tr17 constituting the current mirror circuit are connected to the power supply of the power supply voltage VD2. Therefore, a current having the same value as the current created by the current creating circuit 20 flows through the PMOS transistor Tr11, and the current flowing through the PMOS transistor Tr11 is used as a reference source current of the current mirror circuit. The currents that flow through the PMOS transistors Tr10 in the plurality of pixels 10 in one line can be set to the same value as the current of the reference source.

  Further, according to the present embodiment, the potential of the wiring B drops together according to the voltage drop caused by the current flowing through the source follower circuit. Therefore, the source-gate voltages of the PMOS transistor Tr11 and the constant-current load PMOS transistor Tr10 constituting the current mirror circuit are always the same, and even when the power supply potential VD2 drops, the same current as the reference current is generated in each pixel 10. Supplied.

  In FIG. 4, in the current mirror circuit using the source follower circuit, the gate of the PMOS transistor Tr11 that is the current reference source is not connected to the drain and the wiring B, and the source / drain of the PMOS transistor Tr11 that is the current reference source The wiring B cannot be charged with a current flowing between them (for example, 1 μA). Instead, in this embodiment, from the time when the control signal CC1 is set to the high level until the wiring B reaches a predetermined voltage (gate voltage for copying 1 μA), the power supply of the power supply voltage VD2 applied to the current supply terminal Z is used. Since the current is supplied and charged, the wiring B can be charged at high speed (speeding up the rise of the gate bias of the PMOS transistor Tr10).

  For example, the capacity of the wiring B in the case of full high vision is about 3 pF in total consisting of a parasitic capacity between the wirings and a gate MOS capacity for 1980 pixels in one line. At this time, if the resistance value of the resistor R2 of the source follower circuit including the PMOS transistor Tr17 and the resistor R2 is 4 kΩ, for example, about 0.012 μsec is required to reach the predetermined voltage when the wiring B is charged with 1 μA. This value is about 300 times faster than that of the conventional liquid crystal display device described above.

  In this embodiment, as in the embodiment of FIG. 3, the power supply potentials VDD and VD2 are the same 5.5 V, but the power supply is supplied as a separate power supply from the outside of the panel. In the system, the board that drives the panel may take two systems from the same power supply. However, as in this embodiment, the panel has two power supplies so that the above horizontal band, flicker, burn-in, etc. Improved.

10 pixel 20 current generation circuit 101 N well 102, Tr10 constant current load PMOS transistor 103, Tr5, Tr6 switching PMOS transistor 105, Y current supply terminal of current mirror circuit 109 N well terminal Tr1, Tr2 pixel selection NMOS transistor Tr3 , Tr4 PMOS transistor for source follower Tr10
Tr11, Tr12, Tr15, Tr17 PMOS transistors Tr13, Tr14, Tr16 NMOS transistors R1, R2 Resistance PIX Pixel electrode wiring LC Liquid crystal display element LCM Liquid crystal layer PE Pixel electrode CE Common electrode Di +, Di- Data line (column signal line)
Gj gate line (row scanning line)
S +, S- Gate control signal wiring B Load characteristic control signal wiring Cs1, Cs2 Retention capacitance VDD, VD2 Power supply voltage X Current supply terminal of PMOS transistor Tr10 for constant current load Z Current supply terminal of source follower circuit

Claims (2)

Each of a plurality of pixels provided at intersections where a plurality of sets of data lines and a plurality of row scanning lines intersect each other with two data lines as one set,
A display element in which a liquid crystal layer is sandwiched between a pixel electrode and a common electrode facing each other;
First sampling and holding means for sampling a positive video signal supplied via one of the two data lines in a set and holding it in a first holding capacitor for a certain period;
The negative polarity video signal having the opposite polarity to the positive polarity video signal supplied through the other data line of the set of the two data lines is sampled and held in the second holding capacitor for a certain period. Second sampling and holding means;
First and second source follower transistors;
A positive video signal voltage held in the first holding capacitor input through the first source follower transistor and a negative electrode held in the second holding capacitor input through the second source follower transistor. A first and a second switching transistor that alternately switch a sex video signal voltage at a predetermined cycle shorter than a vertical scanning cycle and alternately apply to the pixel electrode;
A drain is connected to a common connection point between the pixel electrode and the first and second switching transistors, a first power supply voltage is applied to a first current supply terminal, and the first and second A constant current load transistor that operates as a constant current load of the source follower transistor;
A first power supply for applying the first power supply voltage to the first current supply terminal, and a second power supply for applying a second power supply voltage to each well terminal of the transistor in the pixel. Yes, and
The constant current load transistors in each of the plurality of pixels on the same line have the same gate length of the current reference source transistor and the current output side transistor, and the current reference source transistor and the current output side transistor Each of the current output side transistors of the current mirror circuit having a function of flowing a current flowing through the current reference source transistor to the current output side transistor in accordance with a ratio of a gate width of the transistor of In the mirror circuit, the first power supply voltage from the first power supply is applied to a second current supply terminal connected to the current reference transistor,
A gate of the current reference transistor is connected to a connection point between the source of the transistor and the resistor in a source follower circuit in which a source of the transistor is connected to a third current supply terminal via a resistor; and The drain of the current source transistor is connected to the gate of the transistor in the source follower circuit, and the first power supply voltage is supplied from the first power source to the first to third current supply terminals. A liquid crystal display device which is applied . Each of a plurality of pixels provided at intersections where a plurality of sets of data lines and a plurality of row scanning lines intersect each other with two data lines as one set,
A display element in which a liquid crystal layer is sandwiched between a pixel electrode and a common electrode facing each other;
First sampling and holding means for sampling a positive video signal supplied via one of the two data lines in a set and holding it in a first holding capacitor for a certain period;
The negative polarity video signal having the opposite polarity to the positive polarity video signal supplied through the other data line of the set of the two data lines is sampled and held in the second holding capacitor for a certain period. Second sampling and holding means;
First and second source follower transistors each formed of a P-channel MOS transistor;
A positive video signal voltage held in the first holding capacitor input through the first source follower transistor and a negative electrode held in the second holding capacitor input through the second source follower transistor. A first and a second switching transistor that alternately switch a sex video signal voltage at a predetermined cycle shorter than a vertical scanning cycle and alternately apply to the pixel electrode;
A drain is connected to a common connection point between the pixel electrode and the first and second switching transistors, a first power supply voltage is applied to a first current supply terminal, and the first and second A constant current load transistor each configured as a P-channel MOS transistor that operates as a constant current load of a source follower transistor;
A first power supply for applying the first power supply voltage to the first current supply terminal, and a second power supply for applying a second power supply voltage to each well terminal of the transistor in the pixel. Have
The first power supply voltage applied to the first current supply terminal from the first power supply, the constant current load transistor, the first and second transistors from the second power supply different from the first power supply. The second power supply voltage applied to each N well terminal of the two source follower transistors has the same voltage value.
The constant current load transistors in each of the plurality of pixels on the same line have the same gate length of the current reference source transistor and the current output side transistor, and the current reference source transistor and the current output side transistor Each of the current output side transistors of the current mirror circuit having a function of flowing a current flowing through the current reference source transistor to the current output side transistor in accordance with a ratio of a gate width of the transistor of In the mirror circuit, the first power supply voltage from the first power supply is applied to a second current supply terminal connected to the current reference transistor,
A gate of the current reference transistor is connected to a connection point between the source of the transistor and the resistor in a source follower circuit in which a source of the transistor is connected to a third current supply terminal via a resistor; and The drain of the current source transistor is connected to the gate of the transistor in the source follower circuit, and the first power supply voltage is supplied from the first power source to the first to third current supply terminals. A liquid crystal display device which is applied .

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