JP5483400B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device.

A nonvolatile semiconductor memory device stores data by accumulating electric charges in a charge accumulation film. EEPROM (Electronically Erasable and Programmable Read Only Memory) is roughly divided into two structures with different types of charge storage films.
One is an FG (Floating Gate) in which a conductor called a floating gate serving as a charge storage film is surrounded by an oxide film and electrically insulated on a gate insulating film, and charges are stored in the floating gate. Floating gate) type.

  The other is a MNOS (Metal-Nitride-Oxide) that has a charge storage film in which a plurality of insulating films are stacked and stores information by controlling the amount of charge stored in a charge trap in the charge storage film. -Silicon) type and MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type.

  The threshold voltage in the state where electrons are stored in the charge storage film, that is, in the state where write data is stored, is Vtw, and the threshold voltage in the state where holes are stored in the charge storage film, that is, where erase data is stored The voltage is Vte, and the threshold voltage in a state where neither electrons nor holes are accumulated in the charge storage film, that is, the thermal equilibrium state threshold voltage is called V0.

  Here, when the value of the voltage Vcg applied to the gate electrode of the memory element when reading the data stored in the memory element is set so that the relationship of Vte <Vcg <Vtw is established, the drain current of the memory element is Since it does not flow in a state where data is stored but flows in a state where erase data is stored, it is possible to discriminate between write data and erase data.

There is a non-volatile semiconductor memory device that is different from the non-volatile semiconductor memory device that stores data by accumulating the above charges in a charge storage film, and a typical example is a mask ROM. The mask ROM is a ROM in which stored data is written during the LSI manufacturing process. There are roughly two types of mask ROMs with different writing methods.
One is to adjust the impurity concentration in the channel region of the MOS transistor to produce two threshold voltages, similar to the above-mentioned EEPROM, and discriminate the stored data based on the presence or absence of the drain current.
The other is based on the presence or absence of the drain contact hole of the MOS transistor, which also determines the stored data based on the presence or absence of the drain current.

In EEPROM and mask ROM, one or two MOS transistors are required for one bit of stored data, and the ROM cell area increases in proportion to the increase in ROM capacity. There is a problem that it is against the demand for high integration and chip size reduction.
In order to cope with such a problem, as a method of dealing with an increase in the cell area of the ROM, several proposals are being seen (for example, see Patent Document 1).

FIG. 5 is an explanatory diagram of a cross-sectional structure of one cell portion in the semiconductor memory device described in the prior art disclosed in Patent Document 1, and FIG. 6 is an equivalent circuit diagram of the one cell portion shown in FIG. 7 is an equivalent circuit diagram for explaining the circuit configuration.

In FIG. 5, 100 is a memory cell, 101 is a semiconductor substrate, 102 is a drain region, 103 is a source region, 104 is an impurity region, 105 is a charge storage film, 106 is a gate, and 107 is a sidewall.
The semiconductor substrate 101 and the impurity region 104 are P-type, and the drain region 102 and the source region 103 are N-type.

In FIG. 6, S is a source terminal, D is a drain terminal, G is a gate terminal, DD is a diode, and MT is a memory transistor.
The source region 103 and the impurity region 104 form a diode DD, and the charge storage film 105 and the gate 106 form a memory transistor MT.

  In FIG. 7, S1 is a source line, D1 and D2 are drain lines, G1 and G2 are gate lines, DD1 to DD4 are diodes, and MT1 to MT4 are memory transistors.

The conventional erasing and writing operations described in Patent Document 1 will be described with reference to FIG.
Data is erased by applying 0 V to the drain region 102, the source region 103 and the gate 106, 10 V to the semiconductor substrate 101, and extracting the charge accumulated in the charge storage film 105, so that all the cells in the ROM are batched. To do.

  Data is written by applying 0 V to the semiconductor substrate 101, the drain region 102 and the source region 103, and 12 V to the gate 106 and storing charges in the charge storage film 105 to the memory cell to be written.

Next, the write blocking operation of the prior art disclosed in Patent Document 1 will be described with reference to FIGS.
In FIG. 7, when writing is performed to the memory transistor MT1, but not writing is performed to the memory transistors MT2 to MT4, 12V is applied to the gate line G1, 0V is applied to the source line S1, the drain line D1, and the gate line G2, and 7V is applied to the drain line D2. Apply. Although not shown, 0 V is applied to the semiconductor substrate.

By applying the voltage in this way, 0 V, which is the same potential as the semiconductor substrate, is applied to the gate terminals of the memory transistors MT3 and MT4, thereby preventing writing.
Since the memory transistor MT1 and the gate line G1 are common to the memory transistor MT2, 12V is applied to the gate terminal. However, by applying 7V to the drain terminal of the memory transistor MT2, a reverse voltage is applied to the diode DD2 to stop the current flow, so that the channel region on the surface of the semiconductor substrate under the charge storage film is charged up. Since the potential difference between the channel region and the gate terminal is small, writing is not performed.

Next, the reading operation of the prior art disclosed in Patent Document 1 will be described with reference to FIGS.
The stored data is read by applying 5 V to the source region 103 and the gate 106. When 5 V is applied to the source region 103, a forward voltage is applied to the diode DD, and current easily flows. At this time, if writing is performed in the memory cell, the memory transistor MT is turned off, and if erasing is performed, the memory transistor MT is turned on, so that stored data can be discriminated.

  In the prior art disclosed in Patent Document 1, the diode DD whose current flows from the drain region 102 to the source region 103 in the reverse direction is provided on the source side of the memory transistor MT. Therefore, there is no need to provide a selection transistor on the source side, and the cell area of the ROM is reduced.

JP-A-5-326892 (page 6, FIG. 1-2)

  Although the prior art disclosed in Patent Document 1 is certainly a technique that reduces the cell area of the ROM, the data that can be stored in one memory cell is 1 bit as in the prior art, and there is a need for higher integration. There is a problem that can not be answered.

  The present invention has been made to solve such a problem, and an object thereof is to increase the data that can be stored in one memory cell more than one bit.

  In order to solve the above problems, the present invention adopts the following configuration.

A nonvolatile semiconductor memory device comprising a mask ROM and an EEPROM adjacent to each other on the same plane, comprising a memory gate having a charge storage film in a predetermined activation region on the semiconductor substrate, and a memory gate in the activation region A source contact hole for constituting a mask ROM and a source contact hole for constituting an EEPROM are provided in a source region adjacent to the gate ROM, and a mask ROM is constituted in a drain region facing the source region with the memory gate interposed therebetween. A selection contact hole for forming the drain and a drain contact hole for configuring the EEPROM are provided, and a source contact hole for configuring the mask ROM, a source contact hole for configuring the EEPROM, and the mask ROM are configured. Select contact hole for and EEPROM And the drain contact hole for constituting, the same Ippei
It is provided on the surface .

  With such a configuration, the memory capacity can be increased without increasing the size of the memory cell.

  The number of selected contact holes may be the same as the number of memory gates adjacent to the source contact hole.

  With such a configuration, the number of bits of data that can be stored per memory cell can be made 2 bits.

  The charge storage film may be formed by laminating a plurality of insulating films.

  Also in the prior art, by adopting such a MONOS type configuration, higher integration is possible than the FG type in which electrical interference occurs between adjacent memory cells. In the present invention, the MONOS type is used. Further, high integration can be achieved.

  In the nonvolatile semiconductor memory device of the present invention, since the EEPROM and the mask ROM can be configured as one memory cell, the memory capacity can be increased without increasing the size of the memory cell. In this way, a larger storage capacity can be obtained with a small occupied area.

1 is a plan view for explaining the structure of a first embodiment of a nonvolatile semiconductor memory device according to the present invention; It is sectional drawing for demonstrating the cross-sectional structure between the cutting lines AA 'of FIG. FIG. 5 is an equivalent circuit diagram for explaining a second embodiment of a nonvolatile semiconductor memory device according to the present invention. FIG. 6 is an equivalent circuit diagram for explaining a third embodiment of a nonvolatile semiconductor memory device according to the present invention. 10 is a cross-sectional view for explaining a cross-sectional structure of a conventional semiconductor memory device disclosed in Patent Document 1. FIG. 1 is an equivalent circuit diagram of one cell portion of a conventional semiconductor memory device disclosed in Patent Document 1. FIG. 10 is an equivalent circuit diagram for explaining a circuit configuration of a conventional semiconductor memory device disclosed in Patent Document 1. FIG.

The nonvolatile semiconductor memory device of the present invention includes an EEPROM that stores data depending on the presence or absence of charges stored in a charge storage film of a memory transistor, and a mask ROM that stores data depending on the presence or absence of a selective contact hole on the same plane. Configure above. As a result, it is possible to increase the data that can be stored per memory cell to more than 1 bit and up to 2 bits without increasing the gate spacing of the memory transistors.
The EEPROM will be described using an example in which the charge storage film is a MONOS type in which a plurality of insulating films are stacked. The MONOS type EEPROM can be more highly integrated than the FG type in which electrical interference occurs between adjacent memory cells. Also, it is convenient because it can be operated with a low write and erase voltage.
Hereinafter, embodiments will be described with reference to the drawings. In the description, elements not related to the description such as an intermediate insulating film are omitted.

[Description of Structure of First Embodiment: FIGS. 1 and 2]
FIG. 1 is a plan view for explaining the structure of the first embodiment of the nonvolatile semiconductor memory device of the present invention. FIG. 2 is a cross-sectional view illustrating a cross-sectional structure taken along the cutting line AA ′ in FIG.
In FIG. 2, the source wiring and drain wiring of the mask ROM are omitted for easy understanding of the drawing.
In the first embodiment, an example in which a nonvolatile semiconductor memory device is configured by one memory transistor is shown.

  1 and 2, reference numeral 200 denotes a nonvolatile semiconductor memory device of the present invention. Note that the nonvolatile semiconductor memory device 200 integrally includes an EEPROM and a mask ROM, but will be referred to as an EEPROM 201 and a mask ROM 202 for convenience.

SE is a source wiring of the EEPROM 201, CHSE is a contact hole on the source side of the EEPROM 201, DE is a drain wiring of the EEPROM 201, and CHDE is a contact hole on the drain side of the EEPROM 201.
SM is a source wiring of the mask ROM 202, CHSM is a contact hole on the source side of the mask ROM 202, DM is a drain wiring of the mask ROM 202, and CHDM is a selection contact hole on the drain side of the mask ROM 202.

Similarly, 1 is a p-type semiconductor substrate, 2 is an n-type drain region, 3 is an n-type source region, 5 is a charge storage film, 6 is a gate, 8 is a field oxide film, 9 is an intermediate insulating film, 10 Is the channel region.

The drain region 2 and the source region 3 are formed at a predetermined interval in the surface layer portion of the semiconductor substrate 1. On the semiconductor substrate 1, a charge storage film 5 is provided on the channel region 10, which is a region that bridges the drain region 2 and the source region 3. A gate 6 is provided on the charge storage film 5.
The field oxide film 8 is provided on the semiconductor substrate 1 where the drain region 2, the source region 3, and the channel region 10 are not provided, and has a role of an element isolation film.

Contact holes CHSE and CHSM are provided on the source region 3, and contact holes CHDE and a selection contact hole CHDM are provided on the drain region 2, respectively.
The intermediate insulating film 9 is provided above the surface layer portion of the semiconductor substrate 1 so as to cover the gate 6, the drain region 2, the source region 3, and the field oxide film 8, and includes contact holes CHSE, CHSM, CHDE, and selective contact holes CHDM. Is formed. That is, each contact hole is an opening of the intermediate insulating film 9. In other words, a region where each contact hole is not provided is covered with the intermediate insulating film 9.
When the selective contact hole CHDM is not provided, an intermediate insulating film 9 is provided in the region of the selective contact hole CHDM shown in FIGS.

The EEPROM 201 includes a channel region 10, a charge storage film 5, a gate 6, a drain region 2 and a source region 3, contact holes CHSE and CHDE, a source wiring SE, and a drain wiring DE.
The mask ROM 202 includes a channel region 10, a charge storage film 5, a gate 6, a drain region 2 and a source region 3, a contact hole CHSM, a selection contact hole CHDM, a source wiring SM, and a drain wiring DM.

[Description of Data Writing Operation of First Embodiment: FIGS. 1 and 2]
Next, the data write operation of the first embodiment will be described with reference to FIGS.

  The EEPROM 201 stores data depending on the presence / absence of charges accumulated in the charge storage film 5. A state where charges are accumulated is referred to as a written state (a state where write data is stored), and a state where charges are not accumulated is referred to as an erased state (a state where erased data is stored).

  In order to put the EEPROM 201 in the erased state, for example, 0V is applied to the semiconductor substrate 1, the source wiring SE, and the drain wiring DE, and −10V is applied to the gate 6, for example. Is pulled out to the semiconductor substrate 1.

  In order to set the EEPROM 201 in a writing state, for example, 0 V is applied to the semiconductor substrate 1, the source wiring SE, and the drain wiring DE, and 10 V is applied to the gate 6, thereby accumulating charges in the charge storage film 5.

  The mask ROM 202 stores data depending on the presence / absence of the selected contact hole CHDM. A state in which the selected contact hole CHDM is not formed is referred to as a write state (a state in which write data is stored), and a state in which the selected contact hole CHDM is formed is referred to as an erase state (a state in which erase data is stored).

In order to put the mask ROM 202 into the erased state, the selective contact hole CHDM is formed in the step of opening the intermediate insulating film 9 in the manufacturing process of the nonvolatile semiconductor memory device 200.

  In order to set the mask ROM 202 in the writing state, the selective contact hole CHDM is not formed in the step of opening the intermediate insulating film 9 in the manufacturing process of the nonvolatile semiconductor memory device 200.

[Description of Data Reading Operation of First Embodiment: FIGS. 1 and 2]
Next, the data read operation of the first embodiment will be described with reference to FIGS.

In the memory cell of the EEPROM 201 constituting the nonvolatile semiconductor memory device 200, the threshold voltage in the written state is Vw and the threshold voltage in the erased state is Ve.
The read voltages applied to the gate in the read operation of the EEPROM 201 and the mask ROM 202 that constitute the nonvolatile semiconductor memory device 200 are Vr1, Vr2, and Vr3.
Here, Vr1, Vr2, and Vr3 are set to values that satisfy the following conditions.
Vr1 <Ve <Vr2 <Vw <Vr3

  In order to read data stored in the EEPROM 201, Vr2 is applied to the gate 6, 2V is applied to the source wiring SE, and 0V is applied to the drain wiring DE, for example.

If the charge storage film 5 is in the write state, even if Vr2 lower than Vw is applied to the gate 6, the channel region 10 does not serve as a current path, so no current flows from the source line SE to the drain line DE.
On the other hand, if the charge storage film 5 is in the erased state, the channel region 10 becomes a current path by applying Vr2 higher than Ve to the gate 6, and therefore a current flows from the source line SE to the drain line DE.
Therefore, the stored data can be discriminated based on the presence or absence of current to the drain wiring DE.

In order to read the data stored in the mask ROM 202, Vr3 is applied to the gate 6, 2V is applied to the source wiring SM, and 0V is applied to the drain wiring DM, for example.
By applying Vr3 higher than Ve and Vw to the gate 6, the channel region 10 becomes a current path regardless of the presence or absence of charges accumulated in the charge storage film 5.

If the selected contact hole CHDM is not formed and there is a write state, no current flows through the selected contact hole CHDM, and therefore no current flows from the source line SM to the drain line DM.
On the other hand, if the selected contact hole CHDM is formed and in the erased state, a current flows from the source line SM to the drain line DM because there is a current path through the selected contact hole CHDM.
Therefore, the stored data can be discriminated based on the presence or absence of current to the drain wiring DM.

  As described above, the nonvolatile memory according to the first embodiment is configured by configuring the EEPROM 201 that stores data depending on the presence or absence of charges stored in the charge storage film 5 and the mask ROM 202 that stores data depending on the presence or absence of the selection contact hole CHDM on the same plane. The semiconductor memory device 200 can store 2-bit data in one memory cell.

[Description of Circuit Configuration of Second Embodiment: FIG. 3]
FIG. 3 is an equivalent circuit diagram for explaining the circuit configuration of the second embodiment.
The second embodiment is a case where there are a plurality of memory transistors and the EEPROM is a NAND circuit. Since the planar structure and the cross-sectional structure of each memory transistor are the same as those of the first embodiment already described, the description thereof is omitted.

In FIG. 3, reference numeral 300 denotes a nonvolatile semiconductor memory device. Even in the nonvolatile semiconductor memory device 300, the EEPROM and the mask ROM that are integrally formed are referred to as an EEPROM 301 and a mask ROM 302, respectively.
SE is a source wiring of the EEPROM 301, DE is a drain wiring of the EEPROM 301, SM is a source wiring of the mask ROM 302, DM is a drain wiring of the mask ROM 302, and CHDM1 to CHDMn are selective contact holes on the drain side of the mask ROM 302. SS is a switch. MT1 to MTm are memory transistors constituted by the gate, the charge storage film, and the channel region already described in the first embodiment.

The memory transistors MT1 to MTm, the source line SE, and the drain line DE constitute an EEPROM 301.
The selection contact holes CHDM1 to CHDMn, the memory transistors MT1 to MTm, the source line SM, and the drain line DM constitute a mask ROM 302.

[Description of Data Write Operation of Second Embodiment of Nonvolatile Semiconductor Memory Device: FIG. 3]
Next, the data write operation of the second embodiment will be described with reference to FIG.

  In order to put the EEPROM 301 in the erased state, for example, 0 V is applied to the source wiring SE and the drain wiring DE, and, for example, −10 V is applied to all the gates of the memory transistors MT1 to MTm. The charges stored in all the charge storage films are extracted at once.

  In order to set the EEPROM 301 in the writing state, for example, 0V is applied to the gate, the source wiring SE, and the drain wiring DE of the memory transistors that are not written in the memory transistors MT1 to MTm, and the writing in the memory transistors MT1 to MTm is performed. By applying, for example, 10 V to the gate of the memory transistor that performs the operation, charges are selectively stored in the charge storage film from among the memory transistors MT1 to MTm.

  In order to put the mask ROM 302 into the erased state, selective contact holes for erasing the selected contact holes CHDM1 to CHDMn are selectively formed in the manufacturing process of the nonvolatile semiconductor memory device 300.

  In order to set the mask ROM in the writing state, the selection contact holes for writing in the selection contact holes CHDM1 to CHDMn are not selectively formed in the manufacturing process of the nonvolatile semiconductor memory device 300.

[Description of Data Reading Operation of Second Embodiment: FIG. 3]
Next, the data read operation of the second embodiment will be described with reference to FIG.
Here, Vw, Ve, Vr1, Vr2, and Vr3 are the same as those in the first embodiment already described, Vw is the threshold voltage in the written state, Ve is the threshold voltage in the erased state, Vr1, Vr2, and Vr3 is a read voltage and satisfies the following condition.
Vr1 <Ve <Vr2 <Vw <Vr3

First, the reading operation of data stored in the EEPROM 301 will be described.
When reading the data stored in the memory transistor MT1, the memory transistor MT
Vr2 is applied to the gate of 1, Vr3 is applied to the gates of the memory transistors MT2 to MTm, 2V is applied to the source wiring SE, and 0V is applied to the drain wiring DE, for example.

  By applying Vr3 higher than Ve and Vw to the gates of the memory transistors MT2 to MTm, the channel region of the memory transistors MT2 to MTm becomes a current path regardless of the presence or absence of charges accumulated in the charge storage film. All the switches SS are turned off.

If the charge storage film of the memory transistor MT1 is in a write state, even if Vr2 lower than Vw is applied to the gate, the channel region does not become a current path, so no current flows from the source line SE to the drain line DE. .
On the other hand, if the charge storage film of the memory transistor MT1 is in the erased state, the channel region becomes a current path by applying Vr2 higher than Ve to the gate, so that a current flows from the source line SE to the drain line DE. .
Therefore, the data stored in the memory transistor MT1 can be determined based on the presence / absence of a current to the drain wiring DE.

In the case of reading data stored in the memory transistors MT2 to MTm, Vr2 is applied to the gates of the memory transistors to be read and Vr3 is applied to the gates of the other memory transistors as in the read operation of the memory transistors MT1. The stored data can be discriminated.
By reading the data stored in the memory transistors MT1 to MTm according to the above description, the read operation of the EEPROM 301 is completed.

Next, the reading operation of data stored in the mask ROM 302 will be described.
When reading data stored in the selected contact hole CHDM1, Vr3 is applied to the gate of the memory transistor MT1 adjacent to the selected contact hole CHDM1, Vr1 is applied to the gates of the memory transistors MT2 to MTm, and 2V is applied to the source wiring SM, for example. For example, 0 V is applied to the drain wiring DM.

By applying Vr3 higher than Ve and Vw to the gate of the memory transistor MT1, the channel region of the memory transistor MT1 becomes a current path regardless of the presence or absence of charges accumulated in the charge storage film.
By applying Vr1 lower than Ve and Vw to the gates of the memory transistors MT2 to MTm, the channel region of the memory transistors MT2 to MTm does not serve as a current path regardless of the presence or absence of charges accumulated in the charge storage film. All the switches SS are turned on.

If the selected contact hole CHDM1 is in a write state, there is no current path through the selected contact hole CHDM1, and therefore no current flows from the source line SM to the drain line DM.
On the other hand, if the selected contact hole CHDM1 is in the erased state, the current flows from the source line SM to the drain line DM because there is a current path through the selected contact hole CHDM1.
Therefore, the data stored in the selected contact hole CHDM1 can be determined based on the presence / absence of a current to the drain wiring DM.

When reading the data stored in the selected contact holes CHDM2 to CHDMn, Vr3 is set to the gate of the memory transistor adjacent to the selected contact hole to be read and the other memory transistors are read in the same manner as the read operation of the selected contact hole CHDM1. By applying Vr1 to the gate, the stored data can be discriminated.
By reading the data stored in the selected contact holes CHDM1 to CHDMn according to the above description, the read operation of the mask ROM 302 is completed.

As described above, the EEPROM 301 for storing data according to the presence or absence of charges stored in the charge storage films of the memory transistors MT1 to MTm and the mask ROM 302 for storing data according to the presence or absence of the selection contact holes CHDM1 to CHDMn are configured on the same plane. The nonvolatile semiconductor memory device 300 according to the second embodiment can increase the data that can be stored per memory cell to more than one bit without increasing the gate interval of the memory transistors MT1 to MTm. The upper limit of the number of bits can be expressed by the following formula.
Maximum number of bits = [(m + n) / m]

Here, the upper limit of n representing the number of selected contact holes CHDM is m representing the number of memory transistors MT.
By setting n to the same number as the upper limit m, the upper limit of the number of bits shown in the above equation can be set to 2 bits which is the maximum value.

[Description of Circuit Configuration of Third Embodiment: FIG. 4]
FIG. 4 is an equivalent circuit diagram for explaining a circuit configuration of the third embodiment.
The third embodiment is a case where there are a plurality of memory transistors and the EEPROM is a NOR circuit. The planar structure and the cross-sectional structure of each memory transistor are the same as those of the first embodiment already described, but in the third embodiment, an EEPROM source line SE is used instead of the mask ROM source line SM. The following description also shows the case where the EEPROM source wiring SE is used.

In FIG. 4, reference numeral 400 denotes a nonvolatile semiconductor memory device. Even in the nonvolatile semiconductor memory device 400, the EEPROM and the mask ROM that are integrally formed are referred to as an EEPROM 401 and a mask ROM 402, respectively.
SE is the source wiring of the EEPROM 401, DE is the drain wiring of the EEPROM 401, DM is the drain wiring of the mask ROM 402, CHDM1 to CHDMm are the selective contact holes on the drain side of the mask ROM 402, and MT1 to MTm are the gates already described in the first embodiment. The memory transistor SS, which is constituted by the charge storage film and the channel region, is a switch.

The memory transistors MT1 to MTm, the source line SE, and the drain line DE constitute an EEPROM 401.
The selection contact holes CHDM1 to CHDMm, the memory transistors MT1 to MTm, the source line SE, and the drain line DM constitute a mask ROM 402.

[Description of Data Write Operation of Third Embodiment: FIG. 4]
Next, the data write operation of the third embodiment will be described with reference to FIG.

  In order to put the EEPROM 401 in the erased state, for example, 0 V is applied to the source wiring SE and the drain wiring DE, and, for example, −10 V is applied to all the gates of the memory transistors MT1 to MTm. The charges stored in all the charge storage films are extracted at once.

In order to set the EEPROM 401 in the writing state, for example, 0V is applied to the gate, the source wiring SE, and the drain wiring DE of the memory transistors that are not written in the memory transistors MT1 to MTm, and the writing in the memory transistors MT1 to MTm is performed. By applying, for example, 10 V to the gate of the memory transistor that performs the operation, charges are selectively stored in the charge storage film from among the memory transistors MT1 to MTm.

  In order to put the mask ROM 402 into the erased state, selective contact holes for erasing the selected contact holes CHDM1 to CHDMm are selectively formed in the manufacturing process of the nonvolatile semiconductor memory device 400.

  In order to set the mask ROM 402 in the writing state, the selection contact holes for writing in the selection contact holes CHDM1 to CHDMm are not selectively formed in the manufacturing process of the nonvolatile semiconductor memory device 400.

[Description of Data Reading Operation of Third Embodiment: FIG. 4]
Next, the data read operation of the third embodiment will be described with reference to FIG.
Here, Vw, Ve, Vr1, Vr2, and Vr3 are the same as those in the first embodiment already described, Vw is the threshold voltage in the written state, Ve is the threshold voltage in the erased state, Vr1, Vr2, and Vr3 is a read voltage and satisfies the following condition.
Vr1 <Ve <Vr2 <Vw <Vr3

First, the reading operation of data stored in the EEPROM 401 will be described.
When reading data stored in the memory transistor MT1, Vr2 is applied to the gate of the memory transistor MT1, Vr1 is applied to the gates of the memory transistors MT2 to MTm, and 2V is applied to the source line SE and 0V is applied to the drain line DE, for example. To do.

  By applying Vr1 lower than Ve and Vw to the gates of the memory transistors MT2 to MTm, the channel region of the memory transistors MT2 to MTm does not serve as a current path regardless of the presence or absence of charges accumulated in the charge storage film. All the switches SS are turned on.

If the charge storage film of the memory transistor MT1 is in a write state, even if Vr2 lower than Vw is applied to the gate, the channel region does not become a current path, so no current flows from the source line SE to the drain line DE. .
On the other hand, if the charge storage film of the memory transistor MT1 is in the erased state, the channel region becomes a current path by applying Vr2 higher than Ve to the gate, so that a current flows from the source line SE to the drain line DE. .
Therefore, the data stored in the memory transistor MT1 can be determined based on the presence / absence of a current to the drain wiring DE.

In the case of reading data stored in the memory transistors MT2 to MTm, Vr2 is applied to the gates of the memory transistors to be read and Vr1 is applied to the gates of the other memory transistors as in the read operation of the memory transistors MT1. The stored data can be discriminated.
By reading the data stored in the memory transistors MT1 to MTm according to the above description, the reading operation of the EEPROM 401 is completed.

Next, the reading operation of data stored in the mask ROM 402 will be described.
When reading data stored in the selected contact hole CHDM1, Vr3 is applied to the gate of the memory transistor MT1 adjacent to the selected contact hole CHDM1, Vr1 is applied to the gates of the memory transistors MT2 to MTm, and 2V, for example, is applied to the source line SE. For example, 0 V is applied to the drain wiring DM.

By applying Vr3 higher than Ve and Vw to the gate of the memory transistor MT1, the channel region of the memory transistor MT1 becomes a current path regardless of the presence or absence of charges accumulated in the charge storage film.
By applying Vr1 lower than Ve and Vw to the gates of the memory transistors MT2 to MTm, the channel region of the memory transistors MT2 to MTm does not serve as a current path regardless of the presence or absence of charges accumulated in the charge storage film. All the switches SS are turned off.

If the selected contact hole CHDM1 is in a writing state, there is no current path through the selected contact hole CHDM1, and therefore no current flows from the source line SE to the drain line DM.
On the other hand, if the selected contact hole CHDM1 is in the erased state, the current flows from the source line SE to the drain line DM because there is a current path through the selected contact hole CHDM1.
Therefore, the data stored in the selected contact hole CHDM1 can be determined based on the presence / absence of a current to the drain wiring DM.

In the case of reading data stored in the selected contact holes CHDM2 to CHDMm, Vr3 is set to the gate of the memory transistor adjacent to the selected contact hole to be read and the other memory transistors are read in the same manner as the read operation of the selected contact hole CHDM1. By applying Vr1 to the gate, the stored data can be discriminated.
By reading the data stored in the selected contact holes CHDM1 to CHDMm according to the above description, the read operation of the mask ROM 402 is completed.

  As described above, the EEPROM 401 for storing data according to the presence or absence of charges stored in the charge storage films of the memory transistors MT1 to MTm and the mask ROM 402 for storing data according to the presence or absence of the selection contact holes CHDM1 to CHDMm are configured on the same plane. The nonvolatile semiconductor memory device 400 of the third embodiment can increase the data that can be stored per memory cell to 2 bits.

  Since the nonvolatile semiconductor memory device of the present invention can increase the data that can be stored in one memory cell beyond 1 bit, it is suitable for a computer device or an electronic device that requires a high degree of integration.

DESCRIPTION OF SYMBOLS 1,101 Semiconductor substrate 2,102 Drain region 3,103 Source region 5,105 Charge storage film 6,106 Gate 8 Field oxide film 9 Intermediate insulating film 10 Channel region 100 Memory cell 104 Impurity region 107 Side wall 200, 300, 400 Nonvolatile semiconductor memory device 201, 301, 401 EEPROM
202, 302, 402 Mask ROM
SE EEPROM source wiring DE EEPROM drain wiring SM mask ROM source wiring DM mask ROM drain wiring CHSE EEPROM source side contact hole CHDE EEPROM drain side contact hole CHSM mask ROM source side contact hole CHDM mask ROM MT memory transistor SS switch S source terminal D drain terminal G gate terminal DD diode S1 source line D1, D2 drain line G1, G2 gate line DD1-DD4 diode MT1-MT4 memory transistor

Claims (3)

A non-volatile semiconductor memory device comprising a mask ROM and an EEPROM (“EEPROM” is a registered trademark; the same shall apply hereinafter) adjoining on the same plane,
A memory gate having a charge storage film in a predetermined activation region on the semiconductor substrate;
A source contact hole for configuring the mask ROM in a source region adjacent to the memory gate of the activation region, and a source contact hole for configuring the EEPROM;
Provided,
A selection contact hole for configuring the mask ROM, and a drain contact hole for configuring the EEPROM, in a drain region facing the source region across the memory gate;
Provided,
A source contact hole for configuring the mask ROM, a source contact hole for configuring the EEPROM, a selection contact hole for configuring the mask ROM, a drain contact hole for configuring the EEPROM, Are provided on the same plane . A nonvolatile semiconductor memory device, wherein   The nonvolatile semiconductor memory device according to claim 1, wherein the number of the selection contact holes is the same as the number of the memory gates adjacent to the source contact holes.   The nonvolatile semiconductor memory device according to claim 1, wherein the charge storage film is formed by stacking a plurality of insulating films.

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