JP5483231B2 - Voltage uniform circuit - Google Patents

Description

  The present invention relates to a voltage equalizing circuit that is connected to capacitors connected in series for a DC link of a five-level diode clamp type or a four-level diode clamp type inverter and uniformly controls a DC voltage generated in each capacitor.

  By introducing the rotation speed control technology using an inverter to control the air volume and water volume of fans, blowers and pumps, it is possible to achieve significant energy savings compared to conventional damper control.

  Since the conventional high-voltage AC motor variable speed drive using an inverter requires a multi-winding transformer, the weight and volume of the drive system increase (for example, see Non-Patent Document 1). For example, when a 6,6 kV, 1 MW motor drive system is realized using a multi-winding transformer, the power converter weight is 1000 to 2000 kg, whereas the transformer weight reaches 3000 to 4000 kg. .

  On the other hand, a transformerless motor drive system using a multilevel converter capable of increasing the withstand voltage has been proposed (see, for example, Non-Patent Document 2).

  For example, in the case of a 5-level diode clamp type PWM inverter (hereinafter simply referred to as “5-level inverter” in this specification), four units are provided to divide the voltage of the DC power source connected to the DC side of the 5-level inverter by 5 units. DC link capacitors (hereinafter simply referred to as “capacitors”) are connected in series, and the energy stored in the capacitors is used to have a potential of 5 levels corresponding to the above-mentioned 5 partial pressures. An AC output is generated (for example, Patent Document 1).

  In principle, since active power flows into or out of the five-level inverter, average values of DC link voltages (hereinafter simply referred to as “DC voltages”) generated in the four capacitors are not equal. A so-called “partial pressure non-uniformity” problem occurs. In order to make all the wave heights for each level of the AC output equal (uniform), it is necessary to control so that the average values of the DC voltages generated in the capacitors are all equal (uniform). For this reason, a circuit called a voltage uniform circuit (Voltage-Balancing Circuit) is connected to the DC side of the five-level inverter. The problem of non-uniform partial pressure can also occur in multi-level inverters other than 5-level inverters.

  FIG. 15 is a circuit diagram showing a general voltage equalization circuit connected to a motor drive system composed of a diode rectifier and a 5-level inverter. Hereinafter, components having the same reference numerals in different drawings mean components having the same functions.

Four capacitors C _dc are connected in series on the DC side of the 5-level inverter 101 in order to divide the voltage of the DC power source supplied from the diode rectifier 102 by five. Using the energy stored in the capacitor C _dc , an AC output having a five-level potential is generated, and a three-phase AC current i _o is supplied to the induction motor IM (reference numeral 104).

For example, in a motor drive system including a diode rectifier 102 and a 5-level inverter 101 for driving a fan / blower that does not require a regenerative operation, among the four capacitors C _dc connected in series, Since the capacitor is in a discharged state, the DC voltage is reduced, and the two outer capacitors are in a charged state, and thus the DC voltage is increased (see, for example, Non-Patent Document 3). For this reason, the voltage uniform circuit 103 is connected between the capacitor C _dc and the diode rectifier 102 so as to charge the inner two capacitors and discharge the outer two capacitors. The voltage equalization circuit 103 shown in FIG. 15 has a configuration in which two chopper circuits of a boosting system and a bucking system are provided separately on the P side and the N side, respectively. The DC voltage detected in each capacitor C _dc is converted into a digital value by the AD converter 111, arithmetic processing is performed in the DSP 112, and the voltage is uniformed by the PWM generator 113 for generating the switching element pattern of the five-level inverter 101. An optimum switching element pattern to be supplied to the switching elements Q ₁ , Q ₂ , Q ₃ , and Q ₄ in the circuit 103 is generated.

FIG. 16 is a circuit diagram showing still another general voltage equalization circuit. In the illustrated example, only one chopper circuit of the voltage uniform circuit is shown for the sake of simplicity. Since the DC voltage of two DC link capacitors C _dc is ignited in the switching elements Q ₁ and Q ₂ , two switching elements having the same breakdown voltage as the switching element used in the main converter are connected in series. Need to connect.

JP 2006-223209 A

PW Hammond, “A new approach to enhance power medium AC drives”, IEEE Transaction, Ind. Application. 1997, Vol. 33, no. 1, pp202-208 Yosuke Kondo, Hatti Natpongong, Yasufumi Akagi, “Induction motor variable drive system using 5-level diode clamp PWM rectifier and inverter”, IEEJ Transactions D, Japan, 2008, 128, 3, pp 259-266 F. Z. Peng, J.S. Lai, J. McKeever, J. Van Coevering, “Uniform DC voltage A multilevel voltage-source converter system with balanced DC voltages ", Proc, IEEE-PESC '95 Rec. 1995, pp 1144-1150

The voltage uniform circuit of FIG. 15 described above has a structure in which two chopper circuits are simply combined. Therefore, although the switching operation in each chopper circuit can be controlled independently, the inductors L _P and L There is a disadvantage that the weight, volume, and cost of _N increase.

  Further, in the voltage uniform circuit of FIG. 16 described above, if two switching elements are simply connected directly, overvoltage may be applied to one switching element due to variations in turn-on and turn-off time of each switching element. is there.

In any of the voltage uniform circuits described above, the inductor L _P operates as an energy storage element. Since the volume of the inductor L _P is proportional to the stored energy, the volume of the inductor L _P must be large, resulting in an increase in manufacturing cost.

  Accordingly, in view of the above problems, an object of the present invention is connected to capacitors connected in series for a DC link of a five-level diode clamp type or a four-level diode clamp type inverter, and the DC voltage generated in each capacitor is made uniform. An object of the present invention is to provide a voltage uniform circuit which is easy to structure, small in size and low in cost.

  To achieve the above object, in the first aspect of the present invention, the first, second, third and fourth capacitors connected in series for the DC link of the five-level diode clamp type inverter are connected to each other. A voltage equalizing circuit that is connected and uniformly controls a DC voltage generated in each capacitor includes: a first switch group connected to a terminal of the first capacitor opposite to a side to which the second capacitor is connected; The neutral point of the inverter which is a connection point between the cathode connected to the terminal on the opposite side of the first switch group to the side to which the first capacitor is connected, and the second capacitor and the third capacitor A first diode having an anode connected to the first diode, a second diode having a cathode connected to a connection point between the anode and the neutral point of the first diode, and an anode of the second diode. And a second switch group having the other terminal connected to the terminal of the fourth capacitor connected to the terminal opposite to the side to which the third capacitor is connected, The first reactor includes a connection point between the first switch group and the cathode of the first diode, a first capacitor, and a second reactor. And the second winding is connected between the anode of the second diode and the second switch group, the third capacitor, and the fourth capacitor. When the first switch group is turned on, the coupling switch connected between the connection point and the second switch group is turned off, and when the first switch group is turned off, the second switch group is turned on. And a control unit that controls to turn on.

  Further, in the second aspect of the present invention, the DC voltage generated in each capacitor is connected to the first, second and third capacitors connected in series for the DC link of the inverter of the four level diode clamp type. A voltage equalization circuit that uniformly controls the first switch group connected to the terminal of the first capacitor opposite to the side to which the second capacitor is connected, and the first switch group A first diode having a cathode connected to a terminal opposite to a side to which the first capacitor is connected, and an anode connected to a connection point between the second capacitor and the third capacitor; A second diode having a cathode connected to a connection point between the first capacitor and the second capacitor; and one terminal connected to an anode of the second diode; A coupling reactor comprising a second switch group to which the other terminal is connected to a terminal opposite to a side to which the second capacitor is connected, a first winding, and a second winding. The first winding is connected between the connection point of the first switch group and the cathode of the first diode and the connection point of the first capacitor and the second capacitor, and the second winding The winding includes a coupling reactor connected between a connection point between the anode of the second diode and the second switch group, and a connection point between the second capacitor and the third capacitor; A control unit that controls to turn off the second switch group when turning on the switch group and to turn on the second switch group when turning off the first switch group.

  According to the present invention, it is possible to realize a voltage uniform circuit having an easy structure, a small size, and a low cost. The voltage uniform circuit according to the present invention can reduce the inductor volume as compared with the conventional voltage uniform circuit. For example, according to the present invention, the inductor volume can be reduced to about 1/5 as compared with the conventional example described with reference to FIG. As a result, the entire device of the voltage uniform circuit can be realized in a small size and at a low cost. Further, according to the present invention, since the coupling reactor is used, the number of parts can be reduced as compared with the conventional example. Further, according to the present invention, it is possible to realize bias control that suppresses the generation of DC magnetic flux that could not be achieved in the conventional example.

1 is a circuit diagram of a voltage uniform circuit according to a first embodiment of the present invention. FIG. 2 is a diagram defining a relationship between a DC voltage supplied from a DC power supply and a capacitor for voltage division in the 5-level inverter shown in FIG. 1. FIG. 3 is a circuit diagram (No. 1) for explaining an operation principle of the voltage uniform circuit according to the first embodiment of the present invention. FIG. 3 is a circuit diagram (No. 2) for explaining an operation principle of the voltage uniform circuit according to the first embodiment of the present invention. 6 is an equivalent circuit for explaining the effects of the first and second inductors in the voltage uniform circuit according to the first embodiment of the present invention. 6A and 6B are diagrams schematically showing the magnetic flux in the core of the inductor according to the first embodiment of the present invention and the conventional example. FIG. 6A shows the magnetic flux in the conventional example, and FIG. 6B shows the present invention. It is a figure which shows the magnetic flux in 1st Example of this. FIG. 3 is a block diagram showing a control system for voltage uniformity control in the voltage uniformity circuit according to the first embodiment of the present invention, in particular, a block diagram showing a P-side control system. FIG. 3 is a block diagram showing a control system for voltage uniformity control in the voltage uniformity circuit according to the first embodiment of the present invention, in particular, a block diagram showing an N-side control system. It is a block diagram which shows the control system for the bias control in the 1st Example of this invention. It is a figure which shows the experimental waveform at the time of operating the voltage equalization circuit by the 1st Example of this invention, and driving an induction motor. It is a figure which shows the experimental waveform at the time of operating the voltage equalization circuit by 1st Example of this invention, and driving an induction motor, Comprising: It is the figure which expanded FIG. 10 10 time in the time-axis direction. It is a circuit diagram of the voltage equalization circuit by the 2nd Example of this invention. FIG. 5 is a circuit diagram (No. 1) for explaining a basic operation principle of a voltage uniform circuit according to a second embodiment of the present invention. FIG. 6 is a circuit diagram (No. 2) for explaining the basic operation principle of the voltage uniform circuit according to the second embodiment of the present invention. It is a circuit diagram which shows the general voltage equalization circuit connected to the motor drive system which consists of a diode rectifier and a 5-level inverter. It is a circuit diagram which shows another general voltage equalization circuit.

  The voltage equalizing circuit according to the first embodiment of the present invention is connected to a capacitor for a DC link of a five-level diode clamp type inverter and uniformly controls a DC voltage generated in each capacitor. FIG. 1 is a circuit diagram of a voltage uniform circuit according to a first embodiment of the present invention.

In general, a first capacitor C _DC1 , a second capacitor C _DC2 , a third capacitor C _DC3 , and a fourth capacitor C _DC4 for a DC link are connected in series with each other on the DC side of the five-level diode clamp type inverter 101. Has been. Connection points of the first capacitor C _DC1 , the second capacitor C _DC2 , the third capacitor C _DC3 , and the fourth capacitor C _DC4 are P2, P1, M, N1, and N2, as shown in FIG. That is, the connection point M is a neutral point of the five-level inverter 101. A positive electrode of a diode rectifier 102 serving as a DC power supply is connected to a terminal P2 of the first capacitor C _DC1 opposite to the side to which the second capacitor C _DC2 is connected (that is, the connection point P1). The negative electrode of the diode rectifier 102 serving as a DC power source is connected to a terminal N2 on the opposite side of the capacitor C _DC4 to the side to which the third capacitor C _DC3 is connected (that is, the connection point N1).

The voltage equalization circuit 1 according to the first embodiment of the present invention includes a group in which a first capacitor C _DC1 , a second capacitor C _DC2 , a third capacitor C _DC3 , and a fourth capacitor C _DC4 are connected in series, a diode rectifier 102, Connected between.

The voltage equalization circuit 1 includes a first switch group SW1, a second switch group SW2, a first diode D ₁ , a second diode D ₂ , a third diode D ₃ , a fourth diode D ₄ , a coupled reactor. L _M , a first inductor L _EP , a second inductor L _EN , a control unit (not shown), and a current detection unit (not shown).

The first switch group SW1 includes a terminal P2 on the opposite side of the first capacitor C _DC1 to the side to which the second capacitor C _DC2 is connected (that is, the connection point P1), and a first of the coupling reactor L _M. a connection point between the winding L _MP and the first diode D ₁ of the cathode, is connected between the.

The first diode D ₁ includes a cathode connected to a terminal of the first switch group SW 1 on the side opposite to the side to which the first capacitor C _DC1 is connected (that is, the terminal P 2), and a second capacitor C 1. And an anode connected to a neutral point M of the inverter, which is a connection point between _DC2 and the third capacitor _CDC3 .

The second diode D ₂ is the connection point of the connection point between the first diode D ₁ of the anode and the neutral point M, the second winding L _MN and the second switch group SW2 of the coupling reactor L _M And connected between.

Second switch group SW2 is the anode of the second diode D _2, the one terminal connection, the fourth capacitor C _DC4, a third side of the capacitor C _DC3 is connected (i.e. the connection point N1) The other terminal is connected to the terminal N2 on the opposite side.

Coupling reactor L _M comprises a first winding L _MP and the second winding L _MN.

First winding L _MP of coupling reactor L _M includes a first switch group SW1 and a connection point between the first diode D ₁ of the cathode, the first capacitor C _DC1 and the second capacitor C _DC2 It is connected between the connection point P1. Incidentally, the first winding L _MP of coupling reactor L _M, and the opposite side terminal to the side where the first switch group SW1 is connected to the first capacitor C _DC1 and the second capacitor C _DC2 A first inductor _LEP is connected between the connection point P1. Inductance of the first inductor L _EP is set to one sufficiently smaller than the inductance of the first winding L _MP of coupling reactor L _M.

Second winding L _MN of coupling reactor L _M, the anode of the second diode D ₂ and the connection point of the second switch group SW2, the third capacitor C _DC3 and the fourth capacitor C _DC4 It is connected between the connection point N1. Incidentally, the second winding L _MN of coupling reactor L _M, and the opposite side terminal to the side where the second switch group SW2 is connected, the third capacitor C _DC3 and the fourth capacitor C _DC4 A second inductor _LEN is connected between the connection point N1. Inductance of the second inductor L _EN is set to one sufficiently smaller than the inductance of the second winding L _MN of coupling reactor L _M.

The first switch group SW1 includes a first switching element Q connected to a terminal P2 of the first capacitor C _DC1 opposite to the side to which the second capacitor C _DC2 is connected (that is, the connection point P1). ₁ and a second switching element Q ₂ connected in series to the first switching element Q ₁ . When the first switching element Q ₁ is turned on, the first switching element Q ₁ is switched from the terminal P 2 on the opposite side of the first capacitor C _DC1 to the side to which the second capacitor C _DC2 is connected (ie, the connection point P 1). pass current toward the side of the terminal element Q ₂ is connected. The second switching element Q ₂ is, at the time of ON, from the side of the terminal to which the first switching element Q ₁ is connected, towards the side of the terminal to which the first winding L _MP of coupling reactor L _M is connected Pass current.

The second switch group SW2 includes a third switching element Q ₃ connected to the anode of the second diode D ₂ and a fourth switching element Q ₄ connected in series to the third switching element Q _3. Prepare. Third switching element Q ₃ are, at the time of ON, from the side of the terminal to which the second winding L _MN of coupling reactor L _M is connected, towards the fourth side of the terminal switching element Q ₄ is connected The fourth switching element Q ₄ is connected to the third capacitor C _{DC3 of} the fourth capacitor C _DC4 from the terminal on the side to which the third switching element Q ₃ is connected when the fourth switching element Q ₄ is turned on. A current is supplied to the terminal N2 on the side opposite to the side (that is, the connection point N1).

The third diode D ₃ has a cathode connected to a connection point of the first switching element Q ₁ and the second switching element Q _2, connection between the first capacitor C _DC1 and the second capacitor C _DC2 And an anode connected to the point P1.

The fourth diode D ₄ includes an anode connected to a connection point between the _third switching element Q ₃ and the fourth switching element Q _4, and a connection between the third capacitor C _DC3 and the fourth capacitor C _DC4. And a cathode connected to the point N1.

A current detector (not shown) detects a current flowing through the first inductor _LEP and a current flowing through the second inductor _LEN .

Controller (not shown), when the first switch group SW1 (i.e. first switching element Q ₁ and the second switching element Q ₂₎ the on (conductive), the second switch group SW2 (i.e. When the third switching element Q ₃ and the fourth switching element Q ₄ ) are turned off (opened) and the first switch group SW1 is turned off (opened), the second switch group SW2 is turned on (conductive). Control as follows.

  Next, the operation of the voltage uniform circuit according to the first embodiment of the present invention will be described. Prior to this description, the capacitor voltage is defined as shown in FIG.

FIG. 2 is a diagram for defining the relationship between a DC voltage supplied from a DC power supply and a capacitor for voltage division in the 5-level inverter shown in FIG. In FIG. 2, the instantaneous values of the voltages of the first capacitor C _DC1 , the second capacitor C _DC2 , the third capacitor C _DC3 , and the fourth capacitor C _DC4 are represented by v _p2-1 , v _p1-M , and v _M-N1 , respectively. And _vN1-N2 . Note that the average value of the voltage per capacitor is represented by V _dc . The instantaneous value of the DC voltage (DC link voltage) supplied from the DC power supply is represented by v _P2−N2 , and viewed from the neutral point M on the positive side (hereinafter referred to as “P side” in this specification). The instantaneous value of the voltage of a certain first capacitor C _DC1 and second capacitor C _DC2 is represented by v _P2−M , and is on the negative electrode side (hereinafter referred to as “N side” in this specification) as viewed from the neutral point M. The instantaneous value of the voltage of the third capacitor C _DC3 and the fourth capacitor C _DC4 is represented by v _P2−M .

  3 and 4 are circuit diagrams for explaining the basic operation principle of the voltage equalizing circuit according to the first embodiment of the present invention. FIG. 3 shows a state in mode A, and FIG. 4 shows a state in mode B. Show.

When turning on (conducting) the first switch group SW1 (ie, the first switching element Q ₁ and the second switching element Q ₂ ), the control unit sets the second switch group SW2 (ie, the third switching element). Control is performed to turn off (open) Q ₃ and the fourth switching element Q ₄ ). The switching state at this time is referred to as mode A, and the current flow at this time is shown in FIG. The control unit, when the first switch group SW1 (i.e. first switching element Q ₁ and the second switching element Q ₂₎ OFF (open), the second switch group SW2 (i.e. third The switching element Q ₃ and the fourth switching element Q ₄ ) are controlled to be turned on (conductive). The switching state at this time is referred to as mode B, and the current flow at this time is shown in FIG.

First, in the mode A shown in FIG. 3, since the first switching element Q ₁ and the second switching element Q ₂ that are the first switch group SW1 are turned on, the terminal P2 is connected from the first capacitor _CDC1. current i _LP via flows to the first winding L _MP of coupling reactor L _M. The first winding L _MP of coupling reactor L _M if the first inductor L _EP is sufficiently small voltage v _P2-P1 generated in the first capacitor C _DC1 is applied. That is, “v _MP ≈v _P2−P1 ”. This voltage, since also occur second winding L _MN of coupling reactor L _M by electromagnetic induction, a "v _MN ≒ v _P2-P1". At this time, since the voltage is applied to the second diode D ₂ in the forward direction, the current i _LN flows into the third capacitor C _DC3 via the neutral point M. That is, in mode A, the first capacitor C _DC1 is discharged, and the third capacitor C _DC3 is charged by the energy.

On the other hand, in the mode B shown in FIG. 4, since the third switching element Q ₃ and the fourth switching element Q _{4 that} are the second switch group SW2 are on, the terminal N2 is connected from the fourth capacitor _CDC4. current i _LN via the flows through the second winding L _MN of coupling reactor L _M. The second winding L _MPN of coupling reactor L _M if the second inductor L _EN is sufficiently small voltage v _P2-P1 occurring fourth capacitor C _DC4 is applied. That is, “v _MN ≈v _N1−N2 ”. This voltage, since the induced in the first winding L _MP of coupling reactor L _M by electromagnetic induction, a "v _MP ≒ v _N1-N2". At this time, since the voltage is applied to the first diode D ₁ in the forward direction, the current i _P flows into the second capacitor C _DC2 via the connection point P1. That is, in mode B, the fourth capacitor C _DC4 is discharged, and the second capacitor C _DC2 is charged by the energy.

When the voltage equalizing circuit 1 according to the first embodiment of the present invention is not provided, the two outer capacitors, that is, the first capacitor C _DC1 and the fourth capacitor C _DC4 are charged as described above. The DC voltage generated in these capacitors rises, and the two inner capacitors, that is, the second capacitor C _DC2 and the third capacitor C _DC3 are in a discharged state, so that the DC voltage generated in these capacitors decreases. On the other hand, if the voltage equalization circuit 1 according to the first embodiment of the present invention is applied, the two outer capacitors, that is, the first capacitor C _DC1 and the second capacitor are switched by alternately switching the mode A and the mode B described above. The fourth capacitor C _DC4 can be discharged and the inner two capacitors, the second capacitor C _DC2 and the third capacitor C _DC3 can be charged, so the first capacitor C _DC1 , the second capacitor Each DC voltage generated in C _DC2 , third capacitor C _DC3, and fourth capacitor C _DC4 can be made equal (uniform).

  Here, the voltage uniform circuit 1 according to the first embodiment of the present invention and the conventional voltage uniform circuit shown in FIG. 15 are compared in terms of switching operation as follows.

The conventional voltage equalization circuit 103 shown in FIG. 15 has a configuration in which two chopper circuits of a boosting system and a bucking system are separately provided on the P side and the N side, respectively. The switching operation of the switching elements Q ₁ and Q _{2 in} the P-side chopper circuit and the switching operation of the switching elements Q ₃ and Q _{4 in} the N-side chopper circuit can be controlled independently. Therefore, for example, switching elements Q ₁ and Q ₂ and switching elements Q ₃ and Q ₄ may be turned on simultaneously.

In contrast, in the voltage-balancing circuit 1 according to a first embodiment of the present invention, the first switch group SW1 (first switching element Q ₁ and the second switching element Q ₂₎ and the second switch group SW2 ( The third switching element Q ₃ and the fourth switching element Q ₄ ) need to be controlled to be switched on and off. If the first switch group SW1 and the second switch group SW2 are turned on at the same time, the first capacitor C _DC1 , the second capacitor C _DC2 , the third capacitor C _DC3 and the fourth capacitor C _DC4 are _turned on. Each DC voltage generated in each cannot be made uniform. That is, not only the configuration as shown in FIG. 1 is assembled in a circuit but also specific control is required for the switching operation of each switching element.

FIG. 5 is an equivalent circuit for explaining the effects of the first and second inductors in the voltage uniform circuit according to the first embodiment of the present invention. 5 (a) shows the mode A described with reference to FIG. 3, coupling reactor L _M, an equivalent circuit focused on the applied voltage of the first inductor L _EP and second inductors L _EN. Here, the sum of the voltage drops of the first switching element Q ₁ and the second switching element Q ₂ is V _Q, and the voltage drop of the second diode D ₂ is V _D. On the P side, a voltage “v _P2-P1 −V” obtained by subtracting the voltage drop V _Q of the first switching element Q ₁ and the second switching element Q ₂ from the DC voltage v _P2-P1 of the first capacitor C _{DC1. Q} "is applied. A voltage “v _M−N1 + V _D ” obtained by adding the voltage drop V _D of the second diode D ₂ to the DC voltage v _M−N1 of the third capacitor C _DC3 is applied to the N side. Although the mode A has been described here, the same applies to the mode B.

Assuming that the coupling reactor L _M is an ideal transformer, it can be considered that the P side and the N side are short-circuited as shown in FIG. Furthermore, when there is no deviation in the DC voltage generated in each of the first capacitor C _DC1 and the third capacitor C _DC3 and “v _P2−P1 = v _M−N1 ”, Expression (1) is obtained.

From the equation (1), the voltage corresponding to the voltage drop of the first switching element Q ₁ , the second switching element Q ₂ , and the second diode D ₂ is expressed by the first inductor L _EP and the second inductor L _EN. As can be seen from FIG.

If it is assumed that there is no first inductor _LEP and second inductor _LEN , a short circuit of a different voltage source can be considered between the P side and the N side, so that an overcurrent may flow. However, the first inductor _LEP and the second inductor _LEN are provided, and the voltage corresponding to the voltage drop of the first switching element Q ₁ , the second switching element Q ₂ , and the second diode D ₂ is provided to them. By applying the voltage, overcurrent can be prevented.

    Here, the voltage uniform circuit 1 according to the first embodiment of the present invention and the conventional voltage uniform circuit shown in FIG. 15 are compared in terms of the volume of the inductor as follows.

Inductance of the first inductor L _EP and second inductors L _EN affects ripple current width of the current i _LP and i _LN. In the conventional voltage equalizing circuit 103 shown in FIG. 15, a voltage equivalent to one capacitor is applied to the inductor L _P or L _N , but the voltage equalizing circuit 1 according to the first embodiment of the present invention is an element as described above. A voltage corresponding to the voltage drop is applied. Therefore, the first inductance of the first inductor L _EP or second inductor L _EN in the embodiment of the present invention is sufficient but much lower than the inductance in the conventional example. That is, the volume of the first inductor L _EP and second inductors L _EN requires only be significantly smaller than the inductor volume of prior art. Further, the leakage inductance of the coupling reactor, using as an inductance of the first inductor L _EP and second inductors L _EN, can be a coupling reactor and integrated inductors.

In the conventional voltage equalization circuit, the inductor L _P operates as an energy storage element. Since the volume of the inductor L _P is proportional to the stored energy, the volume of the inductor L _P must be large. In contrast, in the voltage-balancing circuit 1 according to a first embodiment of the present invention, since the coupling reactor L _M does not operate as an energy storage element, inductor volume requires significantly smaller than the conventional example.

  FIG. 6 is a diagram schematically showing the magnetic flux in the core of the inductor according to the first embodiment of the present invention and the conventional example. FIG. 6 (a) shows the magnetic flux in the conventional example, and FIG. ) Is a diagram showing magnetic flux in the first embodiment of the present invention.

In the conventional example, since a direct current and a ripple current component are included in the inductor on each of the P side and the N side, a direct current component is also generated in the magnetic flux Φ generated in the core as shown in FIG. On the other hand, in the first embodiment of the present invention, each magnetic flux generated by the currents i _LP and i _LN is generated in a direction that cancels out in the core of the coupling reactor, so as shown in FIG. A direct current component does not occur in the magnetic flux Φ generated in the core. Therefore, in the first embodiment of the present invention, the maximum value of the magnetic flux is reduced as compared with the conventional example. This means that if the core is designed with the same magnetic flux density and the same number of turns, the cross-sectional area of the core can be reduced. That is, according to the first embodiment of the present invention, the inductor volume can be significantly smaller than that of the conventional example.

  According to the first embodiment of the present invention, the inductor volume can be significantly smaller than the conventional example for the various reasons described above. Such a small inductor volume also means that a voltage uniform circuit can be realized at low cost.

  Next, voltage uniformity control in the voltage uniformity circuit according to the first embodiment of the present invention will be described in more detail. 7 and 8 are block diagrams showing a control system for voltage uniformity control in the voltage uniformity circuit according to the first embodiment of the present invention. FIG. 7 shows a P-side control system, and FIG. It is a figure which shows the N side control system.

The carrier signal V _triN for PWM control in the N-side control system is 180 degrees out of phase with the carrier signal V _triP for PWM control in the P-side control system. Thereby, the alternate switching in the first switch group SW1 and the second switch group SW2 by switching between the mode A and the mode B described with reference to FIGS. 3 and 4 can be realized.

As shown in FIG. 7, in the control system on the P side, PI control is used so that the DC voltage v _{P2-P1 of} the first capacitor C _DC1 and the DC voltage v _{P1-M of} the second capacitor C _DC2 match. . Also, P control is used to prevent the reactor current i _LP from vibrating.

Further, as shown in FIG. 8, in the N-side control system, the PI control is performed so that the DC voltage v _{M-N1 of} the third capacitor C _DC3 and the DC voltage v _{N1-N2 of} the fourth capacitor C _DC4 match. Is used. Also, P control is used to prevent the reactor current i _LN from vibrating.

Further, in order to prevent simultaneous on / off of the first switching element Q ₁ and the second switching element Q ₂ and the third switching element Q ₃ and the fourth switching element Q ₄ (hereinafter referred to as the reactor current) , Referred to herein as the “reflux period.”) T ₁ and T ₃ are provided. That is, in the control system on the P side, when the first switching element Q ₁ and the second switching element Q ₂ that are the first switch group SW 1 are turned on, the on-time of the second switching element Q ₂ is set to the first time. Control is performed so as to be longer than the ON time of the switching element Q ₁ . On the other hand, in the N-side control system, when the third switching element Q ₃ and the fourth switching element Q ₄ , which are the second switch group SW 2, are turned on, the on time of the third switching element Q ₃ is set to the fourth time. controls to longer than the oN time of the switching element Q _4. Here, ΔD _P is a ratio of the reflux periods T ₁ and T ₃ occupying one switching cycle on the P side, and is expressed by Expression (2), where T _S is the switching cycle.

Ratio [Delta] D _N reflux period T ₁ and T ₃ occupying the switching cycle of the N-side is the same. These ΔD _P and ΔD _N are used for controlling the demagnetization of the coupling reactor, and the details will be described with reference to FIG.

The average values of the currents i _P1 and i _N1 flowing into or out of the connection points P1 and N1 of the five-level inverter 101 are ideally equal. Therefore, since the current i _LP flowing through the first winding L _MP of the coupled reactor L _M and the current i _LN flowing through the second winding L _MN are equal, a DC magnetic flux is not generated in the core of the coupled reactor L _M. Does not occur. However, in practice, there may be a difference between the average value of the current i _{P1 and} the average value of the current i _N1 due to variations in elements, control system errors, and the like. Therefore, differences occur between the mean value of the average value and the current i _LN current i _LP, since the DC component of the magnetic flux in the core of the coupling reactor L _M is not canceled, the DC magnetic deviation occurs.

Formula (3) between the average value of the current i _P1 flowing average value of the current i _LP flowing through the first winding L _MP of coupling reactor L _M from the connection point P1 to the five-level inverter 101 A relationship is established.

Regarding equation (3), the average value of the current i _P1 is uncontrollable due to a variable determined by the state of the 5-level inverter, whereas ΔD _P is controllable because of the variable by the return period. That is, the average value of the current i _LP can be controlled to a value different from the average value of the current i _P1 by controlling ΔD _P. Here, since “ΔD _P > 0”, the average value of the current i _LP is larger than the average value of the current i _P1 . The same is true for the second winding L _MN of coupling reactor L _M. Therefore, even if there is a difference between the average value of the current i _P1 flowing into the 5-level inverter 101 from the connection point P1 and the average value of the current i _N1 flowing into the 5-level inverter 101 from the connection point N1, it is controllable so that the average value and is equal to the second winding L _MN the flowing current i _LN average value and the coupling reactor L _M of the current i _LP flowing through the first winding L _MP of the reactor L _M .

  FIG. 9 is a block diagram showing a control system for bias control in the first embodiment of the present invention.

As shown in FIG. 9 (a), the average value of the current i _LP flowing through the first inductor L _EP detected by the current detection unit, a current flows through the second inductor L _EN detected by the current detection unit i If greater than the average value of the _LN, by P control using a value obtained by subtracting the current i _LN from current i _LP flowing through the first inductor L _EP flowing through the second inductor L _EN, to determine the [Delta] D _N . Here, a low-pass filter LPF is inserted to remove the ripple current component of the current i _LP and the current i _LN . The determined ΔD _N is input to the control system of the voltage uniformity control described with reference to FIG. 8, and accordingly, the on-time of the _third switching element Q _{3 and} the on-time of the fourth switching element Q ₄ The ratio is determined.

On the other hand, as shown in FIG. 9 (b), the average value of the current i _LP flowing through the first inductor L _EP detected by the current detection unit, flows through the second inductor L _EN detected by the current detection unit If less than the average value of the current i _LN, by proportional control using a value obtained by subtracting the current i _LP from the current i _LN flowing through the second inductor L _EN through the first inductor L _EP, the [Delta] D _P decide. Here, a low-pass filter LPF is inserted to remove the ripple current component of the current i _LP and the current i _LN . The determined ΔD _P is input to the control system of the voltage uniformity control described with reference to FIG. 7, and the ratio between the on-time of the _first switching element Q _{1 and} the on-time of the second switching element Q ₂ is It is determined.

Since and "[Delta] D _P ≠ 0" to provide the reflux period is required to be "[Delta] D _N ≠ 0", and the feedforward the [Delta] D ₀ as both [Delta] D _P and [Delta] D _N initial values.

The ratio between the on-time of the _first switching element Q _{1 and} the on-time of the second switching element Q ₂ determined as described above, and the on-time of the third switching element Q ₃ and the fourth switching element Based on the ratio of Q _{4 to} the ON time, the switching operations of the first switching element Q ₁ , the second switching element Q ₂ , the third switching element Q ₃ and the fourth switching element Q ₄ are controlled.

10 and 11 are diagrams showing experimental waveforms when the induction motor is driven by operating the voltage uniform circuit according to the first embodiment of the present invention. FIG. It is the figure expanded twice. In the experiment, the carrier frequency of the element of the voltage uniform circuit was 2.5 kHz, the carrier frequency of the 5-level inverter was 3 kHz, the inverter modulation factor was 1.0, the output frequency was 50 Hz, and the output voltage was 3.1 kW. As for the switching elements, 600 V IGBTs and 600 V diodes were used for both the voltage uniform circuit and the 5-level inverter. Each waveform includes phase voltage v _u , line voltage v _uv , output current i _o , DC voltage v _P2-M , v _P1-M , v _N1-M and v _N2-M , inductor current i _LP and i _LN . From the experimental results, it can be seen that the phase voltage has 5 levels and the line voltage has 9 levels, and the DC voltage of each capacitor is uniformly controlled.

  The voltage equalizing circuit according to the second embodiment of the present invention is connected to a capacitor for a DC link of a four-level diode clamp type inverter and uniformly controls a DC voltage generated in each capacitor. FIG. 12 is a circuit diagram of a voltage uniform circuit according to the second embodiment of the present invention.

In general, a first capacitor C _DC1 , a second capacitor C _DC2, and a third capacitor C _DC3 for a DC link are connected in series to each other on the DC side of the four-level diode clamp type inverter 101. The connection points of the first capacitor C _DC1 , the second capacitor C _DC2, and the third capacitor C _DC3 are P2, P1, N1, and N2, as shown in FIG. A positive electrode of a diode rectifier 102 serving as a DC power supply is connected to a terminal P2 of the first capacitor C _DC1 opposite to the side to which the second capacitor C _DC2 is connected (that is, the connection point P1). The negative electrode of the diode rectifier 102 serving as a DC power source is connected to a terminal N2 of the capacitor C _DC3 opposite to the side to which the second capacitor C _DC2 is connected (that is, the connection point N1).

The voltage equalizing circuit 2 according to the second embodiment of the present invention is connected between a diode rectifier 102 and a group in which a first capacitor C _DC1 , a second capacitor C _DC2 , and a third capacitor C _DC3 are connected in series. .

The voltage equalization circuit 1 includes a first switch group SW1, a second switch group SW2, a first diode D ₁ , a second diode D ₂ , a third diode D ₃ , a fourth diode D ₄ , a coupled reactor. L _M , a first inductor L _EP , a second inductor L _EN , a control unit (not shown), and a current detection unit (not shown).

The first switch group SW1 includes a terminal P2 on the opposite side of the first capacitor C _DC1 to the side to which the second capacitor C _DC2 is connected (that is, the connection point P1), and a first of the coupling reactor L _M. a connection point between the winding L _MP and the first diode D ₁ of the cathode, is connected between the.

The first diode D ₁ includes a cathode connected to a terminal of the first switch group SW 1 on the side opposite to the side to which the first capacitor C _DC1 is connected (that is, the terminal P 2), and a second capacitor C 1. And an anode connected to a connection point between _DC2 and the third capacitor _CDC3 .

The second diode D ₂ has a cathode and the second winding L _MN and a second switch coupling reactor L _M which is connected to the first capacitor C _DC1 to the connection point P1 of the second capacitor C _DC2 It has an anode connected to a connection point with the group SW2.

Second switch group SW2 is the anode of the second diode D _2, the one terminal connection, the third capacitor C _DC3, the side where the second capacitor C _DC2 is connected (i.e. the connection point N1) The other terminal is connected to the terminal N2 on the opposite side.

Coupling reactor L _M comprises a first winding L _MP and the second winding L _MN.

First winding L _MP of coupling reactor L _M includes a first switch group SW1 and a connection point between the first diode D ₁ of the cathode, the first capacitor C _DC1 and the second capacitor C _DC2 It is connected between the connection point P1. Incidentally, the first winding L _MP of coupling reactor L _M, and the opposite side terminal to the side where the first switch group SW1 is connected to the first capacitor C _DC1 and the second capacitor C _DC2 A first inductor _LEP is connected between the connection point P1. Inductance of the first inductor L _EP is set to one sufficiently smaller than the inductance of the first winding L _MP of coupling reactor L _M.

Second winding L _MN of coupling reactor L _M, the anode of the second diode D ₂ and the connection point of the second switch group SW2, the third capacitor C _DC3 and the fourth capacitor C _DC4 It is connected between the connection point N1. Incidentally, the second winding L _MN of coupling reactor L _M, and the opposite side terminal to the side where the second switch group SW2 is connected, the second capacitor C _DC2 and the third capacitor C _DC3 A second inductor _LEN is connected between the connection point N1. Inductance of the second inductor L _EN is set to one sufficiently smaller than the inductance of the second winding L _MN of coupling reactor L _M.

The first switch group SW1 includes a first switching element Q connected to a terminal P2 of the first capacitor C _DC1 opposite to the side to which the second capacitor C _DC2 is connected (that is, the connection point P1). ₁ and a second switching element Q ₂ connected in series to the first switching element Q ₁ . When the first switching element Q ₁ is turned on, the first switching element Q ₁ is switched from the terminal P 2 on the opposite side of the first capacitor C _DC1 to the side to which the second capacitor C _DC2 is connected (ie, the connection point P 1). pass current toward the side of the terminal element Q ₂ is connected. The second switching element Q ₂ is, at the time of ON, from the side of the terminal to which the first switching element Q ₁ is connected, towards the side of the terminal to which the first winding L _MP of coupling reactor L _M is connected Pass current.

The second switch group SW2 includes a third switching element Q ₃ connected to the anode of the second diode D ₂ and a fourth switching element Q ₄ connected in series to the third switching element Q _3. Prepare. Third switching element Q ₃ are, at the time of ON, from the side of the terminal to which the second winding L _MN of coupling reactor L _M is connected, towards the fourth side of the terminal switching element Q ₄ is connected The fourth switching element Q ₄ is connected to the third capacitor C _{DC3 of} the fourth capacitor C _DC4 from the terminal on the side to which the third switching element Q ₃ is connected when the fourth switching element Q ₄ is turned on. A current is supplied to the terminal N2 on the side opposite to the side (that is, the connection point N1).

The third diode D ₃ has a cathode connected to a connection point of the first switching element Q ₁ and the second switching element Q _2, connection between the first capacitor C _DC1 and the second capacitor C _DC2 And an anode connected to the point P1.

The fourth diode D ₄ has an anode connected to a connection point between the _third switching element Q ₃ and the fourth switching element Q _4, and a connection between the second capacitor C _DC2 and the third capacitor C _DC3. And a cathode connected to the point N1.

A current detector (not shown) detects a current flowing through the first inductor _LEP and a current flowing through the second inductor _LEN .

Controller (not shown), when the first switch group SW1 (i.e. first switching element Q ₁ and the second switching element Q ₂₎ the on (conductive), the second switch group SW2 (i.e. When the third switching element Q ₃ and the fourth switching element Q ₄ ) are turned off (opened) and the first switch group SW1 is turned off (opened), the second switch group SW2 is turned on (conductive). Control as follows.

  Next, the operation of the voltage uniform circuit according to the second embodiment of the present invention will be described. The operation of the voltage uniform circuit according to the second embodiment of the present invention applied to the 4-level inverter is an application of the operation of the voltage uniform circuit according to the first embodiment of the present invention applied to the 5-level inverter. Is similar in principle. Here, the basic operation principle of the voltage uniform circuit related to switching of the switching mode will be described. The specific voltage uniformity control and magnetic bias control of the voltage uniformity circuit 2 according to the second embodiment of the present invention are the same as those in the first embodiment of the present invention described above.

  13 and 14 are circuit diagrams for explaining the basic operation principle of the voltage equalizing circuit according to the second embodiment of the present invention. FIG. 13 shows a state in mode A, and FIG. 14 shows a state in mode B. Show.

When turning on (conducting) the first switch group SW1 (ie, the first switching element Q ₁ and the second switching element Q ₂ ), the control unit sets the second switch group SW2 (ie, the third switching element). Control is performed to turn off (open) Q ₃ and the fourth switching element Q ₄ ). The switching state at this time is referred to as mode A, and the current flow at this time is shown in FIG. The control unit, when the first switch group SW1 (i.e. first switching element Q ₁ and the second switching element Q ₂₎ OFF (open), the second switch group SW2 (i.e. third The switching element Q ₃ and the fourth switching element Q ₄ ) are controlled to be turned on (conductive). The switching state at this time is referred to as mode B, and the current flow at this time is shown in FIG.

First, in mode A shown in FIG. 13, since the first switching element Q ₁ and the second switching element Q _2, which are the first switch group SW1, are turned on, the terminal P2 is connected from the first capacitor _CDC1. current i _LP via flows to the first winding L _MP of coupling reactor L _M. The first winding L _MP of coupling reactor L _M if the first inductor L _EP is sufficiently small voltage generated in the first capacitor C _DC1 is applied. This voltage is also generated in the second winding L _MN of coupling reactor L _M by electromagnetic induction. At this time, the second diode D ₂ is it means that the voltage in the forward direction is applied, the current i _LN flows into the third capacitor C _DC3 via the connection point P1. That is, in mode A, the first capacitor C _DC1 is discharged, and the second capacitor C _DC2 is charged by the energy.

On the other hand, in mode B shown in FIG. 14, since the third switching element Q ₃ and the fourth switching element Q _{4, which} are the second switch group SW2, are turned on, the terminal N1 is connected from the third capacitor _CDC3. current i _LN via the flows through the second winding L _MN of coupling reactor L _M. The second winding L _MPN of coupling reactor L _M if the second inductor L _EN is sufficiently small voltage ₁ is applied resulting in the third capacitor C _DC3. This voltage is also induced in the first winding L _MP of coupling reactor L _M by electromagnetic induction. At this time, since the voltage is applied to the first diode D ₁ in the forward direction, the current i _P flows into the second capacitor C _DC2 via the connection point P1. That is, in mode B, the third capacitor C _DC3 is discharged, and the second capacitor C _DC2 is charged by the energy.

When the voltage equalization circuit 2 according to the second embodiment of the present invention is not provided, the two outer capacitors, that is, the first capacitor C _DC1 and the third capacitor C _DC3 are in a charged state, and thus the direct current generated in these capacitors. The voltage rises, and the inner capacitor, that is, the second capacitor _CDC2 is discharged, so that the DC voltage generated in these capacitors is lowered. On the other hand, if the voltage equalization circuit 2 according to the second embodiment of the present invention is applied, the two outer capacitors, that is, the first capacitor C _DC1 and the second capacitor are switched by alternately switching the mode A and the mode B described above. The third capacitor C _DC3 can be discharged and the inner or second capacitor C _DC2 can be charged, thus the first capacitor C _DC1 , the second capacitor C _DC2 and the third capacitor C _DC3. It is possible to equalize (uniformly) each DC voltage generated in each.

  The present invention can be applied to a voltage uniform circuit connected to a 5-level inverter or a 4-level inverter for motor drive. In particular, the present invention can be applied to a large voltage motor drive for industrial use, for example, a voltage uniform circuit connected to a 5-level inverter or a 4-level inverter for a motor drive such as a fan / blower or a compressor.

1 Voltage Uniform Circuit 2 Voltage Uniform Circuit 101 5 Level Inverter 102 Diode Rectifier 104 Induction Motor C _DC1 First Capacitor C _DC2 Second Capacitor C _DC3 Third Capacitor C _DC4 Fourth Capacitor D ₁ First Diode D ₂ 2nd diode D ₃ 3rd diode D ₄ 4th diode L _EP 1st inductor L _EN 2nd inductor L _M coupling reactor L _MP 1st winding L _MN 2nd winding Q ₁ 1st the switching element Q ₂ second switching element Q ₃ the third switching element Q ₄ fourth switching element SW1 first switch group SW2 second switch group

Claims (8)

A voltage equalizing circuit connected to first, second, third and fourth capacitors connected in series for a DC link of a five-level diode clamp type inverter, and uniformly controlling the DC voltage generated in each capacitor. Because
A first switch group connected to a terminal of the first capacitor opposite to the side to which the second capacitor is connected, the first switch group comprising: A first switching element connected to a terminal opposite to the side to which the second capacitor is connected, and a second switching element connected in series to the first switching element. A group of switches ,
The cathode that is connected to a terminal on the opposite side of the first switch group to the side to which the first capacitor is connected, and the inverter that is a connection point between the second capacitor and the third capacitor A first diode having an anode connected to a neutral point of
A second diode having a cathode connected to a connection point between the anode of the first diode and the neutral point;
One terminal is connected to the anode of the second diode, and the other terminal is connected to the terminal of the fourth capacitor opposite to the side to which the third capacitor is connected. The second switch group includes a third switching element connected to the anode of the second diode, and a fourth switching element connected in series to the third switching element. A second switch group comprising:
A coupling reactor comprising a first winding and a second winding, wherein the first winding is a connection point between the first switch group and a cathode of the first diode, and And the second winding is connected between a connection point between the anode of the second diode and the second switch group, and the connection point between the first capacitor and the second capacitor. A coupling reactor connected between a connection point of a third capacitor and the fourth capacitor;
A control unit that controls to turn off the second switch group when turning on the first switch group, and to turn on the second switch group when turning off the first switch group;
The first winding is connected between a terminal opposite to the side to which the first switch group is connected and a connection point between the first capacitor and the second capacitor. A first inductor;
Connected between a terminal of the second winding opposite to the side to which the second switch group is connected, and a connection point between the third capacitor and the fourth capacitor. A second inductor;
A cathode having a cathode connected to a connection point between the first switching element and the second switching element; and an anode connected to a connection point between the first capacitor and the second capacitor. A diode of
A fourth electrode having an anode connected to a connection point between the third switching element and the fourth switching element; and a cathode connected to a connection point between the third capacitor and the fourth capacitor. A diode of
Equipped with a,
When the first switching element is turned on, from the terminal on the opposite side of the first capacitor to the side to which the second capacitor is connected, to the terminal to which the second switching element is connected Pass current through
When the second switching element is on, a current is passed from a terminal on the side to which the first switching element is connected to a terminal on the side to which the first winding is connected,
When the third switching element is on, a current is passed from a terminal on the side to which the second winding is connected toward a terminal on the side to which the fourth switching element is connected,
When the fourth switching element is turned on, from the terminal on the side to which the third switching element is connected to the terminal on the opposite side of the fourth capacitor to the side to which the third capacitor is connected. A voltage uniform circuit characterized by flowing a current toward . The controller controls the on-time of the second switching element to be longer than the on-time of the first switching element when the first switch group is on, and turns on the second switch group. sometimes, voltage-balancing circuit according to claim 1 for controlling so as to be longer than the oN time of the third the on-time of the switching element of the fourth switching element. A current detection unit for detecting a current flowing through the first inductor and a current flowing through the second inductor;
The controller is
When the detected average value of the current flowing through the first inductor is smaller than the detected average value of the current flowing through the second inductor, the first inductor is changed from the current flowing through the second inductor. By performing proportional control using a value obtained by subtracting the flowing current, the ratio between the on-time of the first switching element and the on-time of the second switching element is determined,
When the detected average value of the current flowing through the first inductor is larger than the detected average value of the current flowing through the second inductor, the second inductor is changed from the current flowing through the first inductor. By performing proportional control using a value obtained by subtracting the flowing current, the ratio between the on-time of the third switching element and the on-time of the fourth switching element is determined,
The ratio between the determined ON time of the first switching element and the ON time of the second switching element, and the ON time of the third switching element and the ON time of the fourth switching element. The voltage uniform circuit according to claim 2 , wherein a switching operation of the first switching element, the second switching element, the third switching element, and the fourth switching element is controlled based on a ratio. A positive electrode of a DC power source is connected to a terminal of the first capacitor opposite to the side to which the second capacitor is connected,
The voltage uniform circuit according to any one of claims 1 to 3 , wherein a negative electrode of a DC power source is connected to a terminal of the fourth capacitor opposite to a side to which the third capacitor is connected. . A voltage equalizing circuit connected to first, second and third capacitors connected in series for a DC link of a four-level diode clamp type inverter and uniformly controlling a DC voltage generated in each of the capacitors. ,
A first switch group connected to a terminal of the first capacitor opposite to the side to which the second capacitor is connected, the first switch group comprising: A first switching element connected to a terminal opposite to the side to which the second capacitor is connected, and a second switching element connected in series to the first switching element. A group of switches ,
The first switch group is connected to a cathode connected to a terminal opposite to the side to which the first capacitor is connected, and to a connection point between the second capacitor and the third capacitor. A first diode having an anode;
A second diode having a cathode connected to a connection point between the first capacitor and the second capacitor;
One terminal is connected to the anode of the second diode, and the other terminal is connected to the terminal of the third capacitor opposite to the side to which the second capacitor is connected. The second switch group includes a third switching element connected to the anode of the second diode, and a fourth switching element connected in series to the third switching element. A second switch group comprising:
A coupling reactor comprising a first winding and a second winding, wherein the first winding is a connection point between the first switch group and a cathode of the first diode, and And the second winding is connected between a connection point between the anode of the second diode and the second switch group, and the connection point between the first capacitor and the second capacitor. A coupling reactor connected between a connection point of a second capacitor and the third capacitor;
A control unit that controls to turn off the second switch group when turning on the first switch group, and to turn on the second switch group when turning off the first switch group;
The first winding is connected between a terminal opposite to the side to which the first switch group is connected and a connection point between the first capacitor and the second capacitor. A first inductor;
The second winding is connected between a terminal opposite to the side to which the second switch group is connected and a connection point between the second capacitor and the third capacitor. A second inductor;
A cathode having a cathode connected to a connection point between the first switching element and the second switching element; and an anode connected to a connection point between the first capacitor and the second capacitor. A diode of
A fourth electrode having an anode connected to a connection point between the third switching element and the fourth switching element; and a cathode connected to a connection point between the second capacitor and the third capacitor. A diode of
Equipped with a,
When the first switching element is turned on, from the terminal on the opposite side of the first capacitor to the side to which the second capacitor is connected, to the terminal to which the second switching element is connected Pass current through
When the second switching element is on, a current is passed from a terminal on the side to which the first switching element is connected to a terminal on the side to which the first winding is connected,
When the third switching element is on, a current is passed from a terminal on the side to which the second winding is connected toward a terminal on the side to which the fourth switching element is connected,
When the fourth switching element is turned on, from the terminal on the side to which the third switching element is connected to the terminal on the opposite side of the fourth capacitor to the side to which the third capacitor is connected. A voltage uniform circuit characterized by flowing a current toward . The controller controls the on-time of the second switching element to be longer than the on-time of the first switching element when the first switch group is on, and turns on the second switch group. 6. The voltage equalization circuit according to claim 5 , wherein sometimes the on-time of the third switching element is controlled to be longer than the on-time of the fourth switching element. A current detection unit for detecting a current flowing through the first inductor and a current flowing through the second inductor;
The controller is
When the detected average value of the current flowing through the first inductor is smaller than the detected average value of the current flowing through the second inductor, the first inductor is changed from the current flowing through the second inductor. By performing proportional control using a value obtained by subtracting the flowing current, the ratio between the on-time of the first switching element and the on-time of the second switching element is determined,
When the detected average value of the current flowing through the first inductor is larger than the detected average value of the current flowing through the second inductor, the second inductor is changed from the current flowing through the first inductor. By performing proportional control using a value obtained by subtracting the flowing current, the ratio between the on-time of the third switching element and the on-time of the fourth switching element is determined,
The ratio between the determined ON time of the first switching element and the ON time of the second switching element, and the ON time of the third switching element and the ON time of the fourth switching element. The voltage uniform circuit according to claim 6 , wherein a switching operation of the first switching element, the second switching element, the third switching element, and the fourth switching element is controlled based on a ratio. A positive electrode of a DC power source is connected to a terminal of the first capacitor opposite to the side to which the second capacitor is connected,
The voltage uniform circuit according to any one of claims 5 to 7 , wherein a negative electrode of a DC power source is connected to a terminal of the third capacitor opposite to a side to which the second capacitor is connected. .

Images