JP5473397B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

Info

Publication number
JP5473397B2
JP5473397B2 JP2009117333A JP2009117333A JP5473397B2 JP 5473397 B2 JP5473397 B2 JP 5473397B2 JP 2009117333 A JP2009117333 A JP 2009117333A JP 2009117333 A JP2009117333 A JP 2009117333A JP 5473397 B2 JP5473397 B2 JP 5473397B2
Authority
JP
Japan
Prior art keywords
region
ion implantation
type
conductivity type
drift layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2009117333A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010267762A (ja
JP2010267762A5 (ko
Inventor
健一 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2009117333A priority Critical patent/JP5473397B2/ja
Publication of JP2010267762A publication Critical patent/JP2010267762A/ja
Publication of JP2010267762A5 publication Critical patent/JP2010267762A5/ja
Application granted granted Critical
Publication of JP5473397B2 publication Critical patent/JP5473397B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/047Making n or p doped regions or layers, e.g. using diffusion using ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608Silicon carbide

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2009117333A 2009-05-14 2009-05-14 半導体装置およびその製造方法 Active JP5473397B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009117333A JP5473397B2 (ja) 2009-05-14 2009-05-14 半導体装置およびその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009117333A JP5473397B2 (ja) 2009-05-14 2009-05-14 半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
JP2010267762A JP2010267762A (ja) 2010-11-25
JP2010267762A5 JP2010267762A5 (ko) 2011-12-22
JP5473397B2 true JP5473397B2 (ja) 2014-04-16

Family

ID=43364498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009117333A Active JP5473397B2 (ja) 2009-05-14 2009-05-14 半導体装置およびその製造方法

Country Status (1)

Country Link
JP (1) JP5473397B2 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108604552A (zh) * 2015-12-02 2018-09-28 Abb瑞士股份有限公司 半导体装置以及用于制造这种半导体装置的方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013161420A1 (ja) * 2012-04-24 2013-10-31 富士電機株式会社 縦型高耐圧半導体装置およびその製造方法
WO2016084141A1 (ja) * 2014-11-26 2016-06-02 株式会社日立製作所 半導体スイッチング素子および炭化珪素半導体装置の製造方法
JP6479615B2 (ja) 2015-09-14 2019-03-06 株式会社東芝 半導体装置の製造方法
JP2017063079A (ja) * 2015-09-24 2017-03-30 住友電気工業株式会社 炭化珪素半導体装置およびその製造方法
WO2017081935A1 (ja) 2015-11-12 2017-05-18 三菱電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
JP6454447B2 (ja) 2015-12-02 2019-01-16 アーベーベー・シュバイツ・アーゲー 半導体装置の製造方法
JP7081087B2 (ja) * 2017-06-02 2022-06-07 富士電機株式会社 絶縁ゲート型半導体装置及びその製造方法
JP6592119B2 (ja) * 2018-01-25 2019-10-16 株式会社日立製作所 半導体スイッチング素子および炭化珪素半導体装置の製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3959856B2 (ja) * 1998-07-31 2007-08-15 株式会社デンソー 炭化珪素半導体装置及びその製造方法
JP2007019146A (ja) * 2005-07-06 2007-01-25 Toshiba Corp 半導体素子
JP4627272B2 (ja) * 2006-03-09 2011-02-09 三菱電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
JP2009302436A (ja) * 2008-06-17 2009-12-24 Denso Corp 炭化珪素半導体装置の製造方法
JP5405089B2 (ja) * 2008-11-20 2014-02-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108604552A (zh) * 2015-12-02 2018-09-28 Abb瑞士股份有限公司 半导体装置以及用于制造这种半导体装置的方法
CN108604552B (zh) * 2015-12-02 2022-03-22 日立能源瑞士股份公司 半导体装置以及用于制造这种半导体装置的方法

Also Published As

Publication number Publication date
JP2010267762A (ja) 2010-11-25

Similar Documents

Publication Publication Date Title
JP5473397B2 (ja) 半導体装置およびその製造方法
JP7182594B2 (ja) ゲート・トレンチと、埋め込まれた終端構造とを有するパワー半導体デバイス、及び、関連方法
JP6475635B2 (ja) ゲート酸化膜層において電界を低下させた半導体デバイス
JP6177812B2 (ja) 絶縁ゲート型炭化珪素半導体装置及びその製造方法
JP5034315B2 (ja) 半導体装置及びその製造方法
JP7190144B2 (ja) 超接合炭化珪素半導体装置および超接合炭化珪素半導体装置の製造方法
JP5592997B2 (ja) 半導体素子およびその製造方法
JP2008294214A (ja) 半導体装置
JP6099749B2 (ja) 炭化珪素半導体装置およびその製造方法
JP2009289904A (ja) 半導体装置
JP5790573B2 (ja) 炭化珪素半導体装置およびその製造方法
JP2008211178A (ja) 電流抑制層を備える絶縁ゲート・バイポーラ・トランジスタ
JP2008258443A (ja) 電力用半導体素子及びその製造方法
JP6802454B2 (ja) 半導体装置およびその製造方法
JP2019003967A (ja) 半導体装置および半導体装置の製造方法
JP5473398B2 (ja) 半導体装置およびその製造方法
JP6571467B2 (ja) 絶縁ゲート型スイッチング素子とその製造方法
JP5676923B2 (ja) 半導体装置の製造方法および半導体装置
JP6463506B2 (ja) 炭化珪素半導体装置
JPWO2013161116A1 (ja) 半導体装置及びその製造方法
JP2019079833A (ja) スイッチング素子とその製造方法
JP2017195224A (ja) スイッチング素子
WO2019186785A1 (ja) 炭化珪素半導体装置およびその製造方法
JP6211933B2 (ja) 半導体装置
KR20130119873A (ko) 파워 소자 및 그 제조방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111109

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20111109

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130808

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130820

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131016

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140107

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140204

R150 Certificate of patent or registration of utility model

Ref document number: 5473397

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250