JP5464981B2 - AC / DC converter - Google Patents

Description

  The present invention relates to an AC / DC converter, and more particularly to a technique for detecting a zero cross and generating a gate signal.

  The AC / DC converter is composed of a plurality of rectifier elements configured in a bridge shape, and controls the thyristor gate of the plurality of rectifier elements in accordance with the phase of the line voltage in the input AC power. It is a device that converts power into DC power. In order to obtain this phase, the control unit of the AC / DC converter detects a point where 0 V is crossed (hereinafter referred to as zero cross) from the line voltage of the input AC power, and the time interval of the zero cross is determined as the input voltage. The phase of the gate signal for turning on the gate of the thyristor is calculated, and the gate signal is output to the thyristor. In this way, the phases of the R-phase gate signal, the S-phase gate signal, and the T-phase gate signal are calculated, and each of the thyristors is ignited and controlled on / off by these gate signals. Converted to DC power.

  Such an AC / DC converter is provided with a low-pass filter to remove harmonic noise. However, in the low-pass filter, the impedance becomes high due to a long wiring or the like, the influence of the low-order high frequency cannot be ignored, and the zero cross may not be detected accurately. Therefore, an AC / DC converter provided with a notch filter instead of a low-pass filter is known (see Patent Document 1). According to this AC / DC converter, it is possible to detect the zero cross based on the input AC voltage of only the fundamental wave from which the harmonic of the specific order is removed by the notch filter. Therefore, the phase of the gate signal can be accurately calculated without being affected by the low-order high frequency, and the gate signal having an appropriate phase can be output to the thyristor.

Japanese Patent Laid-Open No. 11-32483

  However, even in the AC / DC converter provided with the low-pass filter and the AC / DC converter provided with the notch filter of Patent Document 1, disturbance is generated due to external factors such as noise and instantaneous power failure, and the input When the AC voltage is affected, these filters cannot remove the disturbance. For this reason, the control unit of the AC / DC converter erroneously detects a zero cross and calculates an inaccurate input voltage cycle. As a result, there has been a problem that the phase of the gate signal cannot be calculated correctly, and the thyristor is controlled to be turned on / off with an incorrect phase contrary to the intention. This is because the control unit does not determine whether or not the zero cross has been erroneously detected, and the phase of the gate signal is determined based on the time of the zero cross that is erroneously detected due to a disturbance, regardless of the line voltage on the input side. It is because it is calculated.

  If such a disturbance occurs during the precharge operation, the fuse may be blown and the rectifying element may be damaged. Also, when such disturbances occur during steady operation (full fire operation: high load), the output bus voltage of the AC / DC converter becomes low, and an instantaneous power failure is erroneously detected. If it is provided, the inverter may stop operating. Here, the precharge operation refers to an operation for raising the output bus voltage of the AC / DC converter from a value of 0 V to a predetermined voltage value. The steady operation (full fire operation) is an operation after the precharge operation, that is, an operation after the output bus voltage has increased to a predetermined voltage value.

  Therefore, the present invention has been made to solve the above-mentioned problems, and its purpose is to calculate the phase of the gate signal so as not to be directly affected by disturbances due to noise, instantaneous power failure, etc. An object of the present invention is to provide an AC / DC converter capable of on / off control.

In order to achieve the above object, an AC / DC converter according to the present invention detects a zero cross at a point where 0V is crossed from the voltage of an AC power supply, and detects a zero cross detection signal from a zero cross detection signal indicating a timing at which the zero cross is detected. In an AC / DC converter that calculates a period, generates a gate signal based on the period, controls on / off of a thyristor based on the gate signal, and converts AC power of the AC power source into DC power, Based on the line voltage converted by the phase voltage / line voltage conversion unit and the phase voltage / line voltage conversion unit for inputting the voltage and converting the phase voltage to the line voltage, Based on the zero-cross detection unit that generates the zero-cross detection signal and the zero-cross detection signal generated by the zero-cross detection unit, An input voltage cycle calculation unit for calculating an input voltage cycle indicating the cycle of the input phase voltage, and a cycle upper limit value and a cycle lower limit value are set based on the input voltage cycle calculated by the input voltage cycle calculation unit. A model phase that increments from a lower limit value setting unit and a value of 0 is generated, and the input voltage cycle calculated by the input voltage cycle calculation unit is greater than the cycle lower limit value set by the cycle upper and lower limit value setting unit When the zero-cross detection signal is input from the zero-cross detection unit, or when the zero-cross detection signal is not input, the model phase is larger than the cycle upper limit set by the cycle upper / lower limit setting unit If the model phase zero-cross detector for generating a model phase zero-cross detection signal resets the model phase to a value of 0, the model Based on the model phase zero cross detection signal generated by the phase zero cross detection unit, a model phase period calculation unit that calculates a model phase period indicating the period of the model phase, and a model phase period calculated by the model phase period calculation unit And a gate signal generation unit that generates a gate signal.

  In the AC / DC converter according to the present invention, the period upper and lower limit value setting unit is an average of input voltage periods calculated when the AC / DC converter is not operating when the AC / DC converter does not perform processing for converting AC power to DC power. Calculate a value, set a cycle upper limit value and a cycle lower limit value based on the average value, the model phase cycle calculation unit, based on the model phase zero cross detection signal generated by the model phase zero cross detection unit, A model phase period indicating a model phase period is calculated, an average value of the model phase period is calculated, and the gate signal generation unit is based on the average value of the model phase period calculated by the model phase period calculation unit. A gate signal is generated.

  In the AC / DC converter according to the present invention, the zero cross detection unit, the input voltage cycle calculation unit, the cycle upper and lower limit value setting unit, the model phase zero cross detection unit, the model phase cycle calculation unit, and the gate signal generation unit include the AC power source. The R-phase, S-phase, and T-phase thyristors are respectively turned on / off by the respective gate signals generated by the gate signal generator. Features.

  As described above, according to the present invention, the model phase zero cross detection is performed in which the cycle lower limit value and cycle upper limit value of the input voltage cycle in the line voltage are set and the time interval between the cycle lower limit value and the cycle upper limit value is set. A signal is generated, a model phase period which is a time interval of the model phase zero-cross detection signal is calculated, and a gate signal for on / off control of the thyristor is generated based on the model phase period. As a result, the model phase zero cross detection signal and the model phase period are not directly affected by disturbance due to noise, instantaneous power failure, or the like. Therefore, the phase of the gate signal can be calculated and the thyristor can be controlled on / off so as not to be directly affected by such disturbance. As a result, stable operation of the AC / DC converter can be realized.

It is a block diagram which shows the whole structure of the power supply device with which the AC / DC converter by embodiment of this invention is used. It is a block diagram which shows the structure of the control part with which the AC / DC converter by embodiment of this invention was equipped. It is a figure explaining the relationship between a phase voltage and a line voltage. It is a block diagram which shows the structure of a gate signal processing part. It is a block diagram which shows the structure of a zero cross detection part. It is a block diagram which shows the structure of an input voltage period calculation part. It is a block diagram which shows the structure of a period upper / lower limit value setting part. It is a block diagram which shows the structure of a model phase zero cross detection part. It is a block diagram which shows the structure of a model phase period calculation part. It is a block diagram which shows the structure of a gate signal production | generation part. It is a flowchart explaining the process of a model phase zero cross detection part. It is a time chart explaining operation | movement of a model phase zero cross detection part. It is a time chart explaining operation | movement of a gate signal production | generation part.

The best mode for carrying out the present invention will be described below with reference to the drawings.
The AC / DC converter according to the present invention is characterized in that the zero cross is detected from the line voltage of the input AC power and the input voltage cycle is calculated, so that the phase of the gate signal is not calculated, but the actually detected zero cross. The upper and lower limit values of the input voltage cycle are calculated from the model, the model phase zero cross is detected so that it falls within this upper and lower limit value using the actually detected zero cross, and the phase of the gate signal is calculated by calculating the model phase cycle. Is to calculate. As a result, even if the AC / DC converter is affected by disturbance due to noise, instantaneous power failure, etc., the zero-crossing is detected at an incorrect timing and the input voltage cycle fluctuates greatly, the model phase zero-crossing is within the predetermined upper and lower limit values. It does not fluctuate greatly. Therefore, the phase of the gate signal that is not directly affected by the disturbance can be calculated, and the thyristor can be controlled on / off.

[Power supply unit]
FIG. 1 is a block diagram showing an overall configuration of a power supply device in which an AC / DC converter according to an embodiment of the present invention is used. This power supply device includes a reactor 2, an AC / DC converter 5, and an inverter 6, and once converts commercial AC power input from the AC power source 1 into DC power, and converts DC power into AC power having a predetermined frequency. Then, AC power is supplied to the motor 7 as drive power.

  The reactor 2 is connected in series to the wiring of each RST phase between the AC power source 1 and the AC / DC converter 5 for energy control of the power supply device. The AC / DC converter 5 includes a control unit 3 and a power element 4. The control unit 3 inputs the phase voltages VR and VS on the output side of the reactor 2, detects the zero cross, calculates the input voltage cycle, calculates the phase of the gate signal, and calculates each of the GR signal, the GS signal, and the GT signal. A gate signal is generated and output to the power element 4. Details of the control unit 3 will be described later. The power element 4 includes six rectifier elements configured in a bridge shape, and the three rectifier elements connected to the DC bus on the P side which is the output side are thyristors. The gates of these three thyristors (R-phase thyristor, S-phase thyristor, and T-phase thyristor) are supplied with the gate signals of the GR signal, the GS signal, and the GT signal from the control unit 3, and are turned on / off. DC power is output from the power element 4 by the control.

  Here, the phase voltage VR is an R-phase voltage, and the phase voltage VS is an S-phase voltage. The GR signal is a gate signal for turning on / off the gate of the R-phase thyristor, the GS signal is a gate signal for turning on / off the gate of the S-phase thyristor, and the GT signal is This is a gate signal for turning on / off the gate of the T-phase thyristor. A phase voltage VT described later is a T-phase voltage, line voltages Vrs and Vsr are voltages between the phase voltage VR and the phase voltage VS, and line voltages Vrt and Vtr are the phase voltage VR and the phase voltage. The line voltages Vst and Vts are voltages between the phase voltage VS and the phase voltage VT.

  The inverter 6 receives DC power from the AC / DC converter 5, converts it to AC power having a predetermined frequency, and supplies it to the motor 7 as drive power. Here, the inverter 6 has two pairs of rectifying elements facing each other, for example, a pair of IGBTs, whose conduction / shutoff between the collector and the emitter is controlled by a control signal input to the gate thereof, and the on / off operation of the rectifying element By repeating the above, the input DC power is converted into AC power having a rectangular wave AC waveform voltage.

[AC / DC converter controller]
Next, the AC / DC converter 5 according to the embodiment of the present invention will be described in detail. FIG. 2 is a block diagram showing a configuration of the control unit 3 provided in the AC / DC converter 5 shown in FIG. The control unit 3 includes an A / D conversion unit 11, a filter 12, a phase voltage / line voltage conversion unit 13, and gate signal processing units 14-1, 14-2, 14-3. The phase voltages VR and VS are input via the reactor 2, and a GR signal, a GS signal, and a GT signal, which are gate signals for turning on / off the thyristor of the power element 4, are generated and output to the power element 4.

  The A / D converter 11 receives the phase voltages VR and VS, converts the analog signal phase voltages VR and VS into digital signals, and outputs the digital signal phase voltages VR and VS to the filter 12. The filter 12 receives the phase voltages VR and VS of the digital signal from the A / D converter 11 and removes high frequency noise.

The phase voltage / line voltage converter 13 receives the phase voltages VR and VS from which the high frequency has been removed from the filter 12, and converts the phase voltages VR and VS into line voltages Vrs, Vrt, Vsr, Vst, Vts, and Vtr. The line voltages Vrs, Vrt are output to the gate signal processing unit 14-1, the line voltages Vsr, Vst are output to the gate signal processing unit 14-2, and the line voltages Vts, Vtr are output to the gate signal processing unit 14. To -3. Specifically, the phase voltage / line voltage converter 13 performs conversion according to the following equation.
Vrs = VR-VS, Vrt = VR-VT, Vsr = VS-VR, Vst = VS-VT, Vts = VT-VS, Vtr = VT-VR

  FIG. 3 is a diagram for explaining the relationship between the phase voltages VR, VS, and VT and the line voltages Vrs, Vrt, Vsr, Vst, Vts, and Vtr. As shown in FIG. 3, since the phase voltages VR, VS, and VT are three-phase voltages, the phases are shifted by 120 degrees. The line voltages Vrs, Vsr, line voltages Vrt, Vtr, line voltages Vst, Vts are 180 degrees out of phase, and the line voltages Vrs, Vrt, Vst, Vsr, Vtr, Vts are in this order. Are out of phase by 60 degrees.

  Returning to FIG. 2, the gate signal processing unit 14-1 receives the line voltages Vrs and Vrt from the phase voltage / line voltage conversion unit 13, and the AC / DC converter 5 converts AC power into DC power. When the operation is not performed, the zero phase crossing of the R phase voltage (R phase zero crossing) is detected based on the line voltages Vrs and Vrt, the R phase input voltage cycle is calculated, and the input voltage cycle upper and lower limits Calculate the value. Then, when the AC / DC converter 5 performs processing for converting AC power into DC power, the R phase zero cross is detected based on the line voltages Vrs and Vrt, and the detected R phase zero cross is used. Then, the model phase zero cross is detected so as to be within the calculated upper and lower limit values, the model phase period is calculated, and the GR signal which is a gate signal is generated and output to the power element 4. Details of the gate signal processing unit 14-1 will be described later.

  The gate signal processing unit 14-2 receives the line voltages Vsr and Vst from the phase voltage / line voltage conversion unit 13, performs the same processing as the gate signal processing unit 14-1, and outputs a GS signal which is a gate signal. Generated and output to the power element 4. The gate signal processing unit 14-3 receives the line voltages Vts and Vtr from the phase voltage / line voltage conversion unit 13, performs the same processing as the gate signal processing units 14-1 and 14-2, and generates a gate signal. A certain GT signal is generated and output to the power element 4.

[Gate signal processor]
Next, the gate signal processing units 14-1, 14-2, 14-3 of the control unit 3 shown in FIG. 2 will be described in detail. FIG. 4 is a block diagram illustrating a configuration of the gate signal processing unit 14-1. The configuration of the gate signal processing units 14-2 and 14-3 is the same as that of the gate signal processing unit 14-1 shown in FIG. The gate signal processing unit 14-1 includes a zero-cross detection unit 21, an input voltage cycle calculation unit 22, a cycle upper and lower limit setting unit 23, a model phase zero-cross detection unit 24, a model phase cycle calculation unit 25, and a gate signal generation unit 26. I have.

(Zero cross detector)
The zero cross detector 21 receives the line voltages Vrs and Vrt from the phase voltage / line voltage converter 13, detects the R phase zero cross based on the line voltages Vrs and Vrt, and detects the zero cross at the detected timing. The signal is output to the input voltage period calculation unit 22 and the model phase zero cross detection unit 24.

  FIG. 5 is a block diagram showing a configuration of the zero cross detection unit 21. The zero cross detection unit 21 includes a selection circuit 31 and a detection circuit 32. The selection circuit 31 receives the line voltages Vrs and Vrt from the phase voltage / line voltage converter 13 and sets the line voltage Vrs as a positive voltage signal when current flows from the R phase to the S phase, and R The line voltage Vrt, which is a positive voltage signal when a current flows from the phase to the T phase, is compared, and a large line voltage is selected and output to the detection circuit 32. As a result, the line voltage selected by the selection circuit 31 is a voltage for detecting the zero-cross of the R phase that is not influenced by the phase order.

  The detection circuit 32 receives the larger line voltage of the line voltages Vrs and Vrt from the selection circuit 31, detects an upshot in which the line voltage shifts from a negative value to a value of 0 or more, An edge-shaped zero cross detection signal is output to the input voltage period calculation unit 22 and the model phase zero cross detection unit 24 at the detected timing. This up shot is the R phase zero cross.

(Input voltage cycle calculator)
The input voltage cycle calculation unit 22 inputs a zero cross detection signal from the zero cross detection unit 21 at the timing when the zero cross is detected, and inputs the zero cross detection based on a counter value to which a predetermined value is added every execution cycle of one scan. The time difference between the signals is calculated, and the time difference is output to the period upper / lower limit setting unit 23 and the model phase zero-cross detection unit 24 as an R-phase input voltage period. This input voltage cycle is a cycle of the R phase in the AC power source 1 and is updated every time a zero-cross detection signal is input.

  FIG. 6 is a block diagram illustrating a configuration of the input voltage cycle calculation unit 22. The input voltage cycle calculation unit 22 includes a counter 41, transfer circuits 42-1, 42-2, and a difference circuit 43. The counter 41 adds 1 to the count value every 50 μs that is the execution period of one scan in the input voltage period calculation unit 22, and outputs the count value of the addition result to the transfer circuit 42-1 and the difference circuit 43. The transfer circuit 42-1 receives the count value from the counter 41, the zero-cross detection signal from the zero-cross detection unit 21, and the timing at which the zero-cross detection signal is input at the input voltage cycle. To the difference circuit 43. This input voltage cycle is a cycle calculated in the previous scan, and is used to calculate the input voltage cycle of the current scan.

  The difference circuit 43 inputs the count value from the counter 41, inputs the input voltage cycle calculated in the previous scan from the transfer circuit 42-1, subtracts the input voltage cycle calculated in the previous scan from the count value, and subtracts it. The result (the elapsed time from the timing of the zero cross detection signal input in the previous scan) is output to the transfer circuit 42-2. The transfer circuit 42-2 receives an elapsed time as a subtraction result from the difference circuit 43, inputs a zero-cross detection signal from the zero-cross detection unit 21, and inputs the zero-cross detection signal at the timing input at that time. The time is output to the period upper and lower limit setting unit 23 as the input voltage period of the current scan. In this way, the R phase period in the AC power supply 1 is calculated as the input voltage period.

(Cycle upper / lower limit setting part)
The cycle upper / lower limit setting unit 23 receives an input voltage cycle from the input voltage cycle calculation unit 22 when the AC / DC converter 5 is turned off, calculates an average value of a plurality of input voltage cycles, and outputs a predetermined value. The coefficient is multiplied to set a cycle lower limit value L_LMT and a cycle upper limit value P_LMT, which are output to the model phase zero cross detector 24. The cycle lower limit value L_LMT and the cycle upper limit value P_LMT are used as conditions for detecting the model phase zero cross in the model phase zero cross detection unit 24. Further, the cycle lower limit value L_LMT and the cycle upper limit value P_LMT are set when the AC / DC converter 5 is not operating and are not set when the operation is on. When the operation is turned on, the phase voltages VR and VS may be affected by disturbances due to noise, instantaneous power failure, etc., but when the operation is turned off, the phase voltages VR and VS which are not affected by such influence are controlled. This is because the zero cross at the correct timing is detected by being input to the unit 3, and the cycle lower limit value L_LMT and the cycle upper limit value P_LMT are set by the correct input voltage cycle. Thereby, the cycle lower limit L_LMT and the cycle upper limit P_LMT that are not affected by disturbance due to noise, instantaneous power failure, or the like can be set.

  FIG. 7 is a block diagram showing a configuration of the cycle upper / lower limit value setting unit 23. The cycle upper / lower limit setting unit 23 includes an average calculation circuit 51 and multiplication circuits 52 and 53. The average calculation circuit 51 receives the input voltage cycle from the input voltage cycle calculation unit 22, stores the input voltage cycle in the shift register, adds the latest N input voltage cycles stored in the shift register, and divides by N Then, the average value of the input voltage period is obtained and output to the multiplication circuits 52 and 53.

  The multiplication circuit 52 receives the input voltage cycle average value from the average calculation circuit 51, multiplies the input voltage cycle average value by 0.9 to calculate 90% of the value, and sets the cycle lower limit value L_LMT to the model phase zero cross. Output to the detector 24. The multiplier circuit 53 receives the input voltage cycle average value from the average calculation circuit 51, multiplies the input voltage cycle average value by 1.1 to calculate 110% of the value, and sets the cycle upper limit value P_LMT to the model phase zero cross. Output to the detector 24.

(Model phase zero cross detector)
The model phase zero-cross detection unit 24 receives a zero-cross detection signal from the zero-cross detection unit 21, an input voltage cycle from the input voltage cycle calculation unit 22, and a cycle lower limit value L_LMT and a cycle upper limit value P_LMT from the cycle upper and lower limit setting unit 23, respectively. A counter value (model phase) that adds a predetermined value for each execution period of one scan is generated, the counter value is reset under a predetermined condition to detect an R-phase model phase zero cross, and the detected model phase zero cross At this timing, the model phase zero cross detection signal is output to the model phase period calculation unit 25 and the gate signal generation unit 26. Here, the model phase zero-cross detection unit 24 does not reset the model phase even if the zero-cross detection signal is input when the input voltage cycle is equal to or lower than the cycle lower limit value L_LMT. Further, when the zero cross detection signal is input when the input voltage cycle is larger than the cycle lower limit value L_LMT and smaller than the cycle upper limit value P_LMT, the model phase is reset. Further, when the input voltage cycle becomes the cycle upper limit value P_LMT (when the model phase becomes the cycle upper limit value P_LMT), the model phase is reset.

  FIG. 8 is a block diagram showing the configuration of the model phase zero-cross detection unit 24. The model phase zero-cross detector 24 includes an adder circuit 61, a selector circuit 62, comparison circuits 64-1, 64-2, and 68, an AND circuit 65, an OR circuit 66, and an inverting circuit 67. The addition circuit 61 inputs the model phase of the previous scan from the selection circuit 62, adds 1 to the model phase, and outputs the model phase of the addition result to the selection circuit 62.

  The selection circuit 62 receives the model phase from the adder circuit 61, receives the reset signal from the AND circuit 65 and the comparison circuit 64-2, and receives the control signal from the inverting circuit 67. When both reset signals are not input and the control signal is input, the selection circuit 62 outputs the input model phase as it is to the comparison circuit 68 and also adds the addition circuit 61 and the comparison as the model phase of the previous scan. Output to the circuit 64-2. Here, the control signal is input as a 1 signal when both reset signals are 0. Details will be described later. The selection circuit 62 resets the model phase at the timing when any one of the reset signals is input, and outputs the model phase having a value of 0 to the comparison circuit 68, the addition circuit 61, and the comparison circuit 64-2.

  The comparison circuit 64-1 receives an input voltage cycle from the input voltage cycle calculation unit 22, inputs a cycle lower limit value L_LMT from the cycle upper and lower limit setting unit 23, compares the input voltage cycle and the cycle lower limit value L_LMT, When the input voltage cycle is larger than the cycle lower limit value L_LMT, a control signal is output to the AND circuit 65. The AND circuit 65 receives a zero-cross detection signal from the zero-cross detection unit 21, inputs a control signal of 1 from the comparison circuit 64-1, performs an AND operation, and outputs a reset signal to the selection circuit 62 when the operation result is 1. Output. As a result, the zero cross detection signal is output as a reset signal to the selection circuit 62 when the input voltage cycle is larger than the cycle lower limit value L_LMT, and the model phase is reset in the selection circuit 62.

  The comparison circuit 64-2 inputs the cycle upper limit value P_LMT from the cycle upper / lower limit value setting unit 23, and receives the model phase of the previous scan from the selection circuit 62. Then, the comparison circuit 64-2 multiplies the model phase by the time per count (the time per scan in which 1 is added in the addition circuit 61), and converts the model phase into the model phase of the time information. The model phase is compared with the period upper limit value P_LMT, and when the model phase is larger than the period upper limit value P_LMT, a reset signal is output to the selection circuit 62 and the OR circuit 66. Thereby, when the model phase becomes larger than the cycle upper limit value P_LMT, that is, when the model phase exceeds the cycle upper limit value P_LMT, the zero cross detection signal is detected as the reset signal. Assuming that the signal is output to the selection circuit 62, the model phase is reset in the selection circuit 62.

  The OR circuit 66 receives a reset signal from the AND circuit 65, receives a reset signal from the comparison circuit 64-2, performs an OR operation, and outputs a control signal to the inversion circuit 67 when the operation result is 1. The inverting circuit 67 receives the control signal from the OR circuit 66, inverts the control signal, and outputs it to the selection circuit 62. Thereby, one control signal from the inverting circuit 67 is output to the selection circuit 62 when neither the reset signal from the AND circuit 65 nor the reset signal from the comparison circuit 64-2 is present. The input model phase is output as it is.

  The comparison circuit 68 inputs the model phase from the selection circuit 62, compares the model phase with 0, and when the model phase is 0, calculates the model phase period using the edge-like signal as the R-phase model phase zero-cross detection signal. To the unit 25 and the gate signal generator 26.

  FIG. 11 is a flowchart for explaining the processing of the model phase zero-cross detection unit 24. When the zero-cross detection signal is input (step S1101: Y), the model phase zero-cross detection unit 24 resets the model phase when the input voltage cycle is larger than the cycle lower limit L_LMT (step S1102: Y) (step S1103). ), A model phase zero cross detection signal is output (step S1104).

  Further, when a zero-cross detection signal is input (step S1101: Y), the model phase zero-cross detection unit 24 receives the next zero-cross detection signal when the input voltage cycle is not greater than the cycle lower limit L_LMT (step S1102: N). And wait until the model phase exceeds the period upper limit P_LMT.

  Further, when the model phase zero-cross detection unit 24 does not receive a zero-cross detection signal (step S1101: N), when the model phase becomes larger than the cycle upper limit value P_LMT (step S1105: Y), the model phase is detected. Reset (step S1103) and output a model phase zero cross detection signal (step S1104).

  When the model phase zero-cross detection unit 24 does not receive a zero-cross detection signal (step S1101: N), and the model phase is not greater than the cycle upper limit value P_LMT (step S1105: N), Wait for input and wait for the model phase to exceed the period upper limit P_LMT.

  FIG. 12 is a time chart for explaining the operation of the model phase zero cross detector 24. As shown in a, b, f, and g of FIG. 12, when the input voltage cycle is larger than the cycle lower limit value L_LMT at the input timing of the zero cross detection signal, the model phase is reset and the model phase zero cross detection signal is output. (Step S1101: Y, Step S1102: Y, Step S1103, Step S1104). As shown in c and d, when the input voltage cycle is not larger than the cycle lower limit L_LMT at the input timing of the zero cross detection signal, the zero cross detection signal is ignored and the model phase is not reset (step S1101: Y , Step S1102: N). As shown in e, when the model phase becomes larger than the cycle upper limit value P_LMT, that is, when the zero-cross detection signal is not detected even if the model phase becomes larger than the cycle upper limit value P_LMT, the model phase is reset. Then, a model phase zero cross detection signal is output (step S1101: N, step S1105: Y, step S1103, step S1104).

  According to FIG. 12, when the timing of the zero cross detection signal generated based on the input voltage from the AC power supply 1 is compared with the timing of the model phase zero cross detection signal generated based on the model phase, at the time points c and d. The zero cross detection signal is erroneously detected due to the influence of disturbance due to noise, instantaneous power failure, or the like. On the other hand, the model phase zero cross detection signal is not affected by disturbance and is not detected erroneously.

  Further, according to FIG. 12, the timing of the model phase zero cross detection signal varies at the time interval between the cycle lower limit value L_LMT and the cycle upper limit value P_LMT, and Δt2 <Δt <Δt1. However, as will be described later, since the model phase period calculation unit 25 calculates the average value of the model phase period, the variation in the timing of the model phase zero cross detection signal is absorbed in the processing of the model phase period calculation unit 25. Become. Note that Δt is the time between timings of the model phase zero-cross detection signal, and is strictly different in each section.

(Model phase period calculator)
Returning to FIG. 4, the model phase cycle calculation unit 25 inputs the model phase zero cross detection signal from the model phase zero cross detection unit 24 at the timing when the model phase zero cross is detected, and adds a predetermined value every execution cycle of one scan. Calculate the time difference between the input model phase zero-cross detection signals based on the counter value to be set, set the time difference to the model phase period of the R phase, calculate the average value of multiple model phase periods, and calculate the model phase period average The value is output to the gate signal generation unit 26. This model phase period average value is updated every time a model phase zero-cross detection signal is input.

  FIG. 9 is a block diagram illustrating a configuration of the model phase period calculation unit 25. The model phase period calculation unit 25 includes a counter 71, transfer circuits 72-1 and 72-2, a difference circuit 73, and an average calculation circuit 74. The counter 71 adds 1 to the count value every 50 μs that is the execution period of one scan in the model phase period calculation unit 25, and outputs the count value of the addition result to the transfer circuit 72-1 and the difference circuit 73. The transfer circuit 72-1 receives the count value from the counter 71, inputs the model phase zero cross detection signal from the model phase zero cross detection unit 24, and inputs the model phase zero cross detection signal at that time. The count value is output to the difference circuit 73 as a model phase period. This model phase period is a period calculated in the previous scan, and is used to calculate the model phase period of the current scan.

  The difference circuit 73 inputs the count value from the counter 71, inputs the model phase period calculated in the previous scan from the transfer circuit 72-1, subtracts the model phase period calculated in the previous scan from the count value, and subtracts it. The result (the elapsed time from the timing of the model phase zero-cross detection signal input in the previous scan) is output to the transfer circuit 72-2. The transfer circuit 72-2 receives the elapsed time as a subtraction result from the difference circuit 73, inputs the model phase zero cross detection signal from the model phase zero cross detection unit 24, and inputs the model phase zero cross detection signal at that time. The elapsed time input to is output to the average arithmetic circuit 74 as the model phase period of the current scan. The average arithmetic circuit 74 receives the model phase period from the transfer circuit 72-2, stores the model phase period in the shift register, adds the latest N model phase periods stored in the shift register, and divides by N. The model phase period average value is obtained and output to the gate signal generation unit 26.

  As described above, the R-phase period in the AC power source 1 is calculated as the model phase period average value, and the R-phase model phase period average value is the input voltage period calculated based on the actual voltage of the AC power source 1. Instead, it is used to generate a gate signal for on / off control of the R-phase thyristor in the power element 4. Further, since the model phase period calculation unit 25 calculates the average value of the model phase periods, it can absorb the variation in the timing of the model phase zero-cross detection signal.

(Gate signal generator)
The gate signal generation unit 26 receives the model phase zero cross detection signal from the model phase zero cross detection unit 24 and also receives the model phase cycle average value from the model phase cycle calculation unit 25 to generate a GR signal that is a gate signal. Output to the power element 4.

  FIG. 10 is a block diagram illustrating a configuration of the gate signal generation unit 26. FIG. 13 is a time chart for explaining the operation of the gate signal generator 26. The gate signal generation unit 26 includes a phase 60 degree calculation circuit 81, a phase 180 degree calculation circuit 82, a phase 135 degree calculation circuit 83, a phase 240 degree calculation circuit 84, a precharge change calculation circuit 85, and a GR signal generation circuit 86. ing.

  The phase 60 degree calculation circuit 81 inputs the model phase period average value from the model phase period calculation unit 25, associates the range from 0 to the model phase period average value to the range from 0 degree to 360 degrees, The model phase period average value corresponding to the phase is calculated as 60 degree time, and is output to the GR signal generation circuit 86. The phase 180 degree calculation circuit 82 calculates the time of the model phase period average value corresponding to the phase of 180 degrees as 180 degree time, and outputs it to the GR signal generation circuit 86. The phase 135 degree calculation circuit 83 calculates the time of the model phase period average value corresponding to the phase of 135 degrees as 135 degree time, and outputs the calculated time to the precharge change calculation circuit 85 and the GR signal generation circuit 86. The phase 240 degree calculation circuit 84 calculates the time of the model phase period average value corresponding to the phase of 240 degrees as 240 degree time, and outputs it to the precharge change calculation circuit 85 and the GR signal generation circuit 86. As shown in FIG. 13, 60 degree time, 180 degree time, 135 degree time, and 240 degree time are times from the timing when the model phase zero-cross detection signal at which the model phase is reset to 0 is turned on to each phase. It is.

The precharge change calculation circuit 85 receives the 135 degree time from the phase 135 degree calculation circuit 83 and the 240 degree time from the phase 240 degree calculation circuit 84, and sets a precharge setting time (start of precharge operation). The amount of precharge change per cycle (the amount of precharge time change per cycle) is calculated using the time from the time until the completion) and output to the GR signal generation circuit 86. Specifically, assuming that the AC power source 1 is a 50 Hz power source and t is a preset precharge setting time, the precharge change amount S per cycle is calculated by the following equation.
S = (240 degree hours−135 degree hours) / (50 × t)

  The GR signal generation circuit 86 includes a compare match timer for generating a GR signal that is a gate signal, the model phase zero cross detection unit 24 receives the model phase zero cross detection signal, the phase 60 degree calculation circuit 81 receives the 60 degree time, 180 degree time from phase 180 degree calculation circuit 82, 135 degree time from phase 135 degree calculation circuit 83, 240 degree time from phase 240 degree calculation circuit 84, and precharge change amount from precharge change calculation circuit 85, respectively. Then, a compare match A value and a compare match B value indicating the timing for generating the GR signal are set. The GR signal generation circuit 86 resets the compare match timer at the timing when the model phase zero cross detection signal is input, and starts counting from 0. The timer value of the compare match timer, the compare match A value, and the compare match B value And a GR signal that turns on when the timer value reaches the compare match A value and turns off when the timer value reaches the compare match B value is generated and output to the R-phase thyristor in the power element 4 To do.

Here, as shown in FIG. 13, when the AC / DC converter 5 performs the precharge operation, the GR signal generation circuit 86 sets the 240-degree time to the compare match A value, and in the first cycle, the compare match A value. The result of subtracting the amount of change in precharge from is set as the compare match B value. Then, assuming that the number of cycles from the start of the precharge operation is C, the GR signal generation circuit 86 sets the result of the following expression as the compare match B value in the Cth cycle.
B = 240 degrees time− (precharge change amount × C)
In this way, as shown in FIG. 13, the GR signal generation circuit 86 generates and outputs a GR signal with a compare match B value that increases by the precharge change amount each time the cycle proceeds. Then, when the precharge operation starts and the precharge setting time set in advance is reached, the GR signal generation circuit 86 sets the 135 degree time to the compare match B value according to the above formula, and the 240 degree time and the 135 degree time. A GR signal that is in an ON state is generated and output. As a result, the precharge operation ends and the steady operation (full fire operation) is started.

  As shown in FIG. 13, when the precharge operation of the AC / DC converter 5 is finished and the steady operation is started, the GR signal generation circuit 86 sets the 180 ° time to the compare match A value and compares the 60 ° time to the compare time. A match B value is set, and a GR signal is generated and output. As shown in FIGS. 13 and 3, the GR signal that is turned on between 180 degree time and 60 degree time is in a time range in which the R phase voltage VR is larger than the other S phase voltage VS and T phase voltage VT. , A gate signal for turning on the R-phase thyristor.

  As described above, according to the AC / DC converter 5 according to the embodiment of the present invention, the control unit 3 detects the zero cross from the line voltages Vrs and Vrt and generates the zero cross detection signal when the operation is turned off. An input voltage period that is a signal time interval is calculated, and a cycle lower limit value L_LMT corresponding to 90% of the input voltage period and a cycle upper limit value P_LMT corresponding to 110% are set. Then, the control unit 3 generates a model phase internally in the model phase zero-cross detection unit 24 when the operation is on, and inputs a zero-cross detection signal when the input voltage cycle is larger than the cycle lower limit value L_LMT, or When the model phase becomes larger than the cycle upper limit value P_LMT without inputting the zero cross detection signal, the model phase is reset, and the model phase zero cross having a time interval between the cycle lower limit value L_LMT and the cycle upper limit value P_LMT A detection signal is generated. Then, in the model phase cycle calculation unit 25, the control unit 3 calculates the average value of the model phase cycle that is the time interval of the model phase zero cross detection signal, and based on the model phase cycle average value and the model phase zero cross detection signal, A gate signal for ON / OFF control of the thyristor of the power element 4 is generated.

  As a result, the model phase zero cross detection signal is a signal having a time interval between the cycle lower limit value L_LMT and the cycle upper limit value P_LMT even if the AC / DC converter 5 is affected by disturbance due to noise, instantaneous power failure, or the like. Thus, the model phase period also falls within the period lower limit value L_LMT and the period upper limit value P_LMT. Therefore, the phase of the gate signal that is not directly affected by the disturbance can be calculated, and the thyristor can be controlled on / off with a phase that matches the line voltage timing of the AC power supply 1. That is, even when a disturbance due to noise, instantaneous power failure, or the like occurs during the precharge operation of the AC / DC converter 5, the fuse is not blown and the rectifying element is not damaged. In addition, even if such a disturbance occurs when the AC / DC converter 5 is in a steady operation (full fire operation), the output bus voltage of the AC / DC converter 5 does not become low. There is no erroneous detection, and the operation of the inverter 6 provided in the subsequent stage does not stop. As a result, stable operation of the AC / DC converter 5 can be realized.

  The control unit 3 of the AC / DC converter 5 generates independent gate signals by the gate signal processing units 14-1, 14-2, and 14-3 for each phase, and turns on the thyristor for each phase of the power element 4. Since the / off control is performed, it is not necessary to perform complicated processing in consideration of the phase order of the R phase, the T phase, and the S phase.

DESCRIPTION OF SYMBOLS 1 AC power supply 2 Reactor 3 Control part 4 Power element 5 AC / DC converter 6 Inverter 7 Motor 11 A / D conversion part 12 Filter 13 Phase voltage / line voltage conversion part 14 Gate signal processing part 21 Zero cross detection part 22 Input voltage period Calculation unit 23 Period upper / lower limit setting unit 24 Model phase zero cross detection unit 25 Model phase period calculation unit 26 Gate signal generation unit 31 Selection circuit 32 Detection circuit 41 Counter 42 Transfer circuit 43 Difference circuit 51 Average operation circuit 52, 53 Multiplication circuit 61 Adder circuit 62 Selection circuit 64, 68 Comparison circuit 65 AND circuit 66 OR circuit 67 Inversion circuit 71 Counter 72 Transfer circuit 73 Difference circuit 74 Average operation circuit 81 Phase 60 degree calculation circuit 82 Phase 180 degree calculation circuit 83 Phase 135 degree calculation circuit 84 Phase 240 degree calculation circuit 85 Precharge change calculation times 86 GR signal generating circuit

Claims (3)

Detecting a zero cross at a point where 0 V is crossed from the voltage of the AC power supply, calculating a period of the zero cross detection signal from a zero cross detection signal indicating a timing at which the zero cross is detected, generating a gate signal based on the period, In an AC / DC converter that controls on / off of a thyristor by a gate signal and converts AC power of the AC power source into DC power,
A phase voltage / line voltage converter that inputs a phase voltage of an AC power source and converts the phase voltage into a line voltage;
Based on the line voltage converted by the phase voltage / line voltage conversion unit, a zero cross detection unit that detects a zero cross and generates a zero cross detection signal;
An input voltage cycle calculation unit that calculates an input voltage cycle indicating a cycle of the input phase voltage based on a zero cross detection signal generated by the zero cross detection unit;
A cycle upper and lower limit value setting unit that sets a cycle upper limit value and a cycle lower limit value based on the input voltage cycle calculated by the input voltage cycle calculation unit;
A model phase that increments from a value of 0 is generated, and when the input voltage cycle calculated by the input voltage cycle calculation unit is larger than the cycle lower limit value set by the cycle upper and lower limit setting unit, the zero cross detection unit When the zero-cross detection signal is input, or when the model phase is larger than the period upper limit value set by the period upper / lower limit setting unit without the zero-cross detection signal being input, the model phase is A model phase zero-cross detector that resets to a value of 0 and generates a model phase zero-cross detection signal;
Based on the model phase zero-cross detection signal generated by the model phase zero-cross detection unit, a model phase period calculation unit that calculates a model phase period indicating the period of the model phase;
An AC / DC converter comprising: a gate signal generation unit that generates a gate signal based on the model phase period calculated by the model phase period calculation unit. The AC / DC converter according to claim 1.
The cycle upper and lower limit value setting unit calculates an average value of input voltage cycles calculated when the AC / DC converter does not perform processing for converting AC power to DC power, and is based on the average value. Set the cycle upper limit and cycle lower limit,
The model phase period calculation unit calculates a model phase period indicating the model phase period based on the model phase zero cross detection signal generated by the model phase zero cross detection unit, and calculates an average value of the model phase periods And
The AC / DC converter, wherein the gate signal generation unit generates a gate signal based on an average value of the model phase periods calculated by the model phase period calculation unit. The AC / DC converter according to claim 1 or 2 ,
The zero cross detection unit, input voltage cycle calculation unit, cycle upper and lower limit setting unit, model phase zero cross detection unit, model phase cycle calculation unit, and gate signal generation unit are for the R phase, S phase, and T phase of the AC power source. Provided,
An AC / DC converter characterized in that the R-phase, S-phase, and T-phase thyristors are controlled to be turned on / off by the respective gate signals generated by the gate signal generator.

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