JP2005269757A - Inverter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inverter equipped with an individual operation detecting method for reducing a high frequency component of an output current even if a dead band region is reduced so as to improve the individual operation detecting sensitivity, suppressing a current distortion rate of the output current, having good individual operation detecting sensitivity, and reducing a loss generated due to a high frequency current and consumed in an inductive load. <P>SOLUTION: The inverter is provided with a current distortion applying means 13 for applying a current distortion for making a transition and a phase of the inverter output current continuous and generating a discontinuous frequency fluctuation at a frequency of the inverter output current at a peak point of the inverter output and for a predetermined period in the vicinity of the peak point so as to generate a fluctuation at an output frequency of the inverter 2. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a wind power generator that generates power using wind energy, a power generation facility that generates power using solar energy, and a fuel that generates power using fuel such as hydrogen that does not cause pollution. When DC power obtained from power generation facilities such as batteries is returned to AC power and grid-linked operation with commercial power is performed, it is pointed out in the distributed power grid linkage technical guidelines issued by the Japan Electric Association. The frequency shift method (frequency drift method) has been adopted as an active method for detecting isolated operation when the private power generation equipment is not disconnected from the system during a power outage of the AC power system, that is, when it becomes isolated operation. The present invention relates to an inverter device that performs system linkage.

  Conventionally, an inverter device that employs this type of frequency shift method as an active isolated operation detection method is that the AC power system gives a frequency bias to the output of the distributed power supply device during normal operation, and the AC power system during the transition to isolated operation. There is known a method of detecting a change in frequency appearing in a voltage to detect a single operation state (see, for example, Patent Document 1).

  Hereinafter, the configuration of an inverter device that employs the frequency shift method as an isolated operation detection method will be described with reference to FIG. As shown in the figure, the DC power supplied from the DC power source 101 is converted into AC power by being linked to the AC power system 103 by the inverter device 102 and supplied to the load 104. Separately from the inverter device 102, AC power from the AC power system 103 is supplied to the load 104 via a circuit breaker 105 and a pole transformer 106. An over-frequency relay (hereinafter referred to as OFR) 107 that monitors the upper limit fmax of the frequency of the voltage applied to the load 104 and an under-frequency relay (hereinafter referred to as UFR) 108 that monitors the lower limit fmin of the same frequency The inverter device 102 is connected so that it can be detected that the frequency exceeds the range of the upper and lower limit values. As shown in FIG. 9, the load 104 can be expressed by an equivalent circuit of a parallel resonance circuit including a parallel equivalent resistor 109, a parallel equivalent inductance 110, and a parallel equivalent capacitance 111.

  Hereinafter, a detection operation procedure of the conventional inverter device 102 adopting the conventional frequency shift method as the isolated operation detection method will be described with reference to FIG. In the following description, a description will be given assuming a system linkage operation in which the rated frequency of the AC power system is f0 (for example, 60 Hz).

  If the AC power system 103 is normal, the inverter device 102 employing the conventional frequency shift method sets the frequency f of the voltage of the AC power system 103 to approximately f = f0 [Hz] in step 113 of the flowchart shown in FIG. (Here, f0 is a rated frequency of the AC power system, for example, 50 Hz), but it is determined in step 114 that it is within the range of (f0−fa) to (f0 + fa). Step 112 → 113 → 114 → 115 → 116 → 117 → 118 → 119 → 113, 112 → 113 → 114 → 115 → 116 → 120 → 118 → 119 → 113, or 112 → 113 → of the flowchart shown in FIG. Repeat the loop 114 → 115 → 116 → 121 → 118 → 119 → 113 to obtain a frequency via F = f0, that is, the output current of the frequency of F = (f0 + Δf) obtained by applying the bias of + Δf to the rated frequency f0 while inserting the output current of the rated frequency, or the bias of −Δf to the rated frequency f0 Output current having a frequency of F = (f0−Δf) is alternately output.

  When the AC power system 103 has a power failure, when the inverter device 102 outputs an output current having a frequency F = (f0 + Δf) in step 121 of the previous cycle, in step 113, the frequency f of the voltage of the AC power system 103 is Since it is detected as F = (f0 + Δf) equal to the frequency of the output current of the inverter device 102, the inverter device 102 is determined in step 114 to be outside the range of (f0−fa) to (f0 + fa). 122, it is determined that (f> f0), and the loop of steps 112 → 113 → 114 → 122 → 123 → 118 → 119 → 113 shown in FIG. 10 is repeated to increase the frequency of the output current. After repeated several times, the signal of the OFR 107 that was monitoring that the frequency upper limit value fmax was reached was detected. The inverter device 102 executes step 124, detects and stops outputting that became islanding state.

  Further, when the AC power system 103 has a power failure, when the inverter device 102 outputs an output current having a frequency F = (f0−Δf) in Step 121 of the previous cycle, in Step 113, the voltage of the AC power system 103 is changed. The frequency f is detected as F = (f0−Δf) which is equal to the frequency of the output current of the inverter device 102, and the inverter device 102 is outside the range of (f0−fa) to (f0 + fa) in step 114. In step 122, since it is determined that (f <f0), the loop of step 112 → 113 → 114 → 122 → 125 → 118 → 119 → 113 shown in FIG. 10 is repeated to decrease the frequency of the output current. When this loop is repeated several times, the signal of the UFR 108 monitoring that the frequency lower limit fmin has been reached. The inverter device 102 that has detected the signal executes step 124, detects that it has entered the single operation state, and stops the output.

  Hereinafter, the timing of the voltage of the AC power system 103 and the output current of the conventional inverter device 102 according to the conventional isolated operation detection method will be described with reference to FIGS. 11 and 12. 11A shows a voltage waveform of the AC power system 103 and an inverter output current waveform to which distortion giving a frequency variation higher than the rated voltage of the AC power system 103 is given, and FIG. 11B shows an AC power system. 103 shows an inverter output current to which distortion is applied that gives a frequency variation lower than the voltage waveform of 103 and the rated voltage of the AC power system 103. In the figure, a waveform indicated by a dotted line indicates a voltage waveform of the AC power system 103, and a waveform indicated by a solid line indicates an output current waveform of the inverter device 102.

  As shown in FIG. 11A, the conventional inverter device 102 outputs a slightly distorted current in which a predetermined period tz whose end point is the zero cross point is zero so that the frequency of the output current increases. T0 shown in FIG. 11A is a half cycle of the voltage waveform of the AC power system, and t1 is a half cycle of the sine waveform portion of the output current waveform of the inverter device 102. Here, the half cycle of the voltage waveform, that is, the ratio of the zero time tz to t0 is called chopping friction cf (hereinafter referred to as cf value). Since the output current of the inverter device 102 shown in FIG. 11A has a fundamental wave component having a half cycle t1 shorter than the rated half cycle t0 of the AC power system voltage, the rated frequency of the AC power system voltage in the first half cycle. The frequency is higher than f0. When the output current of the inverter device 102 reaches zero before the next second half cycle begins, the output current remains zero for the period of time tz until the next half cycle of the AC power system voltage begins. Continue. For the next half cycle, only the output current of the inverter device 102 and the direction of the AC power system voltage are reversed, and a current with the same distortion as the first half cycle is output.

  As shown in FIG. 11B, the inverter device 102 is slightly distorted to output an arbitrary current on the descending waveform path side from the peak point of the output current waveform to the zero cross point so that the frequency of the output current decreases. Output current. T2 shown in FIG. 11B is a half cycle of the sine waveform portion of the output current waveform of the inverter device 102. Since the output current of the inverter device 102 shown in FIG. 11B has a fundamental wave component having a half cycle t2 longer than the rated half cycle t0 of the AC power system voltage in the first half cycle, the output current is lower than the rated frequency f0. It becomes. For the next half cycle, only the output current of the inverter device 102 and the direction of the AC power system voltage are reversed, and a current with the same distortion as the first half cycle is output.

  The inverter output current waveform is distorted by the inverter device 102 as shown in FIG. 11A, and as shown in FIG. 12A, a predetermined period tz including zero cross points on both sides centered on the peak point. May be applied to the inverter output so that the apparent half cycle t1 of the output current of the inverter device 102 is shorter than the half cycle t0 of the rated frequency. Is higher than the rated frequency f0.

  Furthermore, in addition to that shown in FIG. 11 (b), as shown in FIG. 12 (b), a distortion that outputs an arbitrary current output at the zero cross points on both sides centering on the peak point is added to the inverter output waveform. Also good. Then, the apparent half cycle t2 of the output current of the inverter device 102 becomes longer than the half cycle t0 of the rated frequency, and as a result, the frequency of the output current becomes lower than the rated frequency f0.

  Hereinafter, when the inverter device 102 is controlled according to the detection operation shown in the flowchart of FIG. 10 using the method of distorting the output current of the inverter device 102 as shown in FIGS. The output current waveform of the inverter device 102 when the power system is normal will be described with reference to FIG. In the figure, a current waveform for one cycle of a frequency equal to the rated frequency of the AC power system 103 is inserted between the current waveforms to which the distortion described in the explanation of FIG. In the figure, a waveform indicated by a dotted line indicates a voltage waveform of the AC power system 103, and a waveform indicated by a solid line indicates an output current waveform of the inverter device 102.

  Further, when the inverter device 102 is controlled according to the detection operation shown in the flowchart of FIG. 10 using the method of distorting the output current of the inverter device 102 as shown in FIGS. The output current waveform of the inverter device 102 when the power system is normal will be described with reference to FIG. In the figure, a current waveform for one cycle of a frequency equal to the rated frequency of the AC power system 103 is inserted between the current waveforms to which the distortion described in the explanation of FIG. In the figure, a waveform indicated by a dotted line indicates a voltage waveform of the AC power system 103, and a waveform indicated by a solid line indicates an output current waveform of the inverter device 102.

  If the output current of the inverter device 102 shown in FIG. 13 is Io and the rated angular frequency of the AC power system voltage is ω0, the Fourier series can be expressed as (Equation 1).

Here, a0 is a DC component, and an and bn are Fourier coefficients, which can be expressed as (Equation 2), (Equation 3), and (Equation 4), respectively.

  FIG. 15 shows a frequency spectrum showing the relationship between the order of the output current harmonics and the ratio of the amplitude of the harmonics to the fundamental wave component using the cf value of the conventional inverter device 102 as a parameter. In the figure, the cf value indicates the result of measurement for each of 0.05, 0.02, and 0.01. As apparent from (Equation 1) to (Equation 4), the frequency spectrum becomes a harmonic that is an integral multiple of (ω0 / 3), and the larger the cf value, the larger the amplitude of the harmonic component of the output current. It shows a tendency to become.

  FIG. 16 is a characteristic diagram of the dead zone obtained by plotting the limit point of the parallel equivalent capacitance value that operates as a dead zone with respect to an arbitrary parallel equivalent inductance value for the conventional inverter device 102. That is, for the conventional inverter device 102 employing the conventional frequency shift method, the resistance value of the parallel equivalent resistor 109 of the load 7 described in FIG. 9 is R [Ω], the inductance of the parallel equivalent inductance 110 is L [H], In addition, an experiment in which the dead band is examined when the capacitance of the parallel equivalent capacitance 111 is C [F], the equivalent inductance L is plotted on the horizontal axis, the equivalent capacitance C of the load 7 is plotted on the vertical axis, and the cf value is changed as a parameter. The result is shown in FIG. In the experiment, the case where the equivalent resistance R is 14.4Ω is described. In the figure, two dotted lines parallel to the horizontal axis indicate the limit of the equivalent capacitance C that operates as a dead band for any value of the equivalent inductance L when only the OFR 107 or the UFR 108 is used as a passive islanding detection method. This is a plot of points. That is, a region surrounded by two dotted lines parallel to the horizontal axis indicates a dead zone when only the OFR 107 or UFR 108 is used as a passive islanding detection method.

  Next, a curve indicated by a one-dot chain line or a two-dot chain line is a dead band with respect to an arbitrary equivalent inductance L value for the conventional inverter device 102 using only the conventional frequency shift method as an active islanding detection method. The limit point of the equivalent capacitance C which operates is plotted. That is, a region surrounded by a curve indicated by a one-dot chain line or a two-dot chain line indicates a dead zone when only the conventional frequency shift method is used as an active islanding detection method. If the dead zone due to passive islanding and the dead zone due to active islanding do not overlap, it can be said that the entire system has an ideal characteristic with no dead zone. In addition, when the area where the dead zone due to passive islanding and the dead zone due to active islanding overlap is small, it can be said that the entire system has good characteristics with a small dead zone. As is apparent from the figure, it can be seen that better characteristics can be obtained by selecting a large value for the cf value so that the area where the dead zone overlaps becomes smaller.

  Next, FIG. 17 shows the relationship between the cf value of the conventional inverter device 102 and the distortion rate THDi of the output current. As shown in the figure, it can be seen that the relationship between the cf value and the current distortion rate THDi is linearly proportional. In general, it is known that as the current distortion rate THDi increases, the loss consumed by inductive loads such as transformers and various rotating electrical machines connected to the AC power system increases. The characteristics shown in FIG. From this, it can be seen that as the cf value is increased, the loss consumed by the inductive load or the like increases.

As described above, in the active isolated operation method using the conventional frequency shift method, the cf value is increased in order to reduce the dead zone region or eliminate the dead zone region and improve the isolated operation detection sensitivity. Then, there is a problem that the current distortion rate THDi increases and the loss consumed by the inductive load increases.
JP-A-8-134656

  In such a conventional inverter device, in order to increase the isolated operation detection sensitivity, if the cf value is set large and the dead zone region is reduced, the harmonic component of the output current of the inverter device increases, and the current distortion rate of the output current increases. There is a problem that the loss consumed by the inductive load connected to the AC power system generated due to the harmonic current increases and the AC power system generated due to the harmonic current It is required to reduce the loss consumed by the connected inductive load.

  The present invention solves such a problem, and in order to increase the isolated operation detection sensitivity, even if the dead zone region is reduced, the harmonic component of the output current is small, and the current distortion rate of the output current is suppressed. An object of the present invention is to provide an inverter device equipped with an islanding operation detection method which has good islanding detection sensitivity and can reduce the loss consumed by the inductive load caused by the harmonic current.

  In order to achieve the above object, the inverter device of the present invention converts DC power to AC while linking DC power to the AC power system, supplies it to the load, and starts independent operation after leaving the link with the AC power system. In the inverter device having a single operation detecting means for detecting a single operation of the inverter main circuit by detecting a frequency variation generated in the inverter output voltage or a variation caused by the frequency variation, the frequency of the output current of the inverter device varies. Current distortion is applied so that the displacement or phase of the inverter output current is continuous and the frequency of the inverter output current is discontinuous at the peak point of the output voltage of the inverter device. The current distortion applying means is a range of a predetermined frequency section in which the frequency of the load voltage includes the rated frequency. The first current waveform that is a cosine waveform obtained by concatenating one cycle of the waveform for an arbitrary natural number of times and imparts a current distortion that increases the output frequency, and one cycle of the waveform for an arbitrary cycle. A second cosine waveform that is a natural cosine waveform that is connected several times and gives a current distortion whose output frequency decreases, and a cosine waveform that is an arbitrary odd number of concatenations of half the period of the waveform, and the output frequency is commercial A third current waveform that gives a current distortion having a frequency equal to the power frequency is combined and connected to repeatedly output, and the first current waveform and the second current waveform are generated in the shortest time from the time when the output is completed. At the peak point of the load voltage to be applied, the phase of the inverter output current coincides with the phase of the load voltage so that the displacement or phase is continuous and the frequency increases or decreases or does not change. Concatenate the current waveform that gives distortion at the peak point and output it from the inverter device, reduce the harmonic current of the output current and consume it to the inductive load caused by the harmonic current with good isolated operation detection sensitivity This is an inverter device that can reduce the generated loss.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  Also, the first current waveform for one cycle, the second current waveform for one cycle, and the third current waveform for a half cycle are connected in order and output repeatedly, and the second current waveform completes output. 2. The current distortion applying means according to claim 1, further comprising: a phase of an inverter output current that matches a phase of a load voltage at a peak point of a load voltage generated in a shortest time from a time point when the load is applied. This is an inverter device.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  In addition, the second current waveform for one cycle, the first current waveform for one cycle, and the third current waveform for half a cycle are connected in order and output repeatedly, and the first current waveform has been output. 2. The current distortion applying means according to claim 1, further comprising: a phase of an inverter output current that matches a phase of a load voltage at a peak point of a load voltage generated in a shortest time from a time point when the load is applied. This is an inverter device.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  In addition, the first current waveform for one cycle, the third current waveform for one half cycle, and the second current waveform for one cycle are connected in order and output repeatedly, and the second current waveform completes output. 2. The current distortion applying means according to claim 1, further comprising: a phase of an inverter output current that matches a phase of a load voltage at a peak point of a load voltage generated in a shortest time from a time point when the load is applied. This is an inverter device.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  In addition, the second current waveform for one cycle, the third current waveform for one half cycle, and the first current waveform for one cycle are connected in order and output repeatedly, and the first current waveform completes output. 2. The current distortion applying means according to claim 1, further comprising: a phase of an inverter output current that matches a phase of a load voltage at a peak point of a load voltage generated in a shortest time from a time point when the load is applied. This is an inverter device.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  In addition, the peak of the load voltage generated in the shortest time from the time when the second current waveform completes the output by connecting and repeating the output in the order of the first current waveform, the second current waveform, and the third current waveform. 3. The inverter device according to claim 1, further comprising the current distortion applying means configured such that the phase of the inverter output current matches the phase of the load voltage.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  In addition, the second current waveform, the first current waveform, and the third current waveform are connected in order and repeatedly output, and the peak of the load voltage generated in the shortest time from the time when the first current waveform completes the output. 3. The inverter device according to claim 1, further comprising the current distortion applying means configured such that the phase of the inverter output current matches the phase of the load voltage.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  In addition, the first current waveform, the third current waveform, and the second current waveform are connected in order and repeatedly output, and the peak of the load voltage generated in the shortest time from the time when the second current waveform completes the output. 3. The inverter device according to claim 1, further comprising the current distortion applying means configured such that the phase of the inverter output current matches the phase of the load voltage.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  In addition, the second current waveform, the third current waveform, and the first current waveform are connected in order and repeatedly output, and the peak of the load voltage generated in the shortest time from the time when the first current waveform completes the output. 3. The inverter device according to claim 1, further comprising the current distortion applying means configured such that the phase of the inverter output current matches the phase of the load voltage.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  In addition, the current distortion applying means includes a timing at which the polarity of the load voltage changes from negative to positive and an elapsed time from the timing at which the detected polarity of the load voltage changes from negative to positive within the elapsed time. Voltage cycle calculating means for determining a moving average of the load voltage cycle obtained by dividing by the number of occurrences of the load voltage appearing as one cycle as the voltage cycle, and the voltage from the timing when the polarity of the load voltage varies from negative to positive A peak point detecting means is provided for determining, as a peak point, a timing at which a period corresponding to one-fourth of a period has elapsed and a timing at which a period corresponding to three-fourths of the voltage period has elapsed. The inverter device according to claim 1, 2, 3, 4, 5, 6, 7, 8 or claim 9.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  Further, the current distortion imparting means includes a timing at which the polarity of the load voltage changes from positive to negative and an elapsed time until a timing at which the detected polarity of the load voltage changes from positive to negative within the elapsed time. Voltage cycle calculating means for determining a moving average of the load voltage cycle obtained by dividing by the number of occurrences of the appearing load voltage for one cycle as the voltage cycle, and the voltage from the timing when the polarity of the load voltage varies from positive to negative A peak point detecting means is provided for determining, as a peak point, a timing at which a period corresponding to one-fourth of a period has elapsed and a timing at which a period corresponding to three-fourths of the voltage period has elapsed. The inverter device according to claim 1, 2, 3, 4, 5, 6, 7, 8 or claim 9.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  Further, the current distortion applying means may calculate an elapsed time from a timing at which the polarity of the load voltage changes from positive to negative or from negative to positive to a next timing at which the polarity of the load voltage changes from positive to negative or from negative to positive. A voltage frequency detection means for detecting as a half cycle of the load voltage and detecting twice the reciprocal of the half cycle as the frequency of the load voltage is provided. The inverter device according to claim 7, 8 or claim 9.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  The current distortion applying means may change the inverter output frequency in a positive feedback loop according to the change in the frequency of the load voltage when the frequency of the load voltage is outside the range of the predetermined frequency section including the rated frequency. 10. An inverter device according to claim 1, wherein a current waveform for giving a current distortion is output.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  In addition, the current distortion imparting means, when the frequency of the load voltage is outside the range of the predetermined frequency section including the rated frequency, the frequency abnormality that determines that the independent operation is started after leaving the link with the AC power system The inverter device according to claim 1, 2, 3, 4, 5, 6, 7, 8 or 9, characterized by having a detecting means.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  According to the present invention, in order to increase the isolated operation detection sensitivity, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the harmonic current is generated. Inverter device equipped with an islanding detection method that can reduce the loss consumed by the inductive load, has good isolated operation detection sensitivity, and has low loss consumed by the inductive load caused by the harmonic current Can provide.

  The present invention provides a current waveform in which a displacement or a current distortion whose phase is continuous and whose frequency fluctuates is applied in a predetermined section near the peak point and a current distortion in which an output frequency is increased. The first current waveform, the second current waveform that imparts current distortion with a lower output frequency, and the third current waveform having the output frequency equal to the commercial power frequency are combined and connected to repeatedly output the first current waveform. The phase of the inverter output current coincides with the phase of the load voltage at the peak point of the load voltage that occurs in the shortest time from when the current waveform and the second current waveform complete the output. Since the current waveform has the characteristics of both the odd function and the target wave, the Fourier series of the output current waveform can be expressed only by the sinusoidal series term of the harmonics. Whereas the Fourier series of the current is expressed as the sum of the DC component term, the sine wave series term, and the cosine wave series term, the output current of the inverter device of the present invention has only the amount that there is no cosine wave series term. The amplitude of the harmonic component is reduced. For this reason, the current distortion rate THDi of the inverter device of the present invention is smaller than the current distortion rate THDi of the ch value equal to the frequency fluctuation rate ζ, and the same frequency as the conventional frequency is used in order to improve the detection sensitivity of the isolated operation. Even if current distortion with fluctuations is applied, the current distortion rate of the output current can be suppressed, so that the loss due to the inductive load caused by the harmonic current can be kept to a small value. Compared with the inverter device, an inverter device having a good isolated operation detection sensitivity with a smaller loss consumed in the inductive load caused by the harmonic current can be obtained.

  In addition, when the frequency of the load voltage is within the range of the frequency section including the rated frequency, the first current waveform that applies current distortion that increases the output frequency and the second that applies current distortion that decreases the output frequency. And the third current waveform with the output frequency equal to the commercial power frequency are repeatedly connected in various permutation combinations, and output to the AC power system immediately after shifting to the single operation. Even if the apparent inverter output frequency increases due to the inductive load connected, or the apparent inverter output frequency decreases due to the capacitive load connected to the AC power system, the current is limited for a certain period. Even if frequency fluctuations due to distortion and frequency fluctuations due to load cancel each other and isolated operation cannot be detected, frequency fluctuations will be encouraged in the next period. Has the effect that the inverter output frequency becomes possible to change reliably, the inverter device can be perfectly detected within a short period of time the transition to a single operation can be obtained.

  In addition, the inverter output current outputs waveforms having the same amplitude but different polarities during a period in which the first to third current waveforms are connected and repeated to complete the output twice. Since the average value of inevitably becomes zero and the direct current component disappears, there is an effect that no adverse effect is caused on various electrical devices that are generated when the direct current component is added to the alternating current power system.

  In addition, the voltage cycle calculation means displays the elapsed time until the timing when the polarity of the load voltage changes from positive to negative and the timing when the polarity of the detected load voltage changes from positive to negative within the elapsed time. The moving average of the load voltage period obtained by dividing by the number of occurrences of one load voltage cycle is determined as the voltage period, and the timing at which the polarity of the load voltage fluctuates from positive to negative The voltage cycle measured from the zero-cross point interval is not affected by the waveform change of the load voltage, and a stable voltage cycle can be obtained. In addition, a low-pass filter by calculating the moving average value of the stable voltage cycle A stable voltage period from which high-frequency components are removed can be obtained by the effect.

  In addition, the voltage cycle calculation means displays the elapsed time from the timing when the polarity of the load voltage changes from negative to positive and the timing when the polarity of the detected load voltage changes from negative to positive within the elapsed time. The moving average of the load voltage period obtained by dividing by the number of occurrences of one load voltage cycle is determined as the voltage period, and the timing at which the polarity of the load voltage fluctuates from negative to positive The voltage cycle measured from the zero-cross point interval is not affected by the waveform change of the load voltage, and a stable voltage cycle can be obtained. In addition, a low-pass filter by calculating the moving average value of the stable voltage cycle A stable voltage period from which high-frequency components are removed can be obtained by the effect.

  In addition, the peak point detection unit is configured to detect a timing at which a period corresponding to a quarter of the voltage cycle determined by the voltage cycle calculation unit from a timing at which the polarity of the load voltage changes from positive to negative and the voltage cycle. It is characterized in that the timing at which a period corresponding to three-quarters has elapsed is determined as a peak point, and the stable voltage cycle average value determined by the voltage cycle calculation means from the zero cross point reference point is four minutes. As the peak point is determined as the time when one-third and three-quarters of the time have elapsed, the peak point can be obtained at a stable timing that does not vary the generation timing, and the current based on the peak point can be obtained. It has the effect of ensuring the processing operation of the current distortion applying means of the present invention that applies distortion.

  Also, the voltage frequency detection means loads the elapsed time from the timing when the polarity of the load voltage changes from positive to negative or from negative to positive until the next timing when the polarity of the load voltage changes from positive to negative or from negative to positive. Since the half cycle of the voltage is determined, the period of one cycle of the first current waveform in which the output frequency increases is the period during which the output is completed, or one cycle of the second current waveform in which the output frequency decreases. During the period when the output is completed, the timing at which the polarity of the load voltage changes from positive to negative or from negative to positive always appears once, so the first current waveform and the second current waveform are output. During this period, the timing interval can be determined as a half cycle, and the frequency of the load voltage can be determined reliably during this period. When, an effect that can detect the predetermined frequency range, i.e. can rapidly determine whether outside a predetermined interval A, quickly isolated operation when the transition to the single operation comprising rated frequency.

  In addition, when the frequency of the load voltage is outside the range of the predetermined frequency section including the rated frequency, a current waveform that gives current distortion such that the inverter output frequency changes in the positive feedback loop according to the frequency change of the load voltage. When the inverter device shifts to single operation, the load voltage frequency is accelerated in the positive feedback loop and rapidly fluctuates to determine the single operation. Since the lower limit value is reached, it has the effect that it can quickly detect an isolated operation when shifting to an isolated operation.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram of an inverter apparatus according to an embodiment of the present invention. In the figure, DC power supplied from a DC power source 1 is converted into AC power by being linked to an AC power system 3 by an inverter apparatus 2 and is converted into parallel equivalents. It is supplied to a load 7 composed of a resistor 4, a parallel equivalent inductance 5, and a parallel equivalent capacitance 6. Separately from the inverter device 2, AC power of the AC power system 3 is supplied to the load 7 via a circuit breaker 8 and a pole transformer 9.

  The inverter device 2 includes an inverter main circuit 10 that converts DC power supplied from the DC power source 1 into AC power while being connected to the AC power system 3 and supplies the AC power to the load 7, and a load voltage Vo supplied to the load 7. A voltage detector 11 for detecting the output current, a current detector 12 for detecting the output current Io output from the inverter main circuit 10, and a load voltage Vo and a current for applying current distortion based on the output current Io The inverter main circuit 10 is driven by the current distortion applying means 13 for generating the gate pulse signal GP for PWM control of the inverter main circuit 10 so as to be output from the device 2, and the gate pulse signal GP output by the current distortion applying means 13. A gate drive circuit 14 for generating a gate drive signal GD is provided. Between the inverter main circuit 10 and the load 7, a filter circuit 18 configured by coils 15 and 16 and a capacitor 17 and removing harmonic components contained in the inverter output is inserted.

  The current distortion applying means 13 includes a voltage period calculating means 19 for calculating a voltage period Tv of the load voltage Vo in consideration of a timing when the polarity of the load voltage Vo detected from the voltage detector 11 changes from negative to positive, and a load voltage Vo. The peak point detecting means 20 for generating the peak point synchronizing signal PS by calculating the timing at which the polarity of the signal fluctuates from negative to positive and the timing for generating the peak point from the voltage period Tv, and the peak point synchronizing signal PS and the additional voltage Vo Address pointer generating means 21 for generating the address pointer AP based on the current waveform storage means for outputting the cosine wave pattern stored in the built-in memory as the current waveform data IWD stored at the address indicated by the address pointer AP 22 and the current waveform data IWD are multiplied by the output current setting signal Iset to Multiplier 23 for calculating target value Iobj, current deviation calculator 24 for calculating current deviation ei between output current Io measured from current detector 12 and current target value Iobj, and PI calculation based on current deviation ei PI calculation means 25 for calculating the control amount IY, PWM modulation means 26 for generating the PWM data Dpwm by pulse width modulating the control amount IY, and the load voltage Vo based on the timing at which the polarity of the load voltage Vo changes. The voltage frequency detecting means 27 for detecting the frequency of the load and the frequency of the load voltage Vo are monitored, and if the frequency exceeds the upper and lower limit value range, the frequency abnormality signal FER for stopping the switching control of the gate drive circuit 14 is generated. The frequency abnormality detecting means 28 and the switch of the gate drive circuit 14 when the load voltage Vo is monitored and exceeds the range of the upper and lower limit values And a voltage abnormality detection means 29 for generating a voltage error signal VER to stop the grayed signal.

  Next, the operation of this inverter device will be described. FIGS. 2A to 2B are time charts showing the timing of the load voltage Vo and the peak point synchronization signal PS. The voltage cycle calculation means 19 sets the cycle measured from the timing interval one time before the current timing at which the polarity of the load voltage Vo changes from negative to positive, and sets the polarity of the load voltage Vo from negative to positive. Period T1 measured from the timing interval two times before the timing before the changing timing, and timing (m-2) times before the timing at which the polarity of the load voltage Vo changes from negative to positive (m -1) Period Tm-2 measured from the previous timing interval, and from the (m-1) previous timing interval from the timing when the polarity of the load voltage Vo changes from negative to positive Each measured period Tm−1 is measured, and a moving average value Tavr obtained by dividing the sum of the periods Tk (k = 0 to (m−1)) by the number m of occurrences of the period is expressed by the following equation (5). calculate.

  The arithmetic expression shown in (Equation 5) has an effect as a low-pass filter that suppresses a component that vibrates at a high frequency each time the above-described cycle is measured, and a stable average cycle Tavr that suppresses fluctuations in high frequency components. Is obtained. Depending on the state of the load, the load voltage waveform may be deformed, and the section in which the load voltage Vo is positive and the section in which the load voltage Vo is negative may not be equal, and the polarity of the load voltage Vo is from negative to positive or positive In the method of measuring the negative cycle, that is, the method of measuring the half cycle of the load voltage Vo from the zero-crossing interval, the half cycle measured for each measurement oscillates, but in the voltage cycle calculation means 19 of this embodiment, Since the voltage cycle is measured from the timing interval at which the polarity of the load voltage Vo changes from negative to positive, a stable voltage cycle can be obtained without being affected by the deformation of the load voltage waveform. Further, by calculating the moving average, it is possible to obtain a stable voltage cycle in which fluctuations in high frequency components are suppressed.

  The peak point detection means 20 obtains the average period Tavr by the above-described calculation method, and then the timing when Tavr / 4 has elapsed from the timing when the polarity of the load voltage Vo changes from negative to positive, and the timing when 3 Tavr / 4 has elapsed. Is determined as a peak point, and a peak point synchronization signal PS as shown in FIG. 2B is generated. In the peak point detection means 20 of the present embodiment, the stability obtained by the voltage cycle calculation means 19 described above with the peak point where the generation timing hardly varies due to the influence of the load voltage Vo waveform deformed depending on the load state as a reference point. Since the peak point is the timing at which one-fourth and three-fourths of the average period Tavr has elapsed, the peak point can be obtained at a stable timing with little variation in the generation timing.

  3A to 3E respectively show a load voltage Vo, a peak point synchronization signal PS, and a read increase rate Rc of an address pointer AP, which will be described later, in a normal operation state where the inverter device 2 is not in a single operation state. It is a time chart which shows the timing of the address pointer AP and the inverter output current Io. In FIG. 3 (e), the waveform indicated by the dotted line indicates the waveform of the load voltage Vo, and the waveform indicated by the solid line indicates the waveform of the output current Io of the inverter device 2.

  The peak point detecting means 20 is operated in the vicinity of the peak point of the load voltage Vo shown in FIG. 3A by the operation of the voltage cycle calculating means 19 and the peak point detecting means 20 described above, as shown in FIG. A point synchronization signal PS is generated.

  By the way, the current waveform storage means 22 has a built-in memory, and the built-in memory has five cycles of cosine wave data having a phase proportional to the address deviation from the address N0 at an arbitrary address, that is, a phase range of 0 to 10π. The cosine wave data is stored. Here, cosine wave data having a phase of zero is stored at the address N0, the phase is 2π at the address N2π, the phase is 4π at the address N4π, the phase is 5π at the address N5π, and the phase is 7π at the address N7π. Suppose that address N9π stores cosine wave data having a phase of 9π and address N10π having a phase of 10π. The address pointer generating means 21 outputs an address pointer AP that changes at a timing described later. The current waveform storage means 22 outputs cosine wave data stored in the built-in memory at the address indicated by the address pointer AP as current waveform data IWD.

  Next, feedback processing until the inverter output current Io is generated will be described. The multiplication unit 23 multiplies the output current setting signal Iset and the current waveform data IWD to create a current target value Iobj and outputs it to the current deviation calculation unit 24. The current deviation calculation unit 24 calculates a current deviation ei from the output current Io measured by the current detector 12 and the current target value Iobj, and outputs it to the PI calculation unit 25. The PI calculating means 25 calculates a PI control amount IY obtained by adding a proportional term proportional to the current deviation ei and an integral term proportional to the current deviation integrated value obtained by integrating the current deviation for a certain period, and outputs the PI control amount IY to the PWM modulating means 26. The PWM modulation means 26 generates a gate pulse signal GP for PWM control of the inverter main circuit 10 by performing pulse width modulation on the control amount IY, and outputs it to the gate drive circuit 14. The inverter main circuit 10 PWM-controlled by the gate pulse signal GP through the gate drive circuit 14 outputs an inverter output current Io as shown in FIG.

  At the timing (1) when the peak point rises as shown in FIG. 3B, the address pointer generating means 21 sets the read increase rate Rc to an appropriate value Rc1 of 1 or more, and simultaneously resets the built-in counter. In the T1 period from the timing of (1) to the timing of (2) when the address pointer AP reaches N2π shown in FIG. 3D, the address pointer AP exceeds 1 in the internal counter that keeps counting up. The address shown in FIG. 3D is indicated by adding the address N0 to the product obtained by multiplying the read increase rate Rc1 set to the value. In the T1 period, cosine wave data having a phase in the range of 0 to 2π stored in the built-in memory is output as output current data IWD from the current waveform storage means 22, and the inverter main circuit 10 is controlled by the feedback processing described above. A current waveform (hereinafter referred to as a first current waveform) in which the frequency illustrated in FIG.

  At the timing of (2), the address pointer generating means 21 sets the read increase rate Rc to a value indicated by (Equation 6) and resets the built-in counter.

In the period T2 from the timing of (2) to the timing of (3) when the address pointer AP reaches N4π, the address pointer AP addresses the product obtained by multiplying the internal counter that continues to count up by the read increase rate Rc2. The address shown in FIG. 3D with N2π added is indicated. In the period T2, cosine wave data having a phase stored in the built-in memory in the range of 2π to 4π is output as output current data IWD from the current waveform storage means 22, and the inverter main circuit 10 is controlled by the feedback processing described above. The current waveform shown in FIG. 3E (hereinafter referred to as the second current waveform) is generated.
(Expression 7) is obtained by transforming (Expression 6).

  Assuming that the count value per unit time of the built-in counter is Ct, the built-in counter starts counting from No in period T1 and period T2, and counts up during the period (T1 + T2) when the count value per unit time is Ct. Since the built-in counter reaches the address value N4π, (Equation 8) is established.

  In the period T1, the address pointer AP starts counting from No, the count value per unit time is CtRc1, and as a result of the count-up operation for the period T1, the address pointer AD reaches N2π. To do.

  In the period T2, the address pointer AP starts counting from N2π, and the count value per unit time is CtRc2, and the address pointer AD reaches N4π as a result of the count-up operation for the period T2. To do.

  From (Equation 9) and (Equation 10), (Equation 11) is obtained.

  (Expression 12) is obtained by transforming (Expression 8).

  (Equation 13) is obtained from (Equation 7), (Equation 11), and (Equation 12).

  After setting an appropriate value for the read increase rate Rc1 in the period T1, if the read increase rate Rc2 in the section T2 is set by (Equation 6), (Equation 13) is established, and the first and second current waveforms are output. Is equal to 2T0 for two periods of the load voltage Vo. This means that the timing at which the first and second current waveforms complete the output coincides with the timing at which the load voltage Vo finishes outputting two cycles. That is, when the inverter device 2 is controlled by the current distortion applying means 13 of the inverter device 2 of the present invention, the phase of the inverter output current is at the peak point where the first current waveform and the second current waveform complete the output, It corresponds to the phase of the load voltage Vo, that is, zero (rad). Further, as apparent from the positional relationship shown in FIG. 3, the period T2 of the second current waveform is larger than the rated period T0 of the power system voltage, so the second current waveform is based on the rated frequency of the power system voltage. Becomes a low frequency.

  At the timing (3) when the address pointer AP reaches N4π shown in FIG. 3D or the timing (4) when the peak point rises, the read increase rate Rc is set to 1, and the internal counter is reset. In the T3 period from the timing of (3) or (4) to the timing of (5) when the address pointer AP reaches N5π shown in FIG. 3D, the address pointer AP keeps counting up. The address shown in FIG. 3D is designated by adding the address N4π to the product obtained by multiplying the read increase rate Rc set to 1 by the address N4π. In the T3 period, the cosine wave data having a phase stored in the built-in memory in the range of 4π to 5π is output as the output current data IWD from the current waveform storage means 22, and the inverter main circuit 10 is controlled by the feedback processing described above. A current waveform (hereinafter referred to as a third current waveform) that matches the phase of the load voltage Vo illustrated in FIG.

  At the timing (5) when the address pointer AP reaches 5π shown in FIG. 3D or the timing (6) when the peak point shown in FIG. Rc is again set to an appropriate value Rc1 of 1 or more, and the built-in counter is reset.

  In the period T4 from the timing of (5) or (6) to the timing of (7) when the address pointer AP reaches N7π shown in FIG. 3D, the address pointer AP keeps counting up. The address shown in FIG. 3D is designated by adding the address N5π to the product obtained by multiplying the read increase rate Rc1 set to a value exceeding 1 by the address N5π. In the T4 period, cosine wave data having a phase of 5 to 7π stored in the built-in memory is output from the current waveform storage means 22 as output current data IWD, and the inverter main circuit 10 is controlled by the feedback processing described above. As in the case of the T1 period described above, a first current waveform in which the frequency illustrated in FIG.

  In the period T5 shown in FIG. 3 from the timing of (7) to the timing of (8) when the address pointer AP reaches N9π, if the read increase rate Rc is set to the value shown in (Equation 6), the address pointer The AP designates the address shown in FIG. 3D, which is obtained by adding the address N7π to the product obtained by multiplying the internal counter that continues to count up by the read increase rate Rc2. In the T5 period, cosine wave data having a phase stored in the built-in memory in the range of 7π to 9π is output as output current data IWD from the current waveform storage means 22, and the inverter main circuit 10 is controlled by the feedback processing described above. As in the case of the T2 period described above, the second current waveform shown in FIG. 3 (e) is generated.

  If the reading increase rate Rc2 in the section T5 is set by (Equation 6), for the same reason as described above, (Equation 13) is established, and the period (T1 + T2) in which the first and second current waveforms complete the output is as follows. , Equal to 2T0 for two cycles of the load voltage Vo, and at the peak point where the first current waveform with the frequency increasing and the second current waveform with the frequency decreasing from the inverter device 2 complete the output, the first current The phase of the output current at which the waveform and the second current waveform complete the output coincides with the phase of the load voltage Vo, that is, zero (rad).

  At the timing (8), the read increase rate Rc is set to 1, and the built-in memory is reset. In the period T6 shown in FIG. 3 from the timing of (8) to the timing of (9) when the address pointer AP reaches N10π, the address pointer AP is set to a value of 1 in the internal counter that keeps counting up. The address pointer AP as shown in FIG. 3D is designated by adding the address N9π to the product obtained by multiplying the read increase rate Rc. In the period T6, the cosine wave data having a phase of 9π to 10π stored in the built-in memory is output as the output current data IWD from the current waveform storage means 22, and the inverter main circuit 10 is controlled by the feedback processing described above. As in the case of the T3 period described above, the third current waveform shown in FIG.

  After the timing (9) or (1 '), the same processing as the operation after the timing (1) shown in FIG. 3 is repeatedly repeated.

  FIGS. 4A to 4C show the load voltage Vo, the peak point synchronization signal PS, and the inverter output current in the normal operation state where the inverter device 2 described in FIG. 3 is not in the single operation state. It is a time chart which shows the timing of Io. In FIG. 4C, the waveform indicated by the dotted line indicates the load voltage Vo, and the waveform indicated by the solid line indicates the output current Io of the inverter device 2. As described above, the displacement or phase of the output current Io is continuous, but one period of the output current in the T1 and T4 periods is shorter than the rated period To of the commercial power, and the output current in the T2 and T5 periods One cycle is longer than the rated cycle To of commercial power, and the half cycle of the output current in the periods T3 and T6 is equal to the half cycle of the rated cycle To of commercial power. The frequency becomes discontinuous at the coupling point between the arbitrary period Ti and the next period Ti + 1, that is, at the peak point or a predetermined section in the vicinity thereof, and current distortion occurs at this coupling point. The inverter device 2 outputs a current waveform that imparts current distortion that increases its output frequency in the T1 and T4 periods, and outputs a current waveform that imparts current distortion that decreases its output frequency in the T2 and T5 period sections. In the T3 and T6 period sections, a current waveform that gives a current distortion having a frequency equal to the rated frequency of the commercial power is output.

  Next, a detection method for detecting an isolated operation state caused by a power failure of the AC power system 3 and stopping the inverter output will be described.

  First, the passive islanding detection method will be described. This isolated operation detection method is effective when the reactive power supplied by the inverter device 2 does not match the reactive power requested by the load 7. In this case, when the inverter device 2 enters the single operation state, the frequency of the load voltage Vo rapidly varies from the rated frequency, and the voltage value of the load voltage Vo also varies accordingly. The voltage frequency detection means 27 calculates the frequency of the load voltage Vo from the half cycle of the load voltage Vo measured from the timing interval at which the polarity of the load voltage Vo changes from negative to positive or from positive to negative, and the frequency abnormality detection means 28 Monitors that the frequency of the load voltage Vo deviates from the range of the frequency upper limit value OF to the frequency lower limit value UF, and exceeds the frequency upper limit value OF or falls below the frequency lower limit value UF. It detects and outputs the frequency abnormality signal FER to stop the switching operation of the inverter main circuit 10.

  The voltage abnormality detection means 29 monitors that the load voltage Vo that fluctuates at the same time as the frequency of the load voltage Vo fluctuates from the range of the voltage upper limit value OV to the voltage upper limit value OV. Or exceeding the voltage lower limit value UV, the isolated operation is detected, and the voltage abnormality signal VER is output to stop the switching operation of the inverter main circuit 10.

  Next, an active islanding detection method will be described. When the reactive power supplied by the inverter device 2 substantially matches the reactive power requested by the load 7, the frequency of the load supply voltage Vo hardly changes even when the inverter device 2 enters the single operation state. The above-mentioned passive islanding detection method that monitors the islanding operation by detecting the abnormal frequency of the frequency of the load voltage Vo and the abnormal voltage detection cannot detect the islanding operation. Therefore, the islanding operation is detected by the active islanding detection method described below. To do.

  FIG. 5 shows the relationship between the load voltage frequency measurement value Fi measured in the current cycle and the output current frequency set value Fo of the inverter device 2 controlled by the current distortion applying means 13 in the next cycle. The voltage frequency detection means 27 calculates the frequency of the load voltage Vo from the half cycle of the load voltage Vo measured from the timing interval at which the polarity of the load voltage Vo changes from negative to positive or from positive to negative. The load voltage frequency measurement value Fi measured in this cycle is shown. As shown in FIG. 5, the current distortion generating means 13 provides a predetermined section [f0−Δf, f0 + Δf] (hereinafter referred to as a predetermined section A) including the rated frequency f0, and the frequency of the load voltage Vo is within the predetermined section A. When it is within the range, the inverter device 2 connects and repeatedly outputs the first, second, and third current waveforms as described above. When the load voltage frequency measurement value Fi measured in the current cycle is below the range of the predetermined section A, the output current frequency set value Fo of the inverter device 2 controlled in the next cycle is measured in the current cycle. It is set so as to be even lower than the measured load voltage frequency Fi. When the load voltage frequency measurement value Fi measured in the current cycle exceeds the range of the predetermined section A, the output current frequency set value Fo of the inverter device 2 controlled in the next cycle is measured in the current cycle. The load voltage Vo is set to be higher than the load voltage frequency measurement value Fi.

  By the way, when the method of measuring the cycle from the interval of the timing at which the polarity of the load voltage changes is adopted as the single operation detection method of the inverter device 2, the apparent load voltage frequency of the load voltage immediately after the single operation shift is Affected by the type of load 7. For example, when the load 7 is an inductive load, the load voltage is ahead of the inverter output current, and the polarity of the load voltage detected last time changes, and the polarity of the load voltage detected immediately after the transition to the independent operation changes. The timing interval is reduced, and the apparent load voltage frequency increases. When the load 7 is a capacitive load, the load voltage is delayed in phase with respect to the inverter output current, and the timing at which the polarity of the load voltage detected last time changes and the timing at which the polarity of the load voltage detected immediately after shifting to the single operation changes. The interval is increased and the apparent output frequency is increased. Immediately after the transition to isolated operation, if the apparent frequency that varies depending on the state of the load 7 and the frequency variation caused by the distortion current are the same and the direction is reversed, the frequency variation may not occur and may not occur. Even if the operation has shifted to the single operation, it may take a long time to detect that the operation has been performed after the single operation.

  Therefore, when it is determined that the frequency of the load voltage Vo is within the range of the predetermined section A, as described above, from the inverter device 2, the first current waveform that applies current distortion increasing in frequency and the frequency If the second current waveform that gives the current distortion that falls is alternately output repeatedly, the frequency fluctuation due to the current distortion and the frequency fluctuation due to the load cancel each other for a certain period, In the period, fluctuations in the number of peripheral edges are promoted, the output frequency of the inverter device 2 is surely changed, and the load voltage frequency Fi is below the range of the predetermined section A or above the range of the predetermined section A, which will be described later. Since the process is executed, it is possible to reliably detect the shift to the single operation within a short time.

  Next, when the load voltage frequency Fi measured this time is below the range of the predetermined section A, the output voltage frequency setting value Fo is set so as to be lower than the load voltage frequency Fi. When the load voltage frequency Fo reaches the frequency lower limit value UF, the isolated operation is detected quickly and the frequency abnormality signal FER is output to stop the switching operation of the inverter main circuit 10. Let

  Next, when the load voltage frequency Fi measured this time is equal to or greater than the range of the predetermined section A, the load voltage frequency is set by setting the output current frequency setting value Fo so as to be higher than the load voltage frequency Fi. When the load voltage frequency Fo reaches the frequency lower limit value OF, the independent operation is detected quickly, and the frequency abnormality signal FER is output to stop the switching operation of the inverter main circuit 10. Let

  By the way, the voltage frequency detection means 27 calculates the elapsed time from the timing when the polarity of the load voltage changes from positive to negative or from negative to positive until the next timing when the polarity of the load voltage changes from positive to negative or from negative to positive. Since it is determined as a half cycle of the load voltage, the output of the second current waveform with the output frequency falling is completed during the period when the output current increases for one cycle of the first current waveform Since the timing at which the polarity of the load voltage fluctuates from positive to negative or from negative to positive always appears once during each period, the period of the first current waveform or one period of the second current waveform is During the period when the output is completed, the timing interval can be determined as a half cycle, and the frequency of the load voltage can be determined reliably during this period. When the transition to the rolling, it is possible to load voltage frequency can be determined quickly whether or not out of a predetermined interval A, detects a rapid islanding operation when the transition to independent operation.

  FIG. 6 shows a frequency spectrum showing the relationship between the order of the output current harmonic and the ratio of the amplitude of the harmonic to the fundamental component, using the frequency variation rate ζ of the inverter device 2 of the first embodiment as a parameter. In the figure, the frequency variation rate ζ shows the results of measurement in each case of 0.05, 0.02, and 0.01. That is, from the inverter device 2, one cycle of the first current waveform that applies current distortion with increasing frequency, one cycle of the second current waveform that applies current distortion with decreasing frequency, and the frequency is the commercial power frequency. For the output current waveform shown in FIG. 4 (c), which is output by connecting and repeating the third current waveform half cycle that gives a current distortion of a frequency equal to, the current waveform frequency variation rate ζ is used as a parameter. 3 shows the relationship between the harmonic order of the output current and the ratio of the amplitude of the harmonic component to the fundamental component. Here, as shown in FIG. 4 (c), the period of the current waveform to which distortion with increasing (decreasing) frequency is applied is Ti (i = 1, 2, 3,...), And the rated frequency of the load voltage Vo is T0. In other words, the periodic fluctuation rate ζ is set to (Expression 14).

  By the way, the cf value described in the description of the prior art is defined as the ratio of the zero time tz to the half cycle t0 of the voltage waveform expressed by (Equation 15).

  (Equation 16) is established from (Equation 15).

  Assuming that the time function of the output current Io of the inverter device 2 is Io (t), the output current Io (t) having a waveform as shown in FIG. Since the characteristics of the target wave shown in (Equation 18) are combined, the Fourier series of the output current Io can be expressed as (Equation 19).

  Here, ωo is the rated angular frequency of the AC power system voltage, and a2m + 1 is a Fourier coefficient as shown in (Equation 20).

  As is clear from (Expression 17), the output current has a frequency spectrum in which only a sine wave series obtained by multiplying 1/5 of the fundamental frequency by an odd number is present. Compared with the Fourier series (Equation 1) of the output current Io of the conventional inverter device 102, the harmonic component of the output current Io of the inverter device 2 of the present invention has a smaller harmonic component as much as there is no cosine series term. It should be.

  Compared with the output current waveform of the conventional inverter device shown in FIGS. 11 to 12 and the output current waveform of the inverter device of the present invention shown in FIG. 4C, 2tz in FIGS. c) corresponds to the difference | Ti−T0 | between the current waveform cycle Ti (i = 1, 2,... 6) and the rated cycle T0, and 2t0 in FIGS. 11 to 12 corresponds to the rated cycle T0 in FIG. Accordingly, when 2tz in (Equation 16) is replaced with | Ti-T0 | and 2t0 in (Equation 16) is replaced with T0, (Equation 14) is obtained. That is, the cf value of the conventional inverter device 102 may be considered as an amount corresponding to the periodic fluctuation rate ζ of the present invention. Comparing FIG. 6 and FIG. 14, the harmonic current components when the frequency fluctuation rate ζ of FIG. 6 takes values of 0.01, 0.02, and 0.05 have the same cf value of FIG. It can be seen that there is a reduction compared to the harmonic current component in the case of taking values of 0.01, 0.02, and 0.05. As described above, this is in agreement with a view comparing the mathematical expressions that the harmonic component of the output current Io of the inverter device 2 of the present invention is reduced by the amount of the cosine wave series term.

  FIG. 7 shows the relationship between the periodic fluctuation rate ζ and the output current distortion rate THDi of the inverter device 2 of the present invention, and the relationship between the cf value of the conventional inverter device 102 and the output current distortion rate THDi. In the figure, the solid line shows the relationship between the periodic fluctuation rate ζ and the current distortion rate THDi of the inverter device 2 of the present invention, and the dotted line shows the relationship between the cf value of the conventional inverter device 102 and the current distortion rate THDi. As is apparent from the figure, at the same level of frequency fluctuation rate ζ corresponding to the cf value, the output current distortion rate THDi of the inverter device 2 of the present invention is remarkably reduced as compared with the conventional one. Understand.

  FIG. 8 shows the characteristics of the dead band obtained by plotting the limit point of the value of the parallel equivalent capacitance 6 operating as the dead band with respect to the value of the arbitrary parallel equivalent inductance 5 for the inverter device 2 of the present invention.

  In FIG. 8, the resistance value of the parallel equivalent resistance 4 of the load 7 is R [Ω], the inductance of the parallel equivalent inductance 5 is L [H], and the capacitance of the parallel equivalent capacitance 6 is C [F]. Similarly to the conventional example in which L is on the horizontal axis, capacitance C is on the vertical axis, and the cf value in the conventional example is changed to values of 0.01, 0.02, and 0.05, here, the corresponding parameters The experimental result which investigated the dead zone when changing the frequency fluctuation rate (zeta) which are these to each value of 0.01, 0.02, and 0.05 is shown. In the experiment, as in the conventional example, the case where the equivalent resistance R is 14.4Ω is examined.

  In the figure, two dotted lines parallel to the horizontal axis indicate an equivalent capacitance C that operates as a dead zone for any value of the equivalent inductance L when only the frequency abnormality detection means 28 is used as a passive islanding detection method. This is a plot of the limit points. That is, a region sandwiched between two dotted lines parallel to the horizontal axis represents a dead zone region when only the frequency abnormality detection means 28 is used as a passive islanding detection method.

  Next, a curve indicated by a one-dot chain line or a two-dot chain line indicates an arbitrary equivalent inductance for the inverter device 2 using only the active islanding detection method by the current distortion applying means 13 of the present invention described above as the islanding operation detection method. The limit point of the equivalent capacitance C operating as a dead zone is plotted against the value of L. That is, a region surrounded by a curved line indicated by a one-dot chain line or a two-dot chain line indicates a dead zone when only the active islanding detection method of the present invention is used. If the area where the dead zone by the passive islanding detection method overlaps with the dead zone by the active islanding detection method is small, it can be said that the entire system has good characteristics with a small dead zone. As is clear from comparison between FIG. 8 and FIG. 16, at each value of 0.01, 0.02, 0.05 of the frequency fluctuation rate ζ of the present invention corresponding to the conventional cf value, The dead band characteristics of the inverter device 2 were almost the same as the dead band characteristics of the conventional inverter device 102. Next, consider a case where 0.05 is selected as the frequency variation rate ζ, in which the area where the dead zone regions of the active islanding detection method and the passive islanding detection method overlap is the smallest. When 0.05 is selected as the frequency variation rate ζ, the dead band boundary characteristic of the active islanding detection method and the passive islanding detection method of the inverter device 2 of the present invention is the cf value corresponding to the frequency variation rate ζ. Almost the same characteristics as those of the conventional inverter device 102 with 0.05 selected can be obtained. Therefore, when 0.05 is selected as the frequency variation rate ζ, the dead zone region obtained by the active islanding detection method of the inverter device 2 of the present invention and the dead zone region where the dead zone region obtained by the passive islanding detection method overlaps are represented by frequency fluctuations. When 0.05 is selected as the cf value corresponding to the rate ζ, substantially the same one as that of the conventional inverter device 102 is obtained. Therefore, the independent operation detection sensitivity of the inverter device 2 of the present invention when 0.05 is selected as the frequency variation rate ζ is the conventional inverter device when 0.05 is selected as the cf value corresponding to the frequency variation rate. A sensitivity equivalent to the isolated operation detection sensitivity of 102 is obtained. However, in the description of FIG. 7 described above, the output current distortion rate THDi of the inverter device 2 of the present invention is significantly reduced as compared with the conventional one at the same level of the frequency fluctuation rate ζ corresponding to the cf value. The loss consumed by the inductive load caused by the wave current can be reduced. That is, when the independent operation detection sensitivity of the inverter device 2 of the present invention and the conventional inverter device 102 is set to the same performance, the inverter device 2 of the present invention causes higher harmonic currents than the conventional inverter device 102. Thus, the loss consumed by the inductive load generated can be reduced.

  As described above, the current distortion rate of the output current of the inverter device of the present invention is higher than that of the conventional inverter device compared with the conventional inverter device having the same level as that of the conventional inverter and good isolated operation detection sensitivity. The loss consumed by the inductive load caused by the harmonic current can be reduced compared to the conventional inverter device, the isolated operation detection sensitivity is good, and the harmonics can be reduced. It is possible to provide an ideal inverter device in which the loss consumed by the inductive load caused by the current is smaller.

  In addition, the current distortion imparting means of the embodiment is connected in order of a first current waveform for one cycle, a second current waveform for one cycle, and a third current waveform for a half cycle, and repeatedly outputs them. The phase of the inverter output current matches the phase of the load voltage at the peak point of the load voltage that occurs in the shortest time from when the second current waveform completes output. Current waveform of 1 cycle, a first current waveform for one cycle, and a third current waveform for a half cycle are connected in order and repeatedly output, and the first current waveform is generated in the shortest time from the time when the output is completed. At the peak point of the load voltage, the phase of the inverter output current may coincide with the phase of the load voltage, and there is no difference in the effect.

  In addition, the current distortion imparting means of the embodiment is connected in order of a first current waveform for one cycle, a second current waveform for one cycle, and a third current waveform for a half cycle, and repeatedly outputs them. The phase of the inverter output current matches the phase of the load voltage at the peak point of the load voltage that occurs in the shortest time from when the second current waveform completes output. Current waveform, half-cycle third current waveform, and 1-cycle second current waveform are connected in order and repeatedly output, and the second current waveform is generated in the shortest time from the completion of output. At the peak point of the load voltage, the phase of the inverter output current may coincide with the phase of the load voltage, and there is no difference in the effect.

  In addition, the current distortion imparting means of the embodiment is connected in order of a first current waveform for one cycle, a second current waveform for one cycle, and a third current waveform for a half cycle, and repeatedly outputs them. The phase of the inverter output current matches the phase of the load voltage at the peak point of the load voltage that occurs in the shortest time from when the second current waveform completes output. Current waveform, half-cycle third current waveform, and 1-cycle first current waveform are connected in order and repeatedly output, and the first current waveform is generated in the shortest time from the completion of output. At the peak point of the load voltage, the phase of the inverter output current may coincide with the phase of the load voltage, and there is no difference in the effect.

  In addition, the current distortion imparting means of the embodiment is connected in order of a first current waveform for one cycle, a second current waveform for one cycle, and a third current waveform for a half cycle, and repeatedly outputs them. The phase of the inverter output current coincides with the phase of the load voltage at the peak point of the load voltage that occurs in the shortest time from the time when the second current waveform completes the output. Is a cosine waveform that is connected to an arbitrary natural number of times, and a first current waveform that imparts a current distortion that increases its output frequency, and a cosine waveform that is an arbitrary natural number of concatenations of one period of the waveform, and its output frequency A second current waveform for applying a current distortion that falls, a cosine waveform obtained by connecting half of the waveform for any odd number of times, and a third current waveform having an output frequency equal to the commercial power frequency. Current waveform order The phase of the inverter output current coincides with the phase of the load voltage at the peak point of the load voltage that occurs in the shortest time from the time when the second current waveform completes the output. Good, no difference in its effects.

  In addition, the current distortion imparting means of the embodiment is connected in order of a first current waveform for one cycle, a second current waveform for one cycle, and a third current waveform for a half cycle, and repeatedly outputs them. The phase of the inverter output current coincides with the phase of the load voltage at the peak point of the load voltage that occurs in the shortest time from the time when the second current waveform completes the output. Is a cosine waveform that is connected to an arbitrary natural number of times, and is a second current waveform that imparts a current distortion whose output frequency decreases, and a cosine waveform that is an arbitrary natural number of concatenations of one period of the waveform, and its output frequency A first current waveform that gives rise to current distortion, a cosine waveform obtained by connecting half of the waveform for any odd number of times, and third current that gives current distortion at a frequency equal to the commercial power frequency. Current waveform order The phase of the inverter output current coincides with the phase of the load voltage at the peak point of the load voltage that occurs in the shortest time from the time when the first current waveform completes the output. Good, no difference in its effects.

  In addition, the current distortion imparting means of the embodiment is connected in order of a first current waveform for one cycle, a second current waveform for one cycle, and a third current waveform for a half cycle, and repeatedly outputs them. The phase of the inverter output current coincides with the phase of the load voltage at the peak point of the load voltage that occurs in the shortest time from the time when the second current waveform completes the output. Is a cosine waveform that is connected in an arbitrary natural number of times, and a first current waveform that imparts a current distortion that increases its output frequency, and a cosine waveform that is connected in an arbitrary odd number of half cycles of the waveform, and its output frequency Is a third current waveform that gives a current distortion having a frequency equal to the commercial power frequency, a cosine waveform obtained by concatenating one period of the waveform for an arbitrary natural number of times, and a second current waveform that gives a current distortion whose output frequency decreases. Current waveform order The phase of the inverter output current coincides with the phase of the load voltage at the peak point of the load voltage that occurs in the shortest time from the time when the second current waveform completes the output. Good, no difference in its effects.

  In addition, the current distortion imparting means of the embodiment is connected in order of a first current waveform for one cycle, a second current waveform for one cycle, and a third current waveform for a half cycle, and repeatedly outputs them. The phase of the inverter output current coincides with the phase of the load voltage at the peak point of the load voltage that occurs in the shortest time from the time when the second current waveform completes the output. Is a cosine waveform connected with an arbitrary natural number of times, and a second current waveform giving a current distortion whose output frequency falls, a cosine waveform connected with an arbitrary odd number of half cycles of the waveform, and its output frequency Is a third current waveform that imparts current distortion having a frequency equal to the commercial power frequency, a cosine waveform obtained by connecting one period of the waveform to an arbitrary natural number of times, and first current distortion that increases the output frequency. Current waveform order The phase of the inverter output current coincides with the phase of the load voltage at the peak point of the load voltage that occurs in the shortest time from the time when the first current waveform completes the output. Good, no difference in its effects.

  In addition, the current distortion applying means of the embodiment, the elapsed time from the timing when the polarity of the load voltage changes from negative to positive and the timing after which the polarity of the detected load voltage changes from negative to positive Voltage cycle calculation means that determines the moving average of the load voltage cycle obtained by dividing by the number of occurrences of the load voltage appearing in time as the voltage cycle, and the timing at which the polarity of the load voltage changes from negative to positive Peak point detecting means for determining, as a peak point, a timing at which a period corresponding to one quarter of the voltage period has elapsed and a timing at which a period corresponding to three quarters of the voltage period has elapsed. However, the elapsed time between the timing when the polarity of the load voltage changes from positive to negative and the timing when the polarity of the detected load voltage changes from positive to negative is included in the elapsed time. Voltage cycle calculating means for determining a moving average of the load voltage cycle obtained by dividing by the number of occurrences of the appearing load voltage for one cycle as the voltage cycle, and the voltage from the timing when the polarity of the load voltage varies from positive to negative Peak point detection means may be provided for determining, as a peak point, a timing at which a period corresponding to one quarter of the period has elapsed and a timing at which a period corresponding to three quarters of the voltage period has elapsed. There is no difference in function and effect.

  Note that the current distortion applying means of the embodiment is such that when the frequency of the load voltage is outside the predetermined frequency section including the rated frequency, the inverter output frequency changes in the positive feedback loop according to the frequency change of the load voltage. A current waveform that gives such current distortion, and as a result, when the frequency of the load voltage is outside the range of the predetermined frequency section including the rated frequency, the operation with the AC power system is separated and the single operation is performed. However, if the frequency of the load voltage is outside the range of the predetermined frequency section including the rated frequency, it is immediately determined that the independent operation is started after leaving the link with the AC power system. It does not matter, and there is no difference in its effect.

  When performing grid-linked operation with a commercial power supply using the inverter device of the present invention attached to a power generation facility, it is possible to detect isolated operation with good sensitivity and to have a lot of inductive loads such as motors and transformers. It can also be applied to the use of an inverter device attached to a power generation facility installed in, for example.

The block diagram which shows the Example of this invention (A), (b) The time chart which shows the timing of the same load voltage Vo of the same inverter apparatus, and the peak point synchronizing signal PS (A), (b), (c), (d), (e) Reading of the load voltage Vo, the peak point synchronization signal PS, and the address pointer AP in the normal operation state where the inverter device is not in the single operation state. Time chart showing timing of increase rate Rc, address pointer AP, and inverter output current Io (A), (b), (c) Time chart showing timings of the load voltage Vo, the peak point synchronization signal PS, and the inverter output current Io in a normal operation state where the inverter device is not in a single operation state. Relationship diagram between load voltage frequency measurement value Fi measured in the current cycle of the inverter device and output current frequency set value Fo controlled by the current distortion applying means in the next cycle. Frequency spectrum diagram showing the relationship between the order of the output current harmonic and the ratio of the amplitude of the harmonic to the fundamental wave component using the frequency fluctuation rate ζ of the inverter as a parameter Relationship between period variation rate ζ and output current distortion rate THDi of the same inverter device, and relationship diagram between cf value of conventional inverter device and output current distortion rate THDi A characteristic diagram of the dead zone obtained by plotting the limit point of the parallel equivalent capacitance value that operates as a dead zone against the arbitrary parallel equivalent inductance value of the inverter device. Configuration diagram of a conventional inverter device that adopts the conventional frequency shift method as an isolated operation detection method Flow chart showing the detection operation procedure of a conventional inverter device that employs the same frequency shift method as an isolated operation detection method (A), (b) The time chart which shows the timing of the voltage of the alternating current power system by the same independent operation detection method, and the output current of the conventional inverter apparatus (A), (b) The time chart which shows the timing of the voltage of the alternating current power system by the same independent operation detection method, and the output current of the conventional inverter apparatus Time chart showing the timing of the output current of the inverter device when the AC power system is normal Time chart showing the timing of the output current of the inverter device when the AC power system is normal Frequency spectrum diagram showing the relationship between the order of the output current harmonics using the cf value of the inverter device as a parameter and the ratio of the harmonic amplitude to the fundamental wave component A characteristic diagram of the dead zone obtained by plotting the limit point of the parallel equivalent capacitance value that operates as a dead zone against any parallel equivalent inductance value for the inverter device. Relationship diagram between cf value and distortion rate THDi of output current examined for the inverter device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 DC power supply 2 Inverter apparatus 3 AC power system 7 Load 10 Inverter main circuit 13 Current distortion provision means 19 Voltage cycle calculation means 20 Peak point detection means 28 Frequency abnormality detection means

Claims (14)

The DC power is converted to AC while being linked to the AC power system, supplied to the load, and the frequency fluctuation occurring in the inverter output voltage when starting the independent operation after leaving the linkage with the AC power grid, or the frequency fluctuation In an inverter device having an isolated operation detecting means for detecting an isolated operation and detecting an isolated operation of the inverter main circuit, a peak point of the output voltage of the inverter device so that the frequency of the output current of the inverter device varies. The output current of the inverter output current is continuous and the frequency of the inverter output current is discontinuous, and the current distortion is applied to the load voltage. If the frequency is within the range of the specified frequency section including the rated frequency, the waveform for one cycle is arbitrarily set to any natural number of times. A connected cosine waveform that gives a current distortion that increases its output frequency, and a current that is a cosine waveform obtained by connecting one cycle of the waveform to an arbitrary natural number of times and whose output frequency decreases. A second current waveform for applying distortion, and a third current waveform for applying a current distortion having a frequency equal to the commercial power frequency, which is a cosine waveform obtained by connecting a half period of the waveform for an arbitrary odd number of times. Are combined and repeatedly output, and at the peak point of the load voltage generated in the shortest time from the time when the first current waveform and the second current waveform complete the output, the phase of the inverter output current is the load Concatenate current waveforms that give current distortion at the peak point so that the phase or phase of the voltage is consistent and the frequency increases, decreases, or does not vary so that it matches the phase of the voltage Inverter device that can reduce the loss consumed by the inductive load caused by the harmonic current by reducing the harmonic current of the output current and improving the isolated operation detection sensitivity. . The first current waveform for one cycle, the second current waveform for one cycle, and the third current waveform for half cycle are connected in order and output repeatedly, and the second current waveform completes output 2. The inverter device according to claim 1, further comprising: a current distortion applying unit configured such that a phase of an inverter output current coincides with a phase of a load voltage at a peak point of a load voltage generated in a shortest time from . The second current waveform for one cycle, the first current waveform for one cycle, and the third current waveform for a half cycle are connected in order and repeatedly output, and when the first current waveform completes output 2. The inverter apparatus according to claim 1, further comprising: a current distortion applying unit configured such that a phase of an inverter output current coincides with a phase of a load voltage at a peak point of a load voltage generated in a shortest time from . When the first current waveform for one cycle, the third current waveform for half a cycle, and the second current waveform for one cycle are connected in order and output repeatedly, and the second current waveform completes output 2. The inverter device according to claim 1, further comprising: a current distortion applying unit configured such that a phase of an inverter output current coincides with a phase of a load voltage at a peak point of a load voltage generated in a shortest time from . When the second current waveform for one cycle, the third current waveform for one half cycle, and the first current waveform for one cycle are connected in order and output repeatedly, and the first current waveform completes output 2. The inverter device according to claim 1, further comprising: a current distortion applying unit configured such that a phase of an inverter output current coincides with a phase of a load voltage at a peak point of a load voltage generated in a shortest time from . The first current waveform, the second current waveform, and the third current waveform are connected in order and repeatedly output. At the peak point of the load voltage generated in the shortest time from the time when the second current waveform completes the output. 2. The inverter device according to claim 1, further comprising: the current distortion applying means configured such that the phase of the inverter output current matches the phase of the load voltage. At the peak point of the load voltage generated in the shortest time from the time when the first current waveform completes the output, the second current waveform, the first current waveform, and the third current waveform are connected in order and output repeatedly. 2. The inverter device according to claim 1, further comprising: the current distortion applying means configured such that the phase of the inverter output current matches the phase of the load voltage. At the peak point of the load voltage generated in the shortest time from the time when the second current waveform is output, the first current waveform, the third current waveform, and the second current waveform are connected in order and output repeatedly. 2. The inverter device according to claim 1, further comprising: the current distortion applying means configured such that the phase of the inverter output current matches the phase of the load voltage. The second current waveform, the third current waveform, and the first current waveform are connected in order and repeatedly output, and at the peak point of the load voltage generated in the shortest time from the time when the first current waveform completes the output. 2. The inverter device according to claim 1, further comprising: the current distortion applying means configured such that the phase of the inverter output current matches the phase of the load voltage. The current distortion applying means appears within the elapsed time from the timing when the polarity of the load voltage changes from negative to positive and the timing after which the polarity of the detected load voltage changes from negative to positive. A voltage cycle calculating means for determining, as a voltage cycle, a moving average of a load voltage cycle obtained by dividing by the number of occurrences of one load voltage cycle, and from the timing at which the polarity of the load voltage changes from negative to positive 2. A peak point detecting means for determining, as a peak point, a timing at which a period corresponding to a quarter has elapsed and a timing at which a period corresponding to three quarters of the voltage period has elapsed. The inverter device according to claim 1, 2, 3, 4, 5, 6, 7, 8. The current distortion applying means causes the elapsed time until the timing when the polarity of the load voltage changes from positive to negative and the timing when the polarity of the detected load voltage changes from positive to negative appears within the elapsed time. A voltage cycle calculating means for determining, as a voltage cycle, a moving average of a load voltage cycle obtained by dividing by the number of occurrences of one load voltage cycle, and from the timing at which the polarity of the load voltage varies from positive to negative 2. A peak point detecting means for determining, as a peak point, a timing at which a period corresponding to a quarter has elapsed and a timing at which a period corresponding to three quarters of the voltage period has elapsed. The inverter device according to claim 1, 2, 3, 4, 5, 6, 7, 8. The current distortion applying means calculates the elapsed time from the timing when the polarity of the load voltage changes from positive to negative or from negative to positive until the next timing when the polarity of the load voltage changes from positive to negative or from negative to positive. And a voltage frequency detecting means for detecting twice the reciprocal of the half cycle as the frequency of the load voltage. The inverter apparatus of Claim 8 or Claim 9. The current distortion applying means is a current that causes the inverter output frequency to change in a positive feedback loop in accordance with a change in the frequency of the load voltage when the frequency of the load voltage is outside the range of the predetermined frequency section including the rated frequency. 10. The inverter device according to claim 1, wherein a current waveform for imparting distortion is output. When the frequency of the load voltage is outside the range of the predetermined frequency section including the rated frequency, the current distortion applying means determines a frequency abnormality detection means that determines that the independent operation is started after leaving the link with the AC power system. 10. The inverter device according to claim 1, 2, 3, 4, 5, 6, 7, 8 or 9.

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