JP2005287135A - Inverter device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inverter device which carries a single operation detecting method which can reduce a loss to be consumed by an inductive load generated due to the cause of a harmonic current with good single operation detecting sensitivity by suppressing the current distortion factor of an output current with small harmonic component of the output current even if a dead zone region is reduced to raise the single operation detecting sensitivity. <P>SOLUTION: The inverter device includes a current distortion giving means 13 for giving a current distortion in which the frequency of the inverter output current accompanies discontinuous frequency change in the frequency of the inverter output current with continuous displacement or phase of the inverter output current in the peak point of the inverter output and a predetermined zone near it to generate the change in the output frequency of the inverter device 1. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a wind power generator that generates power using wind energy, a power generation facility that generates power using solar energy, and a fuel that generates power using fuel such as hydrogen that does not cause pollution. When DC power obtained from power generation facilities such as batteries is returned to AC power and grid-linked operation with commercial power is performed, it is pointed out in the distributed power grid linkage technical guidelines issued by the Japan Electric Association. The frequency shift method (frequency drift method) has been adopted as an active method for detecting isolated operation when the private power generation equipment is not disconnected from the system during a power outage of the AC power system, that is, when it becomes isolated operation. The present invention relates to an inverter device that performs system linkage.

  Conventionally, an inverter device that employs this type of frequency shift method as an active isolated operation detection method is that the AC power system gives a frequency bias to the output of the distributed power supply device during normal operation, and the AC power system during the transition to isolated operation. There is known a method of detecting a change in frequency appearing in a voltage to detect a single operation state (see, for example, Patent Document 1).

  Hereinafter, the configuration of the inverter apparatus that employs the frequency shift method as the isolated operation detection method will be described with reference to FIG. As shown in the figure, the DC power supplied from the DC power source 101 is converted into AC power by being linked to the AC power system 103 by the inverter device 102 and supplied to the load 104. Separately from the inverter device 102, AC power from the AC power system 103 is supplied to the load 104 via a circuit breaker 105 and a pole transformer 106. An over frequency relay (hereinafter referred to as OFR) 107 for monitoring the upper limit value fmax of the frequency of the voltage applied to the load 104 and an under frequency relay (hereinafter referred to as UFR) 108 for monitoring the lower limit value fmin of the same frequency are provided. The inverter device 102 is connected so that it can be detected that the frequency exceeds the range of the upper and lower limit values. As shown in FIG. 15, the load 104 can be expressed by an equivalent circuit including a parallel resonance circuit including a parallel equivalent resistor 109, a parallel equivalent inductance 110, and a parallel equivalent capacitance 111.

  Hereinafter, a detection operation procedure of the conventional inverter device 102 adopting the conventional frequency shift method as the isolated operation detection method will be described with reference to FIG. In the following description, description will be made assuming a grid cooperative operation in which the rated frequency of the AC power system is f0 (for example, 60 Hz).

  If the AC power system 103 is normal, the inverter device 102 employing the conventional frequency shift method sets the frequency f of the voltage of the AC power system 103 to approximately f = f0 [Hz] in step 113 of the flowchart shown in FIG. (Here, f0 is a rated frequency of the AC power system, for example, 50 Hz), but it is determined in step 114 that it is within the range of (f0−fa) to (f0 + fa). 16, step 112 → 113 → 114 → 115 → 116 → 117 → 118 → 119 → 113, 112 → 113 → 114 → 115 → 116 → 120 → 118 → 119 → 113, or 112 → 113 → Repeat the loop 114 → 115 → 116 → 121 → 118 → 119 → 113 to obtain a frequency via F = f0, that is, the output current of the frequency of F = (f0 + Δf) obtained by applying the bias of + Δf to the rated frequency f0 while inserting the output current of the rated frequency, or the bias of −Δf to the rated frequency f0 Output current having a frequency of F = (f0−Δf) is alternately output.

  When the AC power system 103 has a power failure, when the inverter device 102 outputs an output current of frequency = (f0 + Δf) in step 121 of the previous cycle, in step 113, the frequency f of the voltage of the AC power system 103 is Equal to the frequency of the output current of the device 102 = (f0 + Δf), and it is determined in step 114 that the inverter device 102 is outside the range of (f0−fa) to (f0 + fa). (> F0), and the loop of step 112 → 113 → 114 → 122 → 123 → 118 → 119 → 113 shown in FIG. 16 is repeated to increase the frequency of the output current, and this loop is repeated several times. By the way, the inverter which detected the signal of OFR which was monitoring frequency upper limit fmax The apparatus 102 executes step 124, detects that it has entered the single operation state, and stops the output.

  Further, when the AC power system 103 has a power failure, when the inverter device 102 outputs an output current having a frequency F = (f0−Δf) in Step 121 of the previous cycle, in Step 113, the voltage of the AC power system 103 is changed. The frequency f is detected as F = (f0−Δf) equal to the frequency of the output current of the inverter device 102, and the inverter device 102 is outside the range of (f0−fa) to (f0 + fa) in step 114. In step 122, since it is determined that (<f0), the loop of step 112 → 113 → 114 → 122 → 125 → 118 → 119 → 113 shown in FIG. 16 is repeated to reduce the frequency of the output current, When this loop is repeated several times, the signal of the UFR 108 that has monitored that the frequency lower limit fmin has been reached. Inverter apparatus 102 that has detected this executes step 124, detects that it has entered the single operation state, and stops output.

  Hereinafter, the timing of the voltage of the AC power system 103 and the output current of the conventional inverter device 102 according to the conventional isolated operation detection method will be described with reference to FIGS. 17 and 18. 17A shows a voltage waveform of the AC power system 103 and an inverter output current waveform to which a distortion giving a frequency variation higher than the rated voltage of the AC power system 103 is given, and FIG. 17B shows an AC power system. 103 shows an inverter output current to which distortion is applied that gives a frequency variation lower than the voltage waveform of 103 and the rated voltage of the AC power system 103. In the figure, a waveform indicated by a dotted line indicates a voltage waveform of the AC power system 103, and a waveform indicated by a solid line indicates an output current waveform of the inverter device 102.

  As shown in FIG. 17A, the conventional inverter device 102 outputs a slightly distorted current in which a predetermined period tz whose end point is the zero cross point is zero, so that the frequency of the output current increases. T0 shown in FIG. 17A is a half cycle of the voltage waveform of the AC power system, and t1 is a half cycle of the sine waveform portion of the output current waveform of the inverter device 102. Here, the half cycle of the voltage waveform, that is, the ratio of the zero time tz to t0 is called chopping friction cf (hereinafter referred to as cf value). Since the output current of the inverter 102 shown in FIG. 17A has a fundamental wave component having a half cycle t1 shorter than the rated half cycle t0 of the AC power system voltage, the rated frequency f0 of the AC power system voltage in the first half cycle. Higher frequency. When the output current of the inverter device 102 reaches zero before the next second half cycle begins, the output current remains zero for the period of time tz until the next half cycle of the AC power system voltage begins. Continue. For the next half cycle, only the output current of the inverter device 102 and the direction of the AC power system voltage are reversed, and a current with the same distortion as the first half cycle is output.

  As shown in FIG. 17B, the inverter device 102 is slightly distorted to output an arbitrary current on the descending waveform path side from the peak point of the output current waveform to the zero cross point so that the frequency of the output current decreases. Output current. T <b> 2 shown in FIG. 17B is a half cycle of the sine waveform portion of the output current waveform of the inverter device 102. Since the output current of the inverter 102 shown in FIG. 17B has a fundamental wave component having a half cycle t2 longer than the rated half cycle t0 of the AC power system voltage in the first half cycle, the output current is lower than the rated frequency f0. Become. For the next half cycle, only the output current of the inverter 102 and the direction of the AC power system voltage are reversed, and a current with the same distortion as the first half cycle is output.

  The inverter output current waveform is distorted by the inverter device 102 as shown in FIG. 17A, and as shown in FIG. 18A, a predetermined period tz including zero cross points on both sides centering on the peak point. May be applied to the inverter output so that the apparent half cycle t1 of the output current of the inverter device 102 is shorter than the half cycle t0 of the rated frequency. Is higher than the rated frequency f0.

  Furthermore, as shown in FIG. 17 (b), as shown in FIG. 18 (b), a distortion that outputs an arbitrary current output at the zero cross points on both sides centering on the peak point is added to the inverter output waveform. Also good. Then, the apparent half cycle t2 of the output current of the inverter device 102 becomes longer than the half cycle t0 of the rated frequency, and as a result, the frequency of the output current becomes lower than the rated frequency f0.

  Hereinafter, when the inverter device 102 is controlled according to the detection operation shown in the flowchart of FIG. 16 using the method of distorting the output current of the inverter device 102 as shown in FIGS. The output current waveform of the inverter device 102 when the power system is normal will be described with reference to FIG. In the figure, a current waveform for one cycle of a frequency equal to the rated frequency of the AC power system 103 is inserted between the current waveforms to which the distortion described in the explanation of FIG. In the figure, a waveform indicated by a dotted line indicates a voltage waveform of the AC power system 103, and a waveform indicated by a solid line indicates an output current waveform of the inverter device 102.

  Further, when the inverter device 102 is controlled according to the detection operation shown in the flowchart of FIG. 16 using the method of distorting the output current of the inverter device 102 as shown in FIGS. The output current waveform of the inverter device 102 when the power system is normal will be described with reference to FIG. In the figure, a current waveform for one cycle of a frequency equal to the rated frequency of the AC power system 103 is inserted between the current waveforms to which the distortion described in the explanation of FIG. In the figure, a waveform indicated by a dotted line indicates a voltage waveform of the AC power system 103, and a waveform indicated by a solid line indicates an output current waveform of the inverter device 102.

  If the output current of the inverter device 102 shown in FIG. 19 is Io and the rated angular frequency of the AC power system voltage is ω0, the Fourier series can be expressed as (Equation 1).

  Here, a0 is a DC component, and an and bn are Fourier coefficients, which can be expressed as (Equation 2), (Equation 3), and (Equation 4), respectively.

  FIG. 21 shows a frequency spectrum showing the relationship between the order of the output current harmonics and the ratio of the amplitude of the harmonics to the fundamental wave component, using the cf value of the conventional inverter device 102 as a parameter. In the figure, the cf value indicates the result of measurement for each of 0.05, 0.02, and 0.01. As apparent from (Equation 1) to (Equation 4), the frequency spectrum becomes a harmonic that is an integral multiple of (ω0 / 3), and the larger the cf value, the larger the amplitude of the harmonic component of the output current. It shows a tendency to become.

  FIG. 22 is a characteristic diagram of the dead zone obtained by plotting the limit point of the parallel equivalent capacitance value that operates as a dead zone with respect to an arbitrary parallel equivalent inductance value in the conventional inverter device 102. That is, for the conventional inverter device 102 employing the conventional frequency shift method, the resistance value of the parallel equivalent resistor 109 of the load 7 described in FIG. 15 is R [Ω], the inductance of the parallel equivalent inductance 110 is L [H], Further, the experimental results of examining the dead band when the capacitance of the parallel equivalent capacitance 111 is C [], the equivalent inductance L is plotted on the horizontal axis, the equivalent capacitance C of the load 7 is plotted on the vertical axis, and the cf value is changed as a parameter. Is FIG. In the experiment, the case where the equivalent resistance R is 14.4Ω is described. In the figure, two dotted lines parallel to the horizontal axis indicate the limit of the equivalent capacitance C that operates as a dead band for any value of the equivalent inductance L when only the OFR 107 or the UFR 108 is used as a passive islanding detection method. This is a plot of points. That is, a region surrounded by two dotted lines parallel to the horizontal axis indicates a dead zone when only the OFR 107 or UFR 108 is used as a passive islanding detection method.

  Next, a curve indicated by a one-dot chain line or a two-dot chain line is a dead band with respect to an arbitrary equivalent inductance L value for the conventional inverter device 102 using only the conventional frequency shift method as an active islanding detection method. The limit point of the equivalent capacitance C which operates is plotted. That is, a region surrounded by a curve indicated by a one-dot chain line or a two-dot chain line indicates a dead zone when only the conventional frequency shift method is used as an active islanding detection method. If the dead zone due to passive islanding and the dead zone due to active islanding do not overlap, it can be said that the entire system has an ideal characteristic with no dead zone. In addition, when the area where the dead zone due to passive islanding and the dead zone due to active islanding overlap is small, it can be said that the entire system has good characteristics with a small dead zone. As is apparent from the figure, it can be seen that better characteristics can be obtained by selecting a large value for the cf value so that the area where the dead zone overlaps becomes smaller.

  Next, FIG. 23 shows the relationship between the cf value of the conventional inverter device 102 and the distortion rate THDi of the output current. As shown in the figure, it can be seen that the relationship between the cf value and the current distortion rate THDi is linearly proportional. In general, it is known that as the current distortion rate THDi increases, the loss consumed by inductive loads such as transformers and various rotating electrical machines connected to the AC power system increases. The characteristics shown in FIG. From this, it can be seen that as the cf value is increased, the loss consumed by the inductive load or the like increases.

As described above, in the active isolated operation method using the conventional frequency shift method, the cf value is increased in order to reduce the dead zone region or eliminate the dead zone region and improve the isolated operation detection sensitivity. Then, there is a problem that the current distortion rate THDi increases and the loss consumed by the inductive load increases.
JP-A-8-134656

  In such a conventional inverter device, in order to increase the isolated operation detection sensitivity, if the cf value is set large and the dead zone region is reduced, the harmonic component of the output current of the inverter device increases, and the current distortion rate of the output current increases. There is a problem that the loss consumed by the inductive load connected to the AC power system generated due to the harmonic current increases and the AC power system generated due to the harmonic current It is required to reduce the loss consumed by the connected inductive load.

  The present invention solves such a problem, and in order to increase the isolated operation detection sensitivity, even if the dead zone region is reduced, the harmonic component of the output current is small, and the current distortion rate of the output current is suppressed. An object of the present invention is to provide an inverter device equipped with an islanding operation detection method which has good islanding detection sensitivity and can reduce the loss consumed by the inductive load caused by the harmonic current.

  In order to achieve the above object, the inverter device of the present invention converts DC power to AC while linking DC power to the AC power system, supplies it to the load, and starts independent operation after leaving the link with the AC power system. In the system-linked inverter device having a single operation detecting means for detecting a single frequency operation of the inverter main circuit by detecting a frequency fluctuation generated in the inverter output voltage or a fluctuation caused by the frequency fluctuation, the frequency of the load voltage is the rated frequency. A first current waveform that is a cosine waveform obtained by concatenating one period of the waveform for an arbitrary natural number of times and that imparts a current distortion that increases its output frequency, A cosine waveform in which half the period of the waveform is connected to any odd number of times except 1 and a second current waveform that gives a current distortion whose output frequency decreases is connected and repeated. Or a third current waveform which is a cosine waveform obtained by concatenating half of the waveform for any odd number of times except 1 and imparts a current distortion that increases the output frequency, and 1 of the waveform A cosine waveform obtained by concatenating a period of an arbitrary natural number of times, and a fourth current waveform giving a current distortion whose output frequency decreases is connected and repeatedly output, and the first, second, and third are output. Alternatively, at the peak point of the load voltage that occurs in the shortest time from the time when any one of the fourth current waveforms completes the output, the phase of the inverter output current matches the phase of the load voltage, With current distortion that provides current distortion with a frequency variation in which the displacement or phase is continuous and the frequency is discontinuous at the connection point connecting the first, second, third or fourth current waveforms. It is obtained by the inverter apparatus characterized in that comprises means.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  In addition, a first current waveform that is a cosine waveform for one cycle and that increases its output frequency, and a current distortion that is a cosine waveform for 1.5 half cycles and whose output frequency decreases are shown. The second current waveform to be applied is connected and repeatedly output, and at the peak point of the load voltage generated in the shortest time from the time when the second current waveform completes the output, the phase of the inverter output current is the load voltage The system-linked inverter device according to claim 1, further comprising the current distortion applying unit configured to match the phase of the current distortion.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  In addition, a third current waveform that is a cosine waveform for 1.5 periods and that increases current distortion, and a current distortion that is a cosine waveform for one period and decreases its output frequency are applied. The fourth current waveform is connected and repeatedly output, and at the peak point of the load voltage that occurs in the shortest time from the time when the fourth current waveform completes the output, the phase of the inverter output current is the load voltage The system-linked inverter device according to claim 1, further comprising the current distortion applying unit configured to match the phase.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  In addition, a first current waveform that is a cosine waveform for one cycle and that increases its output frequency, and a current distortion that is a cosine waveform for 1.5 half cycles and whose output frequency decreases are shown. The second current waveform to be applied is connected and repeatedly output, and at the peak point of the load voltage generated in the shortest time from the time when the first current waveform completes the output, the phase of the inverter output current is the load voltage The system-linked inverter device according to claim 1, further comprising the current distortion applying unit configured to match the phase of the current distortion.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  In addition, a third current waveform that is a cosine waveform for 1.5 periods and that increases current distortion, and a current distortion that is a cosine waveform for one period and decreases its output frequency are applied. The fourth current waveform is connected and repeatedly output, and at the peak point of the load voltage generated in the shortest time from the time when the third current waveform completes the output, the phase of the inverter output current is the load voltage The system-linked inverter device according to claim 1, further comprising the current distortion applying unit configured to match the phase.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  Also, a cosine waveform obtained by connecting one cycle of the waveform to an arbitrary natural number of times, a first current waveform that gives a current distortion that increases its output frequency, and a half cycle of the waveform other than 1 A cosine waveform connected odd number of times, and a second current waveform giving a current distortion whose output frequency is lowered is connected and repeatedly output, and the second current waveform is output in the shortest time from the time when the output is completed. 2. The system-linked inverter device according to claim 1, further comprising the current distortion applying means configured to make the phase of the inverter output current coincide with the phase of the load voltage at the peak point of the generated load voltage. Is.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  Also, a cosine waveform obtained by connecting one cycle of the waveform to an arbitrary natural number of times, a first current waveform that gives a current distortion that increases its output frequency, and a half cycle of the waveform other than 1 A cosine waveform that is connected an odd number of times and a second current waveform that gives a current distortion whose output frequency is lowered is connected and repeatedly output, and the first current waveform is output in the shortest time from the completion of output. 2. The system-linked inverter device according to claim 1, further comprising the current distortion applying means configured to make the phase of the inverter output current coincide with the phase of the load voltage at the peak point of the generated load voltage. Is.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  Also, a third current waveform that is a cosine waveform obtained by connecting the half period of the waveform to any odd number of times except 1 and imparts current distortion that increases the output frequency, and one period of the waveform is arbitrarily set. A cosine waveform that is connected several times in nature, and a fourth current waveform that gives a current distortion whose output frequency is lowered is connected and repeatedly output, and the fourth current waveform is output in the shortest time from the time when the output is completed. 2. The system-linked inverter device according to claim 1, further comprising the current distortion applying means configured to make the phase of the inverter output current coincide with the phase of the load voltage at the peak point of the generated load voltage. Is.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  Also, a third current waveform that is a cosine waveform obtained by connecting the half period of the waveform to any odd number of times except 1 and imparts current distortion that increases the output frequency, and one period of the waveform is arbitrarily set. A cosine waveform that is connected several times in nature, and a fourth current waveform that imparts a current distortion whose output frequency decreases is connected and repeatedly output, and the third current waveform is output in the shortest time from the time when the output is completed. 2. The system-linked inverter device according to claim 1, further comprising the current distortion applying means configured to make the phase of the inverter output current coincide with the phase of the load voltage at the peak point of the generated load voltage. Is.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  In addition, the current distortion applying means includes a timing at which the polarity of the load voltage changes from negative to positive and an elapsed time from the timing at which the detected polarity of the load voltage changes from negative to positive within the elapsed time. Voltage cycle calculating means for determining a moving average of the load voltage cycle obtained by dividing by the number of occurrences of the load voltage appearing as one cycle as the voltage cycle, and the voltage from the timing when the polarity of the load voltage varies from negative to positive A peak point detecting means is provided for determining, as a peak point, a timing at which a period corresponding to one-fourth of a period has elapsed and a timing at which a period corresponding to three-fourths of the voltage period has elapsed. The system-linked inverter device according to claim 1, 2, 3, 4, 5, 6, 7, 8 or claim 9.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  Further, the current distortion imparting means includes a timing at which the polarity of the load voltage changes from positive to negative and an elapsed time until a timing at which the detected polarity of the load voltage changes from positive to negative within the elapsed time. Voltage cycle calculating means for determining a moving average of the load voltage cycle obtained by dividing by the number of occurrences of the appearing load voltage for one cycle as the voltage cycle, and the voltage from the timing when the polarity of the load voltage varies from positive to negative A peak point detecting means is provided for determining, as a peak point, a timing at which a period corresponding to one-fourth of a period has elapsed and a timing at which a period corresponding to three-fourths of the voltage period has elapsed. The system-linked inverter device according to claim 1, 2, 3, 4, 5, 6, 7, 8 or claim 9.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  Further, the current distortion applying means may calculate an elapsed time from a timing at which the polarity of the load voltage changes from positive to negative or from negative to positive to a next timing at which the polarity of the load voltage changes from positive to negative or from negative to positive. A voltage frequency detection means for detecting as a half cycle of the load voltage and detecting twice the reciprocal of the half cycle as the frequency of the load voltage is provided. The system-linked inverter device according to claim 7, 8 or claim 9.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  The current distortion applying means may change the inverter output frequency in a positive feedback loop according to the change in the frequency of the load voltage when the frequency of the load voltage is outside the range of the predetermined frequency section including the rated frequency. 10. A system-linked inverter device according to claim 1, wherein a current waveform that gives a current distortion is output.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  In addition, the current distortion imparting means, when the frequency of the load voltage is outside the range of the predetermined frequency section including the rated frequency, the frequency abnormality that determines that the independent operation is started after leaving the link with the AC power system The system-linked inverter device according to claim 1, 2, 3, 4, 5, 6, 7, 8 or claim 9, further comprising detecting means.

  In order to increase the isolated operation detection sensitivity by this means, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the inductivity caused by the harmonic current is generated. It is possible to reduce the loss consumed by the load, and the inverter device equipped with the islanding detection method that has good islanding detection sensitivity and low loss consumed by the inductive load caused by the harmonic current is obtained. It is done.

  According to the present invention, in order to increase the isolated operation detection sensitivity, even if the dead zone region is reduced, the harmonic component of the output current is small, the current distortion rate of the output current is suppressed, and the harmonic current is generated. Inverter device equipped with an islanding detection method that can reduce the loss consumed by the inductive load, has good isolated operation detection sensitivity, and has low loss consumed by the inductive load caused by the harmonic current Can provide.

  The present invention provides a current waveform in which a displacement or a current distortion whose phase is continuous and whose frequency fluctuates is applied in a predetermined section near the peak point and a current distortion in which an output frequency is increased. The first current waveform, the second current waveform that imparts current distortion with a lower output frequency, and the third current waveform having the output frequency equal to the commercial power frequency are combined and connected to repeatedly output the first current waveform. The phase of the inverter output current coincides with the phase of the load voltage at the peak point of the load voltage that occurs in the shortest time from when the current waveform and the second current waveform complete the output. Since the current waveform has the characteristics of both an odd function and the target wave, the Fourier coefficient of the conventional output current is a harmonic sine series and cosine that is a natural multiple of one third of the fundamental frequency. While represented in the sum of the number, the Fourier series of the output currents of the present invention can be expressed only by sine series of harmonics odd multiple of one-fifth of the fundamental frequency. Furthermore, the amplitude of the component in which the angular velocity of the Fourier coefficient of the sine series of the output current of the inverter device according to the present invention is ω0 / 5, 3ω0 / 5, ω0... (2m + 1) ω0 / 5, Since the angular velocity of the Fourier coefficient (Equation 3) of the sine series of the output current Io is substantially equal to the amplitude of the component of ω0 / 3, 2ω0 / 3, ω0... Nω0 / 3, the term of the sine series of the output current of the present invention. Is approximately equal to a conventional sine series term. Therefore, the amplitude of the harmonic component of the output current of the inverter device of the present invention is the same as that of the conventional current having a frequency close to the harmonic component of the output current of the present invention, because there is no cosine series term in the Fourier series of the conventional inverter device. It becomes smaller than the amplitude of the harmonic component of the output current of the inverter device.

  For this reason, the current distortion rate THDi of the inverter device of the present invention is smaller than the current distortion rate THDi of the cf value having the same value as the frequency variation rate ζ. Even if current distortion with frequency fluctuation is applied, the current distortion rate of the output current can be suppressed, so the loss due to the inductive load caused by the harmonic current can be kept to a small value. Compared with the inverter device of No. 1, there is an effect that an inverter device with a good isolated operation detection sensitivity can be obtained in which the loss consumed in the inductive load caused by the harmonic current is smaller.

  In addition, when the frequency of the load voltage is within the range of the frequency section including the rated frequency, the first current waveform that applies current distortion that increases the output frequency and the second that applies current distortion that decreases the output frequency. And the third current waveform with the output frequency equal to the commercial power frequency are repeatedly connected in various permutation combinations, and output to the AC power system immediately after shifting to the single operation. Even if the apparent inverter output frequency increases due to the inductive load connected, or the apparent inverter output frequency decreases due to the capacitive load connected to the AC power system, the current is limited for a certain period. Even if frequency fluctuations due to distortion and frequency fluctuations due to load cancel each other and isolated operation cannot be detected, frequency fluctuations will be encouraged in the next period. Has the effect that the inverter output frequency becomes possible to change reliably, the inverter device can be perfectly detected within a short period of time the transition to a single operation can be obtained.

  In addition, the inverter output current outputs waveforms having the same amplitude but different polarities during a period in which the first to third current waveforms are connected and repeated to complete the output twice. Since the average value of inevitably becomes zero and the direct current component disappears, there is an effect that no adverse effect is caused on various electrical devices that are generated when the direct current component is added to the alternating current power system.

  In addition, the voltage cycle calculation means displays the elapsed time until the timing when the polarity of the load voltage changes from positive to negative and the timing when the polarity of the detected load voltage changes from positive to negative within the elapsed time. The moving average of the load voltage period obtained by dividing by the number of occurrences of one load voltage cycle is determined as the voltage period, and the timing at which the polarity of the load voltage fluctuates from positive to negative The voltage cycle measured from the zero-cross point interval is not affected by the waveform change of the load voltage, and a stable voltage cycle can be obtained. In addition, a low-pass filter by calculating the moving average value of the stable voltage cycle A stable voltage period from which high-frequency components are removed can be obtained by the effect.

  In addition, the voltage cycle calculation means displays the elapsed time from the timing when the polarity of the load voltage changes from negative to positive and the timing when the polarity of the detected load voltage changes from negative to positive within the elapsed time. The moving average of the load voltage period obtained by dividing by the number of occurrences of one load voltage cycle is determined as the voltage period, and the timing at which the polarity of the load voltage fluctuates from negative to positive The voltage cycle measured from the zero-cross point interval is not affected by the waveform change of the load voltage, and a stable voltage cycle can be obtained. In addition, a low-pass filter by calculating the moving average value of the stable voltage cycle A stable voltage period from which high-frequency components are removed can be obtained by the effect.

  In addition, the peak point detection unit is configured to detect a timing at which a period corresponding to a quarter of the voltage cycle determined by the voltage cycle calculation unit from a timing at which the polarity of the load voltage changes from positive to negative and the voltage cycle. It is characterized in that the timing at which a period corresponding to three-quarters has elapsed is determined as a peak point, and the stable voltage cycle average value determined by the voltage cycle calculation means from the zero cross point reference point is four minutes. As the peak point is determined as the time when one-third and three-quarters of the time have elapsed, the peak point can be obtained at a stable timing that does not vary the generation timing, and the current based on the peak point can be obtained. It has the effect of ensuring the processing operation of the current distortion applying means of the present invention that applies distortion.

  Also, the voltage frequency detection means loads the elapsed time from the timing when the polarity of the load voltage changes from positive to negative or from negative to positive until the next timing when the polarity of the load voltage changes from positive to negative or from negative to positive. Since the half cycle of the voltage is determined, the period of one cycle of the first current waveform in which the output frequency increases is the period during which the output is completed, or one cycle of the second current waveform in which the output frequency decreases. During the period when the output is completed, the timing at which the polarity of the load voltage changes from positive to negative or from negative to positive always appears once, so the first current waveform and the second current waveform are output. During this period, the timing interval can be determined as a half cycle, and the frequency of the load voltage can be determined reliably during this period. When, an effect that can detect the predetermined frequency range, i.e. can rapidly determine whether outside a predetermined interval A, quickly isolated operation when the transition to the single operation comprising rated frequency.

  In addition, when the frequency of the load voltage is outside the range of the predetermined frequency section including the rated frequency, a current waveform that gives current distortion such that the inverter output frequency changes in the positive feedback loop according to the frequency change of the load voltage. When the inverter device shifts to single operation, the load voltage frequency is accelerated in the positive feedback loop and rapidly fluctuates to determine the single operation. Since the lower limit value is reached, it has the effect that it can quickly detect an isolated operation when shifting to an isolated operation.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing the configuration of the first embodiment, in which DC power supplied from a DC power source 1 is converted into AC power while being linked to an AC power system 3 by an inverter device 2, and a parallel equivalent resistance 4 , A parallel equivalent inductance 5 and a parallel equivalent capacitance 6. Apart from the DC power supplied via the inverter device 2, AC power of the AC power system 3 is supplied to the load 7 via the circuit breaker 8 and the pole transformer 9.

  The inverter device 2 includes an inverter main circuit 10 that converts DC power supplied from the DC power source 1 into AC power while being connected to the AC power system 3 and supplies the AC power to the load 7, and a load voltage Vo supplied to the load 7. A voltage detector 11 for detecting the output current, a current detection circuit 12 for detecting the output current Io output from the inverter main circuit 10, and a load voltage Vo and a current for applying current distortion based on the output current Io Current distortion applying means 13 for generating a gate pulse signal GP for PWM control of the inverter main circuit 10 so that the inverter main circuit 10 is output, and a gate for driving the inverter main circuit 10 by the gate pulse signal GP output from the current distortion applying means 13 A gate drive circuit 14 for generating a drive signal GD is provided. Between the inverter main circuit 10 and the load 7, a filter circuit 18 configured by coils 15 and 16 and a capacitor 17 and removing harmonic components contained in the inverter output is inserted.

  The current distortion applying means 13 includes a voltage period calculating means 19 for calculating a voltage period Tv of the load voltage Vo in consideration of a timing when the polarity of the load voltage Vo detected from the voltage detector 11 changes from negative to positive, and a load voltage Vo. The peak point detecting means 20 for generating the peak point synchronization signal PS by determining the timing at which the polarity of the signal fluctuates from negative to positive and the timing for generating the peak point from the voltage period Tv, the peak point synchronization signal PS and the additional voltage Vo Based on the address pointer generating means 21 that generates the address pointer AP, and the cosine wave pattern stored in the internal memory that has the internal memory and is stored at the address indicated by the address pointer AP, is output as the current waveform data IWD. Current waveform storage means 22 for performing current waveform data IWD as output current setting signal I multiplication means 23 for outputting a product obtained by multiplying et as a current target value Iobj; current deviation calculating means 24 for outputting a difference obtained by subtracting the output current Io measured from the current detector 12 from the current target value Iobj as a current deviation ei; , A PI calculation means 25 for calculating a control amount IY obtained by PI calculation based on the current deviation ei, and a PWM for generating a gate pulse signal GP for PWM control of the inverter main circuit 10 by pulse width modulation of the control amount IY. The modulation means 26, the voltage frequency detection means 27 for detecting the frequency of the load voltage Vo based on the timing at which the polarity of the load voltage Vo fluctuates, and the frequency of the load voltage Vo is monitored. A frequency abnormality detection means 28 for generating a frequency abnormality signal FER for stopping the switching control of the gate drive circuit 14 when exceeding the range; Exceeding the range of the upper and lower limits to monitor the load voltage Vo and a voltage abnormality detection means 29 for generating a voltage error signal VER to stop the switching signal of the gate drive circuit 14.

  Next, processing contents of the voltage cycle calculation unit 19 and the peak point detection unit 20 of the first embodiment will be described. FIGS. 2A to 2B are time charts showing the timing of the load voltage Vo and the peak point synchronization signal PS. The voltage cycle calculation means 19 is a cycle To that is measured from the timing interval one time before the current timing of the timing at which the polarity of the load voltage Vo changes from negative to positive, and the polarity of the load voltage Vo changes from negative to positive. The period T1 measured from the timing interval two times before the timing one time before the timing to perform the timing, and (m−2) times from the timing (m−2) times before the timing when the polarity of the load voltage Vo changes from negative to positive. 1) Measured from the timing Tm-2 measured from the previous timing interval, from the timing (m-1) times before the timing when the polarity of the load voltage Vo changes from negative to positive, from the timing interval m times before The moving average value Tavr obtained by dividing the sum of the periods Tk (k = 0 to (m−1)) by the number m of appearances of one period is calculated from the following equation (5). calculate.

  The arithmetic expression shown in (Equation 5) has an effect as a low-pass filter that suppresses a component that vibrates at a high frequency each time the period is measured by the above-described method, and a stable average period Tavr that suppresses high frequency fluctuations. Is obtained. Depending on the state of the load, the load voltage waveform may be deformed, and the section in which the load voltage Vo is positive and the section in which the load voltage Vo is negative may not be equal, and the polarity of the load voltage Vo varies from negative to positive or from positive to negative. In the method of measuring the half cycle of the load voltage Vo from the timing, that is, the interval of zero crossing, the half cycle measured for each measurement vibrates. However, in the voltage cycle calculation means 19 of this embodiment, the load voltage Vo Since the voltage period is measured from the timing interval at which the polarity of the signal changes from negative to positive, a stable voltage period can be obtained without being affected by the deformation of the load voltage waveform. Further, by calculating the moving average, it is possible to obtain a stable voltage cycle in which fluctuations in high frequency components are suppressed.

  The peak point detection means 20 obtains the average period Tavr calculated by the voltage period calculation means 19 described above, and then the timing when Tavr / 4 has elapsed from the timing when the polarity of the load voltage Vo changes from negative to positive, and 3 Tavr / The timing when 4 has elapsed is determined as a peak point, and a peak point synchronization signal PS as shown in FIG. 2B is generated. In the peak point detection means 20 of the first embodiment, the timing of the polarity of the load voltage Vo, whose generation timing hardly varies due to the influence of the load voltage Vo waveform deformed depending on the load state, is based on the timing at which the polarity changes from negative to positive. In addition, since the peak point is the timing at which one-fourth and three-fourths of the stable average period Tavr obtained by the voltage period calculating means 19 described above from the reference point is used, the generation timing is almost Peak points can be obtained with stable timing that does not vary.

  3A to 3E respectively show a load voltage Vo, a peak point synchronization signal PS, a read increase rate Rc, which will be described later, an address pointer AP, and a normal operation state in which the inverter device 2 is not in a single operation state. 4 is a time chart showing the timing of the inverter output current Io. In FIG. 3 (e), a waveform indicated by a dotted line indicates an image of the load voltage Vo, and a waveform indicated by a solid line indicates the waveform of the output current Io of the inverter device 2.

  By the processing of the voltage cycle calculation means 19 and the peak point detection means 20 described above, the peak point detection means 20 synchronizes with the peak point as shown in FIG. 3B in synchronization with the load voltage Vo shown in FIG. A signal PS is generated.

  Incidentally, the current waveform storage means 22 has a built-in memory. The built-in memory stores cosine wave data having a phase proportional to a deviation address from the address N0 in an arbitrary address for five periods, that is, cosine wave data having a phase in the range of 0 to 10π. Here, cosine wave data having a phase of zero at address N0, a phase of 2π at address N2π, a phase of 5π at address N5π, a phase of 7π at address N7π, and a phase of 10π at address N10π is stored. Suppose you are. The address pointer generating means 21 outputs an address pointer AP that changes at a timing described later. The current waveform storage means 22 outputs cosine wave data stored in the built-in memory at the address indicated by the address pointer AP as current waveform data IWD.

  Next, feedback processing until the output current Io is generated from the inverter device 2 will be described. The multiplication unit 23 multiplies the output current setting signal Iset and the current waveform data IWD to create a current target value Iobj and outputs it to the current deviation calculation unit 24. The current deviation calculation means 24 outputs the difference obtained by subtracting the output current Io measured by the current detector 12 from the current target value Iobj to the PI calculation means 25 as a current deviation ei. The PI calculating means 25 calculates a PI control amount IY obtained by adding a proportional term proportional to the current deviation ei and an integral term proportional to the current deviation integrated value obtained by integrating the current deviation ei for a certain interval, and outputs it to the PWM modulating means 26. . The PWM modulation means 26 generates a gate pulse signal GP for PWM control of the inverter main circuit 10 by performing pulse width modulation on the control amount IY, and outputs it to the gate drive circuit 14. The inverter main circuit 10 PWM-controlled by the gate pulse signal GP through the gate drive circuit 14 outputs the output current Io of the inverter device 2. Here, when the output current Io increases for some reason and exceeds the current target value, the current deviation ei becomes negative. At this time, the PI calculation means 25 calculates so that the control amount IY decreases, As a result of PWM modulation of the inverter main circuit 10 with the PWM signal generated by the PWM modulation means 26 based on the decreased control amount IY, the output current Io decreases. Conversely, when the output current Io decreases for some reason and falls below the current target value, the current deviation ei becomes positive. At this time, the PI calculation means 25 calculates so that the control amount IY increases. As a result of PWM modulation of the inverter main circuit 10 with the PWM signal generated by the PWM modulation means 26 based on the increased control amount IY, the output current Io increases. Such feedback processing is repeated until the deviation current ei matches zero, that is, until the output current Io matches the current target value Iobj, and the output current Io tends to converge to the current target value Iobj. By the way, since current waveform data IWD is generated as cosine wave data created by the processing of the address pointer generating means 21 and the current waveform storage means 22 as will be described later, the current target value Iobj proportional thereto is constantly changing. The output current Io tends to converge to the current target value Iobj so as to follow the fluctuating current target value Iobj. As a result, the output current Io as shown by the solid line in FIG. 3D is generated by the feedback process described above, which follows the current target value Iobj.

  Next, the processing of the address pointer generating means 21 and the current waveform storage means 22 will be described. At the timing (a) when the peak point rises as shown in FIG. 3B, the address pointer generating means 21 sets the read increase rate Rc to an appropriate value Rc1 of 1 or more, and simultaneously resets the built-in counter. In the period T1 from the timing of (a) to the timing of (b) when the address pointer AP shown in FIG. 3D reaches N2π, the address pointer AP has a read increase rate set to a value exceeding 1. The address shown in FIG. 3 (d) is indicated by adding the address N0 to the product obtained by multiplying the internal counter that is being counted up by Rc1. In the period T1, cosine wave data having a phase in the range of 0 to 2π stored in the built-in memory is output from the current waveform storage means 22 as output current data IWD, and the inverter main circuit 10 is PWMed by the feedback processing described above. As a result of the control, the output current Io output from the inverter has a current waveform (hereinafter referred to as a first current waveform) whose frequency increases as shown in FIG.

  At the timing (a), the address pointer generator 21 sets the read increase rate Rc to a value indicated by (Equation 6) and resets the built-in counter.

  At the timing (c) when the address pointer AP reaches N5π, or when the timing (d) at which the peak point in FIG. 3B rises precedes the timing (c), the address at the timing (d) The pointer AP indicates the address shown in FIG. 3D, which is obtained by adding the address N5π to the product obtained by multiplying the internal counter that continues to count up by the read increase rate Rc1. In the period T2 from the timing (a) to the timing (c) or (d), cosine wave data having a phase stored in the internal memory in the range of 2π to 5π is output from the current waveform storage unit 22 as the output current. As a result of PWM control of the inverter main circuit 10 output as data IWD and the above-described feedback processing, the output current Io output from the inverter is a current waveform as shown in FIG. (Referred to as a waveform).

  (Expression 7) is obtained by transforming (Expression 6).

  Assuming that the count value per unit time of the built-in counter is Ct, the built-in counter starts counting from N0 in the period T1 and the period T2, and counts up during the period (T1 + T2) when the count value per unit time is Ct. Since the built-in counter reaches the address value N5π, (Equation 8) is established.

  In the period T1, the address pointer AP starts counting from N0, and the count value per unit time is CtRc1, and the address pointer AD reaches N2π as a result of the count-up operation for the period T1, so (Equation 9) is established. To do.

  In the period T2, the address pointer AP starts counting from N2π, and the count value per unit time is CtRc2, and as a result of counting up during the period T2, the address pointer AD reaches N5π. To do.

  From (Equation 9) and (Equation 10), (Equation 11) is obtained.

  (Expression 12) is obtained by transforming (Expression 8).

  (Equation 13) is obtained from (Equation 7), (Equation 11), and (Equation 12).

  After setting an appropriate value for the read increase rate Rc1 in the period T1, if the read increase rate Rc2 in the section T2 is set by (Equation 6), (Equation 13) is established, and the first and second current waveforms are output. Is a period (T1 + T2) in which the load voltage Vo for 2.5 cycles is equal to the period 2.5T0 in which the output is completed, and the timing at which the first and second current waveforms complete the output is 2.5. The load voltage Vo for the period coincides with the timing for completing the output. That is, if the inverter device 2 is controlled by the current distortion applying means 13 of the inverter device 2 of the first embodiment, the timing at which the first current waveform and the second current waveform complete the output is the timing at which the peak point occurs. At this point, the phase of the output current Io matches the phase of the load voltage Vo, ie, zero (rad).

  At the timing of (c) or (d), the address pointer generator 21 sets the read increase rate Rc to an appropriate value Rc1 of 1 or more again, and resets the built-in counter.

  In a period T3 from the timing of (c) or (d) to the timing of (e) when the address pointer AP shown in FIG. 3 (d) reaches N7π, the address pointer AP keeps counting up. The address shown in FIG. 3D is designated by adding the address N5π to the product obtained by multiplying the read increase rate Rc1 set to a value exceeding 1 by the address N5π. In period T3, cosine wave data having a phase in the range of 5π to 7π stored in the built-in memory is output from the current waveform storage unit 22 as output current data IWD, and the inverter main circuit 10 is PWM-controlled by the feedback processing described above. As a result, as in the case of the above-described T1 period, a first current waveform in which the frequency illustrated in FIG.

  At the timing (e), the address pointer generating means 21 sets the read increase rate Rc to Rc2 indicated by (Equation 6) again, and resets the built-in counter.

  In the period T4 shown in FIG. 3 from the timing of (e) to the timing of the address pointer AP reaching N10π (f), the address pointer AP multiplies the internal counter that keeps counting up by the read increase rate Rc2. The address shown in FIG. 3D is designated by adding the address N7π to the product. In period T4, cosine wave data having a phase of 7π to 10π stored in the built-in memory is output from the current waveform storage means 22 as output current data IWD, and the inverter main circuit 10 is PWM-controlled by the feedback processing described above. As a result, as in the case of the above-described period T2, a second current waveform in which the frequency decreases as illustrated in FIG.

  If the read increase rate Rc2 in the period T4 is set by (Equation 6), for the same reason as described above, the inverter device 2 outputs the first current waveform with increasing frequency and the second current waveform with decreasing frequency. At the peak point that completes the output current Io, the phase of the output current Io coincides with the phase of the load voltage Vo, ie, zero (rad).

  Next, when the timing (a) or the timing (a) ′ at which the peak point of FIG. 3B rises precedes the timing (c), the timing (a) is the timing (a) ′. The same processing as described in the above is repeatedly executed. Thereafter, the same operations as (A) to (A) ′ described above are repeated to continue the operation.

  From the positional relationship shown in FIG. 3, one cycle of the output current Io in the periods T1 and T3 is shorter than one cycle of the load voltage Vo, and 1.5 cycles of the output current Io in the periods T2 and T4 are equal to the load voltage Vo. The inverter device 2 outputs a current waveform that gives a current distortion that increases its output frequency in the T1 and T4 periods, and the output frequency decreases in the T2 and T5 period sections. A current waveform that gives current distortion is output.

  As described above, the connection points connecting the first current waveform with increasing frequency and the second current waveform with decreasing frequency, that is, (a), (b), (c), (d), At the timings (e) and (f), the displacement or phase of the output current Io is continuous, but the frequency becomes discontinuous, and current distortion occurs at this point. In addition, the phase of the output current Io and the phase of the load voltage Vo coincide with each other at the timing (c) or (f) when the output of the second current waveform is completed.

  Next, a detection method for detecting an isolated operation state caused by a power failure of the AC power system 3 and stopping the inverter output will be described.

  First, a passive islanding detection method that is effective only when the reactive power supplied by the inverter device 2 does not match the reactive power requested by the load 7 will be described. In the passive islanding detection method of the first embodiment, when the inverter device 2 enters the islanding state, the frequency of the load voltage Vo suddenly varies from the rated frequency, and the voltage value of the load voltage Vo also varies accordingly. This is detected and isolated operation is detected. The voltage frequency detection means 27 calculates the frequency of the load voltage Vo from the half cycle of the load voltage Vo measured from the timing interval at which the polarity of the load voltage Vo changes from negative to positive or from positive to negative, and the frequency abnormality detection means 28 Monitors that the frequency of the load voltage Vo deviates from the range of the frequency upper limit value OF to the frequency lower limit value UF, and exceeds the frequency upper limit value OF or falls below the frequency lower limit value UF. It detects and outputs the frequency abnormality signal FER to stop the switching operation of the inverter main circuit 10. At the same time, the voltage abnormality detection means 29 monitors that the load voltage Vo, which fluctuates at the same time as the frequency of the load voltage Vo fluctuates, deviates from the voltage upper limit value OV from the voltage lower limit value UV. When the value exceeds OV or falls below the voltage lower limit value UV, the isolated operation is detected, and the voltage abnormality signal VER is output to stop the switching operation of the inverter main circuit 10.

  Next, an active islanding detection method that is effective even when the reactive power supplied by the inverter device 2 substantially matches the reactive power requested by the load 7 will be described. When the reactive power supplied by the inverter device 2 substantially matches the reactive power requested by the load 7, the frequency of the load supply voltage Vo hardly changes even when the inverter device 2 enters the single operation state. The above-mentioned passive islanding detection method that monitors the islanding operation by detecting the abnormal frequency of the frequency of the load voltage Vo and the abnormal voltage detection cannot detect the islanding operation. Therefore, the islanding operation is detected by the active islanding detection method described below. To do.

  FIG. 4 shows the relationship between the load voltage frequency measurement value Fi measured in the current cycle and the output current frequency set value Fo of the inverter device 2 controlled by the current distortion applying means 13 in the next cycle. The voltage frequency detector 27 measures the half cycle of the load voltage Vo from the timing interval at which the polarity of the load voltage Vo changes from negative to positive or from positive to negative, and calculates the frequency of the load voltage Vo. This frequency is defined as a load voltage frequency measurement value Fi measured in the current cycle. The current distortion generating means 13 provides a predetermined section [f0−Δf, f0 + Δf] (hereinafter referred to as a predetermined section A) including the rated frequency f0 shown in FIG. 4 and the frequency of the load voltage Vo is within the range of the predetermined section A. In some cases, the inverter device 2 connects the first and second current waveforms as described above and repeatedly outputs them. When the load voltage frequency measurement value Fi measured in the current cycle falls below the range of the predetermined section A, the output current frequency set value Fo of the inverter device 2 controlled in the next cycle is measured in the current cycle. It is set so as to be even lower than the measured load voltage frequency Fi. Thereafter, the operation of rapidly decreasing the load voltage frequency is repeated, and when the load voltage frequency Fo reaches the frequency lower limit value UF, the isolated operation is detected quickly, and the frequency abnormality signal FER is output to output the inverter main circuit 10. The switching operation is stopped.

  When the load voltage frequency measurement value Fi measured in the current cycle exceeds the range of the predetermined section A, the output current frequency set value Fo of the inverter device 2 controlled in the next cycle is measured in the current cycle. The load voltage Vo is set to be higher than the load voltage frequency measurement value Fi. Thereafter, the operation of rapidly increasing the load voltage frequency is repeated, and when the load voltage frequency Fo reaches the frequency lower limit value OF, the independent operation is detected quickly, and the frequency abnormality signal FER is output to output the inverter main circuit 10. The switching operation is stopped.

  By the way, when the method of calculating the frequency by measuring the half cycle from the timing interval at which the polarity of the load voltage changes is adopted as the isolated operation detection method of the inverter device 2, the apparent load voltage immediately after the transition to the isolated operation Is affected by the type of load 7. For example, when the load 7 is an inductive load, the load voltage Vo immediately after the transition to the single operation becomes a phase that is more advanced than the output current Io, and the timing at which the polarity of the load voltage detected last time changes and is detected immediately after the single operation shifts. The interval of timing at which the polarity of the load voltage changes is shortened, and the apparent load voltage frequency is increased. When the load 7 is a capacitive load, the load voltage immediately after the shift to the single operation is delayed from the inverter output current, the timing at which the polarity of the load voltage detected last time changes, and the load voltage detected immediately after the shift to the single operation The interval of timing when the polarity changes is extended, and the apparent output frequency decreases. Immediately after the transition to isolated operation, if the apparent frequency that varies depending on the state of the load 7 and the frequency variation caused by the distortion current are the same and the direction is reversed, the frequency variation may not occur and may not occur. Even if the operation has shifted to the single operation, the fact that the operation has shifted to the single operation is not easily detected, and the time required for detection may be prolonged.

  Therefore, when it is determined that the frequency of the load voltage Vo is within the range of the predetermined section A, as described above, from the inverter device 2, the first current waveform that applies current distortion increasing in frequency and the frequency If the second current waveform that gives the current distortion that falls is alternately output repeatedly, the frequency fluctuation due to the current distortion and the frequency fluctuation due to the load cancel each other for a certain period, In the period, the peripheral frequency fluctuation is promoted, the output frequency of the inverter device 2 fluctuates reliably, and the load voltage frequency Fi falls below the predetermined section A range or above the predetermined section A range. Since the process in the case of deviating from the predetermined section A is executed, the shift to the single operation can be reliably detected in a short time.

  By the way, the voltage frequency detection means 27 calculates the elapsed time from the timing when the polarity of the load voltage changes from positive to negative or from negative to positive until the next timing when the polarity of the load voltage changes from positive to negative or from negative to positive. Since it is determined as a half cycle of the load voltage, the output of the second current waveform with the output frequency falling is completed during the period when the output current increases for one cycle of the first current waveform Since the timing at which the polarity of the load voltage fluctuates from positive to negative or from negative to positive always appears once every 1.5 cycles, the first and second current waveforms complete the output. During this period, the half cycle can be measured reliably and the frequency of the load voltage can be measured. Therefore, whether or not the load voltage frequency deviates from the predetermined section A when the inverter device shifts to the single operation. Quickly can be determined, it is possible to detect rapidly isolated operation when the transition to independent operation.

  FIG. 5 shows a frequency spectrum showing the relationship between the order of the output current harmonic and the ratio of the amplitude of the harmonic to the fundamental component, using the frequency variation rate ζ of the inverter device 2 of the first embodiment as a parameter. In the figure, the frequency variation rate ζ shows the results of measurement in each case of 0.05, 0.02, and 0.01. That is, from the inverter device 2, one cycle of the first current waveform that applies current distortion with increasing frequency, one cycle of the second current waveform that applies current distortion with decreasing frequency, and the frequency is the commercial power frequency. For the output current waveform shown in FIG. 3 (e), which is output by repeatedly connecting the third half of the current waveform that gives a current distortion having a frequency equal to the frequency, the frequency fluctuation rate ζ of the current waveform is used as a parameter. 3 shows the relationship between the harmonic order of the output current and the ratio of the amplitude of the harmonic component to the fundamental component. Here, as shown in FIG. 3 (e), the period of the current waveform that gives the distortion of increasing (decreasing) frequency is Ti (i = 1, 2, 3,...), And the rated frequency of the load voltage Vo is T0. In other words, the periodic fluctuation rate ζ is set to (Expression 14).

  By the way, the cf value described in the description of the prior art is defined as the ratio of the zero time tz to the half cycle t0 of the voltage waveform expressed by (Equation 15).

  (Equation 16) is established from (Equation 15).

  If the time function of the output current Io of the inverter device 2 is Io (t), the output current Io (t) having a waveform as shown in FIG. Since the characteristics of the target wave shown in (Equation 18) are combined, the Fourier series of the output current Io can be expressed as (Equation 19).

  Here, ωo is the rated angular frequency of the AC power system voltage, and a2m + 1 is a Fourier coefficient as shown in (Equation 20).

  Whereas the Fourier series (Formula 1) of the output current of the conventional inverter device 102 can be expressed as the sum of the sine series, cosine series and average value of harmonics obtained by multiplying one third of the fundamental frequency by a natural number. The Fourier series (Expression 19) of the output current of the inverter device 2 according to the first embodiment can be expressed only by a harmonic sine series obtained by oddly multiplying one fifth of the fundamental frequency. As apparent from the comparison of the Fourier coefficients, the components of the angular velocities of the Fourier coefficients (Equation 3) of the sine series of the output current Io of the conventional inverter device 2 are ω0 / 3, 2ω0 / 3, ω0... Nω0 / 3. The amplitudes are components of which the angular velocities of the Fourier coefficients (Equation 19) of the sine series of the output current Io of the inverter device 2 of Embodiment 1 are ω0 / 5, 3ω0 / 5, ω0 (2m + 1) ω0 / 5, respectively. Since it becomes almost equal to the amplitude, the term of the sine series of the output current in the first embodiment is almost equal to the sine series of the conventional output current. Therefore, the amplitude of the harmonic component of the output current Io of the inverter device 2 according to the first embodiment is equal to the output of the first embodiment by the amount of the cosine series term in the Fourier series (Equation 1) of the conventional inverter device 102. It should be smaller than the amplitude of the harmonic component of the output current Io of the conventional inverter device 102 having a frequency close to the harmonic component of the current.

  17 to FIG. 18 is compared with the output current waveform of the conventional inverter device shown in FIG. 17 and the output current waveform of the inverter device of the first embodiment shown in FIG. 3 (e) corresponds to the difference | Ti−T0 | between the current waveform period Ti (i = 1, 2,... 6) and the rated period T0, and 2t0 in FIGS. 17 to 18 corresponds to the rated period T0 in FIG. Therefore, when 2tz in (Equation 16) is replaced with | Ti-T0 | and 2t0 in (Equation 16) is replaced with T0, (Equation 14) is obtained. That is, the cf value of the conventional inverter device 102 may be considered as an amount corresponding to the periodic fluctuation rate ζ of the first embodiment. FIG. 5 is compared with FIG. 21, and the harmonic current component when the frequency variation rate ζ of FIG. 5 takes values of 0.01, 0.02, and 0.05 has the same cf value of FIG. 21. It can be seen that there is a reduction compared to the harmonic current component in the case of taking values of 0.01, 0.02, and 0.05. As described above, this is in agreement with the opinion comparing the mathematical formulas that the harmonic component of the output current Io of the inverter device 2 of the first embodiment is reduced by the amount of the cosine series term. Yes.

  FIG. 6 shows the relationship between the periodic fluctuation rate ζ and the output current distortion rate THDi of the inverter device 2 according to the first embodiment, and the relationship between the cf value of the conventional inverter device 102 and the output current distortion rate THDi. In the figure, the solid line shows the relationship between the periodic fluctuation rate ζ and the current distortion rate THDi of the inverter device 2 of the first embodiment, and the dotted line shows the relationship between the cf value of the conventional inverter device 102 and the current distortion rate THDi. As is apparent from the figure, at the frequency variation rate ζ having the same value as the cf value, the output current distortion rate THDi of the inverter device 2 of the first embodiment is remarkably reduced as compared with the conventional one. Understand.

  FIG. 7 shows the characteristics of the dead band obtained by plotting the limit point of the value of the parallel equivalent capacitance 6 operating as the dead band with respect to the value of the arbitrary parallel equivalent inductance 5 for the inverter device 2 of the first embodiment. .

  In FIG. 7, the resistance value of the parallel equivalent resistance 4 of the load 7 is R [Ω], the inductance of the parallel equivalent inductance 5 is L [H], and the capacitance of the parallel equivalent capacitance 6 is C []. Is the horizontal axis, the capacitance C is the vertical axis, and the cf value of the conventional example is changed to values of 0.01, 0.02, and 0.05. The experimental result which investigated the dead zone when changing a certain frequency fluctuation rate (zeta) to each value of 0.01, 0.02, and 0.05 is shown. In the experiment, as in the conventional example, the case where the equivalent resistance R is 14.4Ω is examined.

  In the figure, two dotted lines parallel to the horizontal axis indicate an equivalent capacitance C that operates as a dead zone for any value of the equivalent inductance L when only the frequency abnormality detection means 28 is used as a passive islanding detection method. This is a plot of the limit points. That is, a region sandwiched between two dotted lines parallel to the horizontal axis represents a dead zone region when only the frequency abnormality detection means 28 is used as a passive islanding detection method.

  Next, a curve indicated by a one-dot chain line or a two-dot chain line is an arbitrary one for the inverter device 2 that uses only the active islanding detection method by the current distortion applying unit 13 of the first embodiment described above as the islanding operation detection method. The limit point of the equivalent capacitance C operating as a dead zone is plotted against the value of the equivalent inductance L. That is, a region surrounded by a curved line indicated by a one-dot chain line or a two-dot chain line indicates a dead zone when only the active islanding detection method of the first embodiment is used. If the area where the dead zone by the passive islanding detection method overlaps with the dead zone by the active islanding detection method is small, it can be said that the entire system has good characteristics with a small dead zone. As is clear from comparison between FIG. 7 and FIG. 22, the frequency fluctuation rate ζ according to the first embodiment corresponding to the conventional cf value is implemented at each value of 0.01, 0.02, 0.05. The dead zone characteristic of the inverter device 2 of the first embodiment was substantially the same as the dead zone property of the conventional inverter device 102. Next, consider a case where 0.05 is selected as the frequency variation rate ζ, in which the area where the dead zone regions of the active islanding detection method and the passive islanding detection method overlap is the smallest. When 0.05 is selected as the frequency variation rate ζ, the dead band boundary characteristics of the active islanding detection method and the passive islanding detection method of the inverter device 2 of the first embodiment are cf corresponding to the frequency variation rate ζ. Almost the same characteristics as those of the conventional inverter device 102 in which 0.05 is selected as the value can be obtained. Therefore, when the frequency variation rate ζ is selected as 0.05, the dead zone region obtained by the active islanding detection method of the inverter device 2 according to the first embodiment overlaps with the dead zone region obtained by the passive islanding detection method. When 0.05 is selected as the cf value corresponding to the frequency variation rate ζ, substantially the same one as that of the conventional inverter device 102 is obtained. Therefore, the independent operation detection sensitivity of the inverter device 2 according to the first embodiment when 0.05 is selected as the frequency variation rate ζ is the conventional sensitivity when 0.05 is selected as the cf value corresponding to the frequency variation rate. A value almost equal to the isolated operation detection sensitivity of the inverter device 102 is obtained. However, in the description of FIG. 6 described above, the output current distortion rate THDi of the inverter device 2 of the first embodiment is significantly reduced compared to the conventional one at the same level of the frequency fluctuation rate ζ corresponding to the cf value. The loss consumed by the inductive load generated due to the harmonic current can be reduced. That is, when the independent operation detection sensitivity of the inverter device 2 of the first embodiment and that of the conventional inverter device 102 are set to the same performance, the inverter device 2 of the first embodiment has higher harmonics than the conventional inverter device 102. The loss consumed by the inductive load caused by the wave current can be reduced.

  As described above, the current distortion rate of the output current of the inverter device of the first embodiment is higher than that of the conventional inverter device having the same level of isolated operation detection sensitivity as that of the conventional inverter. Since it can be made even smaller than the device, the loss consumed by the inductive load caused by the harmonic current can be reduced compared to the conventional inverter device, the isolated operation detection sensitivity is good, and the harmonic It is possible to provide an ideal inverter device in which the loss consumed by the inductive load caused by the wave current is smaller.

(Embodiment 2)
A description of portions having the same configuration and processing as those of the first embodiment will be omitted, and only different portions will be described.

  FIGS. 8A to 8E respectively show a load voltage Vo, a peak point synchronization signal PS, and a read increase rate Rc, which will be described later, in a normal operation state where the inverter device 2 of the second embodiment is not in the single operation state. 4 is a time chart showing the timing of an address pointer AP and an inverter output current Io. In FIG. 8E, the waveform indicated by the dotted line indicates the image of the load voltage Vo, and the waveform indicated by the solid line indicates the waveform of the output current Io of the inverter device 2.

  The peak point detecting means 20 shown in FIG. 8 (b) is synchronized with the load voltage Vo shown in FIG. 8 (a) by the processing of the voltage cycle calculating means 19 and the peak point detecting means 20 described in the first embodiment. Such a peak point synchronization signal PS is generated.

  Incidentally, the current waveform storage means 22 has a built-in memory. The built-in memory stores cosine wave data having a phase proportional to a deviation address from the address N0 in an arbitrary address for five periods, that is, cosine wave data having a phase in the range of 0 to 10π. Here, cosine wave data having a phase of zero at address N0, a phase of 3π at address N3π, a phase of 5π at address N5π, a phase of 8π at address N8π, and a phase of 10π at address N10π is stored. Suppose you are. The address pointer generating means 21 outputs an address pointer AP that changes at a timing described later. The current waveform storage means 22 outputs cosine wave data stored in the built-in memory at the address indicated by the address pointer AP as current waveform data IWD.

  Next, the processing of the address pointer generating means 21 and the current waveform storage means 22 will be described. At the timing (a) when the peak point rises as shown in FIG. 8B, the address pointer generator 21 sets the read increase rate Rc to an appropriate value Rc1 of 1 or less, and simultaneously resets the built-in counter. In the period T1 from the timing of (a) to the timing of (b) when the address pointer AP reaches N3π shown in FIG. 8D, the address pointer AP has a read increase rate set to a value exceeding 1. The address shown in FIG. 8D is indicated by adding the address N0 to the product obtained by multiplying the internal counter which is being counted up by Rc1. In period T1, the current waveform storage means 22 outputs cosine wave data having a phase in the range of 0 to 3π stored in the built-in memory as output current data IWD. The inverter main circuit 10 is PWMed by the feedback processing described above. As a result of the control, the output current Io output from the inverter has a current waveform (hereinafter referred to as a second current waveform) with a decreasing frequency as illustrated in FIG.

  At the timing (a), the address pointer generator 21 sets the read increase rate Rc to a value indicated by (Equation 21), and resets the built-in counter.

  The address at the timing (c) when the address pointer AP reaches N5π or when the timing (d) at which the peak point in FIG. 8B rises precedes the timing (c) at the timing (d). The pointer AP indicates the address shown in FIG. 8D, which is obtained by adding the address N5π to the product obtained by multiplying the internal counter that continues to count up by the read increase rate Rc1. In a period T2 from the timing (b) to the timing (c) or (d), cosine wave data having a phase stored in the built-in memory in the range of 3π to 5π is output current from the current waveform storage unit 22. As a result of PWM control of the inverter main circuit 10 output as data IWD and the above-described feedback processing, the output current Io output from the inverter is a current waveform as shown in FIG. (Referred to as a waveform).

  (Equation 22) is obtained by transforming (Equation 21).

  Assuming that the count value per unit time of the built-in counter is Ct, the built-in counter starts counting from N0 in the period T1 and the period T2, and counts up during the period (T1 + T2) when the count value per unit time is Ct. Since the built-in counter reaches the address value N5π, (Equation 23) is established.

  In the period T1, the address pointer AP starts counting from N0, and the count value per unit time is CtRc1, and the address pointer AD reaches N3π as a result of the count-up operation for the period T1, so (Equation 24) is established. To do.

  In the period T2, the address pointer AP starts counting from N3π, and the count value per unit time is CtRc2, and the address pointer AD reaches N5π as a result of the count-up operation during the period T2. To do.

  From (Equation 24) and (Equation 25), (Equation 26) is obtained.

  (Expression 27) is obtained by transforming (Expression 23).

  (Expression 28) is obtained from (Expression 22), (Expression 26), and (Expression 27).

  After setting an appropriate value for the read increase rate Rc1 in the period T1, if the read increase rate Rc2 in the section T2 is set by (Equation 21), (Equation 28) is established, and the second and first current waveforms are output. The period (T1 + T2) in which the load voltage Vo for 2.5 cycles is equal to the period 2.5T0 in which the output is completed, and the timing at which the second and first current waveforms complete the output is 2.5. The load voltage Vo for the period coincides with the timing for completing the output. That is, if the inverter device 2 is controlled by the current distortion applying means 13 of the inverter device 2 according to the second embodiment, the timing at which the second and first current waveforms complete the output coincides with the timing at which the peak point occurs. At this point, the phase of the output current Io coincides with the phase of the load voltage Vo, that is, zero (rad).

  At the timing of (c) or (d), the address pointer generator 21 sets the read increase rate Rc to an appropriate value Rc1 of 1 or less again, and resets the built-in counter.

  In the period T3 from the timing of (c) or (d) to the timing of (e) when the address pointer AP shown in FIG. 8D reaches N8π, the address pointer AP keeps counting up. The address shown in FIG. 8D is indicated by adding the address N5π to the product obtained by multiplying the read multiplication rate Rc1 set to a value exceeding 1 by the address N5π. In period T3, cosine wave data having a phase in the range of 5 to 8π stored in the built-in memory is output as output current data IWD from the current waveform storage means 22, and the inverter main circuit 10 is PWM-controlled by the feedback processing described above. As a result, as in the case of the T1 period described above, a second current waveform in which the frequency illustrated in FIG.

  At the timing (e), the address pointer generating means 21 sets the read increase rate Rc to Rc2 indicated by (Equation 6) again, and resets the built-in counter.

  In the period T4 shown in FIG. 8 from the timing of (e) to the timing of the address pointer AP reaching N10π (f), the address pointer AP multiplies the internal counter that keeps counting up by the read increase rate Rc2. The address shown in FIG. 8D is indicated by adding the address N8π to the product. In period T4, cosine wave data having a phase stored in the built-in memory in the range of 8π to 10π is output as output current data IWD from the current waveform storage means 22, and the inverter main circuit 10 is PWM-controlled by the feedback processing described above. As a result, as in the case of the period T2 described above, a second current waveform with a decreasing frequency as shown in FIG. 8E is generated.

  If the read increase rate Rc2 in the period T4 is set by (Equation 6), for the same reason as described above, the output current Io at the peak point where the first current waveform whose frequency rises from the inverter device 2 completes the output. Is in phase with the load voltage Vo, ie, zero (rad).

  Next, when the timing (a) or the timing (a) ′ at which the peak point of FIG. 8B rises precedes the timing (c), the timing (a) is the timing (a) ′. The same processing as described in the above is repeatedly executed. Thereafter, the same operations as (A) to (A) ′ described above are repeated to continue the operation.

  From the positional relationship shown in FIG. 8, 1.5 period of the output current Io in the periods T1 and T3 is longer than 1.5 period of the load voltage Vo, and one period of the output current Io in the periods T2 and T4 is the load voltage. It becomes shorter than one cycle of Vo, and the inverter device 2 outputs a current waveform that gives a current distortion in which the output frequency decreases in the T1 and T3 periods, and the output frequency increases in the T2 and T5 period sections. A current waveform that gives current distortion is output.

  As described above, the connection points connecting the first current waveform with increasing frequency and the second current waveform with decreasing frequency, that is, (a), (b), (c), (d), At the timings (e) and (f), the displacement or phase of the output current Io is continuous, but the frequency becomes discontinuous, and current distortion occurs at this point. In addition, the phase of the output current Io and the phase of the load voltage Vo coincide with each other at the timing (c) or (f) when the output of the second current waveform is completed.

  As described above, in the second embodiment, for the same reason as described in the first embodiment, the second distortion is applied that is a cosine waveform for 1.5 cycles and the output frequency thereof decreases. And a first current waveform that is a cosine waveform for one cycle and imparts a current distortion that increases its output frequency are repeatedly output and the output of the first current waveform is completed. At the peak point of the load voltage generated in the shortest time from the point in time, the phase of the inverter output current is made to coincide with the phase of the load voltage, and the displacement or phase at the coupling point connecting the second and first current waveforms. As compared with a conventional inverter device having a single operation detection sensitivity of the same level as that of a conventional inverter, the second embodiment is applied with current distortion accompanied by frequency fluctuations that are continuous and discontinuous in frequency. Since the current distortion rate of the output current of the inverter device can be made smaller than that of the conventional inverter device, the loss consumed by the inductive load caused by the harmonic current is less than that of the conventional inverter device. Therefore, it is possible to provide an ideal inverter device in which the isolated operation detection sensitivity is good and the loss consumed by the inductive load caused by the harmonic current is smaller.

(Embodiment 3)
A description of portions having the same configuration and processing as those of the first embodiment will be omitted, and only different portions will be described.

  FIGS. 9A to 9E respectively show a load voltage Vo, a peak point synchronization signal PS, and a read increase rate Rc described later in a normal operation state where the inverter device 2 of the third embodiment is not in the single operation state. 4 is a time chart showing the timing of an address pointer AP and an inverter output current Io. In FIG. 9 (e), a waveform indicated by a dotted line indicates an image of the load voltage Vo, and a waveform indicated by a solid line indicates a waveform of the output current Io of the inverter device 2.

  By the processing of the voltage cycle calculating means 19 and the peak point detecting means 20 described in the first embodiment, the peak point detecting means 20 is shown in FIG. 9 (b) in synchronization with the load voltage Vo shown in FIG. 9 (a). Such a peak point synchronization signal PS is generated.

  Incidentally, the current waveform storage means 22 has a built-in memory. The built-in memory stores cosine wave data having a phase proportional to a deviation address from the address N0 in an arbitrary address for five periods, that is, cosine wave data having a phase in the range of 0 to 10π. Here, cosine wave data having a phase of zero at address N0, a phase of 3π at address N3π, a phase of 5π at address N5π, a phase of 8π at address N8π, and a phase of 10π at address N10π is stored. Suppose you are. The address pointer generating means 21 outputs an address pointer AP that changes at a timing described later. The current waveform storage means 22 outputs cosine wave data stored in the built-in memory at the address indicated by the address pointer AP as current waveform data IWD.

  Next, the processing of the address pointer generating means 21 and the current waveform storage means 22 will be described. At the timing (a) when the peak point rises as shown in FIG. 9B, the address pointer generating means 21 sets the read increase rate Rc to an appropriate value Rc1 of 1 or more, and simultaneously resets the built-in counter. In the period T1 from the timing of (a) to the timing of (b) when the address pointer AP reaches N3π shown in FIG. 9D, the address pointer AP has a read increase rate set to a value exceeding 1. The address shown in FIG. 9 (d) is designated by adding the address N0 to the product obtained by multiplying the internal counter that is being counted up by Rc1. In period T1, the current waveform storage means 22 outputs cosine wave data having a phase in the range of 0 to 3π stored in the built-in memory as output current data IWD. The inverter main circuit 10 is PWMed by the feedback processing described above. As a result of the control, the output current Io output from the inverter has a current waveform as shown in FIG. 9E (hereinafter referred to as a third current waveform).

  At the timing (a), the address pointer generator 21 sets the read increase rate Rc to a value indicated by (Equation 21), and resets the built-in counter.

  When the address pointer AP reaches N5π (c), or when the timing (d) at which the peak point in FIG. 9B rises (d) precedes the timing (c), the address The pointer AP indicates the address shown in FIG. 9D, which is obtained by adding the address N5π to the product obtained by multiplying the internal counter that continues to count up by the read increase rate Rc1. In a period T2 from the timing (b) to the timing (c) or (d), cosine wave data having a phase stored in the built-in memory in the range of 3π to 5π is output current from the current waveform storage unit 22. As a result of PWM control of the inverter main circuit 10 that is output as data IWD and has been subjected to the above-described feedback processing, the output current Io output from the inverter is a current waveform as shown in FIG. (Referred to as a waveform).

  (Equation 22) is obtained by transforming (Equation 21).

  Assuming that the count value per unit time of the built-in counter is Ct, the built-in counter starts counting from N0 in the period T1 and the period T2, and counts up during the period (T1 + T2) when the count value per unit time is Ct. Since the built-in counter reaches the address value N5π, (Equation 23) is established.

  In the period T1, the address pointer AP starts counting from N0, and the count value per unit time is CtRc1, and the address pointer AD reaches N3π as a result of the count-up operation for the period T1, so (Equation 24) is established. To do.

  In the period T2, the address pointer AP starts counting from N3π, and the count value per unit time is CtRc2, and the address pointer AD reaches N5π as a result of the count-up operation during the period T2. To do.

  From (Equation 24) and (Equation 25), (Equation 26) is obtained.

  (Expression 27) is obtained by transforming (Expression 23).

  (Expression 28) is obtained from (Expression 22), (Expression 26), and (Expression 27).

  After setting an appropriate value for the read increase rate Rc1 in the period T1, if the read increase rate Rc2 in the section T2 is set by (Equation 21), (Equation 28) is established, and the third and fourth current waveforms are output. During the period (T1 + T2), the load voltage Vo for 2.5 cycles is equal to the period 2T0 during which the output is completed, and the timing at which the third and fourth current waveforms complete the output is 2.5 cycles. Load voltage Vo coincides with the timing of completing the output. That is, if the inverter device 2 is controlled by the current distortion applying means 13 of the inverter device 2 according to the third embodiment, a peak point occurs at the timing when the third current waveform and the fourth current waveform complete the output. It coincides with the timing, and at this point, the phase of the output current Io coincides with the phase of the load voltage Vo, that is, zero (rad).

  At the timing of (c) or (d), the address pointer generator 21 sets the read increase rate Rc to an appropriate value Rc1 of 1 or more again, and resets the built-in counter.

  In the period T3 from the timing of (c) or (d) to the timing of (e) when the address pointer AP reaches N8π shown in FIG. 9D, the address pointer AP keeps counting up. The address shown in FIG. 9D is designated by adding the address N5π to the product obtained by multiplying the read multiplication rate Rc1 set to a value exceeding 1 by the address N5π. In period T3, cosine wave data having a phase in the range of 5 to 8π stored in the built-in memory is output as output current data IWD from the current waveform storage means 22, and the inverter main circuit 10 is PWM-controlled by the feedback processing described above. As a result, as in the case of the above-described T1 period, a third current waveform in which the frequency illustrated in FIG.

  At the timing (e), the address pointer generating means 21 sets the read increase rate Rc to Rc2 indicated by (Equation 6) again, and resets the built-in counter.

  In the period T4 shown in FIG. 9 from the timing of (e) to the timing of the address pointer AP reaching N10π (f), the address pointer AP multiplies the internal counter that keeps counting up by the read increase rate Rc2. The address shown in FIG. 9D is designated by adding the address N8π to the product. In period T4, cosine wave data having a phase stored in the built-in memory in the range of 8π to 10π is output as output current data IWD from the current waveform storage means 22, and the inverter main circuit 10 is PWM-controlled by the feedback processing described above. As a result, a fourth current waveform as shown in FIG. 9E is generated as in the case of the period T2 described above.

  If the read increase rate Rc2 in the period T4 is set by (Equation 6), for the same reason as described above, the inverter device 2 outputs the third current waveform in which the frequency increases and the fourth current waveform in which the frequency decreases. At the peak point that completes the output current Io, the phase of the output current Io coincides with the phase of the load voltage Vo, ie, zero (rad).

  Next, when the timing (a) or the timing (a) ′ at which the peak point of FIG. 9B rises precedes the timing (c), the timing (a) is the timing (a) ′. The same processing as described in the above is repeatedly executed. Thereafter, the same operations as (A) to (A) ′ described above are repeated to continue the operation.

  From the positional relationship shown in FIG. 9, the 1.5 period of the output current Io in the T1 and T3 periods is shorter than the 1.5 period of the load voltage Vo, and the one period of the output current Io in the T2 and T4 periods is the load voltage. It becomes longer than one cycle of Vo, and the inverter device 2 outputs a current waveform that imparts current distortion that increases its output frequency in the T1 and T4 periods, and the output frequency decreases in the T2 and T5 period sections. A current waveform that gives current distortion is output.

  As described above, the connection point that connects the third current waveform with increasing frequency and the fourth current waveform with decreasing frequency, that is, (a), (b), (c), (d), At the timings (e) and (f), the displacement or phase of the output current Io is continuous, but the frequency becomes discontinuous, and current distortion occurs at this point. In addition, at the timing of (c) or (f) when the fourth current waveform completes output, the phase of the output current Io and the phase of the load voltage Vo coincide.

  As described above, in the third embodiment, for the same reason as described in the first embodiment, the current distortion that is a cosine waveform corresponding to 1.5 cycles and whose output frequency is increased is added. And a fourth current waveform which is a cosine waveform for one cycle and which gives a current distortion whose output frequency decreases, are repeatedly output and the output of the fourth current waveform is completed. At the peak point of the load voltage generated in the shortest time from the point in time, the phase of the inverter output current is made to coincide with the phase of the load voltage, and the displacement or phase at the coupling point connecting the third and fourth current waveforms. The third embodiment provides a current distortion with a frequency fluctuation that is continuous and discontinuous in frequency, compared with a conventional inverter device having a single operation detection sensitivity of the same level as that of a conventional inverter. Since the current distortion rate of the output current of the inverter device can be made smaller than that of the conventional inverter device, the loss consumed by the inductive load caused by the harmonic current is less than that of the conventional inverter device. Therefore, it is possible to provide an ideal inverter device in which the isolated operation detection sensitivity is good and the loss consumed by the inductive load caused by the harmonic current is smaller.

(Embodiment 4)
A description of portions having the same configuration and processing as those of the first embodiment will be omitted, and only different portions will be described.

  10 (a) to 10 (e) show a load voltage Vo, a peak point synchronization signal PS, and a read increase rate Rc, which will be described later, in a normal operation state where the inverter device 2 of the fourth embodiment is not in a single operation state. 4 is a time chart showing the timing of an address pointer AP and an inverter output current Io. In FIG. 10 (e), a waveform indicated by a dotted line indicates an image of the load voltage Vo, and a waveform indicated by a solid line indicates a waveform of the output current Io of the inverter device 2.

  By the processing of the voltage cycle calculating means 19 and the peak point detecting means 20 described in the first embodiment, the peak point detecting means 20 is shown in FIG. 10 (b) in synchronization with the load voltage Vo shown in FIG. 10 (a). Such a peak point synchronization signal PS is generated.

  Incidentally, the current waveform storage means 22 has a built-in memory. The built-in memory stores cosine wave data having a phase proportional to a deviation address from the address N0 in an arbitrary address for five periods, that is, cosine wave data having a phase in the range of 0 to 10π. Here, cosine wave data having a phase of zero at address N0, a phase of 2π at address N2π, a phase of 5π at address N5π, a phase of 7π at address N7π, and a phase of 10π at address N10π is stored. Suppose you are. The address pointer generating means 21 outputs an address pointer AP that changes at a timing described later. The current waveform storage means 22 outputs cosine wave data stored in the built-in memory at the address indicated by the address pointer AP as current waveform data IWD.

  Next, the processing of the address pointer generating means 21 and the current waveform storage means 22 will be described. At the timing (a) when the peak point rises as shown in FIG. 10B, the address pointer generating means 21 sets the read increase rate Rc to an appropriate value Rc1 of 1 or less, and simultaneously resets the built-in counter. In the period T1 from the timing (a) to the timing (b) when the address pointer AP shown in FIG. 10 (d) reaches N2π, the address pointer AP has a read increase rate set to a value exceeding 1. The address shown in FIG. 10 (d) is designated by adding the address N0 to the product obtained by multiplying the built-in counter being counted up by Rc1. In the period T1, cosine wave data having a phase in the range of 0 to 2π stored in the built-in memory is output from the current waveform storage means 22 as output current data IWD, and the inverter main circuit 10 is PWMed by the feedback processing described above. As a result of the control, the output current Io output from the inverter has a current waveform (hereinafter referred to as a fourth current waveform) as shown in FIG.

  At the timing (a), the address pointer generator 21 sets the read increase rate Rc to a value indicated by (Equation 6) and resets the built-in counter.

  When the address pointer AP reaches N5π (C), or when the peak point (D) at which the peak point in FIG. 10B rises precedes (C) timing, The pointer AP indicates the address shown in FIG. 10D, which is obtained by adding the address N5π to the product obtained by multiplying the internal counter that keeps counting up by the read increase rate Rc1. In the period T2 from the timing (a) to the timing (c) or (d), cosine wave data having a phase stored in the internal memory in the range of 2π to 5π is output from the current waveform storage unit 22 as the output current. As a result of PWM control of the inverter main circuit 10 that is output as data IWD and is performed by the feedback processing described above, the output current Io output from the inverter is a current waveform as shown in FIG. (Referred to as a waveform).

  (Expression 7) is obtained by transforming (Expression 6).

Assuming that the count value per unit time of the built-in counter is Ct, the built-in counter starts counting from N0 in the period T1 and the period T2, and counts up during the period (T1 + T2) when the count value per unit time is Ct. Since the built-in counter reaches the address value N5π, (Equation 8) is established.

  In the period T1, the address pointer AP starts counting from N0, and the count value per unit time is CtRc1, and the address pointer AD reaches N2π as a result of the count-up operation for the period T1, so (Equation 9) is established. To do.

  In the period T2, the address pointer AP starts counting from N2π, and the count value per unit time is CtRc2, and as a result of counting up during the period T2, the address pointer AD reaches N5π. To do.

  From (Equation 9) and (Equation 10), (Equation 11) is obtained.

  (Expression 12) is obtained by transforming (Expression 8).

  (Equation 13) is obtained from (Equation 7), (Equation 11), and (Equation 12).

  After setting an appropriate value for the read increase rate Rc1 in the period T1, if the read increase rate Rc2 in the section T2 is set by (Equation 6), (Equation 13) is established, and the fourth and third current waveforms are output. During the period (T1 + T2), the load voltage Vo for 2.5 cycles is equal to the period 2.5T0 during which the output is completed, and the timing at which the fourth and third current waveforms complete the output is 2.5. The load voltage Vo for the period coincides with the timing for completing the output. That is, if the inverter device 2 is controlled by the current distortion applying means 13 of the inverter device 2 of the fourth embodiment, the timing when the fourth and third current waveforms complete the output coincides with the timing when the peak point occurs. At this point, the phase of the output current Io coincides with the phase of the load voltage Vo, that is, zero (rad).

  At the timing of (c) or (d), the address pointer generator 21 sets the read increase rate Rc to an appropriate value Rc1 of 1 or less again, and resets the built-in counter.

  In the period T3 from the timing of (c) or (d) to the timing of (e) when the address pointer AP shown in FIG. 10 (d) reaches N7π, the address pointer AP keeps counting up. The address shown in FIG. 10D is indicated by adding the address N7π to the product obtained by multiplying the product by the read increase rate Rc1 set to a value exceeding 1. In period T3, cosine wave data having a phase in the range of 5 to 7π stored in the built-in memory is output as output current data IWD from the current waveform storage means 22, and the inverter main circuit 10 is PWM-controlled by the feedback processing described above. As a result, as in the case of the T1 period described above, a fourth current waveform in which the frequency illustrated in FIG.

  At the timing (e), the address pointer generating means 21 sets the read increase rate Rc to Rc2 indicated by (Equation 6) again, and resets the built-in counter.

  In the period T4 shown in FIG. 10 from the timing (e) to the timing (f) when the address pointer AP reaches N10π, the address pointer AP multiplies the internal counter that keeps counting up by the read increase rate Rc2. The address shown in FIG. 10D is designated by adding the address N7π to the product. In period T4, cosine wave data having a phase of 7π to 10π stored in the built-in memory is output from the current waveform storage means 22 as output current data IWD, and the inverter main circuit 10 is PWM-controlled by the feedback processing described above. As a result, as in the case of the above-described period T2, a third current waveform whose frequency is increased as shown in FIG. 10E is generated.

  If the read increase rate Rc2 in the period T4 is set by (Equation 6), for the same reason as described above, the output current Io at the peak point where the third current waveform whose frequency rises from the inverter device 2 completes the output. Is in phase with the load voltage Vo, ie, zero (rad).

  Next, when the timing (a) or the timing (a) ′ at which the peak point of FIG. 10B rises precedes the timing (c), the timing (a) is the timing (a) ′. The same processing as described in the above is repeatedly executed. Thereafter, the same operations as (A) to (A) ′ described above are repeated to continue the operation.

  From the positional relationship shown in FIG. 10, one cycle of the output current Io in the T1 and T3 periods is longer than one cycle of the load voltage, and 1.5 cycles of the output current Io in the T2 and T4 periods is 1 of the load voltage Vo. The inverter device 2 outputs a current waveform that gives a current distortion in which the output frequency decreases during the periods T1 and T3, and the current that increases the output frequency during the periods T2 and T5. A current waveform that gives distortion is output.

  As described above, the coupling point connecting the fourth current waveform with decreasing frequency and the third current waveform with increasing frequency, that is, (a), (b), (c), (d), At the timings (e) and (f), the displacement or phase of the output current Io is continuous, but the frequency becomes discontinuous, and current distortion occurs at this point. In addition, at the timing of (c) or (f) when the third current waveform completes the output, the phase of the output current Io and the phase of the load voltage Vo coincide.

  As described above, in the fourth embodiment, for the same reason as described in the first embodiment, the fourth current is a cosine waveform for one cycle and gives a current distortion in which the output frequency decreases. A waveform and a third current waveform that is a cosine waveform for 1.5 cycles and gives a current distortion that increases its output frequency are connected and repeatedly output, and the output of the third current waveform is completed. At the peak point of the load voltage generated in the shortest time from the point in time, the phase of the inverter output current is made to coincide with the phase of the load voltage, and the displacement or phase at the connection point connecting the fourth and third current waveforms. 4 is compared with a conventional inverter device having a single operation detection sensitivity of the same level as that of a conventional inverter by applying current distortion with continuous frequency fluctuation and discontinuous frequency fluctuation. Since the current distortion rate of the output current of the inverter device can be made smaller than that of the conventional inverter device, the loss consumed by the inductive load caused by the harmonic current is less than that of the conventional inverter device. Therefore, it is possible to provide an ideal inverter device in which the isolated operation detection sensitivity is good and the loss consumed by the inductive load caused by the harmonic current is smaller.

(Embodiment 5)
A description of portions having the same configuration and processing as those of the first embodiment will be omitted, and only different portions will be described.

  11 (a) to 11 (e) show a load voltage Vo, a peak point synchronization signal PS, and a read increase rate Rc, which will be described later, in a normal operation state in which the inverter device 2 of the fifth embodiment is not in a single operation state. 4 is a time chart showing the timing of an address pointer AP and an inverter output current Io.

  By the processing of the voltage cycle calculating means 19 and the peak point detecting means 20 described in the first embodiment, the peak point detecting means 20 is shown in FIG. 11 (b) in synchronization with the load voltage Vo shown in FIG. 11 (a). Such a peak point synchronization signal PS is generated.

  Incidentally, the current waveform storage means 22 has a built-in memory. The built-in memory stores cosine wave data having a phase proportional to a deviation address from the address N0 in an arbitrary address for (2m + n) cycles, that is, cosine wave data having a phase in the range of 0 to (4πm + 2πn). Here, m is an arbitrary natural number, n is an arbitrary odd number excluding 1, an address N0 has a phase of zero, an address N2πm has a phase of 2πm, an address N2πm + πn has a phase of 2πm + πn, an address N4πm + πn has a phase of 4πm + πn, It is assumed that cosine wave data having a phase of 4πm + 2πn is stored in the address N4πm + 2πn, respectively. The address pointer generating means 21 outputs an address pointer AP that changes at a timing described later. The current waveform storage means 22 outputs cosine wave data stored in the built-in memory at the address indicated by the address pointer AP as current waveform data IWD.

  Next, the processing of the address pointer generating means 21 and the current waveform storage means 22 will be described. At the timing (a) when the peak point rises as shown in FIG. 11B, the address pointer generating means 21 sets the read increase rate Rc to an appropriate value Rc1 of 1 or more, and simultaneously resets the built-in counter. In the period T1 from the timing of (a) to the timing of (b) when the address pointer AP shown in FIG. 11 (d) reaches N2πm, the address pointer AP has a read increase rate set to a value exceeding 1. The address shown in FIG. 11 (d) is indicated by adding the address N0 to the product obtained by multiplying the built-in counter that is being counted up by Rc1. In period T1, cosine wave data having a phase in the range of 0 to 2πm stored in the built-in memory is output from the current waveform storage means 22 as output current data IWD, and the inverter main circuit 10 is PWMed by the feedback processing described above. As a result of the control, the output current Io output from the inverter has a current waveform (hereinafter referred to as a first current waveform) as shown in FIG.

  At the timing (a), the address pointer generator 21 sets the read increase rate Rc to a value indicated by (Equation 29) and resets the built-in counter.

  At the timing (c) when the address pointer AP reaches N2πm + πn, or when the timing (d) at which the peak point in FIG. 11 (b) rises precedes the timing (c), the address at the timing (d) The pointer AP points to the address shown in FIG. 11D, which is obtained by adding the address N2πm to the product obtained by multiplying the internal counter that keeps counting up by the read increase rate Rc1. In a period T2 from the timing (a) to the timing (c) or (d), cosine wave data having a phase stored in the built-in memory in the range of 2πm to 2πm + πn from the current waveform storage means 22 is output current. As a result of PWM control of the inverter main circuit 10 that is output as data IWD and performed by the feedback processing described above, the output current Io output from the inverter is a current waveform as shown in FIG. (Referred to as a waveform).

  (Expression 29) is obtained by transforming (Expression 29).

  Assuming that the count value per unit time of the built-in counter is Ct, the built-in counter starts counting from N0 in the period T1 and the period T2, and counts up during the period (T1 + T2) when the count value per unit time is Ct. Since the built-in counter reaches the address value N2πm + πn, (Equation 31) is established.

  In the period T1, the address pointer AP starts counting from N0, and the count value per unit time is CtRc1, and the address pointer AD reaches N2πm as a result of the count-up operation for T1, so (Equation 32) is established. To do.

  In the period T2, the address pointer AP starts counting from N2πm, and the count value per unit time is CtRc2, and as a result of the count-up operation for the period T2, the address pointer AD reaches N2πm + πn. To do.

  From (Equation 32) and (Equation 33), (Equation 34) is obtained.

  (Equation 31) is transformed to obtain (Equation 35).

  (Equation 36) is obtained from (Equation 39), (Equation 34), and (Equation 35).

  After setting an appropriate value for the read increase rate Rc1 in the period T1, if the read increase rate Rc2 in the section T2 is set according to (Equation 29), (Equation 36) is established, and the first and second current waveforms Io are obtained. In the period (T1 + T2) for completing the output, the load voltage Vo for (m + n / 2) cycles is equal to the period (m + n / 2) To for completing the output, and the first and second current waveforms complete the output. The timing coincides with the timing at which the load voltage Vo for (m + n / 2) cycles completes the output. That is, if the inverter device 2 is controlled by the current distortion applying means 13 of the inverter device 2 of the fifth embodiment, the timing at which the second and first current waveforms complete the output coincides with the timing at which the peak point occurs. At this point, the phase of the output current Io coincides with the phase of the load voltage Vo, that is, zero (rad).

  At the timing of (c) or (d), the address pointer generator 21 sets the read increase rate Rc to an appropriate value Rc1 of 1 or less again, and resets the built-in counter.

  In a period T3 from the timing of (c) or (d) to the timing of (e) when the address pointer AP shown in FIG. 11 (d) reaches N4πm + πn, the address pointer AP keeps counting up. The address shown in FIG. 11D is indicated by adding the address N2πm + πn to the product obtained by multiplying the read increase rate Rc1 set to a value exceeding 1 by the address N2πm + πn. In period T3, cosine wave data having a phase in the range of 2πm + πn to 4πm + πn stored in the built-in memory is output as output current data IWD from the current waveform storage means 22, and the inverter main circuit 10 is PWM-controlled by the above-described feedback processing. As a result, the first current waveform shown in FIG. 11E is generated as in the case of the T1 period described above.

  At the timing (e), the address pointer generating means 21 sets the read increase rate Rc to Rc2 indicated by (Equation 29) again, and resets the built-in counter.

  In the period T4 shown in FIG. 11 from the timing of (e) to the timing of (f) when the address pointer AP reaches N4πm + 2πn, the address pointer AP multiplies the internal counter that continues to count up by the read increase rate Rc2. The address shown in FIG. 11D is indicated by adding the address N4πm + πn to the product. In period T4, cosine wave data having a phase stored in the built-in memory in the range of 4πm + πn to 4πm + 2πn is output from the current waveform storage unit 22 as output current data IWD, and the inverter main circuit 10 is PWM-controlled by the feedback processing described above. As a result, as in the case of the above-described period T2, a second current waveform in which the frequency decreases as illustrated in FIG. 11E is generated.

  If the read increase rate Rc2 in the period T4 is set by (Equation 29), for the same reason as described above, the output current Io at the peak point where the output of the second current waveform whose frequency drops from the inverter device 2 is completed. Is in phase with the load voltage Vo, ie, zero (rad).

  Next, when the timing (a) or the timing (a) ′ at which the peak point of FIG. 11B rises precedes the timing (c), the timing (a) is the timing (a) ′. The same processing as described in the above is repeatedly executed. Thereafter, the same operations as (A) to (A) ′ described above are repeated to continue the operation.

  From the positional relationship shown in FIG. 11, the periods T1 and T3 in which the output current Io for m cycles are output are shorter than the period mTo in which the load voltage Vo for m cycles is completed, and output for n / 2 cycles. In the period T2 and T4 in which the current Io is output, the load voltage Vo for n / 2 cycles is longer than the period nTo / 2 in which the output is completed, and the inverter device 2 has an output frequency in the period T1 and T3. A current waveform that gives an increasing current distortion is output, and a current waveform that gives a current distortion whose output frequency decreases is output in the T2 and T4 period sections.

  As described above, the connection points connecting the first current waveform with increasing frequency and the second current waveform with decreasing frequency, that is, (a), (b), (c), (d), At the timings (e) and (f), the displacement or phase of the output current Io is continuous, but the frequency becomes discontinuous, and current distortion occurs at this point. In addition, the phase of the output current Io and the phase of the load voltage Vo coincide with each other at the timing (c) or (f) when the output of the second current waveform is completed.

  As described above, in the fifth embodiment, for the same reason as described in the first embodiment, the first current is a cosine waveform corresponding to m cycles and gives a current distortion that increases its output frequency. A waveform and a second current waveform that is a cosine waveform for n / 2 cycles and gives a current distortion whose output frequency is lowered are connected and repeatedly output, and the output of the second current waveform is completed. The phase of the inverter output current is made to coincide with the phase of the load voltage at the peak point of the load voltage generated in the shortest time from the point in time, and the displacement or phase at the coupling point where the first and second current waveforms are connected. In the fifth embodiment, a current distortion with a frequency fluctuation that is continuous and discontinuous in frequency is applied to the conventional inverter device having the same level of isolated operation detection sensitivity as that of the conventional inverter. Since the current distortion rate of the output current of the inverter device can be made smaller than that of the conventional inverter device, the loss consumed by the inductive load caused by the harmonic current is less than that of the conventional inverter device. Therefore, it is possible to provide an ideal inverter device in which the isolated operation detection sensitivity is good and the loss consumed by the inductive load caused by the harmonic current is smaller.

(Embodiment 6)
A description of portions having the same configuration and processing as those of the first embodiment will be omitted, and only different portions will be described.

  12 (a) to 12 (e) show a load voltage Vo, a peak point synchronization signal PS, and a read increase rate Rc, which will be described later, in a normal operation state in which the inverter device 2 of the sixth embodiment is not in the single operation state. 4 is a time chart showing the timing of an address pointer AP and an inverter output current Io.

  The peak point detecting means 20 shown in FIG. 12 (b) is synchronized with the load voltage Vo shown in FIG. 12 (a) by the processing of the voltage cycle calculating means 19 and the peak point detecting means 20 described in the first embodiment. Such a peak point synchronization signal PS is generated.

  Incidentally, the current waveform storage means 22 has a built-in memory. The built-in memory stores cosine wave data having a phase proportional to a deviation address from the address N0 in an arbitrary address for (2m + n) cycles, that is, cosine wave data having a phase in the range of 0 to (4πm + 2πn). Here, m is an arbitrary natural number, n is an arbitrary odd number excluding 1, phase is zero at address N0, phase is πn at address Nπn, phase is 2πm + πn at address N2πm + πn, phase is 2πm + 2πn at address N2πm + 2πn, It is assumed that cosine wave data having a phase of 4πm + 2πn is stored in the address N4πm + 2πn, respectively. The address pointer generating means 21 outputs an address pointer AP that changes at a timing described later. The current waveform storage means 22 outputs cosine wave data stored in the built-in memory at the address indicated by the address pointer AP as current waveform data IWD.

  Next, the processing of the address pointer generating means 21 and the current waveform storage means 22 will be described. At the timing (a) when the peak point rises as shown in FIG. 12B, the address pointer generating means 21 sets the read increase rate Rc to an appropriate value Rc1 of 1 or more, and simultaneously resets the built-in counter. In the period T1 from the timing of (a) to the timing of (b) when the address pointer AP shown in FIG. 12D reaches Nπn, the address pointer AP has a read increase rate set to a value exceeding 1. The address shown in FIG. 12 (d) is indicated by adding the address N0 to the product obtained by multiplying the internal counter that is being counted up by Rc1. In the period T1, cosine wave data having a phase in the range of 0 to πn stored in the built-in memory is output as output current data IWD from the current waveform storage unit 22, but the inverter main circuit 10 is PWMed by the feedback processing described above. As a result of the control, the output current Io output from the inverter has a current waveform (hereinafter referred to as a second current waveform) as illustrated in FIG.

  At the timing (a), the address pointer generator 21 sets the read increase rate Rc to a value indicated by (Equation 37), and resets the built-in counter.

  At the timing (c) when the address pointer AP reaches N2πm + πn, or when the timing (d) at which the peak point in FIG. 12B rises precedes the timing (c), the address at the timing (d) The pointer AP indicates the address shown in FIG. 12D, which is obtained by adding the address Nπn to the product obtained by multiplying the internal counter that continues to count up by the read increase rate Rc2. In a period T2 from the timing (a) to the timing (c) or (d), cosine wave data having a phase stored in the built-in memory in the range of πn to 2πm + πn from the current waveform storage means 22 is output current. As a result of PWM control of the inverter main circuit 10 output as data IWD and the above-described feedback processing, the output current Io output from the inverter is a current waveform as shown in FIG. (Referred to as a waveform).

  (Equation 38) is obtained by transforming (Equation 37).

  Assuming that the count value per unit time of the built-in counter is Ct, the built-in counter starts counting from N0 in the period T1 and the period T2, and counts up during the period (T1 + T2) when the count value per unit time is Ct. Since the built-in counter reaches the address value N2πm + πn, (Equation 39) is established.

  In the period T1, the address pointer AP starts counting from N0, and the count value per unit time is CtRc1, and the address pointer AD reaches Nπn as a result of the count-up operation for the period T1, so (Equation 40) is established. To do.

  In the period T2, the address pointer AP starts counting from Nπn, and the count value per unit time is CtRc2, and as a result of the count-up operation for the period of T2, the address pointer AD reaches N2πm + πn, so (Equation 41) is established. To do.

  From (Equation 40) and (Equation 41), (Equation 42) is obtained.

  (Equation 43) is obtained by transforming (Equation 39).

  (Equation 44) is obtained from (Equation 38), (Equation 42), and (Equation 43).

  After setting an appropriate value for the read increase rate Rc1 in the period T1, if the read increase rate Rc2 in the section T2 is set by (Equation 37), (Equation 44) is established, and the second and first current waveforms Io are obtained. In the period (T1 + T2) for completing the output, the load voltage Vo for (m + n / 2) cycles is equal to the period (m + n / 2) To for completing the output, and the second and first current waveforms complete the output. The timing coincides with the timing at which the load voltage Vo for (m + n / 2) cycles completes the output. That is, if the inverter device 2 is controlled by the current distortion applying means 13 of the inverter device 2 of the sixth embodiment, the timing when the third and fourth current waveforms complete the output coincides with the timing when the peak point occurs. At this point, the phase of the output current Io coincides with the phase of the load voltage Vo, that is, zero (rad). At the timing of (c) or (d), the address pointer generator 21 sets the read increase rate Rc to an appropriate value Rc1 of 1 or less again, and resets the built-in counter.

  In the period T3 from the timing of (c) or (d) to the timing of (e) when the address pointer AP shown in FIG. 12 (d) reaches N2πm + 2πn, the address pointer AP keeps counting up. The address shown in FIG. 12D is indicated by adding the address N2πm + πn to the product obtained by multiplying the read increment rate Rc1 set to a value exceeding 1 by the address N2πm + πn. In period T3, cosine wave data having a phase in the range of 2πm + πn to 2πm + 2πn stored in the built-in memory is output as output current data IWD from the current waveform storage means 22, and the inverter main circuit 10 is PWM-controlled by the above-described feedback processing. As a result, the third current waveform shown in FIG. 12E is generated as in the case of the T1 period described above.

  At the timing (e), the address pointer generating means 21 sets the read increase rate Rc to Rc2 indicated by (Equation 29) again, and resets the built-in counter.

  In the period T4 shown in FIG. 12 from the timing of (e) to the timing of (f) when the address pointer AP reaches N4πm + 2πn, the address pointer AP multiplies the internal counter that keeps counting up by the read increase rate Rc2. The address shown in FIG. 12D is designated by adding the address N2πm + 2πn to the product. In the period T4, cosine wave data having a phase stored in the built-in memory in the range of 2πm + 2πn to 4πm + 2πn is output as output current data IWD from the current waveform storage means 22, and the inverter main circuit 10 is PWM-controlled by the feedback processing described above. As a result, a fourth current waveform as shown in FIG. 12E is generated as in the case of the period T2 described above.

  If the read increase rate Rc2 in the period T4 is set by (Equation 29), for the same reason as described above, the output current Io at the peak point where the output of the second current waveform whose frequency drops from the inverter device 2 is completed. Is in phase with the load voltage Vo, ie, zero (rad).

  Next, when the timing (a) or the timing (a) ′ at which the peak point of FIG. 12B rises precedes the timing (c), the timing (a) is the timing (a) ′. The same processing as described in the above is repeatedly executed. Thereafter, the same operations as (A) to (A) ′ described above are repeated to continue the operation.

  From the positional relationship shown in FIG. 12, the periods T1 and T3 in which the output current Io for n / 2 periods is output are longer than the period nTo / 2 in which the load voltage Vo for n / 2 periods completes output, m The periods T2 and T4 in which the output current Io for the period is output are shorter than the period mTo in which the load voltage Vo for the m periods is completed, and the output frequency of the inverter device 2 is in the period T1 and T3. A current waveform that gives a decreasing current distortion is outputted, and a current waveform that gives a current distortion whose output frequency rises is outputted in the T2 and T4 period sections.

  As described above, the coupling point connecting the second current waveform with decreasing frequency and the first current waveform with increasing frequency, that is, (a), (b), (c), (d), At the timings (e) and (f), the displacement or phase of the output current Io is continuous, but the frequency becomes discontinuous, and current distortion occurs at this point. In addition, the phase of the output current Io and the phase of the load voltage Vo coincide with each other at the timing (c) or (f) when the output of the first current waveform is completed.

  As described above, in the sixth embodiment, for the same reason as described in the first embodiment, the second distortion is applied that is a cosine waveform corresponding to n / 2 periods and whose output frequency decreases. And a first current waveform that is a cosine waveform for m cycles and gives a current distortion that increases its output frequency are repeatedly output and the output of the first current waveform is completed. The phase of the inverter output current is made to coincide with the phase of the load voltage at the peak point of the load voltage generated in the shortest time from the point in time, and the displacement or phase at the coupling point where the second and first current waveforms are connected. As compared with a conventional inverter device having a single-operation detection sensitivity of the same level as that of a conventional inverter, the current distortion with continuous frequency and discontinuous frequency fluctuation is applied, so that the sixth embodiment Since the current distortion rate of the output current of the inverter device can be made smaller than that of the conventional inverter device, the loss consumed by the inductive load caused by the harmonic current is less than that of the conventional inverter device. Therefore, it is possible to provide an ideal inverter device in which the isolated operation detection sensitivity is good and the loss consumed by the inductive load caused by the harmonic current is smaller.

(Embodiment 7)
A description of portions having the same configuration and processing as those of the first embodiment will be omitted, and only different portions will be described.

  FIGS. 13A to 13E respectively show a load voltage Vo, a peak point synchronization signal PS, and a read increase rate Rc described later in a normal operation state where the inverter device 2 of the seventh embodiment is not in the single operation state. 4 is a time chart showing the timing of an address pointer AP and an inverter output current Io.

  By the processing of the voltage cycle calculating means 19 and the peak point detecting means 20 described in the first embodiment, the peak point detecting means 20 is shown in FIG. 13 (b) in synchronization with the load voltage Vo shown in FIG. 13 (a). Such a peak point synchronization signal PS is generated.

  Incidentally, the current waveform storage means 22 has a built-in memory. The built-in memory stores cosine wave data having a phase proportional to a deviation address from the address N0 in an arbitrary address for (2m + n) cycles, that is, cosine wave data having a phase in the range of 0 to (4πm + 2πn). Here, m is an arbitrary natural number, n is an arbitrary odd number excluding 1, phase is zero at address N0, phase is πn at address Nπn, phase is 2πm + πn at address N2πm + πn, phase is 2πm + 2πn at address N2πm + 2πn, It is assumed that cosine wave data having a phase of 4πm + 2πn is stored in the address N4πm + 2πn, respectively. The address pointer generating means 21 outputs an address pointer AP that changes at a timing described later. The current waveform storage means 22 outputs cosine wave data stored in the built-in memory at the address indicated by the address pointer AP as current waveform data IWD.

  Next, the processing of the address pointer generating means 21 and the current waveform storage means 22 will be described. At the timing (a) when the peak point rises as shown in FIG. 13B, the address pointer generating means 21 sets the read increase rate Rc to an appropriate value Rc1 of 1 or more, and simultaneously resets the built-in counter. In the period T1 from the timing of (a) to the timing of (b) when the address pointer AP shown in FIG. 13D reaches Nπn, the address pointer AP has a read increase rate set to a value exceeding 1. The address shown in FIG. 13 (d) is designated by adding the address N0 to the product obtained by multiplying the built-in counter being counted up by Rc1. In the period T1, cosine wave data having a phase in the range of 0 to πn stored in the built-in memory is output from the current waveform storage means 22 as output current data IWD, and the inverter main circuit 10 is PWMed by the feedback processing described above. As a result of the control, the output current Io output from the inverter has a current waveform as shown in FIG. 13E (hereinafter referred to as a third current waveform).

  At the timing (a), the address pointer generator 21 sets the read increase rate Rc to a value indicated by (Equation 37), and resets the built-in counter.

  At the timing (c) when the address pointer AP reaches N2πm + πn, or when the timing (d) at which the peak point in FIG. 13 (b) rises precedes the timing (c), the address at the timing (d) The pointer AP points to the address shown in FIG. 13D, which is obtained by adding the address Nπn to the product obtained by multiplying the internal counter that continues to count up by the read increase rate Rc2. In a period T2 from the timing (a) to the timing (c) or (d), cosine wave data having a phase stored in the built-in memory in the range of πn to 2πm + πn from the current waveform storage means 22 is output current. As a result of PWM control of the inverter main circuit 10 that is output as data IWD and is performed by the feedback processing described above, the output current Io output from the inverter is a current waveform as shown in FIG. (Referred to as a waveform).

  (Equation 38) is obtained by transforming (Equation 37).

  Assuming that the count value per unit time of the built-in counter is Ct, the built-in counter starts counting from N0 in the period T1 and the period T2, and counts up during the period (T1 + T2) when the count value per unit time is Ct. Since the built-in counter reaches the address value N2πm + πn, (Equation 39) is established.

  In the period T1, the address pointer AP starts counting from N0, and the count value per unit time is CtRc1, and the address pointer AD reaches Nπn as a result of the count-up operation for the period T1, so (Equation 40) is established. To do.

  In the period T2, the address pointer AP starts counting from Nπn, and the count value per unit time is CtRc2, and as a result of the count-up operation for the period of T2, the address pointer AD reaches N2πm + πn, so (Equation 41) is established. To do.

  From (Equation 40) and (Equation 41), (Equation 42) is obtained.

  (Equation 43) is obtained by transforming (Equation 39).

  (Equation 44) is obtained from (Equation 38), (Equation 42), and (Equation 43).

After setting an appropriate value for the read increase rate Rc1 in the period T1, if the read increase rate Rc2 in the section T2 is set by (Equation 29), (Equation 36) is established,
The period (T1 + T2) in which the third and fourth current waveforms Io complete the output is equal to the period (m + n / 2) To in which the load voltage Vo for (m + n / 2) cycles completes the output. The timing at which the fourth current waveform completes the output coincides with the timing at which the load voltage Vo for (m + n / 2) cycles completes the output. That is, when the inverter device 2 is controlled by the current distortion applying means 13 of the inverter device 2 according to the seventh embodiment, the timing when the third and fourth current waveforms complete the output coincides with the timing when the peak point occurs. At this point, the phase of the output current Io coincides with the phase of the load voltage Vo, that is, zero (rad). At the timing (c) or (d), the address pointer generator 21 sets the read increase rate Rc to an appropriate value Rc1 of 1 or less again, and resets the built-in counter.

  In the period T3 from the timing of (c) or (d) to the timing of (e) when the address pointer AP shown in FIG. 13 (d) reaches N2πm + 2πn, the address pointer AP keeps counting up. The address shown in FIG. 13D is indicated by adding the address N2πm + πn to the product obtained by multiplying the read increase rate Rc1 set to a value exceeding 1 by the address N2πm + πn. In period T3, cosine wave data having a phase in the range of 2πm + πn to 2πm + 2πn stored in the built-in memory is output as output current data IWD from the current waveform storage means 22, and the inverter main circuit 10 is PWM-controlled by the above-described feedback processing. As a result, the third current waveform shown in FIG. 13E is generated as in the case of the T1 period described above.

  At the timing (e), the address pointer generating means 21 sets the read increase rate Rc to Rc2 indicated by (Equation 29) again, and resets the built-in counter.

  In the period T4 shown in FIG. 13 from the timing of (e) to the timing of (f) when the address pointer AP reaches N4πm + 2πn, the address pointer AP multiplies the internal counter that keeps counting up by the read increase rate Rc2. The address shown in FIG. 13D is designated by adding the address N2πm + 2πn to the product. In period T4, cosine wave data having a phase stored in the built-in memory in the range of 2πm + 2πn to 4πm + 2πn is output from the current waveform storage means 22 as output current data IWD, and the inverter main circuit 10 is PWM-controlled by the feedback processing described above. As a result, a fourth current waveform as shown in FIG. 13E is generated as in the case of the period T2 described above.

  If the read increase rate Rc2 in the period T4 is set by (Equation 29), for the same reason as described above, the output current Io at the peak point where the output of the second current waveform whose frequency drops from the inverter device 2 is completed. Is in phase with the load voltage Vo, ie, zero (rad).

  Next, when the timing (a) or the timing (a) ′ at which the peak point of FIG. 13B rises precedes the timing (c), the timing (a) is the timing (a) ′. The same processing as described in the above is repeatedly executed. Thereafter, the same operations as (A) to (A) ′ described above are repeated to continue the operation.

  From the positional relationship shown in FIG. 13, the periods T1 and T3 in which the output current Io for n / 2 periods is output are shorter than the period nTo / 2 in which the load voltage Vo for n / 2 periods completes output, m The periods T2 and T4 in which the output current Io for the period is output are longer than the period mTo in which the load voltage Vo for the m periods is completed, and the inverter device 2 has an output frequency in the periods T1 and T3. A current waveform that gives an increasing current distortion is output, and a current waveform that gives a current distortion whose output frequency decreases is output in the T2 and T4 period sections.

  As described above, the connection point that connects the third current waveform with increasing frequency and the fourth current waveform with decreasing frequency, that is, (a), (b), (c), (d), At the timings (e) and (f), the displacement or phase of the output current Io is continuous, but the frequency becomes discontinuous, and current distortion occurs at this point. In addition, the phase of the output current Io and the phase of the load voltage Vo coincide with each other at the timing (c) or (f) when the output of the second current waveform is completed.

  As described above, in the seventh embodiment, for the same reason as described in the first embodiment, the current distortion is applied to the cosine waveform for n / 2 periods and the output frequency is increased. And a fourth current waveform that is a cosine waveform for m periods and gives a current distortion whose output frequency decreases, are repeatedly output, and the output of the second current waveform is completed. The phase of the inverter output current is made to coincide with the phase of the load voltage at the peak point of the load voltage generated in the shortest time from the point in time, and the displacement or phase at the coupling point where the third and fourth current waveforms are connected. Compared with a conventional inverter device having a single operation detection sensitivity of the same level as that of a conventional inverter, by applying current distortion with continuous frequency fluctuation and discontinuous frequency fluctuation, the embodiment Since the current distortion rate of the output current of the inverter device 7 can be made smaller than that of the conventional inverter device, the loss consumed by the inductive load caused by the harmonic current is reduced. It is possible to provide an ideal inverter device that can be reduced compared to the device, has a good isolated operation detection sensitivity, and requires less loss for the inductive load caused by the harmonic current. it can.

(Embodiment 8)
A description of portions having the same configuration and processing as those of the first embodiment will be omitted, and only different portions will be described.

  FIGS. 14A to 14E respectively show a load voltage Vo, a peak point synchronization signal PS, and a read increase rate Rc, which will be described later, in a normal operation state in which the inverter device 2 of the eighth embodiment is not in the single operation state. 4 is a time chart showing the timing of an address pointer AP and an inverter output current Io.

  By the processing of the voltage cycle calculating means 19 and the peak point detecting means 20 described in the first embodiment, the peak point detecting means 20 is shown in FIG. 14 (b) in synchronization with the load voltage Vo shown in FIG. 14 (a). Such a peak point synchronization signal PS is generated.

  Incidentally, the current waveform storage means 22 has a built-in memory. The built-in memory stores cosine wave data having a phase proportional to a deviation address from the address N0 in an arbitrary address for (2m + n) cycles, that is, cosine wave data having a phase in the range of 0 to (4πm + 2πn). Here, m is an arbitrary natural number, n is an arbitrary odd number excluding 1, an address N0 has a phase of zero, an address N2πm has a phase of 2πm, an address N2πm + πn has a phase of 2πm + πn, an address N4πm + πn has a phase of 4πm + πn, It is assumed that cosine wave data having a phase of 4πm + 2πn is stored in the address N4πm + 2πn, respectively. The address pointer generating means 21 outputs an address pointer AP that changes at a timing described later. The current waveform storage means 22 outputs cosine wave data stored in the built-in memory at the address indicated by the address pointer AP as current waveform data IWD.

  Next, the processing of the address pointer generating means 21 and the current waveform storage means 22 will be described. At the timing of (a) when the peak point rises as shown in FIG. 14B, the address pointer generating means 21 sets the read increase rate Rc to an appropriate value Rc1 of 1 or more, and simultaneously resets the built-in counter. In the period T1 from the timing of (a) to the timing of (a) when the address pointer AP reaches N2πm shown in FIG. 14 (d), the address pointer AP has a read increase rate set to a value exceeding 1. The address shown in FIG. 14D is indicated by adding the address N0 to the product obtained by multiplying Rc1 by the built-in counter being counted up. In period T1, cosine wave data having a phase in the range of 0 to 2πm stored in the built-in memory is output from the current waveform storage means 22 as output current data IWD, and the inverter main circuit 10 is PWMed by the feedback processing described above. As a result of the control, the output current Io output from the inverter has a current waveform as shown in FIG. 14E (hereinafter referred to as a fourth current waveform).

  At the timing (a), the address pointer generator 21 sets the read increase rate Rc to a value indicated by (Equation 29) and resets the built-in counter.

  At the timing (c) when the address pointer AP reaches N2πm + πn, or when the timing (d) at which the peak point in FIG. 14 (b) rises precedes the timing (c), the address at the timing (d) The pointer AP points to the address shown in FIG. 14D, which is obtained by adding the address N2πm to the product obtained by multiplying the internal counter that continues to count up by the read increase rate Rc1. In a period T2 from the timing (a) to the timing (c) or (d), cosine wave data having a phase stored in the built-in memory in the range of 2πm to 2πm + πn from the current waveform storage means 22 is output current. As a result of PWM control of the inverter main circuit 10 that is output as data IWD and has been subjected to the above-described feedback processing, the output current Io output from the inverter is a current waveform as shown in FIG. (Referred to as a waveform).

  (Expression 29) is obtained by transforming (Expression 29).

  Assuming that the count value per unit time of the built-in counter is Ct, the built-in counter starts counting from N0 in the period T1 and the period T2, and counts up during the period (T1 + T2) when the count value per unit time is Ct. Since the built-in counter reaches the address value N2πm + πn, (Equation 31) is established.

  In the period T1, the address pointer AP starts counting from N0, and the count value per unit time is CtRc1, and the address pointer AD reaches N2πm as a result of the count-up operation for T1, so (Equation 32) is established. To do.

  In the period T2, the address pointer AP starts counting from N2πm, and the count value per unit time is CtRc2, and as a result of the count-up operation for the period T2, the address pointer AD reaches N2π + πn. To do.

  From (Equation 32) and (Equation 33), (Equation 34) is obtained.

  (Equation 31) is transformed to obtain (Equation 35).

  (Equation 36) is obtained from (Equation 30), (Equation 34), and (Equation 35).

After setting an appropriate value for the read increase rate Rc1 in the period T1, if the read increase rate Rc2 in the section T2 is set by (Equation 29), (Equation 36) is established,
The period (T1 + T2) in which the fourth and third current waveforms Io complete the output is equal to the period (m + n / 2) To in which the load voltage Vo for (m + n / 2) cycles completes the output. The timing at which the third current waveform completes the output coincides with the timing at which the load voltage Vo for (m + n / 2) cycles completes the output.

  That is, if the inverter device 2 is controlled by the current distortion applying means 13 of the inverter device 2 of the eighth embodiment, the timing when the fourth and third current waveforms complete the output coincides with the timing when the peak point occurs. At this point, the phase of the output current Io coincides with the phase of the load voltage Vo, that is, zero (rad). At the timing of (c) or (d), the address pointer generator 21 sets the read increase rate Rc to an appropriate value Rc1 of 1 or less again, and resets the built-in counter.

  In the period T3 from the timing of (c) or (d) to the timing of (e) when the address pointer AP shown in FIG. 14 (d) reaches N4πm + πn, the address pointer AP keeps counting up. The address shown in FIG. 14D is indicated by adding the address N2πm + πn to the product obtained by multiplying the read multiplication rate Rc1 set to a value exceeding 1 by the address N2πm + πn. In period T3, cosine wave data having a phase stored in the built-in memory in the range of 2πm + πn to 4πm + πn is output from the current waveform storage means 22 as output current data IWD, and the inverter main circuit 10 is PWM-controlled by the feedback processing described above. As a result, the first current waveform shown in FIG. 14E is generated as in the case of the T1 period described above.

  At the timing (e), the address pointer generating means 21 sets the read increase rate Rc to Rc2 indicated by (Equation 29) again, and resets the built-in counter.

  In the period T4 shown in FIG. 14 from the timing of (e) to the timing of (f) when the address pointer AP reaches N4πm + 2πn, the address pointer AP multiplies the internal counter that keeps counting up by the read increase rate Rc2. The address shown in FIG. 14D is designated by adding the address N4πm + πn to the product obtained. In period T4, cosine wave data having a phase stored in the built-in memory in the range of 4πm + πn to 4πm + 2πn is output from the current waveform storage means 22 as output current data IWD, and the inverter main circuit 10 is PWM-controlled by the feedback processing described above. As a result, as in the case of the above-described period T2, a second current waveform in which the frequency decreases as illustrated in FIG.

  If the read increase rate Rc2 in the period T4 is set by (Equation 29), for the same reason as described above, the output current Io at the peak point where the output of the second current waveform whose frequency drops from the inverter device 2 is completed. Is in phase with the load voltage Vo, ie, zero (rad).

  Next, when the timing (a) or the timing (a) ′ at which the peak point of FIG. 14B rises precedes the timing (c), the timing (a) is the timing (a) ′. The same processing as described in the above is repeatedly executed. Thereafter, the same operations as (A) to (A) ′ described above are repeated to continue the operation.

  From the positional relationship shown in FIG. 14, the periods T1 and T3 in which the output current Io for m cycles is output are longer than the period mTo in which the load voltage Vo for m cycles is completed, and output for n / 2 cycles. In the periods T2 and T4 in which the current Io is output, the load voltage Vo for n / 2 cycles is shorter than the period nTo / 2 in which the output is completed, and the inverter device 2 has its output frequency in the periods T1 and T3. A current waveform that gives a decreasing current distortion is outputted, and a current waveform that gives a current distortion whose output frequency rises is outputted in the T2 and T4 period sections.

  As described above, the coupling point connecting the fourth current waveform with decreasing frequency and the third current waveform with increasing frequency, that is, (a), (b), (c), (d), At the timings (e) and (f), the displacement or phase of the output current Io is continuous, but the frequency becomes discontinuous, and current distortion occurs at this point. In addition, at the timing of (c) or (f) when the third current waveform completes the output, the phase of the output current Io and the phase of the load voltage Vo coincide.

  As described above, in the eighth embodiment, for the same reason as described in the first embodiment, the fourth current is a cosine waveform corresponding to m periods and gives a current distortion whose output frequency decreases. A waveform and a third current waveform which is a cosine waveform for n / 2 cycles and gives a current distortion whose output frequency is increased are connected and repeatedly output, and the third current waveform completes output. The phase of the inverter output current is made to coincide with the phase of the load voltage at the peak point of the load voltage generated in the shortest time from the point in time, and the displacement or phase at the coupling point where the fourth and third current waveforms are connected. 8 is compared with a conventional inverter device having a single operation detection sensitivity of the same level as that of a conventional inverter, by applying current distortion with continuous frequency fluctuation and discontinuous frequency fluctuation. Since the current distortion rate of the output current of the inverter device can be made smaller than that of the conventional inverter device, the loss consumed by the inductive load caused by the harmonic current is less than that of the conventional inverter device. Therefore, it is possible to provide an ideal inverter device in which the isolated operation detection sensitivity is good and the loss consumed by the inductive load caused by the harmonic current is smaller.

  In addition, the current distortion applying means of the embodiment, the elapsed time from the timing when the polarity of the load voltage changes from negative to positive and the timing after which the polarity of the detected load voltage changes from negative to positive Voltage cycle calculation means that determines the moving average of the load voltage cycle obtained by dividing by the number of occurrences of the load voltage appearing in time as the voltage cycle, and the timing at which the polarity of the load voltage changes from negative to positive Peak point detecting means for determining, as a peak point, a timing at which a period corresponding to one quarter of the voltage period has elapsed and a timing at which a period corresponding to three quarters of the voltage period has elapsed. However, the elapsed time between the timing when the polarity of the load voltage changes from positive to negative and the timing when the polarity of the detected load voltage changes from positive to negative is included in the elapsed time. Voltage cycle calculating means for determining a moving average of the load voltage cycle obtained by dividing by the number of occurrences of the appearing load voltage for one cycle as the voltage cycle, and the voltage from the timing when the polarity of the load voltage varies from positive to negative Peak point detection means may be provided for determining, as a peak point, a timing at which a period corresponding to one quarter of the period has elapsed and a timing at which a period corresponding to three quarters of the voltage period has elapsed. There is no difference in function and effect.

  Note that the current distortion applying means of the embodiment is such that when the frequency of the load voltage is outside the predetermined frequency section including the rated frequency, the inverter output frequency changes in the positive feedback loop according to the frequency change of the load voltage. A current waveform that gives such current distortion, and as a result, when the frequency of the load voltage is outside the range of the predetermined frequency section including the rated frequency, the operation with the AC power system is separated and the single operation is performed. However, if the frequency of the load voltage is outside the range of the predetermined frequency section including the rated frequency, it is immediately determined that the independent operation is started after leaving the link with the AC power system. It does not matter, and there is no difference in its effect.

  When performing system linkage operation with a commercial power source using the inverter device of the present invention attached to a power generation facility, it is possible to detect isolated operation with good sensitivity and to have a lot of inductive loads such as motors and transformers. It can also be applied to the use of an inverter device attached to a power generation facility installed in, for example.

The block diagram which shows the structure of Embodiment 1-8. (A), (b) The time chart which shows the timing of the same load voltage Vo of the same inverter apparatus, and the peak point synchronizing signal PS (A), (b), (c), (d), (e) Load voltage Vo, peak point synchronization signal PS, address in the normal operation state where the inverter device of the first embodiment is not in the single operation state Time chart showing timing of read increase rate Rc of pointer AP, address pointer AP, and inverter output current Io Relationship diagram between load voltage frequency measurement value Fi measured in the current cycle of the inverter device of the first to eighth embodiments and the output current frequency set value Fo controlled by the current distortion applying means in the next cycle. Frequency spectrum diagram showing the relationship between the order of the output current harmonic and the ratio of the amplitude of the harmonic to the fundamental wave component using the frequency fluctuation rate ζ of the inverter as a parameter Relationship between period variation rate ζ and output current distortion rate THDi of the same inverter device, and relationship diagram between cf value of conventional inverter device and output current distortion rate THDi A characteristic diagram of the dead zone obtained by plotting the limit point of the parallel equivalent capacitance value that operates as a dead zone against the arbitrary parallel equivalent inductance value of the inverter device. (A), (b), (c), (d), (e) The load voltage Vo, peak point synchronization signal PS, address in the normal operation state where the inverter device of the second embodiment is not in the single operation state Time chart showing timing of read increase rate Rc of pointer AP, address pointer AP, and inverter output current Io (A), (b), (c), (d), (e) The load voltage Vo, peak point synchronization signal PS, address in the normal operation state where the inverter device of the third embodiment is not in the single operation state Time chart showing timing of read increase rate Rc of pointer AP, address pointer AP, and inverter output current Io (A), (b), (c), (d), (e) Load voltage Vo, peak point synchronization signal PS, address in the normal operation state where the inverter device of the fourth embodiment is not in the single operation state Time chart showing timing of read increase rate Rc of pointer AP, address pointer AP, and inverter output current Io (A), (b), (c), (d), (e) The load voltage Vo, peak point synchronization signal PS, address in the normal operation state where the inverter device of the fifth embodiment is not in the single operation state Time chart showing timing of read increase rate Rc of pointer AP, address pointer AP, and inverter output current Io (A), (b), (c), (d), (e) The load voltage Vo, peak point synchronization signal PS, address in the normal operation state where the inverter device of the sixth embodiment is not in the single operation state Time chart showing timing of read increase rate Rc of pointer AP, address pointer AP, and inverter output current Io (A), (b), (c), (d), (e) The load voltage Vo, peak point synchronization signal PS, address in the normal operation state where the inverter device of the seventh embodiment is not in the single operation state Time chart showing timing of read increase rate Rc of pointer AP, address pointer AP, and inverter output current Io (A), (b), (c), (d), (e) The load voltage Vo, peak point synchronization signal PS, address in the normal operation state where the inverter device of the eighth embodiment is not in the single operation state Time chart showing timing of read increase rate Rc of pointer AP, address pointer AP, and inverter output current Io Configuration diagram of a conventional inverter device that adopts the conventional frequency shift method as an isolated operation detection method Flow chart showing the detection operation procedure of a conventional inverter device that employs the same frequency shift method as an isolated operation detection method (A), (b) The time chart which shows the timing of the voltage of the alternating current power system by the same independent operation detection method, and the output current of the conventional inverter apparatus (A), (b) The time chart which shows the timing of the voltage of the alternating current power system by the same independent operation detection method, and the output current of the conventional inverter apparatus Time chart showing the timing of the output current of the inverter device when the AC power system is normal Time chart showing the timing of the output current of the inverter device when the AC power system is normal Frequency spectrum diagram showing the relationship between the order of the output current harmonics using the cf value of the inverter device as a parameter and the ratio of the harmonic amplitude to the fundamental wave component A characteristic diagram of the dead zone obtained by plotting the limit point of the parallel equivalent capacitance value that operates as a dead zone against any parallel equivalent inductance value for the inverter device. Relationship diagram between cf value and distortion rate THDi of output current examined for the inverter device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 DC power supply 2 Inverter apparatus 3 AC power system 7 Load 10 Inverter main circuit 13 Current distortion provision means 19 Voltage cycle calculation means 20 Peak point detection means 28 Frequency abnormality detection means

Claims (14)

The DC power is converted to AC while being linked to the AC power system, supplied to the load, and the frequency fluctuation occurring in the inverter output voltage when starting the independent operation after leaving the linkage with the AC power grid, or the frequency fluctuation In a grid-linked inverter device having a single operation detecting means for detecting a single operation of the inverter main circuit by detecting a variation caused by the load voltage, when the frequency of the load voltage is within a predetermined frequency section including the rated frequency, A cosine waveform obtained by concatenating one period of the waveform to an arbitrary natural number of times, and a first current waveform that imparts a current distortion that increases the output frequency, and an arbitrary odd number of times excluding 1 for the half period of the waveform. A second current waveform that gives a current distortion whose output frequency decreases is connected and repeatedly output, or a half period of the waveform is divided by 1 A third current waveform which is a cosine waveform connected with an arbitrary odd number of times and gives a current distortion whose output frequency rises, and a cosine waveform which is connected with an arbitrary natural number of one period of the waveform, and its output frequency The fourth current waveform that gives the current distortion of decreasing is connected and repeatedly output, and the current waveform of any one of the first, second, third, or fourth current waveform is output. The phase of the inverter output current coincides with the phase of the load voltage at the peak point of the load voltage generated in the shortest time from the completion time point, and the first, second, third or fourth current waveform An inverter device comprising: current distortion applying means for applying current distortion with a frequency variation in which the displacement or phase is continuous and the frequency is discontinuous at a connection point connecting the two. A first current waveform that is a cosine waveform for one period and that increases its output frequency, and a current distortion that is a cosine waveform for 1.5 half periods and that decreases its output frequency. The second current waveform is connected and repeatedly output, and the phase of the inverter output current is the phase of the load voltage at the peak point of the load voltage that occurs in the shortest time from when the second current waveform completes the output. The system-linked inverter device according to claim 1, further comprising the current distortion applying unit configured to match the current level. A first current waveform that is a cosine waveform for one period and that increases its output frequency, and a current distortion that is a cosine waveform for 1.5 half periods and that decreases its output frequency. The second current waveform is connected and repeatedly output, and the phase of the inverter output current is the phase of the load voltage at the peak point of the load voltage generated in the shortest time from the time when the first current waveform completes the output. The system-linked inverter device according to claim 1, further comprising: a current distortion applying unit configured to match the current distortion. A third current waveform that gives a current distortion that is a cosine waveform for 1.5 periods and whose output frequency increases, and a third current waveform that gives a current distortion that is a cosine waveform for one period and whose output frequency decreases. 4 current waveforms are connected and repeatedly output, and at the peak point of the load voltage that occurs in the shortest time from the time when the fourth current waveform completes the output, the phase of the inverter output current becomes the phase of the load voltage. 2. The grid-linked inverter device according to claim 1, further comprising a current distortion applying unit adapted to match. A third current waveform that gives a current distortion that is a cosine waveform for 1.5 periods and whose output frequency increases, and a third current waveform that gives a current distortion that is a cosine waveform for one period and whose output frequency decreases. 4 are connected and repeatedly output, and the phase of the inverter output current becomes the phase of the load voltage at the peak point of the load voltage that occurs in the shortest time from the time when the third current waveform completes the output. 2. The grid-linked inverter device according to claim 1, further comprising a current distortion applying unit adapted to match. A cosine waveform obtained by connecting one cycle of the waveform to an arbitrary natural number of times, a first current waveform that gives a current distortion that increases the output frequency, and an odd number of times except 1 for a half cycle of the waveform A second current waveform which is a connected cosine waveform and gives a current distortion whose output frequency is lowered is connected and repeatedly output, and the second current waveform is generated in the shortest time from the time when the output is completed. 2. The grid-linked inverter device according to claim 1, further comprising the current distortion applying means configured such that the phase of the inverter output current coincides with the phase of the load voltage at the peak point of the load voltage. A cosine waveform obtained by connecting one cycle of the waveform to an arbitrary natural number of times, a first current waveform that gives a current distortion that increases the output frequency, and an odd number of times except 1 for a half cycle of the waveform A second current waveform that is a concatenated cosine waveform and gives a current distortion whose output frequency decreases is connected and repeatedly output, and the first current waveform is generated in the shortest time from the time when the output is completed. 2. The grid-linked inverter device according to claim 1, further comprising the current distortion applying means configured such that the phase of the inverter output current coincides with the phase of the load voltage at the peak point of the load voltage. A third current waveform that is a cosine waveform obtained by concatenating half of the waveform for any odd number of times except 1 and imparts current distortion that increases the output frequency, and one cycle of the waveform for any natural number of times A fourth current waveform which is a connected cosine waveform and gives a current distortion whose output frequency decreases is connected and repeatedly output, and the fourth current waveform is generated in the shortest time from the time when the output is completed. 2. The grid-linked inverter device according to claim 1, further comprising the current distortion applying means configured such that the phase of the inverter output current coincides with the phase of the load voltage at the peak point of the load voltage. A third current waveform that is a cosine waveform obtained by concatenating half of the waveform for any odd number of times except 1 and imparts current distortion that increases the output frequency, and one cycle of the waveform for any natural number of times A fourth current waveform which is a connected cosine waveform and gives a current distortion whose output frequency is lowered is connected and repeatedly output, and the third current waveform is generated in the shortest time from the time when the output is completed. 2. The grid-linked inverter device according to claim 1, further comprising the current distortion applying means configured such that the phase of the inverter output current coincides with the phase of the load voltage at the peak point of the load voltage. The current distortion applying means appears within the elapsed time from the timing when the polarity of the load voltage changes from negative to positive and the timing after which the polarity of the detected load voltage changes from negative to positive. A voltage cycle calculating means for determining, as a voltage cycle, a moving average of a load voltage cycle obtained by dividing by the number of occurrences of one load voltage cycle, and from the timing at which the polarity of the load voltage changes from negative to positive 2. A peak point detecting means for determining, as a peak point, a timing at which a period corresponding to a quarter has elapsed and a timing at which a period corresponding to three quarters of the voltage period has elapsed. The system linkage inverter device according to claim 1, 2, 3, 4, 5, 6, 7, 8, or 10. The current distortion applying means causes the elapsed time until the timing when the polarity of the load voltage changes from positive to negative and the timing when the polarity of the detected load voltage changes from positive to negative appears within the elapsed time. A voltage cycle calculating means for determining, as a voltage cycle, a moving average of a load voltage cycle obtained by dividing by the number of occurrences of one load voltage cycle, and from the timing at which the polarity of the load voltage varies from positive to negative 2. A peak point detecting means for determining, as a peak point, a timing at which a period corresponding to a quarter has elapsed and a timing at which a period corresponding to three quarters of the voltage period has elapsed. The system linkage inverter device according to claim 1, 2, 3, 4, 5, 6, 7, 8, or 10. The current distortion applying means calculates the elapsed time from the timing when the polarity of the load voltage changes from positive to negative or from negative to positive until the next timing when the polarity of the load voltage changes from positive to negative or from negative to positive. And a voltage frequency detecting means for detecting twice the reciprocal of the half cycle as the frequency of the load voltage. The grid connection inverter apparatus of Claim 8 or Claim 9. The current distortion applying means is a current that causes the inverter output frequency to change in a positive feedback loop in accordance with a change in the frequency of the load voltage when the frequency of the load voltage is outside the range of the predetermined frequency section including the rated frequency. 10. The grid-linked inverter device according to claim 1, wherein a current waveform for imparting distortion is output. When the frequency of the load voltage is outside the range of the predetermined frequency section including the rated frequency, the current distortion applying means determines a frequency abnormality detection means that determines that the independent operation is started after leaving the link with the AC power system. 10. The grid-linked inverter device according to claim 1, 2, 3, 4, 5, 6, 7, 8, or 9.

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