JP5458902B2 - Analog to digital converter - Google Patents

Description

  The present invention relates to an analog-digital conversion device including an analog-digital converter that converts an analog value into a digital value, and more particularly to an analog-digital conversion device including two analog-digital converters in order to improve reliability.

  In a control device or the like that requires high reliability, an analog-to-digital conversion device including two analog-to-digital converters may be required for failure detection. FIG. 3 is a block diagram illustrating a configuration example of a conventional analog-digital conversion apparatus including two analog-digital converters (ADC).

  In the example of this figure, the analog-to-digital conversion apparatus 20 includes two systems of AD converters, a main ADC 210 and a sub ADC 220, and further, a difference calculation unit 230 and an error detection unit 240 in order to detect a failure of the AD converter. It has.

  An analog signal input from IN is input in parallel to the main ADC 210 and the sub ADC 220, and is converted into a digital signal by each AD converter. The conversion result of the main ADC 210 is output as an OUT signal of the analog / digital conversion device 20.

  Also, the difference calculation unit 230 calculates the difference between the conversion result of the main ADC 210 and the sub ADC 220 conversion result. If the conversion result of the main ADC 210 and the conversion result of the sub ADC 220 are different and the difference is large, it is considered that a failure has occurred in one of the AD converters. For this reason, the error detection unit 240 detects an error when the difference exceeds a predetermined reference value, and outputs an ERROR signal.

JP 2003-168976 A

  In general, components of an analog-digital converter have an offset voltage error that causes a voltage value to be regarded as being input even if the input voltage is zero. In the example of this figure, the main ADC 210 has an offset error value OS1, and the sub ADC 220 has an offset error value OS2.

  Even if these offset voltage errors are calibrated at the time of manufacturing, if the offset voltage error changes due to the influence of temperature or time, an analog-digital conversion error occurs.

  As countermeasures against offset voltage errors, auto-zero amplifiers, chopper amplifiers, etc. have been put into practical use for amplifiers alone, but switching processing for offset detection is required, resulting in discontinuous operation and frequency characteristics. It cannot be applied as it is to an analog-to-digital conversion apparatus that has problems such as badness and requires high reliability and continuity of analog-to-digital conversion operation.

  Accordingly, the present invention provides an analog-to-digital conversion apparatus having two analog-to-digital converters for ensuring high reliability, and is capable of canceling an offset voltage error while performing continuous analog-to-digital conversion processing. Objective.

  In order to solve the above-described problems, an analog-to-digital converter according to the present invention is an analog-to-digital converter that includes a first analog-to-digital converter and a second analog-to-digital converter, to the second analog-to-digital converter. A switch for switching the input between an input analog signal and a reference potential (0 potential), a second register for storing an output value of the second analog-digital converter when the switch is switched to a reference potential, The output value of the second analog-digital converter when the switch is switched to the input analog signal is subtracted from the sum of the conversion result of the input analog signal in the first analog-digital converter and the stored value of the second register. The first arithmetic unit, the first register for storing the output value of the first arithmetic unit, and the first analog-digital converter From the conversion result of the input analog signal by subtracting the stored value of the first register and a second arithmetic unit for the output digital signal that.

  Here, the stored value of the first register and the stored value of the second register are monitored, and an error signal is output when the value of the first register or the stored value of the second register does not satisfy a predetermined criterion. You may make it further provide an error detection part.

  According to the present invention, an offset voltage error can be canceled while performing continuous analog-digital conversion processing in an analog-digital conversion apparatus having two analog-digital converters for ensuring high reliability.

It is a block diagram which shows the structural example of the analog-digital converter provided with 2 types of AD converters concerning this embodiment. It is a flowchart explaining the analog digital conversion process of an analog digital converter. It is a block diagram which shows the structural example of the conventional analog-digital conversion apparatus provided with 2 types of AD converters.

  Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration example of an analog-digital conversion apparatus including two AD converters according to the present embodiment.

  As shown in the figure, the analog-to-digital converter 10 includes two systems of AD converters, a main ADC 110 and a sub ADC 120, in order to ensure high reliability, and further performs AD processing while performing continuous analog-digital conversion processing. In order to detect a failure of the converter, a switch 130, a first register 140, a second register 150, a first calculation unit 160, a second calculation unit 170, an error detection unit 180, and a control unit 190 are provided.

  The main ADC 110 receives the input analog signal IN, converts it into a digital signal, and outputs it. The main ADC 110 includes an offset error value OS1 as an offset voltage error, and a value corresponding to the offset error value OS1 is output even when the input signal is 0 V of the reference potential. The main ADC 110 functions as a first analog / digital converter.

  The sub ADC 120 receives the input analog signal IN or the reference potential, converts it into a digital signal, and outputs it. The sub ADC 120 includes an offset error value OS2 as an offset voltage error, and a value corresponding to the offset error value OS2 is output even when the input signal is 0 V of the reference potential. The sub ADC 120 functions as a second analog / digital converter.

  The switch 130 switches the input to the sub ADC 120 between the input analog signal IN and the reference potential (0 potential).

  The second register 150 stores the output value of the sub ADC 120 when the switch 130 is switched to the reference potential.

  The first arithmetic unit 160 subtracts the output value of the sub ADC 120 when the switch 130 is switched to the input analog signal IN from the sum of the conversion result of the input analog signal IN in the main ADC 110 and the stored value of the second register 150. Perform the operation.

  The first register 140 stores the output value of the first calculation unit 160.

  The second operation unit 170 performs an operation of subtracting the stored value of the first register 140 from the conversion result of the input analog signal IN in the main ADC 110, and outputs the operation result as an output digital signal OUT.

  The error detection unit 180 outputs an ERROR signal when at least one of the stored value of the first register 140 and the stored value of the second register 150 exceeds a predetermined reference value. At this time, a signal for identifying which register value is abnormal may be output together.

  The control unit 190 controls switching of the switch 130 and storage processing of the first register 140 and the second register 150.

  Next, the analog-digital conversion processing of the analog-digital conversion apparatus 10 in the present embodiment will be described with reference to the flowchart of FIG.

  When the analog-digital conversion process is started, first, the offset error value OS2 in which the sub ADC 120 is present is acquired (S101: Yes). The offset error value OS2 needs to obtain an initial value first, but after that, it may be performed every sampling of the input analog signal IN, or may be performed regularly or irregularly at intervals. It may be. In general, the offset error is greatly influenced by the environment such as temperature. For this reason, in a stable environment, it is sufficient to obtain the offset error value OS2 at an appropriate interval, and it is not always necessary to perform it every sampling.

  In obtaining the offset error value OS2, the control unit 190 switches the switch 130 to the reference potential side (S102). Since a zero value is input to the sub ADC 120 at this time, the value output from the sub ADC 120 is the offset error OS2 of the sub ADC 120. This offset error OS2 is stored in the second register 150 (S103).

  Next, the control unit 190 switches the switch 130 to the input analog signal IN side (S104). Of course, if the switch 130 is on the input analog signal IN side, the state may be kept as it is. As a result, the output value of the sub ADC 120 is a value obtained by digitally converting the input analog signal IN. This value includes the offset error OS2.

  Then, the first calculation unit 160 calculates a value obtained by subtracting the output value of the sub ADC 120 from the sum of the output result of the main ADC 110 and the stored value of the second register 150, that is, the offset error OS2, and the control unit 190 1 is stored in the register 140 (S105).

  The value obtained by subtracting the stored value of the second register 150 from the sub ADC 120 output value is a value obtained by removing the offset error OS2 from the sub ADC 120 output value. By subtracting this value from the output result of the main ADC 110, a value corresponding to the offset error OS1 of the main ADC 110 is calculated. Therefore, the first register 140 stores a value corresponding to the offset error OS1 of the main ADC 110.

  Here, the error detection unit 180 determines whether the absolute value of the offset error OS1 stored in the first register 140 or the absolute value of the offset error OS2 stored in the second register 150 is larger than a predetermined reference value. (S106), and if the value of at least one of the registers is an abnormal value larger than a predetermined reference value (S106: Yes), an ERROR signal is output as a failure in the analog-to-digital conversion apparatus 10. (S108). It should be noted that by providing an appropriate margin for this determination result, such as a series of abnormal values, it is possible to prevent erroneous determination of the influence of noise or the like as a failure. Further, as described above, a signal indicating which register value is abnormal may be added.

  When the stored value of the register is not abnormal (S106: No), the second arithmetic unit 170 subtracts the stored value of the first register 140, that is, the offset error OS1 of the main ADC 110 from the output result of the main ADC 110. Is output as the output digital signal OUT (S107). The value of the output digital signal OUT corresponds to a value obtained by digitally converting the input digital signal IN, and is a value obtained by canceling the offset error OS1.

  By repeating the above processing, the analog-digital conversion result can be output continuously. The first register 140 stores the latest offset error OS1 of the main ADC 110, and the output digital signal OUT becomes an accurate digital conversion value of the input digital signal IN from which the offset error OS1 has been canceled.

  That is, the main ADC 110 operates continuously at all times, and the value of the output digital signal OUT is not interrupted. Furthermore, even if the values of the offset error OS1 and the offset error OS2 change due to environmental temperature and changes over time, the values are automatically reflected in the stored values of the first register 140 and the second register 150. Can be canceled.

  In the present embodiment, the case where the process (S107) is included in the repetitive loop is illustrated, but the main ADC 110 may be operated more frequently than the sub ADC 120. That is, in addition to the processing (S107) included in the iterative loop of FIG. 2, processing for outputting the value of the main ADC (mADC) 110-first register (1Reg) 140 may be performed as appropriate.

  In the analog-digital conversion apparatus 10 of the present embodiment, the switch 130 is a component that handles analog signals, but is a simpler and less expensive component than an amplifier or an analog-digital converter. In addition, the control unit 190, the first register 140, the second register 150, the error detection unit 180, and the like can be realized with a digital circuit or firmware at low cost. For this reason, the analog-digital conversion apparatus 10 of this embodiment has few additional circuits with respect to the conventional structure, and can be implement | achieved without causing a cost increase with a simple structure.

  Further, in the conventional configuration, a failure of the analog-digital converter is detected by evaluating the difference between the conversion values of the two analog-digital converters. However, in this method, the offset error tends to be the same. In the case of a change, the change value is canceled out, so that there is a problem that failure detection is not sufficient. On the other hand, since the analog-to-digital conversion apparatus 10 of this embodiment monitors both the offset error OS1 and the offset error OS2, not only the offset voltage error is canceled but also the offset error is caused by a failure of the analog-to-digital converter. Abnormalities can also be detected when they change with the same tendency.

When the output value of the main ADC 110 and the output value of the sub ADC 120 are greatly different, the value of the offset error OS1 increases and is detected by the error detection unit 180. Therefore, two conventional analog-digital converters are used. The function of improving the reliability by collating the conversion values of is maintained.

  As described above, according to the present embodiment, in an analog-to-digital converter having two analog-to-digital converters for ensuring high reliability, an offset voltage error is reduced while performing continuous analog-to-digital conversion processing. You can cancel.

DESCRIPTION OF SYMBOLS 10 ... Analog-digital converter, 20 ... Analog-digital converter, 110 ... Main ADC, 120 ... Sub ADC, 130 ... Switch, 140 ... 1st register, 150 ... 2nd register, 160 ... 1st calculating part, 170 ... 1st 2 computing units, 180 ... error detecting unit, 190 ... control unit, 210 ... main ADC, 220 ... sub ADC, 230 ... difference computing unit, 240 ... error detecting unit

Claims (2)

An analog-digital converter comprising a first analog-digital converter and a second analog-digital converter,
A switch for switching an input to the second analog-digital converter between an input analog signal and a reference potential;
A second register for storing an output value of the second analog-digital converter when the switch is switched to a reference potential;
From the sum of the conversion result of the input analog signal in the first analog-digital converter and the stored value of the second register, the output value of the second analog-digital converter when the switch is switched to the input analog signal is obtained. A first calculation unit to be subtracted;
A first register for storing an output value of the first arithmetic unit;
An analog-to-digital conversion apparatus comprising: a second operation unit that subtracts the storage value of the first register from the conversion result of the input analog signal in the first analog-to-digital converter to generate an output digital signal.   An error detection unit that monitors the stored value of the first register and the stored value of the second register, and outputs an error signal when the value of the first register or the stored value of the second register does not satisfy a predetermined criterion The analog-digital conversion apparatus according to claim 1, further comprising: