JP5451405B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, and particularly to a technique for controlling a configuration having redundancy.

  Transistors used in semiconductor integrated circuits usually have aging characteristics such as HCI (Hot Carrier Injection), NGTI (Negative Bias Temperature Instability), etc., and switching performance (response speed) according to energization (use) time It will be lowered. Depending on the application of the semiconductor integrated circuit, it is necessary to maintain a high switching performance of the transistor for a long period of time. In such a case, measures are taken such as securing a margin corresponding to the deterioration with time according to the expected product life when designing the semiconductor integrated circuit, or making a partial circuit that requires performance maintenance redundant.

  In Patent Document 1, a disk array device including a plurality of HDDs (Hard Disk Drives) manages the energization time of each HDD in cooperation with a microcomputer and firmware, and has the longest energization time. A configuration for setting an HDD as a spare disk is disclosed.

  Further, in Patent Document 2, a method of configuring a semiconductor circuit including at least two same or similar functional units, the unit comprising a means for detecting a defect of each functional unit, and determined to be defective The structure which interrupts | blocks the electrical connection of is disclosed.

  Further, Patent Document 3 discloses an integrated circuit including a diagnostic circuit capable of diagnosing a fault even during operation, and holding the internal state of the logic circuit and returning it after diagnosis.

  Furthermore, Patent Document 4 discloses an arrangement for a thermal head integrated circuit that individually controls energization times to a plurality of heating resistors.

JP 2000-293315 A Special table 2009-514064 gazette JP 2006-300650 A Japanese Patent Laid-Open No. 11-277786

  As described above, in a semiconductor integrated circuit that requires long-term reliability, it is necessary to incorporate a margin for dealing with deterioration over time at the time of designing, and therefore, a high-spec circuit that fully utilizes the original switching performance of a transistor is provided. There is a problem that can not be. Further, when making a partial circuit that requires long-term reliability redundant, if the partial circuit to be used is not appropriately selected from among the plurality of partial circuits, the same partial circuit will continue to be used. The problem of deterioration cannot be solved.

  Further, the configuration disclosed in Patent Document 1 requires a microcomputer controlled by firmware in order to manage the energization time of each HDD. Such a configuration is suitable for a configuration in which an HDD installed in a computer system separately from the main control system and is replaceable, and has a partial circuit on one or a small number of chips. However, when applied to a semiconductor integrated circuit that is basically installed in a non-replaceable manner, various problems are caused in terms of design and cost.

  Furthermore, although the configuration disclosed in Patent Document 2 can make a defective circuit inactive, it cannot delay the deterioration of the circuit (transistor) over time and extend its life.

  Therefore, an object of the present invention is to extend the life of a semiconductor integrated circuit including a partial circuit that requires long-term reliability.

  In one embodiment of the present invention for solving the above problems, a plurality of partial circuits having the same or similar functions, a storage circuit that stores a total energization time during which the partial circuits are supplied with power, for each partial circuit, and The power supply to the partial circuit can be cut off for each partial circuit, and the respective partial energization times stored in the storage circuit are referred to, and the partial circuit has the shortest total energization time. And a power supply control circuit for controlling the power supply cutoff circuit so as to cut off the power supply to the partial circuits except for the semiconductor integrated circuit.

  According to another aspect of the present invention, there are provided a plurality of partial circuits having the same or similar functions, a storage circuit for storing the total energization time during which the partial circuits are supplied with power, for each partial circuit, and the partial circuits. The power supply to a circuit can be cut off for each partial circuit, and the total energization time stored in the storage circuit is referred to, and the partial energization time is the shortest except for the partial circuit A power supply control circuit for controlling the power supply cutoff circuit so as to cut off the power supply to the partial circuit; and at the time of the power supply to the first partial circuit, the first partial circuit of the first circuit A semiconductor integrated circuit comprising: an internal state transfer circuit for transferring an internal state of the first partial circuit to the second partial circuit when a total energization time exceeds the total energization time of the second partial circuit It is.

  According to the above aspect of the present invention, power is supplied only to the partial circuit with the shortest total energization time based on the total energization time corresponding to each partial circuit. Thereby, it is possible to equalize the total energization time of each partial circuit, and to prevent the bias of deterioration with time of each partial circuit. Thereby, the lifetime of the whole partial circuit can be extended. Moreover, according to the other aspect of the present invention, in addition to the above-described effect, the process can be continued without causing any trouble without performing a process such as initialization when switching the partial circuit to be used. .

1 is a block diagram showing a functional configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. 3 is a diagram illustrating a specific configuration of a power supply cutoff circuit according to Embodiment 1. FIG. 3 is a diagram illustrating a specific configuration of a memory circuit and a power supply cutoff control circuit according to Embodiment 1. FIG. It is a block diagram which shows the functional structure of the semiconductor integrated circuit which concerns on Embodiment 2 of this invention. It is a figure which illustrates the specific structure of the internal state transfer circuit which concerns on Embodiment 2. FIG. 6 is a diagram illustrating a specific configuration of a memory circuit and a power supply cutoff control circuit according to Embodiment 2. FIG. 6 is a time chart showing the operation of the semiconductor integrated circuit according to the second embodiment. 8 is a time chart showing in detail the operation of a clock cycle T2 in the time chart shown in FIG.

  Embodiments of the present invention will be described below with reference to the accompanying drawings. Note that, in different embodiments, the same or similar parts are denoted by the same reference numerals and description thereof is omitted.

Embodiment 1
FIG. 1 shows a functional configuration of a semiconductor integrated circuit 1 according to the present embodiment. The semiconductor integrated circuit 1 includes a power supply (power supply wiring) 2, partial circuits 3-1, 3-2, 3-3,..., 3-n, power supply cutoff circuits 4-1, 4-2, 4-3,. .., 4-n, memory circuit 5 and power supply control circuit 6 are included.

  The power source 2 corresponds to a mechanism such as a battery that generates electric power, or wiring connected to the battery or the like.

  The plurality of partial circuits 3-1, 3-2, 3-3,..., 3 -n are each operated by supplying power from the power supply 2, and all have the same or similar functions. Each of the partial circuits 3-1, 3-2, 3-3,..., 3-n is connected to the power source 2 by an independent connection path 10-1, 10-2, 10-3,. Connected.

  The plurality of power shutoff circuits 4-1, 4-2, 4-3,..., 4-n are connected to the connection paths 10-1, 10-2, 10-3,. The power supply to each partial circuit 3-1, 3-2, 3-3,..., 3-n can be cut off independently. Each of the power cut-off circuits 4-1, 4-2, 4-3,..., 4-n has power cut-off control signals 11-1, 11-2, 11-3,. , 11-n.

  The memory circuit 5 indicates the total energization time indicating the sum of the time during which power is supplied to the partial circuits 3-1, 3-2, 3-3,. This is stored every 2, 3-3,..., 3-n. The total energization time is, for example, the partial paths 3-1, 3-2, 3-3,. The time when the power supply to n is cut off (or the permitted time) can be detected by grasping from the control process of the power supply control circuit 6 or the like.

  Based on the total energization time of each of the partial circuits 3-1, 3-2, 3-3,..., 3-n stored in the storage circuit 5, the power supply control circuit 6 In order to supply power only to the circuits 3-1, 3-2, 3-3,..., 3-n, the power cut-off circuits 4-1, 4-2, 4-3,. The power cutoff control signals 11-1, 11-2, 11-3,..., 11-n to be controlled are output.

  FIG. 2 illustrates a specific configuration of the power cutoff circuit 4 (4-1, 4-2, 4-3,..., 4-n). The power cutoff circuit 4 includes a plurality of p-MOS transistors 15. A signal line 16 connected to the power supply control circuit 6 is connected to the gate of each p-MOS transistor 15. The p-MOS transistor 15 is turned off when the power cutoff control signals 11-1, 11-2, 11-3,..., 11-n input from the signal line 16 are logic “1”, and the partial circuit Shut off the power supply to 3. On the other hand, when the power cutoff control signals 11-1, 11-2, 11-3,..., 11-n are logic “0”, the p-MOS transistor 15 is turned on and the power to the partial circuit 3 is turned on. Supply is made.

  FIG. 3 illustrates a specific configuration of the memory circuit 5 and the power cutoff control circuit 6. This example shows a case where the semiconductor integrated circuit 1 includes four partial circuits 3 (3-1, 3-2, 3-3, 3-4).

  The storage circuit 5 according to this example stores the total energization time of each partial circuit 3 expressed in seconds. By assigning a 32-bit wide storage area to each partial circuit 3, a time corresponding to about 136 years can be handled. Four 32-bit width signals 21, 22, 23, and 24 output from the storage circuit 5 indicate the total energization time of the partial circuit 3, respectively.

  At initialization of the semiconductor integrated circuit 1, signals 21, 22, 23, and 24 read from the storage circuit 5 are passed through selectors 27, 28, 29, and 30, respectively, and elapsed time registers 33, 34, 35, 36. The outputs of the elapsed time registers 33, 34, 35, and 36 are compared by comparison circuits 39, 40, 41, 42, 43, and 44. These comparison results are input to the determination circuits 47, 48, 49, and 50, and the determination circuits 47, 48, 49, and 50 determine which partial circuit 3 has the shortest total energization time by combinational logic. Each determination circuit 47, 48, 49, 50 is associated with each partial circuit 3. The outputs of the determination circuits 47, 48, 49, 50 corresponding to the partial circuit 3 with the shortest total energization time are logic “0”, and the outputs of the other determination circuits 47, 48, 49, 50 are logic “1”. It becomes. The outputs of the determination circuits 47, 48, 49, 50 are held in flip-flops 59, 60, 61, 62 via selectors 53, 54, 55, 56, respectively. Each flip-flop 59, 60, 61, 62 outputs the power-off control signal 11-1, 11-2, 11-3, 11-4 described above.

  After the initialization of the semiconductor integrated circuit 1, the selectors 53, 54, 55, and 56 are the power cutoff control signals 11-1, 11-2, and 11-3 that are the outputs of the flip-flops 59, 60, 61, and 62, respectively. 11-4 are selected as inputs and output to flip-flops 59, 60, 61, 62. As a result, the values of the flip-flops 59, 60, 61, 62 do not change thereafter, and the states of the power shut-off signals 11-1, 11-2, 11-3, 11-4 are maintained.

  The adder circuits 70, 71, 72, 73 output values obtained by adding 1 to the values of the elapsed time registers 33, 34, 35, 36. After the initialization of the semiconductor integrated circuit 1, the selectors 27, 28, 29, and 30 are changed according to the values of the power cutoff control signals 11-1, 11-2, 11-3, and 11-4. The output to 33, 34, 35, 36 is changed. That is, the selectors 27, 28, 29, and 30 are added to the adder circuits 70, 71, 72, and 73 when the power control signals 11-1, 11-2, 11-3, and 11-4 are logic “0”. Is output to the elapsed time registers 33, 34, 35, and 36, and when the power control signals 11-1, 11-2, 11-3, and 11-4 are logic "1", the elapsed time register 33 is output. , 34, 35, 36 are output to the elapsed time registers 33, 34, 35, 36. As a result, the power cutoff control signals 11-1, 11-2, 11-3, 11-4 become logic "1", and the elapsed time registers 33, 34, 35, 36 corresponding to the partial circuit 3 whose power supply has been cut off. The value of is retained. On the other hand, the values of the elapsed time registers 33, 34, 35, and 36 corresponding to the partial circuit 3 to which the power cutoff control signals 11-1, 11-2, 11-3, and 11-4 are logic "0" and supplied with power are Count up in synchronization with the clock signal.

  The values of the elapsed time registers 33, 34, 35, and 36 are input to the memory circuit 5 and written as signals 76, 77, 78, and 79. The timing register 82 receives a fixed value “0” via the selector 83 when the semiconductor integrated circuit 1 is initialized, and holds this. After the initialization is completed, the adder circuit 84 outputs a value obtained by adding 1 to the value of the timing register 82, and the selector 83 selects the output of the adder circuit 84 and outputs it to the timing register 82. Thereby, the value of the timing register 82 is counted up in synchronization with the clock signal.

  The write control circuit 87 generates a signal 88 that is a write instruction to the storage circuit 5 by AND operation of all the bits of the timing register 82. The memory circuit 5 takes in the values of the elapsed time registers 33, 34, 35, and 36 from the signals 76, 77, 78, and 79 in synchronization with the clock signal 90 when the signal 88 is logic “1”. The total energization time of the partial circuit 3 (3-1, 3-2, 3-3, 3-4) is stored.

  In the above configuration, the power supply control circuit 6 operates in synchronization with the clock signal 90. The clock signal 90 is also used as a reference time for integrating the total energization time. For example, the frequency is preferably 1 Hz.

  Each signal 21, 22, 23, 24 output from the storage circuit 5 is input to the input 1X of the selectors 27, 28, 29, 30. When the reset signal 91 becomes logic “1” at the start of use of the semiconductor integrated circuit 1, the values of the inputs 1X of the selectors 27, 28, 29, 30 are selected, and these values are used as the elapsed time registers 33, 34, 35, 36. The elapsed time registers 33, 34, 35, and 36 receive and hold values output from the selectors 27, 28, 29, and 30 in synchronization with the clock signal 90.

  The selectors 27, 28, 29, and 30 indicate that when the reset signal 91 is logic “0”, the power cutoff control signals 11-1, 11-2, 11-3, and 11-4 input to the input S0 are logic. If it is "1", the output of the elapsed time registers 33, 34, 35, 36 input to the input 01 is selected and output.

  The adder circuits 70, 71, 72, 73 output a value obtained by adding 1 to the values of the elapsed time registers 33, 34, 35, 36. The selectors 27, 28, 29, and 30 indicate that when the reset signal 91 is logic “0”, the power cutoff control signals 11-1, 11-2, 11-3, and 11-4 input to the input S0 are logic. If it is “0”, the outputs of the adder circuits 70, 71, 72, 73 input to the input 00 are selected and output. The adder circuits 70, 71, 72, 73, the selectors 27, 28, 29, 30 and the elapsed time registers 33, 34, 35, 36 have the same bit width as the signals 21, 22, 23, 24 output from the storage circuit 5. Shall be handled.

  The comparison circuits 39, 40, 41, 42, 43, and 44 compare the outputs of the elapsed time registers 33, 34, 35, and 36, and when the value of the input A is equal to or less than the value of the input B, the logic “1”. Is output. By making the bit width of data compared by the comparison circuits 39, 40, 41, 42, 43, and 44 smaller than the bit width of the elapsed time registers 33, 34, 35, and 36, the circuit scale can be reduced. Become. For example, if the upper 16 bits of 32-bit data are to be compared, the granularity of determination is 35536 seconds (about 18 hours).

  The determination circuits 47, 48, 49, 50 are composed of NAND circuits, and determine the partial circuit 3 with the shortest total energization time from the outputs of the comparison circuits 39, 40, 41, 42, 43, 44. The determination circuits 47, 48, 49, and 50 correspond to the partial circuit 3 (3-1, 3-2, 3-3, 3-4), respectively, and correspond to the partial circuit 3 having the shortest total energization time. The outputs of the determination circuits 47, 48, 49, 50 are logic “0”, and the other outputs are logic “1”. The outputs of the determination circuits 47, 48, 49, 50 are respectively input to the inputs 1 of the selectors 53, 54, 55, 56, and when the reset signal 91 becomes logic “1” at the start of use of the semiconductor integrated circuit 1, the selector 53 , 54, 55, and 56 are selected and output to flip-flops 59, 60, 61, and 62, respectively. The flip-flops 59, 60, 61 and 62 receive and hold the values output from the selectors 53, 54, 55 and 56 in synchronization with the clock signal 90.

  The flip-flops 59, 60, 61, 62 output power cutoff control signals 65, 66, 67, 68. The selectors 53, 54, 55, and 56 are the values of the input 0 to which the power cutoff control signals 11-1, 11-2, 11-3, and 11-4 are input when the reset signal 91 is logic “0”. Select and output. When the reset signal 91 is ethical “1”, the selectors 53, 54, 55, and 56 select a fixed value where the value of the input 1 is 0 and output it.

  The timing register 82 inputs the output of the selector 83 in synchronization with the clock signal 90 and holds it. The adder circuit 84 outputs a value obtained by adding 1 to the value of the timing register 82. When the reset signal 91 is logic “0”, the input 0 of the selector 83 is selected and the value of the adder circuit 84 is output. The write control circuit 87 calculates an AND of all the bits of the timing register 82 and outputs the result as a signal 88.

  When the signal 88 is logic “1”, the memory circuit 5 takes in the values of the elapsed time registers 33, 34, 35, and 36 from the signals 76, 77, 78, and 79 in synchronization with the clock signal 90. The total energization time of the partial circuit 3 is stored. Note that the bit widths of the timing register 82, the adder circuit 84, and the selector 83 are preferably set in consideration of the write cycle of the total energization time to the storage circuit 5. For example, when the bit width is 8 bits, logic “1” is output to the signal 88 in a cycle of 256 seconds for one clock period, and the contents of the storage circuit 5 are updated once every 256 seconds. The present invention allows various variations in the bit width and unit of information stored in the storage circuit 5, the frequency of the clock signal 90, and the like.

  According to the semiconductor integrated circuit 1 configured as described above, the total energization time of each of the plurality of partial circuits 3 is stored. Then, based on each total energization time, the power cutoff circuit 4 corresponding to the partial circuit 3 except the partial circuit 3 with the shortest total energization time is shut off, and power is supplied only to the partial circuit 3 with the shortest total energization time. Is called. Thereby, equalization of the total energization time of each partial circuit 3 can be achieved. As a result, it is possible to prevent the partial circuits 3 from being unevenly deteriorated over time, and the lifetime of the partial circuits 3 as a whole can be extended. Further, according to the above configuration, it is not necessary to ensure an excessive design margin in the delay design of the semiconductor integrated circuit 1, and a high-spec circuit that fully utilizes the original switching performance of the transistors constituting the semiconductor integrated circuit 1 can be obtained. Can be provided. Further, in the above configuration, the presence of the redundant partial circuit 3 is hidden from the outside. Therefore, when the user uses the semiconductor integrated circuit 1, the user has a special choice for selecting the partial circuit 3 and controlling the power supply. Does not require knowledge or procedures.

Embodiment 2
FIG. 4 shows a functional configuration of the semiconductor integrated circuit 101 according to the present embodiment. The partial circuits 3-1, 3-2, 3-3,..., 3 -n according to the present embodiment have internal state transfer circuits 110-1, 110-2, 110-3,. n. The power supply control means 106 according to the present embodiment controls the power cutoff circuits 4-1, 4-2, 4-3,..., 4-n as shown in the first embodiment. , 110-n are controlled by internal state transfer circuits 110-1, 110-2, 110-3,.

  The power supply control means 106 includes the total energization time of the partial circuits 3-1, 3-2, 3-3,..., 3-n being used (power supply) and the other partial circuits 3-1 and 3. Compared with the total energization time of -2, 3-3,..., 3-n, and the total energization time of the partial circuits 3-1, 3-2, 3-3,. However, when the total energization time of the other partial circuits 3-1, 3-2, 3-3,. , 3-3,..., 3-n so that power is supplied to the power cutoff circuits 4-1, 4-2, 4-3,. -2, 11-3, 11-4 are output.

  Further, the power supply control means 106 uses the partial circuit used when executing the process of switching the partial circuits 3-1, 3-2, 3-3,. To transfer the internal state of 3-1, 3-2, 3-3,..., 3-n to the partial circuits 3-1, 3-2, 3-3,. In addition, transfer control signals 115-1, 115-2, 115-3,..., 115-n are output to the internal state transfer circuits 110-1, 110-2, 110-3,.

  The internal state transfer circuits 110-1, 110-2, 110-3,..., 110-n follow the transfer control signals 115-1, 115-2, 115-3,. -1, 3-2, 3-3,..., 3 -n transfer signals 116-1, 116-2, 116-3,. Transfer signals 116-1, 116-2, 116-3,..., 116-n are input and set as internal states of the partial circuits 3-1, 3-2, 3-3,. .

  FIG. 5 illustrates a specific configuration of the internal state transfer circuit 110 (110-1, 110-2, 110-3,..., 110-n). In the internal state transfer circuit 110 according to this example, all flip-flops 120 constituting the logic functions of the partial circuits 3-1, 3-2, 3-3,. Works. When any of the transfer control signals 115-1, 115-2, 115-3,..., 115-n becomes logic “1”, the scan mode signal 124 becomes logic “1”. The scan mode signal 124 is input to the selection control input S of all selectors 125. The selector 124 takes in data from the input 1 and outputs it when the scan mode signal 124 becomes logic “1”. As a result, all the flip-flops 120 are logically connected in a straight line and constitute a scan path that functions as one shift register. At this time, the number of flip-flops 120 becomes the scan bit length of the scan path.

  The transfer control signals 115-1, 115-2, 115-3,..., 115-n are controlled exclusively, and at a certain point in time, all the signals become logic “0” or logic “1”. Become. The transfer signals 116-1, 116-2, 116-3,..., 116-n are masked by AND operations with the transfer control signals 115-1, 115-2, 115-3,. Is done. That is, among the transfer signals 116-1, 116-2, 116-3,..., 116-n, the corresponding transfer control signals 115-1, 115-2, 115-3,. Those having logic “1” are selected and output as the transfer signal 130. When the scan mode signal 124 is logic “1”, the value of the transfer signal 130 is taken into the flip-flop 120 of the sequential scan path in synchronization with the system clock signal 121. At the same time, the data held in the flip-flop 120, that is, the internal state is output as the transfer signal 131 from the last flip-flop 120 in the scan path.

  FIG. 6 illustrates a specific configuration of the memory circuit 105 and the power cutoff circuit 106 of the semiconductor integrated circuit 101 according to this embodiment. In this example, the semiconductor integrated circuit 101 includes four partial circuits 3 (3-1, 3-2, 3-3, 3-4).

  In this embodiment, the outputs of the determination circuits 47, 48, 49, and 50 are held in flip-flops 140, 141, 142, and 143 that operate in synchronization with the clock signal 90. It is held in flip-flops 144, 145, 146, 147 in a clock cycle.

  The power shutdown control signals 11-1, 11-2, 11-3, and 11-4 perform an AND operation on the outputs of the flip-flops 140, 141, 142, and 143 and the outputs of the flip-flops 144, 145, 146, and 147. Is generated. When both of these inputs are logic “1”, a signal of logic “1” which is an instruction to cut off the power supply is output. When the transfer mode signal 150 compares the outputs of the flip-flops 140, 141, 142, and 143 with the outputs of the flip-flops 144, 145, 146, and 147 by a logical operation, there is at least one signal whose values do not match. Therefore, the logic is “1”.

  The flip-flops 155 and 156 and the scan control register 157 operate in synchronization with the system clock signal 121. The system clock signal 121 is a clock used for realizing the logical functions of the partial circuits 3-1, 3-2, 3-3 and 3-4, and has a higher frequency than the clock signal 90. The transfer mode signal 150 is input to the flip-flop 155 in synchronization with the system clock signal 121, and its output is held in the flip-flop 156 in the next clock cycle. When the output of the flip-flop 155 is logic “1” and the output of the flip-flop 156 is logic “0”, the transfer activation signal 159 becomes logic “1”.

  The selector 161 selects the input 1X when the transfer activation signal 159 input to the selection control input S1 is logic “1”. The input 1X is supplied with the scan bit length (fixed value) of the scan path built in the partial circuits 3-1, 3-2, 3-3, 3-4. For example, when a 511-bit flip-flop exists in the partial circuits 3-1, 3-2, 3-3, and 3-4 and a 511-bit scan path is configured, the numerical value 511 is expressed in binary. Input 1X. The output of the selector 161 is input to the scan control register 157 and held.

  The subtraction circuit 163 outputs a value obtained by subtracting 1 from the value of the scan control register 157. The transfer execution signal 165 becomes logic “1” when the value of the scan control register 157 is other than 0. When the transfer start signal 159 is logic “0” and the transfer execution signal 165 is logic “1”, the selector 161 takes in and outputs the value of the subtraction circuit 163 from the input 01, and the transfer execution signal 165 is logic “0”. Then, the value of the scan control register 157 is fetched from the input 00 and output. As a result, the value of the scan control register 157 is decreased in synchronization with the system clock signal 121. When the value reaches 0, the state is maintained until the next transfer start signal 159 becomes logic “1”.

  FIG. 7 shows the operation of the semiconductor integrated circuit 101 according to this embodiment. In the clock cycle T0, the first partial circuit 3-1 is used, and the output of the first determination circuit 47 is logic “0”. At this time, the outputs of the second to fourth determination circuits 48, 49 and 50 corresponding to the second to fourth partial circuits 3-2, 3-3 and 3-4 which are not used are logical “1”. It becomes. Assuming that this state has continued from before the clock cycle T0, the outputs of the flip-flops 140 and 144 corresponding to the first partial circuit 3-1 become logic “0”, and the other flip-flops 141, 142, 143, and 143 The outputs of 145, 146, and 147 are logic "1". As a result, the first power cut-off control signal 11-1 becomes logic “0”, and enters a state instructing execution of power supply to the first partial circuit 3-1. Further, the second to fourth power shutoff control signals 11-2, 11-3, 11-4 become logic "1", and the second to fourth partial circuits 3-2, 3-3, 3-4. It is in a state of instructing to cut off the power supply to

  In the clock cycle T1, the first elapsed time register 33 becomes larger than the second elapsed time register 34 by a predetermined value or more, the output of the first determination circuit 47 becomes logic “1”, and the second determination circuit 48 The output becomes logic “0”.

  Next, in clock cycle T2, the values of both determination circuits 47 and 48 are taken into flip-flops 140 and 141, and the respective values become logic “1” and “0”. At this time, since the flip-flop 144 maintains the logic “0”, the first power-off control signal 11-1 is in the logic “0” state, that is, the power supply to the first partial circuit 3-1. Continue to execute instructions. On the other hand, the second power-off control signal 11-2 transitions from logic “1” to “0” when the flip-flop 141 changes to logic “0”. That is, power is also supplied to the second partial circuit 3-2. At the same time, the transfer mode signal 150 transitions from logic “0” to “1” and transfers the internal state of the first partial circuit 3-1 to the second partial circuit 3-2 (internal The state transfer process is started. The internal state transfer process is completed in clock cycle T2.

  Next, in the clock cycle T3, the values of the flip-flops 140 and 141 are taken into the flip-flops 144 and 145, and the respective states are inverted. As a result, the state of the first power cut-off control signal 11-1 changes from logic “0” to “1”, and the power supply to the first partial circuit 3-1 is cut off. At the same time, the transfer mode signal 150 transitions from logic “1” to “0”, and the internal state transfer process ends. Thereafter, the state of each part does not change after the clock cycle T4.

  FIG. 8 is a time chart showing in detail the operation of the clock cycle T2 in the time chart shown in FIG. The clock cycle in the figure corresponds to the system clock signal 121. In the clock cycle T0, the transfer mode signal 150 is logic “0”, and the internal state transfer process is not started. At this time, the flip-flops 155 and 156 maintain the logic “0”, and the transfer activation signal 159 is also in the logic “0” state. Therefore, the value of the scan control register 157 is 0, and the transfer execution signal 165 and the first to fourth transfer control signals 115-1, 115-2, 115-3, and 115-4 are logic "0". As a result, the internal state transfer process is not executed.

  Next, in clock cycle T1, transfer mode signal 150 transitions from logic “0” to “1”, and in clock cycle T2, flip-flop 155 captures this, so that transfer start signal 159 changes from logic “0” to “1”. Transition to “1”. Thereby, an internal state transfer process is started.

  Next, in clock cycle T 3, the scan bit length of the first partial circuit 3-1 is fetched from the input 1 X of the selector 161 and set in the scan control register 157. The scan bit length in this example is 511. As a result, the transfer execution signal 165 transitions to the logic “1”, and the first transfer control signal 115-1 corresponding to the first partial circuit 3-1 used so far also transitions to the logic “1”. . At this time, the other transfer control signals 115-2, 115-3, and 115-4 maintain the logic "0" state. As a result, the first and second partial circuits 3-1 and 3-2 that are supplied with power at this time have the internal state of the first partial circuit 3-1 in the second portion after the next clock cycle. It operates so as to be sequentially transferred to the circuit 3-2. In the clock cycle T3, the flip-flop 156 takes in the value of the flip-flop 155 and transitions to the logic “1”, so that the transfer activation signal 159 returns to the logic “0”.

  After the clock cycle T4, the value of the scan control register 157 is decremented by 1 every clock cycle and becomes 0 at the clock cycle T514. As a result, the transfer execution signal 165 transitions to logic “0”, the first transfer control signal 115-1 also returns to logic “0”, and the internal state transition process ends. After the clock cycle T516, the value of the scan control register 157 is maintained at 0, and the state is maintained until the next transfer mode signal 150 transitions to logic “1”.

  According to the semiconductor integrated circuit 101 having the above configuration, in addition to the effects of the first embodiment, when the partial circuit 3 to be used is switched, the processing is continued without causing any trouble even if the initialization is not performed. can do. The semiconductor integrated circuit 101 according to the present embodiment can be suitably used for, for example, a product that is required to operate continuously until the product life is reached after the start of operation.

  The present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit of the present invention.

1,101 Semiconductor integrated circuit 2 Power supply 3 (3-1, 3-2, 3-3,..., 3-n) Partial circuit 4 (4-1, 4-2, 4-3,..., 4- n) Power shutdown circuit 5 Memory circuit 6,106 Power supply control circuit 11 (11-1, 11-2, 11-3,..., 11-n) Power shutdown control signal 110 (110-1, 110-2, 110-3, ..., 110-n) Internal state transfer means 115 (115-1, 115-2, 115-3, ..., 115-n) Transfer control signal

Claims (2)

A plurality of partial circuits having the same or similar functions;
A storage circuit for storing the total energization time during which the partial circuit is supplied with power for each partial circuit;
A power cutoff circuit capable of shutting off the power supply to the partial circuit for each partial circuit;
A power source that controls the power shut-off circuit with reference to each of the total energization times stored in the storage circuit so as to shut off the power supply to the partial circuits except the partial circuit with the shortest total energization time. A supply control circuit;
A time the power supply to the first part worth circuit included in the plurality of partial circuits, the second part component circuit in which the total energization time of the first partial circuit is included in the plurality of partial circuits An internal state transfer circuit for transferring the internal state of the first partial circuit to the second partial circuit when the total energization time of
A semiconductor integrated circuit comprising: The power supply control circuit is configured by a combination of logic circuits.
The semiconductor integrated circuit according to claim 1 .

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