JP2010016653A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which achieves a low power consumption LSI and reduce power consumption of the LSI without deteriorating other performances. <P>SOLUTION: A low power consumption LSI 101 includes an aging deterioration coefficient table 104 which stores mainly an operating voltage value obtained by subtracting a voltage corresponding to an aging deterioration margin from a reference voltage in an early stage of operation where degradation is small, and the operating voltage value gradually getting close to the reference voltage to guarantee the same performance with the progress of the aging deterioration. A power-supply voltage control unit 102 obtains the optimal operating voltage value based on an actual use time stored in a nonvolatile storage unit 105 and the value in the aging deterioration coefficient table 104 and changes a power-supply voltage based on this operating voltage value. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly, to an improvement in a low power consumption LSI and a technique for reducing the power consumption of an LSI.

  The system LSI has realized high performance by increasing the speed of semiconductor elements and the number of mounted transistors in accordance with the market demand for high-speed processing / high-speed communication and the progress of miniaturization technology of the semiconductor manufacturing process. According to Moore's Law proposed by Golden Moore, it is said that the number of transistors integrated on a semiconductor chip doubles every two years. In recent years, the limit is approaching Moore's Law. One of the grounds is an increase in power consumption of LSI. In the field of mobile products, reducing the power consumption of LSI has already become an important issue. In the field of servers and home products that are not driven by a battery, heat generation due to an increase in power consumption is a problem, and low power consumption of LSIs is a major issue.

Power consumption in the system LSI can be broadly divided into dynamic power and leakage power resulting from transistor switching. The dynamic power Pd in the CMOS circuit is expressed by the following formula (1).
Pd = αCV ^2f (1)
Where α: switching established, C: load capacity, V: power supply voltage, f: operating frequency

  With the miniaturization of the process, the power supply voltage V has been lowered, and the dynamic power has been reduced per unit transistor. However, in recent years, there is a tendency that the power supply voltage V cannot be lowered even if the process evolves due to an increase in leakage current accompanying a decrease in Vth. The dynamic power Pd tends to increase. Examples of techniques for reducing dynamic power include clock gating that stops clocks at places where switching is not required, multi-power supplies that use a plurality of power supply voltages in the LSI, and DVFS (dynamically changing the voltage and frequency according to the processing load) Dynamic Voltage and Frequency Scaling) is used.

  On the other hand, the leakage current is classified into a subthreshold leakage current, a gate leakage current, a junction leakage current, and the like. In order to maintain the same performance at a low voltage, it is necessary to reduce the gate oxide film thickness and reduce the threshold voltage Vth. As a result, subthreshold leakage current and gate leakage current have increased due to miniaturization. In addition, leakage power when viewed as an LSI has increased dramatically in recent years due to the influence of the adoption of a low Vt cell due to high speed, the increase in the number of elements due to high integration, and self-heating due to the increase in power density. Unless special measures are taken, the leak current is so large that it is said to occupy the same proportion as the dynamic power in the process generation of 65 nm or less. Technologies to reduce leakage power include high-k insulating film, multi-Vth that uses multiple types of Vth transistors properly, power shut-off that divides the LSI into multiple power domains and shuts off unnecessary domain power, and substrate power Substrate bias control for applying a bias to Vth to control Vth is used.

  Further, when Vth is reduced as the process is miniaturized, even if the absolute value of the variation amount of Vth is the same as the conventional one, the ratio of the absolute value to Vth increases. Yes.

Patent Document 1 discloses a semiconductor integrated circuit device in which a performance measurement circuit is provided inside an LSI, and the operation speed, power consumption, and the like of the circuit function module are measured and stored at the time of LSI inspection. The device described in Patent Document 1 considers manufacturing variations for each chip, and selects the frequency, power supply voltage, and substrate bias that can achieve the lowest power consumption with the same performance.
JP 2004-228417 A

  Incidentally, the variation in Vth includes variations due to aging as well as variations in manufacturing. For example, one example is that hot carriers generated in the channel of the MOSFET are injected and captured in the gate insulating film to cause fluctuations in Vth (speed deterioration). Therefore, in order to guarantee the operation of the LSI for a specified period, it is necessary to design and inspect such semiconductor devices over time. For this reason, in general, a design in which a speed deterioration due to secular change is added as a design margin in advance is performed. Further, in the inspection, a technique such as guaranteeing the operation during a specified period by subtracting the design margin from the inspection voltage in advance is employed.

  As described above, the LSI considering the aging deterioration has a problem as described below because it is necessary to add a design coefficient for guaranteeing the specified operation period.

  First, since the design is performed assuming that the operation speed becomes slow due to aging deterioration, there is an unnecessary speed margin in the initial stage of use where no aging deterioration has occurred. That is, at the initial stage of use, the device operates at a voltage value higher than the device capability.

  Secondly, when operating at the same voltage value as after aging even at the initial stage of use where no aging has occurred, the degree of aging is lower than when operating at the optimum operating voltage according to aging. Will become bigger.

  The method for reducing power consumption disclosed in Patent Document 1 takes into account manufacturing variations, but cannot provide a solution to these problems due to aging.

  SUMMARY An advantage of some aspects of the invention is that it provides a low power consumption LSI and a semiconductor integrated circuit device that achieves low power consumption of the LSI without reducing other performance.

  A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device in which transistors operating with a power supply voltage are integrated, and includes an actual use time measuring means for measuring the application time of the power supply voltage as an actual use time, and a measured actual use Storage means for storing time, an aging deterioration coefficient table for storing in advance the relationship between the power supply voltage application time and the operation voltage for guaranteeing the operation speed of the transistor, and the actual use time stored in the storage means An optimum operating voltage value is obtained from the value of the aging degradation coefficient table, and a power supply voltage control means for changing the power supply voltage based on the operating voltage value is adopted.

  According to the present invention, the low power consumption LSI and the low power consumption of the LSI can be achieved without degrading other performances by operating at a voltage that is lower by the aging deterioration margin at the initial stage of operation with little aging deterioration. be able to.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Principle explanation)
First, the basic concept of the present invention will be described.

  FIG. 1 is a diagram showing the amount of transistor deterioration with respect to the actual use time, with the actual use time on the horizontal axis and the transistor deterioration [%] on the vertical axis.

  In FIG. 1, the amount of deterioration increases with time from the initial deterioration amount Y (0) at the start of use, and finally deteriorates to the time point Y (X) of the product warranty period X (see FIG. 1a). Indicates progress. From the initial deterioration amount Y (0) at the start of use to the time point Y (X) of the product warranty period X is the transistor deterioration amount due to the use of X years (see FIG. 1b).

  Here, the reason why the deterioration amount at the start of use is not 0 but Y (0) is as follows. That is, in a normal LSI inspection, a burn-in test for screening initial defects is performed. For this reason, a certain degree of deterioration occurs even at the start of use. Therefore, the amount of deterioration that occurs due to the actual usage time of the product warranty period X is Y (X) -Y (0). In other words, from the viewpoint of design, the LSI needs to be designed with a margin so that it can operate even if Y (X) speed degradation occurs. Y (0) before shipment is also Y (0). This means that an inspection considering the deterioration of X) is necessary.

  FIG. 2 is a diagram showing the transistor operation lower limit voltage with respect to the actual use time. FIG. 2 is obtained by replacing the vertical axis of the graph of FIG. 1 with the operating voltage of the transistor. The curve in FIG. 2 is an operation lower limit voltage (V.limit), and indicates that it is necessary to supply a voltage equal to or higher than V.limit in order to operate the LSI normally. As is apparent from FIG. 2, at the start of use, that is, when there is no deterioration due to actual use, the LSI can be operated at a lower voltage V (0) as much as there is no speed deterioration. As the time elapses, the operation lower limit voltage (V.limit) increases, and it is finally necessary to supply V (X). For this reason, conventionally, it has been necessary to apply the reference operating voltage V.Ref so that the voltage does not become lower than the operation lower limit voltage V (X) in the product warranty period X.

  Here, when comparing the reference operating voltage V.Ref and the operating lower limit voltage V.limit, it can be seen that the difference between V.Ref and V.limit is particularly large at the initial stage of use. The inventor pays attention to this point and updates the set voltage in a certain period as V.New. In other words, at the initial stage of design, the voltage is set to a value as close as possible to V (0) and operated at a low voltage. As the aging progresses, the voltage value is periodically updated so that it does not become lower than V.limit. Finally, the voltage is set so as to approach V.Ref. Figure 2b. The shaded portion shown in FIG.

  In this way, at the initial stage of operation with little aging degradation, it is possible to achieve low power consumption without degrading performance by operating at a voltage that is as low as the aging degradation margin.

(Embodiment 1)
FIG. 3 is a block diagram showing a configuration of the semiconductor integrated circuit device according to the first embodiment of the present invention based on the above basic concept. The present embodiment is an example applied to a low power consumption LSI in which MOSFETs are integrated.

  In FIG. 3, the low power consumption LSI 101 includes a power supply voltage control unit 102, an actual usage time measurement unit 103, an aging degradation coefficient table 104, a nonvolatile storage device 105, and a power supply 106.

  FIG. 3 shows the minimum necessary functional blocks. In an actual LSI, there are a plurality of functional blocks in addition to the functional blocks. The low power consumption LSI 101 is supplied with a system power source 110 and a power-on reset 109 from an external power source 107. Further, the low-power consumption LSI 101 is supplied with a low-speed clock 111 from an RTC (Real Time Clock) 108 to the actual usage time measuring unit 103.

  The power supply voltage control unit 102 is optimized according to the power supply voltage application time of the low power consumption LSI 101 based on the values of the power-on reset 109 from the external power supply 107 and the actual usage time measurement unit 103 and the aging degradation coefficient table 104. An operating voltage value is obtained, and the power supply voltage is changed based on the operating voltage value. Specifically, the power supply voltage control unit 102 instructs the optimum operating voltage corresponding to the usage time to the power supply 106 using information in the actual usage time measurement unit 103 and the aging degradation coefficient table 104. In particular, the power supply voltage control unit 102 converts the speed deterioration due to aging deterioration into voltage, and performs power supply voltage control that lowers the operating power supply voltage and increases the voltage according to aging deterioration at the initial stage of use. In addition, the power supply voltage control unit 102 periodically updates the aging deterioration time stored in the nonvolatile storage device 105 to the latest value.

  The actual use time measuring unit 103 measures the power-on reset 109 from the external power supply 107 and the power supply voltage application time of the low power consumption LSI 101 as the actual use time. In particular, the actual use time measuring unit 103 measures the power supply voltage application time supplied to the LSI from the outside.

  The aging degradation coefficient table 104 stores a relationship between a power supply voltage application time and an operation voltage for guaranteeing the operation speed of the transistor as a table value in advance. That is, in the aging deterioration coefficient table 104, the operation voltage value obtained by subtracting a voltage corresponding to the aging deterioration margin from the reference voltage is mainly stored at the initial stage of operation with little aging deterioration. In order to guarantee the performance, the operation voltage value that approaches the reference voltage step by step is stored.

  The nonvolatile storage device 105 stores the actual usage time measured by the actual usage time measurement unit 103. Specifically, since the nonvolatile storage device 105 periodically stores and updates the measured aging deterioration time, it stores the total aging deterioration time even when the external power source 107 is shut off. The nonvolatile storage device 105 is configured by a nonvolatile memory such as an EEPROM, for example.

  The power supply 106 is supplied with a system power supply 110 from an external power supply 107, and supplies an operating power supply voltage variably to the inside of the low power consumption LSI 101 supplied based on the system power supply 110. The power supply 106 can change the power supply voltage based on the operating voltage value notified by the power supply voltage control unit 102.

  The operation of the semiconductor integrated circuit device configured as described above will be described below.

  First, the system power supply 110 is turned on from the external power supply 107, and the operating power supply voltage of the low power consumption LSI 101 is boosted. After the power supply is stabilized, the power-on reset 109 is canceled, and the power supply voltage control unit 102 and the actual usage time measurement unit 103 start operating. The actual usage time measurement unit 103 counts time using the low-speed clock 111 supplied from the RTC 108. Here, an example is shown in which a low-speed clock supplied from the RTC 108 is used as a time measuring means for convenience, but any device capable of measuring time may be used.

  Next, the actual usage time measurement unit 103 supplies an interrupt signal 112 to the power supply voltage control unit 102 when measuring a certain period of time. When the power supply voltage control unit 102 detects the interrupt signal 112, it reads the actual use time stored from the nonvolatile storage device 105 and adds the value measured by the actual use time measurement unit 103 to calculate the current use time. To do. Then, the power supply voltage control unit 102 refers to the aging degradation coefficient table 104 and finds an optimum operating voltage corresponding to the calculated usage time. Thereafter, the power supply voltage control unit 102 notifies the power supply 106 of the power supply voltage control signal 113. The calculated actual use time is written in the nonvolatile storage device 105.

  The power supply 106 changes the power supply voltage 114 according to the instruction of the power supply voltage control signal 113. This cycle is periodically repeated to control the operating voltage to change according to the aging time.

  In this way, at the initial stage of operation with little aging degradation, it is possible to achieve low power consumption without degrading performance by operating at a voltage that is as low as the aging degradation margin.

  As described above, according to the present embodiment, the low power consumption LSI 101 mainly uses an operation voltage value obtained by subtracting a voltage corresponding to an aging deterioration margin from a reference voltage in an initial operation stage with little aging deterioration. The aging deterioration coefficient table 104 stores the operation voltage value that gradually approaches the reference voltage in order to guarantee the same performance as the aging deterioration proceeds. The optimum operating voltage value is obtained from the actual usage time stored in the device 105 and the value of the aging deterioration coefficient table 104, and the power supply voltage is changed based on this operating voltage value. The power consumption of the power-powered LSI 101 can be reduced. That is, at the initial stage of the start of use, it is possible to operate even at a lower voltage than the speed margin. In addition, it is possible to mitigate the aging deterioration by setting the optimum operating voltage according to the aging deterioration. As a result, since the speed margin required at the time of design can be reduced in advance, the circuit itself can be designed to have a smaller area / low power consumption at the time of design.

  In the present embodiment, the speed margin due to aging deterioration is converted into voltage, and is subtracted from the operating power supply voltage to achieve low power consumption of the device in the initial stage of use without degrading performance. In addition, since the operating power supply voltage can be set low at the beginning of use, the degree of aging deterioration with respect to the usage time can be alleviated, and the life of the device can be extended. On the other hand, if the guaranteed operation period is determined, the speed margin required at the time of design can be reduced by taking this mitigation into consideration, so the designed circuit itself can be designed to have a smaller area and lower power consumption. Is possible.

  In this embodiment, the interrupt signal 112 is supplied from the actual usage time measurement unit 103. However, the power supply voltage control unit 102 uses another signal as a trigger to read the value of the actual usage time measurement unit 103. May be.

(Embodiment 2)
In the first embodiment, the case where the actual usage time measurement unit 103 and the RTC 108 are used has been described. In the second embodiment, a semiconductor integrated circuit device using a receiving unit that receives time information from a wired / wireless network instead of the actual usage time measuring unit 103 will be described.

  FIG. 4 is a block diagram showing a configuration of the semiconductor integrated circuit device according to the second embodiment of the present invention. The same components as those in FIG. 3 are denoted by the same reference numerals, and description of overlapping portions is omitted.

  In FIG. 4, the low power consumption LSI 201 includes a power supply voltage control unit 202, a baseband signal processing unit 213, an aging degradation coefficient table 104, a nonvolatile storage device 205, and a power supply 106.

  FIG. 4 shows the minimum necessary functional blocks, and an actual LSI includes a plurality of functional blocks in addition to the functional blocks. The low power consumption LSI 201 is supplied with a system power supply 110 and a power-on reset 109 from an external power supply 107. In addition, the RF receiving unit 212 and the antenna 211 are connected to the baseband signal processing unit 213 of the low power consumption LSI 201.

  The operation of the semiconductor integrated circuit device configured as described above will be described below.

  The RF receiving unit 212 receives an RF signal 214 from an unshown wireless network via the antenna 211. The RF receiving unit 212 outputs the received baseband signal 215 including the time information to the baseband signal processing unit 213.

  The baseband signal processing unit 213 receives time information from the wireless network received by the RF receiving unit 212.

  In addition to the function of the nonvolatile storage device 105 of FIG. 3, the nonvolatile storage device 205 stores a shipping time in advance at the time of LSI inspection.

  In addition to the function of the power supply voltage control unit 102 in FIG. 3, the power supply voltage control unit 202 measures the real time from the difference between the time information received by the RF reception unit 212 and the shipping time stored in the nonvolatile storage device 205. I do.

  As described above, according to the present embodiment, the actual use time can be calculated by subtracting the LSI shipping time from the current time information acquired by the RF receiver 212, and the same effects as in the first embodiment, It is possible to achieve low power consumption of the low power consumption LSI 101 without lowering other performance.

  Further, the actual usage time measurement unit 103 of FIG. 3 does not need to be installed in the low power consumption LSI 201, and the RTC 108 is unnecessary, so that the circuit can be simplified and the cost can be reduced. For example, when the low power consumption LSI 201 is mounted on a communication terminal such as a mobile phone, the baseband signal processing unit of these communication devices can be used.

  In the present embodiment, a case where time information is received from a wireless network is described as an example, but a wired network may be used.

(Embodiment 3)
FIG. 5 is a block diagram showing a configuration of the semiconductor integrated circuit device according to the third embodiment of the present invention. The same components as those in FIG. 3 are denoted by the same reference numerals, and description of overlapping portions is omitted.

  In FIG. 5, the low power consumption LSI 301 includes a power supply voltage control unit 102, an actual usage time measurement unit 103, an aging degradation coefficient table 104, and a nonvolatile storage device 105.

  The low power consumption LSI 301 is supplied with a system power source 110 and a power-on reset 109 from an external power source 307. Further, the power supply voltage control unit 102 outputs a power supply voltage control signal 313 to the external power supply 307.

  As a result, the low power consumption LSI 301 is supplied with the internal power supply voltage from the external power supply 307, and the power supply 106 shown in FIG.

(Embodiment 4)
FIG. 6 is a block diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 4 of the present invention. The same components as those in FIG. 5 are denoted by the same reference numerals, and description of overlapping portions is omitted.

  In FIG. 6, the low power consumption LSI 401 includes a power supply voltage control unit 102, an actual usage time measurement unit 103, and an aging degradation coefficient table 104.

  The low power consumption LSI 401 uses a nonvolatile storage device 405 as an external device.

  The nonvolatile storage device 405 stores the actual usage time measured by the actual usage time measurement unit 103, similarly to the nonvolatile storage device 105 of FIG. The nonvolatile storage device 405 stores the total aging time even when the external power supply 307 is shut off.

  As described above, the nonvolatile storage device 405 may be configured by an external device instead of the low power consumption LSI 401.

(Embodiment 5)
FIG. 7 is a block diagram showing a configuration of a semiconductor integrated circuit device according to the fifth embodiment of the present invention. The same components as those in FIG. 5 are denoted by the same reference numerals, and description of overlapping portions is omitted.

  In FIG. 7, the low power consumption LSI 501 includes a power supply voltage control unit 502, an actual usage time measurement unit 103, an aging degradation coefficient table 504, a nonvolatile storage device 105, and a substrate voltage output power supply 506.

  The aging degradation coefficient table 504 stores in advance the relationship between the power supply voltage application time and the substrate voltage for guaranteeing the operation speed of the transistor.

  The substrate voltage output power supply 506 supplies the substrate voltage inside the low power consumption LSI 501. The substrate voltage output power supply 506 supplies the internal power supply voltage 514 to the power supply voltage control unit 502, the actual usage time measurement unit 103, the aging degradation coefficient table 504, and the nonvolatile memory device 105. In addition, the power supply voltage control unit 502 outputs a power supply voltage control signal 513 to the substrate voltage output power supply 506.

  Based on the values of the actual usage time measurement unit 103 and the aging degradation coefficient table 504, the power supply voltage control unit 502 supplies an optimum substrate voltage value corresponding to the power supply voltage application time of the low power consumption LSI 501 to the substrate voltage output power supply 506. Inform. The substrate voltage output power source 506 changes the substrate voltage based on the notified substrate voltage value.

  As described above, according to the present embodiment, the power supply voltage control unit 502 controls the substrate bias instead of controlling the operation power supply voltage as in the above embodiments. That is, at the initial stage of use, reverse bias is applied to the substrate to reduce the leakage current, and the substrate voltage is increased by an amount that cancels out the speed deterioration due to aging according to the usage time. It is suitable for application to substrate bias control in which a substrate power supply is biased to control Vth. Therefore, as in the case of each of the above embodiments, the operating power supply voltage can be set low at the beginning of use, and accordingly, the degree of aging deterioration with respect to the use time can be reduced, and the device life can be extended. it can. On the contrary, when the operation guarantee years are determined, the speed margin required at the time of design can be reduced by taking this mitigation into consideration, so that the designed circuit itself can be designed to have a smaller area / low power consumption. Is possible.

  Of course, this embodiment may be combined with each of the above embodiments.

  The above description is an illustration of a preferred embodiment of the present invention, and the scope of the present invention is not limited to this. For example, each of the above embodiments is applied to a semiconductor integrated circuit device in which MOSFETs are integrated, but the same effect can be obtained also in the case of a CMOS circuit and a low power consumption LSI using the same. .

  In each of the above embodiments, the name “semiconductor integrated circuit device” is used. However, this is for convenience of description, and may be a low power consumption LSI, a semiconductor integrated circuit, a method for reducing power consumption of an LSI, or the like. Of course.

  Further, the types, numbers, connection methods, and the like of each circuit unit constituting the semiconductor integrated circuit device, for example, the deterioration coefficient table are not limited to the above-described embodiments.

  The semiconductor integrated circuit device according to the present invention is not only useful for products in the mobile field where a longer operating time is required, but is also widely applied to servers and home products where low power consumption is required. To get.

The figure which shows the transistor deterioration amount with respect to the actual use time of this invention The figure which shows the transistor operation minimum voltage with respect to the actual use time of this invention 1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. A block diagram showing a configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention. Block diagram showing a configuration of a semiconductor integrated circuit device according to a third embodiment of the present invention. Block diagram showing a configuration of a semiconductor integrated circuit device according to a fourth embodiment of the present invention. Block diagram showing a configuration of a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

Explanation of symbols

101, 201, 301, 401, 501 Low power consumption LSI
102, 202, 502 Power supply voltage control unit 103 Actual use time measurement unit 104, 504 Aging coefficient table 105, 205, 405 Non-volatile storage device 106 Power supply 107, 307 External power supply 108 RTC
211 Antenna 212 RF Reception Unit 213 Baseband Signal Processing Unit 506 Substrate Voltage Output Power Supply

Claims (8)

A semiconductor integrated circuit device in which transistors operating with a power supply voltage are integrated,
An actual usage time measuring means for measuring the application time of the power supply voltage as an actual usage time;
Storage means for storing the measured actual use time;
Aged deterioration coefficient table for storing in advance the relationship between the power supply voltage application time and the operating voltage for guaranteeing the operating speed of the transistor;
Power supply voltage control means for obtaining the optimum operating voltage value from the actual use time stored in the storage means and the value of the aging degradation coefficient table, and changing the power supply voltage based on the operating voltage value;
A semiconductor integrated circuit device.   The aging degradation coefficient table stores the operating voltage value obtained by subtracting the voltage corresponding to the aging degradation margin from the reference voltage at the initial stage of operation with little aging degradation, and is stepwise to guarantee the same performance as the aging progresses. 2. The semiconductor integrated circuit device according to claim 1, wherein the operating voltage value is stored such that the operating voltage value approaches the reference voltage.   2. The semiconductor integrated circuit device according to claim 1, wherein said power supply voltage control means converts the speed deterioration due to aging deterioration into voltage, lowers the operating power supply voltage at the initial stage of use, and increases the voltage according to aging deterioration. . It has a power supply that supplies the substrate voltage,
The power supply voltage control means obtains the optimum substrate voltage value from the actual use time stored in the storage means and the value of the aging degradation coefficient table, and changes the substrate voltage based on the substrate voltage value. The semiconductor integrated circuit device described.   The power supply voltage control means converts the speed deterioration due to aging to the substrate voltage, and at the initial stage of use, reverse bias is applied to the substrate to reduce the leakage current, and the speed deterioration due to aging according to the usage time. 5. The semiconductor integrated circuit device according to claim 4, wherein the substrate voltage is increased by the amount to be offset.   2. The semiconductor integrated circuit device according to claim 1, wherein the actual use time measuring means measures a power supply voltage application time supplied from outside. The actual usage time measuring means includes receiving means for receiving time information from the outside,
Shipping time storage means for storing the shipping time;
2. The semiconductor integrated circuit device according to claim 1, wherein the actual use time is calculated by subtracting the shipping time from the acquired current time information. 2. The semiconductor integrated circuit device according to claim 1, wherein the storage means is a nonvolatile storage device that stores a total aging time when the power is turned off.

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