JP5450580B2 - Digital modulation signal generator and digital modulation signal generation method - Google Patents

Description

  The present invention reduces a skew (signal timing deviation) generated between signal generators when the output signals of a plurality of signal generators are combined and output to a MIMO terminal, for example, for testing a MIMO terminal. For technology.

MIMO (Multi Input) used in mobile communications
Multi Output) is a method for performing high-speed data communication using M × N paths formed between a plurality of M antennas of a base station and a plurality of N antennas of a terminal.

  In order to test the reception function of a terminal corresponding to the MIMO system, a signal generating means for transmitting a plurality of M-sequence digital modulation signals modulated with different data signals is required. A single device to be configured with a container becomes large and expensive.

  Therefore, a conventional method has been adopted in which multiple general-purpose single-system digital modulation signal generators are used, their signal outputs are combined, and this is given to the test object as a test signal that simulates a MIMO propagation signal. Has been.

  When a test signal simulating a MIMO propagation signal is generated by combining the output signals of a plurality of digital modulation signal generators as described above, a common system clock is usually supplied to the plurality of signal generators for synchronization. However, due to the difference in signal delay in each signal generator, timing deviation (skew) occurs in the signal data output from each digital modulation signal generator. If this skew becomes so large that it cannot be ignored with respect to the data bit rate, the MIMO test cannot be performed correctly.

  A digital modulation signal generator that generates a digital modulation signal whose phase and amplitude are modulated in accordance with the D / A conversion of the baseband signal and input to the quadrature modulator is disclosed in, for example, the following patent: It is disclosed in Document 1 and the like.

JP 2007-116240 A

  As described in Reference 1, the digital modulation signal generator performs D / A conversion on each of the I and Q baseband signals generated and output at a predetermined sampling rate, and orthogonally modulates the carrier signal with the output value. Since it has a configuration that generates and outputs a digital modulation signal having an amplitude and phase corresponding to the baseband signals of I and Q, the baseband signals of I and Q are stored in the memory in synchronization with the sampling clock. However, it is possible to change the data output timing by adopting a configuration in which the read timing is delayed by an integer number of sampling clocks, but in that case, an integer multiple of the sampling clock period (that is, in units of samples) However, it was not sufficient in terms of accuracy, because it was only possible to adjust the timing at the time, and could not cope with a finer timing shift.

  An object of the present invention is to solve this problem and to provide a digital modulation signal generating apparatus and method capable of adjusting timing in a time shorter than the period in addition to an integral multiple of the period of the sampling clock.

In order to achieve the above object, a digital modulation signal generator according to claim 1 of the present invention comprises:
A baseband signal generator (21) for outputting a baseband signal in synchronization with a predetermined sampling clock;
A delay processing unit (22) for giving a desired delay to the baseband signal output from the baseband signal generating unit and outputting the delayed signal,
A digital modulation signal generator for outputting a modulation signal modulated by a baseband signal output from the delay processing unit,
The delay processing unit
Sequentially storing the baseband signal input in synchronization with the sampling clock, and a memory for reading out the stored order (24A, 24B), a time difference between the write timing and read timing of the baseband signal against in the memory A coarse control unit (23), which comprises a memory control unit (25) for controlling to a desired value, and gives a delay of a desired integer multiple of the period of the sampling clock to the input baseband signal, and outputs it.
A digital filter (27A, 27B) that multiplies a plurality of consecutively input baseband signals and a plurality of preset filter coefficients and outputs the sum, and a signal output from the digital filter includes A coefficient memory (31) that stores in advance a plurality of sets of filter coefficients necessary for providing a desired delay in units of time shorter than the period of the sampling clock, and a time shorter than the period of the sampling clock from the coefficient memory And a coefficient setting unit (32) for reading out a filter coefficient for setting a unit delay to a desired value and setting the filter coefficient in the digital filter. The input baseband signal includes a desired unit in a time unit shorter than the period of the sampling clock. It is characterized by comprising a fine adjustment section (26) for providing a delay.

According to a second aspect of the present invention, there is provided a digital modulation signal generating method.
A baseband signal generation stage for outputting the baseband signal in synchronization with a predetermined sampling clock; and
A delay processing step of giving a desired delay to the generated baseband signal and outputting it,
A digital modulation signal generating method for outputting a modulation signal modulated by the delayed baseband signal,
The delay processing step includes:
For the memory for sequentially storing the input baseband signal in synchronization with the sampling clock , and for reading in the stored order, the time difference between the write timing and the read timing of the baseband signal is controlled to a desired value , A coarse adjustment processing step for outputting a baseband signal having a desired integer multiple of a delay of the sampling clock period to output,
Multiplying a plurality of consecutively input baseband signals and a plurality of preset filter coefficients, outputting the sum, and outputting a desired delay in a unit of time shorter than the sampling clock period to the output signal And a fine adjustment processing step of selectively setting a filter coefficient necessary for providing a predetermined delay time and adding a desired delay in a unit of time shorter than the period of the sampling clock to the input baseband signal. It is characterized by.

  As described above, the digital modulation signal generating apparatus and method according to the present invention provide the coarse adjustment delay in units of the sampling clock period and the desired fine adjustment delay in units of time shorter than the period of the sampling clock using the digital filter method. A baseband signal can be generated, and the output timing of a digital modulation signal modulated by the baseband signal can be finely adjusted over a wide range.

  Therefore, timing adjustment of digital modulation signals output from a plurality of digital modulation signal generators can be easily performed, and a terminal test corresponding to the MIMO system can be performed by a plurality of general-purpose digital modulation signal generators. .

Overall configuration diagram of an embodiment of the present invention A diagram for explaining a set of filter coefficients Diagram showing delay added to baseband signal The figure which shows the structural example which selectively outputs either the original baseband signal or the delayed baseband signal

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows the configuration of a digital modulation signal generator 20 to which the present invention is applied.

  The digital modulation signal generator 20 includes a baseband signal generator 21, a delay processor 22, D / A converters 41 and 42, and a quadrature modulator 50.

  The baseband signal generator 21 outputs baseband signals I and Q used for modulation in synchronization with a sampling clock Cs having a predetermined frequency fs (= 1 / Ts).

  The delay processing unit 22 receives the baseband signals I and Q from the baseband signal generation unit 21 and outputs them with a delay designated by the user. The delay processing unit 22 includes a coarse adjustment unit 23 and a fine adjustment unit 26. Yes.

  The coarse adjustment unit 23 includes a pair of FIFO memories 24A and 24B and a memory control unit 25. The baseband signals I and Q that are input are sequentially stored in the FIFO memories 24A and 24B, respectively, and are read in the stored order. As a result, a delay (rough adjustment process) between the write timing and the read timing is given.

  Since the writing process and the reading process are performed in synchronization with the output interval (sampling clock period) of the baseband signals I and Q, the delay time due to the difference inevitably becomes an integer P times one sample time Ts. This integer P can be arbitrarily set within the range of the number of addresses of the FIFO memories 24A and 24B.

  However, as will be described later, since the fine adjustment unit 26 also includes a fixed delay that is an integer r times the one sample time Ts, the memory control unit 25 uses an integer value equal to U−r with respect to the user-specified integer value U. Is set to P, and a delay corresponding to the integer value is set between the write timing and the read timing. For this reason, the coarse adjustment unit 23 outputs baseband signals I ′ and Q ′ delayed by P · Ts with respect to the input baseband signals I and Q.

  On the other hand, the fine adjustment unit 26 performs a delay process (fine adjustment process) in units of time shorter than the sampling clock period by using a data interpolation process by a digital filter, and a pair of FIR type digital filters 27A and 27B and a coefficient memory 31. , A coefficient setting unit 32, and clipping processing units 33A and 33B.

  The FIR digital filters 27A and 27B store flip-flops 28 (1) connected in series in a plurality of R stages so as to store the baseband signals I ′ and Q ′ input at the sampling clock period and sequentially shift them to the subsequent stage. To 28 (R), multipliers 29 (1) to 29 (R) for multiplying the outputs of the respective flip-flops 28 (1) to 28 (R) by coefficients k (1) to k (R), and multipliers The adder 30 is configured to add the outputs 29 (1) to 29 (R) to obtain the sum U.

  Here, the tap number R of the digital filters 27A and 27B is an odd number, for example, 25, and the filter coefficient to be multiplied by the output of the 13th [r = (R + 1) / 2] center flip-flop 28 (13) from the input side is 1. If the other filter coefficients are 0, the input baseband signals I and Q are output after receiving a fixed delay of 13 Ts by 13 flip-flops.

  This is an example in which a filter coefficient corresponding to an impulse response waveform sinx / x that has a peak value of 1 with respect to the output of the 13th flip-flop and 0 with respect to the outputs of other flip-flops is set. Then, the impulse response waveform is shifted by the fineness of 1 (= ΔT) of an integer W (for example, W = 100) of one sample time Ts of the baseband signal, and the value taken by the shifted impulse response waveform at the sampling interval is filtered. By giving as a coefficient, it is possible to generate a signal with a delay that is an integral multiple of ΔT with respect to the input baseband signals I ′ and Q ′.

  In order to realize this, the coefficient memory 31 corresponds to an impulse response waveform that peaks at each timing when the sampling interval Ts of the baseband signals I and Q is divided into a plurality of W, as shown in FIG. W sets of filter coefficients k (0,1), k (0,2), ..., k (0, R), k (1,1), k (1,2), ..., k (1, R) , ..., k (W-1, 1), k (W-1, 2), ... k (W-1, R) are stored in advance.

  For example, assuming that R = 25 (r = 13), 25 continuous data d (1) to d (25) of the baseband signal are taken into the digital filter as shown in FIG. Think about the state. In this case, for example, the first set of filter coefficients k (0,1) to k (0,25) for setting the delay in units of ΔT to 0, and the impulse response waveform sinx as shown in FIG. The value 1 / x taken at the position x = 0 is the intermediate filter coefficient k (0,13), and the impulse response waveform sinx / x is the value 0 taken at the position x = ± 2π, ± 4π,. ) To other filter coefficients, the output value of the digital filter becomes equal to the intermediate storage data d (13), and this storage value d (13) is output. The data is updated to d (14), and the updated data d (14) is output. Hereinafter, the input data is sequentially output with a delay of r · Ts.

  In addition, for example, the second set of filter coefficients k (1,1) to k (1,25) for adding a delay of ΔT is a reference impulse response waveform sinx /, as shown in FIG. For an impulse response waveform sin (x + ΔT) / (x + ΔT) obtained by shifting x by ΔT = (2π / W) along the time axis, a value sin (ΔT) / (ΔT) taken at the position of x = 0 is an intermediate 13 The value of sin (2π + ΔT) / (2π + ΔT) taken at the position of x = 2π is taken as the 14th filter coefficient k (1,14), and taken at the position of x = −2π. The value sin (−2π + ΔT) / (− 2π + ΔT) is set as the twelfth filter coefficient k (1,12).

That is, the first to twelfth filter coefficients are as follows.
k (1,1) = sin (−24π + ΔT) / (− 24π + ΔT)
k (1,2) = sin (−22π + ΔT) / (− 22π + ΔT)
......
k (1, N) = sin [−2 (13−N) π + ΔT] / [− 2 (13−N) π + ΔT]
......
k (1,11) = sin (−4π + ΔT) / (− 4π + ΔT)
k (1,12) = sin (−2π + ΔT) / (− 2π + ΔT)

The 14th to 25th filter coefficients are as follows.
k (1,14) = sin (2π + ΔT) / (2π + ΔT)
k (1,15) = sin (4π + ΔT) / (4π + ΔT)
......
k (1, N) = sin [2 (N-13) π + ΔT] / [2 (N-13) π + ΔT]
......
k (1,24) = sin (22π + ΔT) / (22π + ΔT)
k (1,25) = sin (24π + ΔT) / (24π + ΔT)

  Similarly to the above, the second set of filter coefficients k (1,1) to k (1,25) is set in a state where 25 consecutive data d (1) to d (25) are captured. Then, the value corresponding to the timing (x = −ΔT) at which the impulse response waveform sin (x + ΔT) / (x + ΔT) peaks, that is, the value interpolated between the data d (12) and d (13) at ΔT intervals. Among them, the interpolation value h (ΔT) delayed by ΔT from the data d (13) is calculated and output.

Similarly, among the filter coefficients k (2,1) to k (2,25) of the third set of filter coefficients for imparting a delay of 2ΔT, the middle thirteenth filter coefficient k (2,13 )
k (2,13) = sin (2ΔT) / (2ΔT)
It becomes.

The first to twelfth filter coefficients are as follows.
k (2,1) = sin (−24π + 2ΔT) / (− 24π + 2ΔT)
k (2,2) = sin (−22π + 2ΔT) / (− 22π + 2ΔT)
......
k (2, N) = sin [−2 (13−N) π + 2ΔT] / [− 2 (13−N) π + 2ΔT]
......
k (2,11) = sin (−4π + 2ΔT) / (− 4π + 2ΔT)
k (2,12) = sin (−2π + 2ΔT) / (− 2π + 2ΔT)

The 14th to 25th filter coefficients are as follows.
k (2,14) = sin (2π + 2ΔT) / (2π + 2ΔT)
k (2,15) = sin (4π + 2ΔT) / (4π + 2ΔT)
......
k (2, N) = sin [2 (N-13) π + 2ΔT] / [2 (N-13) π + 2ΔT]
......
k (2,24) = sin (22π + 2ΔT) / (22π + 2ΔT)
k (2,25) = sin (24π + 2ΔT) / (24π + 2ΔT)

That is, when (R + 1) / 2 = r and the filter coefficient is expressed by the general formula k (MN),
If N = r,
k (MN) = sin (M · ΔT) / (M · ΔT)
In the range of N <r,
k (MN) = sin [−2 (r−N) π + M · ΔT] / [− 2 (r−N) π + M · ΔT]
In the range of N> r,
k (MN) = sin [2 (Nr) π + M · ΔT] / [2 (Nr) π + M · ΔT]
It becomes.

  The coefficient setting unit 32 selects a set of filter coefficients corresponding to the value M arbitrarily designated by the user from among the filter coefficients corresponding to the impulse response shifted by the fineness of 1 / W of the sampling period Ts as described above. A desired delay M in units of time (ΔT) shorter than the sampling interval Ts is obtained from the coefficient memory 31 and set in the digital filter 27 to a fixed delay r · Ts inevitably generated in the structure of the digital filter with respect to the input signal. A signal with ΔT is generated at the sampling period Ts.

  As a result, the base band signals I ′ and Q ′ input to the fine adjustment unit 26 as shown in FIG. 3A are delayed by r · Ts + M · ΔT as shown in FIG. 3B. The band signals I ″ and Q ″ can be output from the fine adjustment unit 26, and if the delay of Ts unit in the coarse adjustment unit 23 is included, U · Ts + M · ΔT of the original baseband signals I and Q A delay was given.

  In addition, the clipping processing units 33A and 33B are configured to prevent baseband signals Iout and Qout in which the addition result is limited to an upper limit value in order to prevent the addition result obtained by the digital filters 27A and 27B from being bit-overflowed and being inverted. Is output.

  In this way, the baseband signals Iout and Qout that have been delayed by U · Ts + M · ΔT with respect to the user-specified values U and M are converted into analog signals by the D / A converters 41 and 42 and are orthogonally modulated. The high-frequency signal S that is input to the device 50 and digitally modulated with the phase and amplitude determined by the baseband signals Iout and Qout is output.

  The modulation signal component of the signal S is subjected to an arbitrary delay indicated by U · Ts + M · ΔT with respect to the designated values U and M by the delay processing unit 22, and ΔT is the period of the sampling clock of the baseband signal. The interval can be set sufficiently fine with respect to Ts.

  Therefore, when a signal for a MIMO terminal test is generated by combining with an output signal of another digital modulation signal generator receiving a common sampling clock, the delay time of the digital modulation signal generator 20 of the present embodiment is reduced. By finely adjusting the timing, it is possible to accurately match the timing with the output signal of another signal generator.

  In the above-described embodiment, the delay processing in units of the sampling cycle by the fine adjustment unit 26 is performed after the delay processing in units of the sampling cycle by the coarse adjustment unit 23. However, the unit of time is shorter than the sampling cycle by the fine adjustment unit 26. After this delay processing, the coarse adjustment unit 23 may perform delay processing in units of sampling periods.

  Further, in the above embodiment, the delay processing in units of time shorter than the sampling period in the fine adjustment unit 26 is performed at intervals shifted by ΔT intervals up to the maximum Ts with respect to the intermediate stored values of the digital filters 27A and 27B. However, it is also possible to carry out the intermediate storage value at intervals shifted by ΔT intervals up to ± Ts / 2 in both directions before and after.

Also in this case, if (R + 1) / 2 = r and the filter coefficient is represented by the general formula k (MN), the M of the specified value (integer) of fine adjustment is in the range of − (Ts / 2W) to (Ts / 2W). And as before,
When N = r
k (MN) = sin (M · ΔT) / (M · ΔT)
In the range of N <r,
k (MN) = sin [−2 (r−N) π + M · ΔT] / [− 2 (r−N) π + M · ΔT]
In the range of N> r,
k (MN) = sin [2 (Nr) π + M · ΔT] / [2 (Nr) π + M · ΔT]
It becomes.

  In this embodiment, the baseband signals I and Q are delayed by the delay processing unit 22 and input to the quadrature modulator 50. However, as shown in FIG. The baseband signals Iout and Qout output from the unit 22 may be supplied to the data selection unit 51 and either one of them may be selectively output.

  DESCRIPTION OF SYMBOLS 20 ... Digital modulation signal generator, 21 ... Baseband signal generation part, 22 ... Delay processing part, 23 ... Coarse adjustment part, 24A, 24B ... FIFO memory, 25 ... Memory control part, 26 ... Fine adjustment unit, 27A, 27B ... digital filter, 31 ... coefficient memory, 32 ... coefficient setting unit, 33A, 33B ... clipping processing unit, 41, 42 ... D / A converter, 50 ... quadrature modulator 51 …… Data selection part

Claims (2)

A baseband signal generator (21) for outputting a baseband signal in synchronization with a predetermined sampling clock;
A delay processing unit (22) for giving a desired delay to the baseband signal output from the baseband signal generating unit and outputting the delayed signal,
A digital modulation signal generator for outputting a modulation signal modulated by a baseband signal output from the delay processing unit,
The delay processing unit
Sequentially storing the baseband signal input in synchronization with the sampling clock, and a memory for reading out the stored order (24A, 24B), a time difference between the write timing and read timing of the baseband signal against in the memory A coarse control unit (23), which comprises a memory control unit (25) for controlling to a desired value, and gives a delay of a desired integer multiple of the period of the sampling clock to the input baseband signal, and outputs it.
A digital filter (27A, 27B) that multiplies a plurality of consecutively input baseband signals and a plurality of preset filter coefficients and outputs the sum, and a signal output from the digital filter includes A coefficient memory (31) that stores in advance a plurality of sets of filter coefficients necessary for providing a desired delay in units of time shorter than the period of the sampling clock, and a time shorter than the period of the sampling clock from the coefficient memory And a coefficient setting unit (32) for reading out a filter coefficient for setting a unit delay to a desired value and setting the filter coefficient in the digital filter. The input baseband signal includes a desired unit in a time unit shorter than the period of the sampling clock. And a digital modulation signal generator comprising a fine adjustment section (26) for providing a delay. . A baseband signal generation stage for outputting the baseband signal in synchronization with a predetermined sampling clock; and
A delay processing step of giving a desired delay to the generated baseband signal and outputting it,
A digital modulation signal generating method for outputting a modulation signal modulated by the delayed baseband signal,
The delay processing step includes:
For the memory for sequentially storing the input baseband signal in synchronization with the sampling clock , and for reading in the stored order, the time difference between the write timing and the read timing of the baseband signal is controlled to a desired value , A coarse adjustment processing step for outputting a baseband signal having a desired integer multiple of a delay of the sampling clock period to output,
Multiplying a plurality of consecutively input baseband signals and a plurality of preset filter coefficients, outputting the sum, and outputting a desired delay in a unit of time shorter than the sampling clock period to the output signal And a fine adjustment processing step of selectively setting a filter coefficient necessary for providing a predetermined delay time and adding a desired delay in a unit of time shorter than the period of the sampling clock to the input baseband signal. A method for generating a digital modulation signal.

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