JP2000244367A - Spread spectrum receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a spread spectrum receiver provided with a matched filter of a small size and low power consumption and a circulation integrator. SOLUTION: The spread spectrum receiver taking the timing synchronization of a received spread signal by using the matched filter is provided with the matched filter 1 without over-sampling for executing the correlation arithmetic of the received spread signal and a reference code and an interpolation device 2 for interpolating the output of the matched filter with N-fold (N is an integer >=1) over sampling timing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum communication type receiving apparatus, and more particularly to a spread spectrum receiving apparatus which synchronizes a received signal using a matched filter.

[0002]

2. Description of the Related Art A conventional spread spectrum receiver will be described below. In the spread spectrum communication system, the transmitting side performs spread modulation at a chip rate higher than the information rate using a spreading code, for example, and transmits the spread signal to the receiving side. On the other hand, the receiving side generates a reference code that is a replica of the spreading code used on the transmitting side,
Despread the received spread signal.

[0003] However, since the reference code used for such despreading needs to be used at the same timing as the spread code used on the transmission side, in order to despread the received spread signal, the spread code must be used. It is necessary to accurately detect the timing to be used. For example, it is necessary to detect the timing with an accuracy of four times or more the chip rate. For this reason, the timing is detected by oversampling four times the chip rate. Further, in an environment where the propagation environment changes at a high speed, such as mobile communication, it is necessary to detect the timing of using a spreading code at a high speed and update the demodulation timing. Therefore, as a method of updating the demodulation timing, for example, a method using a matched filter has been proposed.

A matched filter usually includes an input register for storing a received spread signal, a reference code register for storing the reference code, and a plurality of samples for multiplying each tap output of the input register by the reference code on a sample basis. It comprises a multiplier and an adder for adding all the outputs of the multipliers in sample units.

FIG. 26 shows an output example of the matched filter configured as described above. The input signal stored in the input register of the matched filter is 64 samples, and the correlation value of the received spread signal is repeatedly calculated in the period of 64 samples. Then, as shown in FIG. 26, the timing at which the correlation of the matched filter becomes particularly large is the reception timing of the spread signal.

FIG. 27 is a diagram for explaining the operation of cyclic integration. For example, the output of the matched filter is set to 64 using a cyclic integration method as shown in the figure.
By adding at the sample period (indicating the sample timing), ie, by adding (A) + (B) +
By calculating (C) + (D), the SN ratio (Signal
to Noise ratio) to detect timing.

[0007] Japanese Patent Application Laid-Open No. Hei 10-285079 discloses a document relating to the matched filter in the spread spectrum communication system and the method using the cyclic integration. FIG. 28 shows, for example, Japanese Patent Application Laid-Open No. 10-285079.
29 shows a conventional matched filter and a conventional cyclic integrator shown in FIG. 29. FIG. 29 shows a configuration of the matched filter shown in FIG. 28. FIG. 30 shows a configuration of the cyclic integrator shown in FIG. 2 shows the configuration.

In FIG. 28, reference numeral 500 denotes a matched filter, and 600 denotes a cyclic integrator. In the matched filter 500, reference numeral 501 denotes a register.
02 is a write control device, and 503a, 503b,
503c are selectors, 504a, 504b,.
504c is a multiplier, 505 is a reference code register, and 506 is an adder. Also, the cyclic integrator 600
In the above, 601 is an adder, 602 is a memory, and 603 is an address generator.

Both the matched filter 500 and the cyclic integrator 600 configured as described above operate with four times oversampling. For example, the matched filter 500 includes 64 taps, and 64 multipliers (14a, 14,... 14c) corresponding to each tap multiply the output of each tap by a reference code for each sample. Thereafter, in the matched filter 500, the adder 5
06 adds all the multiplication results and outputs the result. On the other hand, in the cyclic integrator 600, the adder 601 outputs the matched filter output and the memory 502 corresponding to the address generated by the address generator 603 at a predetermined timing.
(See FIG. 27) to output a correlation value.

Note that CDMA (Code Division Multiple)
In the Access method, the receiving side does not know the timing at the start of communication. Therefore, for example, in the conventional spread spectrum receiving apparatus, in order to obtain a correlation output, the above operation is performed using the received spread signal and the reference code shown in FIG. Otherwise, a large correlation value cannot be obtained.

As described above, the conventional spread spectrum receiving apparatus searches the reception timing of the received spread signal by synchronizing with the phase of the reference code having the maximum value among the correlation values obtained by the above method. ing.

[0012]

SUMMARY OF THE INVENTION However,
In the conventional spread spectrum receiving apparatus, the matched filter and the cyclic integrator have a problem that the circuit scale and the power consumption are very large because they operate with 4 times oversampling.

More specifically, in the conventional matched filter 500 shown in FIG. 29, the required number of registers 501 for storing received data is four times 64 taps, that is, 256, and the circuit scale is large. growing. Furthermore, since the register 501 performs over-sampling by four times, each selector needs an operation of selecting the output of each tap from the register 501 at high speed.

The selectors 503a to 503c
Also, since the required number is 64, the circuit scale becomes large, and furthermore, since the operation is 4 times oversampling, the power consumption becomes large. Similarly, the required number of multipliers 504a to 504c is 64, so that the circuit scale becomes large.
Power consumption increases because of double sampling. The adder 506 also has a very large circuit scale because it has 64 multipliers, and also has a very large power consumption because its operation is also four times oversampled and high speed.

The cyclic integrator 600 has 64
A memory 602 of 256 words, which is four times the tap, is required, and accordingly the circuit scale becomes large.
Since the operation speed is 4 times oversampling similarly to the above, power consumption is also increased.

The present invention has been made in view of the above, and an object of the present invention is to provide a spread spectrum receiving apparatus including a small-sized low-power-consumption matched filter and a cyclic integrator.

[0017]

Means for Solving the Problems The above-mentioned problems are solved,
In order to achieve the object, in a spread spectrum receiving apparatus according to the present invention, a matched filter without oversampling for performing a correlation operation between a received spread signal and a reference code (corresponding to a matched filter 1 in an embodiment described later). And an interpolating means (corresponding to the interpolating device 2) for interpolating the matched filter output at N times (N is 1 or more) oversampling timing to synchronize the timing of the received spread signal.

According to the present invention, the matched filter does not require a selector associated with oversampling, so that the circuit scale can be significantly reduced, and the number of registers for storing received signals is also reduced. Therefore, the circuit scale can be significantly reduced here as well. Further, according to the present invention, since there is no oversampling, the operation speed of the matched filter is reduced.
Accordingly, power consumption can be reduced. Although the time resolution of the output of the matched filter is reduced for the same reason, according to the present invention, the time resolution can be improved by the interpolation means, and the same performance as that of the related art can be realized.

In the spread spectrum receiver according to the next invention, a cyclic integration means for coherently integrating the output of the matched filter coherently without oversampling is provided between the matched filter and the interpolation means. And the interpolation means interpolates the output of the cyclic integration means at N times oversampling timing.

According to the present invention, the operation speed of the cyclic integration means can be made slower than that of the prior art, and the operation can be performed without oversampling.
The memory capacity can be reduced to １ ／, for example, from 256 words to 64 words. This allows
The circuit scale can be significantly reduced compared to the past,
Power consumption can also be significantly reduced.

In the spread spectrum receiving apparatus according to the next invention, a matched filter without oversampling (corresponding to a matched filter 1 in an embodiment described later) for performing a correlation operation between a received spread signal and a reference code, and A first cyclic integration means (corresponding to a first cyclic integrator 3a) for cyclically integrating the matched filter output coherently without oversampling;
First interpolating means (corresponding to the first interpolating device 2a) for interpolating at double oversampling timing, and second cyclic integrating means (which converts the output of the first interpolating means into electric power and then performs cyclic integration. A second cyclic integrator 3b) and a second interpolating means (corresponding to the second interpolating device 2b) for interpolating the output of the second cyclic integrator at M times (M is 2 or more) oversampling timing. ) And a path detecting means (path detector 4) for detecting a signal timing from the output of the second interpolation means.
), And the timing of the received spread signal is synchronized.

According to the present invention, in the matched filter, a selector accompanying oversampling is not required, so that the circuit scale can be significantly reduced, and the number of registers for storing received signals is also reduced. Therefore, the circuit scale can be significantly reduced here as well. Further, since there is no oversampling, the operation speed of the matched filter is reduced, and accordingly, power consumption can be reduced. Although the time resolution of the output of the matched filter is reduced for the same reason, according to the present invention, the time resolution can be improved by the first and second interpolation means, and the performance equivalent to the conventional one can be obtained. Can be realized. Further, since the second cyclic integration means operates with double oversampling, the memory capacity can be reduced by half and the power consumption can be reduced by half as compared with the conventional technique operating with quadruple oversampling. Can be.

In the spread spectrum receiving apparatus according to the next invention, the output of the second cyclic integration means is replaced by the second interpolation means and the path detection means connected to the second cyclic integration means. A second path detecting means (corresponding to a path detector 4 in an embodiment to be described later) for detecting the timing of the signal from L, and L signals before and after the timing detected by the second path detecting means (L is 1 or more) ) Of the second cyclic integration means (M is 4 or more) at an oversampling timing of M times (M is 4 or more), and a third interpolation means (corresponding to the third interpolation device 2c). I do.

According to the present invention, since the interpolation is performed after the timing of each path is detected, the operation speed of the path detecting means can be further reduced, and further, the vicinity of the path detected by the third interpolating means can be reduced. , The amount of calculation can be reduced.

In the spread spectrum receiving apparatus according to the next invention, the output of the second cyclic integration means is interpolated by the second interpolation means at four times oversampling timing. Interpolating L (L is an integer of 1 or more) outputs of the second interpolating means before and after the detected timing at M times (M is 4 or more) oversampling timing (an embodiment to be described later) (Corresponding to the third interpolation device 2c).

According to the present invention, when the accuracy of the detection timing is to be equal to or higher than the eight-times oversampling accuracy, the accuracy is changed to the four times oversampling accuracy by the second interpolation means.
The timing is detected by the path detecting means, and the signal near the detected timing is further changed to eight times oversampling accuracy by the third interpolation means. This allows
Further, the accuracy of the detection timing can be improved.

In the spread spectrum receiving apparatus according to the next invention, the sampling means capable of sampling the received spread signal by N times (N is an integer of 1 or more) oversamples (the sampler 5 of the embodiment to be described later). Equivalent), sample timing control means (corresponding to the sample timing control device 6) for switching the sample timings of the N sample means, and a matched filter (matched filter) without oversampling for performing a correlation operation between the output of the sample means and a reference code. A cyclic integration means (corresponding to a cyclic integrator 3) for coherently and cyclically integrating the matched filter output without oversampling at every N sample timings, and N cyclic integration means. Smoothing means (smoothing device 7) for smoothing the output
And path detecting means (corresponding to the path detector 4) for detecting the timing of the signal from the output of the smoothing means, and synchronizes the timing of the received spread signal.

According to the present invention, the timing of the received signal input to the matched filter is switched by the sample timing control means, for example, in units of 1/2 chip, and cyclic integration is performed at each timing switched by the cyclic integration means. The noise is cut by the smoothing means. As a result, the problem of aliasing is eliminated, and even if the matched filter is a 1-times oversample, it can be accurately converted to a 2-times oversample. Further, the matched filter does not require a selector associated with oversampling, so that the circuit size can be significantly reduced. Further, the number of registers for storing received signals is also reduced, so that the matched filter is also significantly reduced. The circuit scale can be reduced. Further, since the matched filter has no oversampling, the operation speed of the matched filter is reduced, and accordingly, power consumption can be reduced.

In the spread spectrum receiver according to the next invention, the output of the matched filter is coherently integrated without oversampling by replacing the cyclic integration means, the smoothing means, and the path detection means. A first cyclic integration means (corresponding to a first cyclic integrator 3a of an embodiment described later), and a first interpolation means for interpolating the output of the first cyclic integration means at double oversampling timing ( A first interpolator 2a) and a second interpolator that converts the output of the first interpolator into electric power and performs cyclic integration.
And second interpolation means (corresponding to the second cyclic integrator 3b) for interpolating the output of the second cyclic integration means at M times (M is an integer of 2 or more) oversample timing. 2) and path detecting means (corresponding to the path detector 4) for detecting the timing of the signal from the output of the second interpolating means.

According to the present invention, the memory capacity of the first cyclic integration means can be significantly reduced, and the operation speed of the first interpolation means can be made slower than that of the smoothing means. Since the number can be greatly reduced, the circuit scale and the power consumption can be further significantly reduced.

In the spread spectrum receiving apparatus according to the next invention, the output of the second cyclic integration means is replaced with the second interpolation means and path detection means connected to the second cyclic integration means. A second path detecting means (corresponding to a path detector 4 in an embodiment to be described later) for detecting the timing of the signal from L, and L signals before and after the timing detected by the second path detecting means (L is 1 or more) And third interpolation means (corresponding to the third interpolation device 2c) for interpolating the output of the second cyclic integration means of the second cyclic integration means at M times (M is an integer of 4 or more) oversampling timing. Features.

According to the present invention, the path detecting means is performed with double oversampling accuracy, and after the path is detected, the data before and after the timing is interpolated using the third interpolating means. Thus, the operation speed of the path detection unit can be reduced, and the operation is performed only in the vicinity of the path detected by the third interpolation unit. Therefore, the amount of calculation can be further reduced.

In the spread spectrum receiving apparatus according to the next invention, the output of the second cyclic integration means is interpolated by the second interpolation means at four times oversampling timing. Third interpolating means (M to be described later) for interpolating L (L is an integer of 1 or more) outputs of the second interpolating means before and after the detected timing at M times (M is an integer of 4 or more) oversampling timing (Corresponding to the third interpolating device 2c of the form (1)).

According to the present invention, when the accuracy of the detection timing is to be equal to or more than eight times the sampling accuracy, the timing is detected by the path detecting means after the second interpolating means attains the quadruple oversampling accuracy, and the timing is detected. Based on the neighboring data, the third interpolating means makes the oversampling accuracy eight times or more. Thereby, the detection probability can be further improved.

In the spread spectrum receiving apparatus according to the next invention, the first sampling means (the later described embodiment of the present invention) capable of sampling the received spread signal by N times (N is an integer of 1 or more) oversamples. One sampler 5a) and a second sampler (second sampler 5b) that samples the output of the first sampler once every N times.
), Sample timing control means (corresponding to the sample timing control device 6) for switching the N sample timings of the second sample means, and an overrun for performing a correlation operation between the output of the second sample means and a reference code. A matched filter without samples (corresponding to matched filter 1), first cyclic integration means (corresponding to first cyclic integrator 3a) for coherently and cyclically integrating the matched filter output without oversampling, and 1
A first interpolating means (corresponding to the first interpolating device 2a) for interpolating the output of the cyclic integration means at double oversampling timing, and a second integration means for converting the output of the first interpolating means into electric power and performing cyclic integration. 2 cyclic integration means (second cyclic integrator 3b)
) And the output of the second cyclic integration means is multiplied by M (M
The second interpolation means (corresponding to the second interpolation device 2b) for interpolating at the oversampling timing, and the path detection means (the path detector 4 for detecting the signal timing from the output of the second interpolation means). And a fourth interpolating means (a fourth interpolating device 2d) for interpolating the first sampling means at K times (an integer satisfying K> N) oversampling timing.
And a signal demodulating means (corresponding to the signal demodulator 8) for demodulating the received signal at the timing detected by the path detector 4, and synchronizes the timing of the received spread signal. I do.

According to the present invention, the first sampling means can perform the double oversampling operation, and the power consumption can be reduced by half compared to the case where the first sampling means operates by the quadruple oversampling. Further, since the twice-oversampled signal is converted to four-times oversampled by the fourth interpolation means, the same performance as that of the conventional signal demodulation means can be obtained.

[0037]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a spread spectrum receiving apparatus according to the present invention. The present invention is not limited by the embodiment.

Embodiment 1 FIG. 1 is a diagram illustrating a configuration of a spread spectrum receiving apparatus according to a first embodiment of the present invention. A spread spectrum receiving apparatus according to the present invention interpolates a matched filter 1 without oversampling for performing a correlation operation between a received spread signal and a reference code and an output of the matched filter 1 at N times (N is 1 or more) oversampling timing. A matched filter 1 comprising an interpolation device 2
Operates at the chip rate, i.e., 1x oversampling.

FIG. 2 is a diagram showing a configuration example of the matched filter 1 shown in FIG. In FIG. 2, reference numeral 11 denotes an input register for storing the received spread signal in a register 111 (corresponding to R _{0 to} R ₆₃ shown) at the control timing of the write control device 112, and 12 denotes a reference code register for storing a reference code. , 14 is a multiplier for multiplying the output of each tap of the input register 11 by the reference code, and 13 is an adder for adding the output of each multiplier. Here, for convenience of explanation, the number of taps is 64, but the present invention does not depend on the number of taps.

In this embodiment, since oversampling is not performed, the register 111 has the same number as the number of taps.
That is, only 64 pieces are required. For the same reason, a selector for selecting the output of the register 111 (FIG. 29)
) Is unnecessary. As a result,
The circuit scale and current consumption can be greatly reduced. Also, since oversampling is not performed, the multiplier 14 and the adder 13
Becomes the chip rate, and the current consumption can be further reduced.

Here, the received spread signal input to the matched filter 1 and the output of the matched filter will be specifically described. FIG. 3 is a diagram showing the spectrum of the received spread signal. In FIG. 3, R indicates the chip rate, α indicates the roll-off rate, and the bandwidth is represented by R × (1 + α). In the matched filter 1, the multiplier 14 performs convolution integration of the reference code and the received spread signal. If the reference code is an impulse train in chip units and is white on the frequency axis,
The spectrum of the matched filter output can be considered equivalent to the spectrum of the received spread signal.

FIG. 4 is a diagram showing a spectrum of a matched filter output operating with twice oversampling. Since the operation is performed with twice oversampling, the frequency is repeated every 2R. FIG. 5 is a diagram illustrating a spectrum of a matched filter output that operates without oversampling (one-time oversampling). Since sampling is performed at the chip rate R, the frequency is repeated for each R. Also, the signal in the portion spread by the roll-off is aliasing.

FIG. 6 is a diagram showing a configuration example of the interpolation device 2 shown in FIG. In FIG. 6, reference numerals 21a to 21e denote delayers for delaying an input signal for each sample.
2c is an adder for adding the outputs of the corresponding delay devices,
23a to 13c are coefficient units for multiplying the output of each adder by a coefficient, 24 is an adder for adding the output of each coefficient unit, and 25 is a selector for alternately selecting a delayed sample value and an interpolation value. .

For example, when a signal without oversampling (see FIG. 5) is converted into a double oversampling, the signal represented by the spectrum of FIG. 5 is passed through, for example, a filter shown in FIG. A signal equivalent to the signal shown in FIG. This filter is a low-pass filter with twice oversampling, and can be easily realized with a transversal filter configuration. Note that the aliasing portion is slightly different from the ideal case of double oversampling, but there is no particular problem as long as the signal energy in this portion is sufficiently small and negligible.
In addition, when there is a margin in performance, a one-time oversampling can be used to reduce power consumption and circuit scale.

As described above, in the interpolation device 2, even with a matched filter without oversampling, an output equivalent to twice oversampling can be obtained. Further, by repeating this method many times, Performance equivalent to higher oversampling can also be obtained.

Hereinafter, a description will be given of a case where the interpolating device 2 of the present embodiment interpolates the value between samples of the input signal to double the time resolution, for example. FIG. 8 is a diagram showing a specific operation example of the interpolation device 2 shown in FIG. For example, if the input signal of the interpolation device 2 is I
(0), I (1), I (2)...
Between (k) and I (k + 1), the interpolation point (I (k + 3) +
I (k-2)) W2 + (I (k + 2) + I (k-1))
W1 + (I (k + 1) + Ik) W0 is inserted (k is an arbitrary integer). Note that the output of the delay unit is cleared at the first interpolation point and the second interpolation point.
The coefficients used in the interpolation device 2 are, for example, W0 = 0.625, W1 = −0.1875, W2 =
0.09375 shall be used.

FIG. 9 is a diagram for specifically explaining the operation of the interpolation device 2. In the interpolation device 2, FIG.
As shown in (2), the output of the matched filter 1 is used as a sample point, the interpolation point is calculated by the interpolation device 2, and the interpolation point and the sample point are alternately output by the selector 25. For example, interpolation points F are sample points A, C, E,
From G, I and K, (A + K) W2 + (C + I) W1 + (E
+ G) W0. Also, the interpolation point H
Is (C + M) from the sample points C, E, G, I, K, M
W2 + (E + K) W1 + (G + I) W0.

As described above, in the present embodiment, the selector associated with oversampling is not required as compared with the conventional spread spectrum receiving apparatus shown in FIG. 28, so that the circuit scale is greatly reduced. In addition, since the number of registers 111 in the input register 11 is also reduced to 、, the circuit scale is greatly reduced here. Further, in the present embodiment, since the operation speed is reduced to ４, the power consumption is accordingly reduced to １ ／ or less. Further, for the same reason, the time resolution of the matched filter output is reduced to 1/4 of the conventional one, but in this embodiment, the same performance as the conventional one is realized by improving the time resolution by the interpolation device 2. are doing.

Therefore, according to the present embodiment, the provision of the interpolation device 2 makes it possible to greatly reduce the circuit scale as compared with the conventional matched filter, and furthermore,
Power consumption can be reduced to 1/4 or less.

Embodiment 2 FIG. 10 is a diagram illustrating a configuration of a spread spectrum receiving apparatus according to a second embodiment of the present invention. A spread spectrum receiving apparatus according to the present invention includes a matched filter 1 without oversampling for performing a correlation operation between a received spread signal and a reference code, a cyclic integrator 3 for cyclically integrating the output of the matched filter 1 coherently without oversampling, An interpolator 2 interpolates the output of the cyclic integrator 3 at N times (N is 1 or more) oversampling timing. The matched filter 1 has a chip rate of
That is, the operation is performed with 1-time oversampling. Therefore, the difference from the first embodiment is that the matched filter 1
The point is that the cyclic integrator 3 is disposed between the interpolation integrator 2 and the interpolator 2. In the present embodiment, the same components as those in the first embodiment described above are denoted by the same reference numerals, and description thereof is omitted.

FIG. 11 is a diagram showing a configuration example of the cyclic integrator 3 shown in FIG. In FIG. 11, reference numeral 31 denotes an adder for cyclically adding the output of the matched filter and the output of a memory 32 described later; 32, a memory of 64 words equal to the number of taps of the matched filter 1;
An address generator for generating an address of
The operating speed is the chip rate. Since the cyclic integrator 3 performs a linear operation, the same result can be obtained when interpolation is performed after performing cyclic integration and when interpolation is performed before cyclic integration. Therefore, by performing the interpolation after the cyclic integration, the operation speed and the memory capacity of the cyclic integrator 3 can be reduced.

Therefore, in the present embodiment, the same effects as those of the first embodiment described above can be obtained, that is, the matched filter 1 and the interpolator 2 have a larger circuit size than the conventional spread spectrum receiver. And power consumption (（or less) can be greatly reduced, and the operation speed of the cyclic integrator 3 can be reduced to 1/4 of that of the conventional cyclic integrator 600 shown in FIG. The memory capacity can be reduced from 256 words to 64 words to 1/4. As a result, according to the present embodiment, the circuit scale can be significantly reduced as compared with the related art, and the power consumption can be reduced to １ ／ or less.

Embodiment 3 FIG. 12 is a diagram illustrating a configuration of a spread spectrum receiving apparatus according to a third embodiment of the present invention. A spread spectrum receiving apparatus according to the present invention includes a matched filter 1 without oversampling for performing a correlation operation between a received spread signal and a reference code, and a first cyclic integrator for cyclically integrating the output of the matched filter 1 coherently without oversampling. 3a, a first interpolator 2a for interpolating the output of the first cyclic integrator 3a at double oversampling timing, and a second cyclic integrator for converting the output of the first interpolator 2a into electric power and performing cyclic integration 3b, a second interpolator 2b for interpolating the output of the second cyclic integrator 3b at M-times (M is 2 or more) oversampling timing, and a second interpolator 2b
path detector 4 for detecting signal timing from output b
And the matched filter 1 operates at the chip rate, that is, at 1 × oversampling.

Since the matched filter 1 and the first cyclic integrator 3a have the same configurations as those of the first and second embodiments described above, the same reference numerals (the reference numeral 3 denotes 3a)
) And the description is omitted. The first interpolator 2a and the second interpolator 2b have the same configuration as the interpolator 2 of the first and second embodiments described above, but the number of stages of the delay units 21a to 21e and the coefficient unit 23a ~ 23
The coefficient of c may be set to an optimal number of stages and a value in consideration of the balance of the performance and the circuit scale of each interpolation device.

FIG. 13 is a diagram showing a configuration example of the second cyclic integrator 3b shown in FIG. In FIG. 13, reference numeral 34 denotes a power value calculator that converts the output of the first interpolation device 2a into power, and 35 denotes an adder that cyclically adds the output of the power value calculator 34 and the output of a memory 36 described later. 36 is 12
An eight-word memory, an address generator 37 for generating an address of the memory 35, and a twice-oversampling operation.

In the present embodiment configured as described above, the first cyclic integrator 3a coherently and cyclically integrates the output of the matched filter 1 in the first and second embodiments.
However, when the phase of the signal is rotated due to carrier frequency deviation or fading fluctuation, the effect of cyclic integration is lost. That is, for example, when the phase is rotated by 180 degrees, the signal is canceled and disappears. Therefore, in order to perform long-term averaging and obtain a highly accurate correlation value, it is only necessary to convert a signal into electric power and perform cyclic integration.

Then, in the second cyclic integrator 3b, the input signal is converted into power by the power value calculator 34, and thereafter,
Performs cyclic integration. However, when converted into power, the signal bandwidth is doubled, so a double oversampling operation is required. Therefore, in order to operate the second cyclic integrator 3b with double oversampling, a signal without oversampling is interpolated by the first interpolator 2a to convert the signal to double oversampling, and then convert the signal to power. Will do.
Since the second cyclic integrator 3b operates with double oversampling, the memory 36 stores the data of the first interpolator 2a.
This is 128 words, which is twice as long.

The path detector 4 is a device for detecting a timing at which the signal becomes maximum or a plurality of timings at which the signal exceeds the threshold. In the present embodiment, the detection timing is set to 4 in order to improve the time resolution (to obtain the same performance as the related art).
Since double oversampling accuracy is required, the signal of the double oversampling in the second cyclic integrator 3b is converted into a quadruple oversampling by the second interpolator 2b before performing path detection.

Therefore, in the present embodiment, the same effects as those in the first and second embodiments described above can be obtained, that is, the same effects can be obtained in matched filter 1 and first cyclic integrator 3a. In addition, since the second cyclic integrator 3b operates with twice oversampling, the memory capacity can be halved compared to the prior art operating with four times oversampling, and the power consumption is accordingly increased. Can be halved.

Embodiment 4 FIG. 14 is a diagram illustrating a configuration of a spread spectrum receiving apparatus according to a fourth embodiment of the present invention. A spread spectrum receiving apparatus according to the present invention includes a matched filter 1 without oversampling for performing a correlation operation between a received spread signal and a reference code, and a first cyclic integrator for cyclically integrating the output of the matched filter 1 coherently without oversampling. 3a, a first interpolator 2a for interpolating the output of the first cyclic integrator 3a at double oversampling timing, and a second cyclic integrator for converting the output of the first interpolator 2a into electric power and performing cyclic integration 3b and a path detector 4 for detecting the timing of the signal from the output of the second cyclic integrator 3b
And outputs L (L is an integer of 1 or more) second cyclic integrators 3b before and after the timing detected by the path detector 4.
And a third interpolator 2c for interpolating at double (M is 4 or more) oversampling timing, and the matched filter 1 operates at the chip rate, that is, at 1x oversampling.

The matched filter 1, the first cyclic integrator 3a, the first interpolator 2a, and the second cyclic integrator 3b have the same configuration as that of the third embodiment described above. Therefore, the same reference numerals are given and the description is omitted. The path detector 4 has the same configuration as that of the third embodiment described above, but operates differently. The third interpolator 2c has the same configuration as the first interpolator 2a, but includes the number of stages of the delay units 21a to 21e and the coefficient units 23a to 23e.
The coefficient of 23c may be set to the optimum number of stages and values in consideration of the performance of each interpolation device, the balance of the circuit scale, and the like.

Therefore, the present embodiment is different from the third embodiment in that the path detector 4 is operated with twice the oversampling accuracy, and the data before and after the detected timing (corresponding to the multipath) is obtained. 3 in that interpolation is performed using the interpolation device 2c. Thus, in the present embodiment, the interpolation is performed after the timing of each path is detected, so that the operation speed of the path detector 4 can be made lower than that of the third embodiment. Since the operation is performed only near the detected path, the amount of calculation can be reduced.

Embodiment 5 FIG. FIG. 15 is a diagram illustrating a configuration of a spread spectrum receiving apparatus according to a fifth embodiment of the present invention. A spread spectrum receiving apparatus according to the present invention includes a matched filter 1 without oversampling for performing a correlation operation between a received spread signal and a reference code, and a first cyclic integrator for cyclically integrating the output of the matched filter 1 coherently without oversampling. 3a, a first interpolator 2a for interpolating the output of the first cyclic integrator 3a at double oversampling timing, and a second cyclic integrator for converting the output of the first interpolator 2a into electric power and performing cyclic integration 3b, a second interpolator 2b for interpolating the output of the second cyclic integrator 3b at four times oversampling timing, a path detector 4 for detecting a signal timing from the output of the second interpolator 2b, Vessel 4
A third interpolator 2c for interpolating L (L is an integer of 1 or more) outputs of the second interpolator 2b before and after the timing detected at the M times (M is 4 or more) oversampling timing
And the matched filter 1 operates at the chip rate, that is, at 1 × oversampling.

The matched filter 1, the first cyclic integrator 3a, the first interpolator 2a, the second cyclic integrator 3b, the second interpolator 2b, and the path detector 4 Since the configuration is similar to that of the third embodiment described above, the same reference numerals are given and the description is omitted. The third interpolator 2c has the same configuration as that of the first interpolator 2a, but includes the number of stages of the delay units 21a to 21e and the coefficient units 23a to 2e.
The coefficient of 3c may be set to an optimal number of stages and a value in consideration of the performance of each interpolation device, the balance of the circuit scale, and the like.

Therefore, the present embodiment is different from the third embodiment in that the path detector 4 is operated with 4 times oversampling accuracy, and the data before and after the detected timing (corresponding to the multipath) is obtained. 3 is that interpolation can be further performed using the third interpolation device 2c.

For example, in the fourth embodiment, the timing of the path is detected from the signal of twice oversampling. However, in the path detection, since the maximum value is detected and the threshold is determined, the nonlinearity is strong. Further, in order to perform detection with a high detection probability, an operation of at least about 4 times oversampling is required.

Therefore, in the present embodiment, when the accuracy of the detection timing is set to be equal to or more than eight times the oversampling accuracy, the timing is not detected by the configuration of the fourth embodiment, but the timing is detected by the second interpolator 2b. After changing to the double oversampling accuracy, the timing is detected by the path detector 4, and the signal near the detected timing is further changed to the eight times oversampling accuracy by the third interpolation device 2c. Thereby, the accuracy of the detection timing can be further improved compared to the fourth embodiment.

Embodiment 6 FIG. FIG. 16 is a diagram showing a configuration of the spread spectrum receiving apparatus according to the sixth embodiment of the present invention. A spread spectrum receiving apparatus according to the present invention includes a sample apparatus 5 capable of sampling a received spread signal by N times (N is an integer of 1 or more) oversamples, and sample timing control for switching N sample timings of the sample apparatuses 5 Apparatus 6, matched filter 1 without oversampling for performing correlation operation between output of sampler 5 and reference code, and cyclic integrator for coherently integrating the output of matched filter 1 coherently without oversampling at every N sample timings 3, a smoothing device 7 for smoothing the N outputs of the cyclic integrator 3, and a path detector 4 for detecting signal timing from the smoothing device 7 output.
And the matched filter 1 operates at the chip rate, that is, at 1 × oversampling.

Since the matched filter 1, the cyclic integrator 3, the first interpolator 2a, and the path detector 4 have the same configuration as those of the first to fifth embodiments described above, they are the same. The description is omitted by attaching reference numerals. The matched filter 1 operates in the same manner as the other embodiments except that the sample timing changes.

In the spread spectrum receiving apparatus configured as described above, for example, as shown in FIG. 17, the sample timing is shifted by チ ッ プ chip, and the cyclic integrator 3 inserts the sample timing which is alternately shifted. The integration is performed, noise outside the signal band is cut by the smoothing device 7, and the timing of the path is detected by the path detector 4. At this time, control for changing the sample timing is performed by the sample timing control device 6, and the sample processing is performed by the sample device 5. Further, in this embodiment, since the cyclic integrator 3 operates at the chip rate and performs cyclic addition for each sample selected by the sample timing control device 6, a memory requires 128 words.

FIG. 18 is a diagram showing a configuration example of the smoothing device 7 shown in FIG. In FIG. 18, reference numeral 71 denotes a plurality of delay units for delaying an input signal for each sample.
a, 72b, and 72c are adders for adding the outputs of the corresponding delay units, 73a, 73b, and 73c are coefficient units for multiplying the outputs of the adders, and 74 is an adder for adding the outputs of the respective coefficient units. And the operation is twice oversampling for both input and output. The coefficients used in the smoothing device 7 are, for example, W0 = 0.625, W1 =
-0.1875, W2 = 0.09375 are used.

For example, as shown in FIG. 17, consider the spectrum when the sample timing of the matched filter without oversampling is shifted by 1/2 chip during the operation and alternately arranged. FIG. 19 is a diagram showing the spectrum of a signal and the spectrum of noise converted from no oversampling to double oversampling by switching the timing. Assuming that the signals do not change between 0 and 63 and between 64 and 127, as shown in FIG. 19, the signals in the aliasing portion are added in opposite phases, so that the effect of aliasing can be eliminated. By performing such an operation, the problem of aliasing is released even without oversampling. However, the noise is white because there is no correlation for each sample. Therefore, it is necessary to filter noise and improve the SN ratio.

FIG. 20 is a diagram showing an operation example of the smoothing device 7 shown in FIG. As shown, both the input signal and the output signal have twice the oversampling accuracy. The result of the cyclic integration performed by the cyclic integrator 3 at each sample timing is input to the smoothing device 7, and a signal from which noise outside the signal band is removed by filtering is output.

As described above, in the sixth embodiment, the timing of the received signal input to the matched filter 1 is switched in units of 制 御 chip by the sample timing controller 6, and each time the switching is performed by the cyclic integrator 3. Since the cyclic integration is performed and noise is cut by the smoothing device 7, the problem of aliasing is eliminated.
Even if the matched filter 1 is oversampled by 1 times,
It can be converted to exactly 2 times oversample. Further, the matched filter 1 has no oversampling, so that the circuit scale can be reduced, and the power consumption can be reduced to 1/4 or less as compared with the conventional four times oversampling. Also, the cyclic integrator 3
Performs the cyclic integration without oversampling, so that the power consumption can be reduced to about 1/4 and the memory capacity to be used is reduced to 1/2 compared to the conventional cyclic integrator having 4 times oversampling.
Can be.

Embodiment 7 FIG. 21 is a diagram showing a configuration of the spread spectrum receiving apparatus according to the seventh embodiment of the present invention. A spread spectrum receiving apparatus according to the present invention includes a sample apparatus 5 capable of sampling a received spread signal by N times (N is an integer of 1 or more) oversamples, and sample timing control for switching N sample timings of the sample apparatuses 5 A matched filter 1 without oversampling for performing a correlation operation between the output of the sampler 5 and the reference code, a first cyclic integrator 3a for coherently and cyclically integrating the output of the matched filter 1 without oversampling, A first interpolator 2a for interpolating the output of the cyclic integrator 3a at twice the oversampling timing, a second cyclic integrator 3b for converting the output of the first interpolator 2a into electric power and performing cyclic integration, and a second interpolator 3b. A second interpolating device 2b for interpolating the output of the cyclic integrator 3b at M times (M is 2 or more) oversampling timing; A path detector 4 for detecting the timing of the signal from between device 2b outputs, consists, matched filter 1, at the chip rate, that is, operating at 1 times oversampled.

The matched filter 1, the first cyclic integrator 3a, the first interpolator 2a, the second cyclic integrator 3b, the second interpolator 2b, and the path detector 4 Since the configuration is similar to that of the third embodiment described above, the same reference numerals are given and the description is omitted. In addition, the sample device 5
Since the configuration of the sample timing control device 6 is the same as that of the sixth embodiment described above, the same reference numerals are given and the description is omitted. In the first interpolation device 2a and the second interpolation device 2b, the number of stages of the delay devices 21a to 21e and the coefficient of the coefficient devices 23a to 23c are determined in consideration of the performance of each interpolation device, the balance of the circuit scale, and the like. The optimum number of stages and values may be set.

In the spread spectrum receiving apparatus configured as described above, the sample timing is switched by サ ン プ ル chip by the sample timing control device 6 as in the sixth embodiment, but the operation of the first cyclic integrator 3a is not changed. Instead of performing cyclic integration at each switched sample timing, cyclic integration is performed using the same memory regardless of the sample timing. Therefore, the first cyclic integrator 3
The memory capacity of “a” may be 64 words, which is half that of the sixth embodiment.

In the present embodiment, the output of the first cyclic integrator 3a is interpolated by the first interpolator 2a to double oversampling accuracy, and is converted into electric power by the second cyclic integrator 3b. Performs cyclic integration. At this time, the second cyclic integrator 3b performs cyclic integration while compensating for the timing shifted by the sample timing control device 6.

FIG. 22 is a diagram showing an operation example of the second cyclic integrator 3b shown in FIG. Here, the output of the first interpolator 2a output with double oversampling accuracy is converted into electric power, and cyclic integration is performed. The M shown
_n represents the value of the address n of the memory. Further, an offset is added to the address of the memory to be cyclically added in accordance with the timing switched by the sample timing control device 6.

As described above, in the present embodiment, the memory capacity of the first cyclic integrator 3a is 64 words (Embodiment 6).
Of the smoothing device 7 of the sixth embodiment.
Since the operation speed of the first interpolation device 2a is half and the number of delay units is also half, the circuit scale and power consumption can be further reduced.

Embodiment 8 FIG. FIG. 23 is a diagram showing a configuration of the spread spectrum receiving apparatus according to the eighth embodiment of the present invention. A spread spectrum receiving apparatus according to the present invention includes a sample apparatus 5 capable of sampling a received spread signal by N times (N is an integer of 1 or more) oversamples, and sample timing control for switching N sample timings of the sample apparatuses 5 A matched filter 1 without oversampling for performing a correlation operation between the output of the sampler 5 and the reference code, a first cyclic integrator 3a for coherently and cyclically integrating the output of the matched filter 1 without oversampling, A first interpolator 2a for interpolating the output of the cyclic integrator 3a at twice the oversampling timing, a second cyclic integrator 3b for converting the output of the first interpolator 2a into electric power and performing cyclic integration, and a second interpolator 3b. A path detector 4 for detecting a signal timing from the output of the cyclic integrator 3b,
The output of the L (L is an integer of 1 or more) second cyclic integrators 3b before and after the timing detected by M times (M is 4 or more)
Third interpolation device 2 for interpolating at oversampling timing
c, and the matched filter 1 operates at the chip rate, that is, with 1-times oversampling.

The matched filter 1, the first cyclic integrator 3a, the first interpolator 2a, the second cyclic integrator 3b, the path detector 4, and the third interpolator 2c Since the configuration is similar to that of the fourth embodiment described above, the same reference numerals are given and the description is omitted. In addition, the sample device 5
Since the sample timing control device 6 has the same configuration as those of the sixth and seventh embodiments described above, the same reference numerals are given and the description is omitted. Also, the third interpolation device 2c
, The number of stages of the delay units 21a to 21e and the coefficient unit 23a
Coefficients .about.23c may be set to the optimum number of stages and values in consideration of the performance of each interpolation device, the balance of the circuit scale, and the like.

In the spread spectrum receiving apparatus configured as described above, based on the output of the second cyclic integrator 3b,
Since the path detector 4 performs path detection, the path detector 4
The signal input to is oversampled twice,
The load on the path detector 4 is halved compared to the path detector 4 of the seventh embodiment described above. Further, using the data near the timing detected by the third interpolator 2c, a signal with double oversampling accuracy is obtained by, for example,
Interpolate to 4x oversampling accuracy.

The present embodiment is different from the seventh embodiment in that the path detector 4 is operated with twice the oversampling accuracy, and after the path is detected, the third interpolator 2c is obtained from the data before and after the timing. That is, interpolation is performed using As described above, in the present embodiment, the operation speed of the path detector 4 can be reduced by performing interpolation after path detection, and further, only in the vicinity of the path detected by the third interpolation device 2c. Since it operates, the amount of calculation can be further reduced.

Embodiment 9 FIG. 24 is a diagram showing a configuration of the ninth embodiment of the spread spectrum receiving apparatus according to the present invention. A spread spectrum receiving apparatus according to the present invention includes a sample apparatus 5 capable of sampling a received spread signal by N times (N is an integer of 1 or more) oversamples, and sample timing control for switching N sample timings of the sample apparatuses 5 A matched filter 1 without oversampling for performing a correlation operation between the output of the sampler 5 and the reference code, a first cyclic integrator 3a for coherently and cyclically integrating the output of the matched filter 1 without oversampling, A first interpolator 2a for interpolating the output of the cyclic integrator 3a at twice the oversampling timing, a second cyclic integrator 3b for converting the output of the first interpolator 2a into electric power and performing cyclic integration, and a second interpolator 3b. Interpolator 2b that interpolates the output of the cyclic integrator 3b at 4x oversampling timing
A path detector 4 for detecting the timing of a signal from the output of the second interpolator 2b; and L (L is an integer of 1 or more) second interpolators 2b before and after the timing detected by the path detector 4. And a third interpolator 2c for interpolating the output at M times (M is 4 or more) oversampling timing.
The matched filter 1 has a chip rate of 1
Operates on double oversampling.

The matched filter 1, the first cyclic integrator 3a, the first interpolator 2a, the second cyclic integrator 3b, the second interpolator 2b, the path detector 4, Since the third interpolation device 2c has the same configuration as that of the fifth embodiment described above, the same reference numerals are given and the description is omitted. Further, since the sample device 5 and the sample timing control device 6 have the same configuration as those of the sixth, seventh and eighth embodiments described above, the same reference numerals are given and the description is omitted. The third interpolating device 2c has a delay device 2
The number of stages 1a to 21e and the coefficients of the coefficient units 23a to 23c are as follows.
In consideration of the performance of each interpolation device, the balance of the circuit scale, and the like, the number of stages and the value may be optimized.

In Embodiment 8 described above, the path timing is detected from the signal of twice oversampling. However, the path detection is usually performed in a non-linear manner because the maximum value is detected and the threshold is determined. In order to perform detection with a high probability and a high detection probability, data of about 4 times oversampling is required.

Therefore, in the spread spectrum receiving apparatus configured as described above, when the accuracy of the detection timing is to be equal to or more than eight times the sample accuracy, the second interpolator 2b sets the accuracy of the four times over sample before the path detection. The timing is detected by the detector 4, and based on the data near the timing, the third interpolator 2c makes the oversampling accuracy eight times or more. Thereby, the detection probability can be further improved.

Embodiment 10 FIG. FIG. 25 is a diagram illustrating a configuration of a spread spectrum receiving apparatus according to a tenth embodiment of the present invention. The spread spectrum receiving apparatus according to the present invention includes: a first sampler 5 capable of sampling a received spread signal by N times (N is an integer of 1 or more) oversamples;
A second sample device 5b that samples the output of the sample device 5 every N times, and N second sample devices 5
, A matched filter 1 without oversampling for performing a correlation operation between the output of the second sampler 5b and a reference code, and the output of the matched filter 1 is coherently integrated without oversampling. First cyclic integrator 3a
A first interpolator 2a for interpolating the output of the first cyclic integrator 3a at double oversampling timing, and a second cyclic integrator 3b for converting the output of the first interpolator 2a into electric power and performing cyclic integration. And a second interpolator 2b for interpolating the output of the second cyclic integrator 3b at M times (M is 2 or more) oversampling timing, and a path detector for detecting the timing of the signal from the output of the second interpolator 2b 4, a fourth interpolator 2d for interpolating the first sampler 5a at K times (an integer satisfying K> N) oversampling timing, and a path detector 4
And a signal demodulator 8 that demodulates the received signal at the timing detected by the above. The matched filter 1 operates at the chip rate, that is, at 1-times oversampling.

The first sampling device 5a (corresponding to the sampling device 5), the matched filter 1, the first cyclic integrator 3a, the first interpolation device 2a, and the second cyclic integrator 3b , The second interpolator 2b, the path detector 4, the sampler 5, and the sample timing controller 6 have the same configurations as those of the seventh embodiment described above, Description is omitted. Also, a first interpolation device 2a, a second interpolation device 2b, and a fourth interpolation device 2d
, The number of stages of the delay units 21a to 21e and the coefficient unit 23a
Coefficients .about.23c may be set to the optimum number of stages and values in consideration of the performance of each interpolation device, the balance of the circuit scale, and the like.

In the spread spectrum receiving apparatus configured as described above, the received signal is demodulated by the signal demodulator 8 at the timing detected by the path detector 4. At this time,
When it is necessary to continuously demodulate by the signal demodulator 8, the performance deteriorates at the sample timing changed by the sample timing control device 6. Therefore, it is necessary to input the signal from the first sampling device 5a to the signal demodulator 8. In this case, since the timing of the received signal obtained by the path detector 4 has quadruple oversampling accuracy, the operation of the first sampling device 5a requires quadruple oversampling. Then, by performing interpolation by the fourth interpolation device 2d, the first sampling device 5b can be operated at a speed lower than 4 times oversampling.

The second sampling device 2b operates without oversampling, but the sample timing is varied by チ ッ プ chip by the sample timing control device 6. Therefore, the first sampling device 5a needs to operate with double oversampling, and the fourth interpolator 2d needs to convert from double oversampling to quadruple oversampling.

As described above, in the present embodiment, in addition to the effect similar to that of the above-described embodiment, the first sampling device 5a can perform the double oversampling operation, and can operate with the quadruple oversampling. Power consumption is reduced by half
Can be Further, since the twice-oversampled signal is converted into a four-times oversampled signal by the fourth interpolation device 2d, the same performance as that of the conventional signal demodulator 8 can be obtained.

Therefore, according to the first to tenth embodiments, it is possible to obtain a spread spectrum receiving apparatus that realizes a significant reduction in circuit scale and power consumption.

[0095]

As described above, according to the present invention, in the matched filter, the selector accompanying the oversampling becomes unnecessary, so that the circuit scale can be greatly reduced, and the received signal can be reduced. Since the number of registers to be stored is also reduced, there is an effect that the circuit scale can be significantly reduced here as well. Further, according to the present invention, since there is no over-sampling, the operation speed of the matched filter is reduced, and accordingly, there is an effect that power consumption can be reduced accordingly. Further, for the same reason, the time resolution of the matched filter output is reduced. However, according to the present invention, the time resolution can be improved by the interpolation means, and the same performance as that of the related art can be realized. This has the effect.

According to the next invention, the operation speed of the cyclic integration means can be made slower than that of the prior art, and since it operates without oversampling,
The memory capacity can be reduced to １ ／, for example, from 256 words to 64 words. This allows
The circuit scale can be significantly reduced compared to the past,
The effect is that power consumption can be greatly reduced.

According to the next invention, in the matched filter, a selector accompanying oversampling is not required, so that the circuit scale can be greatly reduced, and the number of registers for storing received signals is also reduced. Therefore, there is an effect that the circuit scale can be significantly reduced here. Further, since there is no over-sampling, the operation speed of the matched filter is reduced, and accordingly, power consumption can be reduced.
This has the effect. Although the time resolution of the output of the matched filter is reduced for the same reason, according to the present invention, the time resolution can be improved by the first and second interpolation means, and the performance equivalent to the conventional one can be obtained. This has the effect that it can be realized. Also, the second
Is operated with twice oversampling, so that the memory capacity can be halved and the power consumption can be halved in comparison with the prior art which operates with four times oversampling. It works.

According to the next invention, since the interpolation is performed after the timing of each path is detected, the operation speed of the path detecting means can be made lower, and furthermore, in the vicinity of the path detected by the third interpolating means. Since only the operation is performed, the effect that the amount of calculation can be reduced is achieved.

According to the next invention, when the accuracy of the detection timing is made equal to or more than the eight-times oversampling accuracy, the timing is detected by the path detection means after changing to the four times oversampling accuracy by the second interpolation means. Then, the signal near the detected timing is further changed to eight-times oversampling accuracy by the third interpolation means. Thereby, there is an effect that the accuracy of the detection timing can be further improved.

According to the next invention, the timing of the received signal input to the matched filter is switched by the sample timing control means, for example, in units of チ ッ プ chip, and the cyclic integration is performed at each timing switched by the cyclic integration means. The noise is cut by the smoothing means. This eliminates the problem of aliasing, and has the effect that even if the matched filter is a 1-times oversample, it can be accurately converted to a 2x oversample. Also, the matched filter is
Since a selector associated with oversampling is not required, the circuit scale can be significantly reduced.
Since the number of registers for storing received signals is also reduced,
Also in this case, there is an effect that the circuit scale can be significantly reduced. Further, since there is no over-sampling, the operation speed of the matched filter is reduced, so that the power consumption can be reduced accordingly.

According to the next invention, the memory capacity of the first cyclic integration means can be greatly reduced, and the operation speed of the first interpolation means can be reduced as compared with the smoothing means.
Since the number of delay units can be significantly reduced, the circuit scale and power consumption can be significantly reduced.

According to the next invention, the path detecting means is performed with double oversampling accuracy, and after the path is detected, the data before and after the timing is interpolated using the third interpolating means. Accordingly, the operation speed of the path detection unit can be reduced, and since the operation is performed only in the vicinity of the path detected by the third interpolation unit, the amount of calculation can be further reduced. .

According to the next invention, when the accuracy of the detection timing is to be equal to or more than eight times the sampling accuracy, the timing is detected by the path detecting means after the second interpolating means attains the accuracy of four times over sampling. , The third interpolating means makes the oversampling accuracy 8 times or more. Thereby, there is an effect that the detection probability can be further improved.

According to the next invention, there is an effect that the first sampling means can perform the double oversampling operation and the power consumption can be halved compared to the case where the first sampling means operates with the quadruple oversampling. . Further, since the twice-oversampled signal is converted into four-times oversampled by the fourth interpolation means, the signal demodulation means has the effect of obtaining the same performance as the conventional one.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a spread spectrum receiving apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a matched filter illustrated in FIG. 1;

FIG. 3 is a diagram showing a spectrum of a received spread signal.

FIG. 4 is a diagram illustrating a spectrum of a matched filter output operating with twice oversampling.

FIG. 5 No oversampling (1x oversampling)
FIG. 9 is a diagram showing a spectrum of a matched filter output operated by the above.

FIG. 6 is a diagram illustrating a configuration example of an interpolation device illustrated in FIG. 1;

FIG. 7 is a diagram illustrating a frequency characteristic of a filter that converts from no oversampling to double oversampling.

FIG. 8 is a diagram illustrating a specific operation example of the interpolation device illustrated in FIG. 6;

FIG. 9 is a diagram for specifically explaining the operation of the interpolation device.

FIG. 10 is a diagram illustrating a configuration of a spread spectrum receiving apparatus according to a second embodiment of the present invention.

11 is a diagram illustrating a configuration example of a cyclic integrator illustrated in FIG. 10;

FIG. 12 is a diagram illustrating a configuration of a spread spectrum receiving apparatus according to a third embodiment of the present invention.

13 is a diagram illustrating a configuration example of a second cyclic integrator illustrated in FIG. 12;

FIG. 14 is a diagram showing a configuration of a spread spectrum receiving apparatus according to a fourth embodiment of the present invention.

FIG. 15 is a diagram showing a configuration of a spread spectrum receiving apparatus according to a fifth embodiment of the present invention.

FIG. 16 is a diagram showing a configuration of a spread spectrum receiving apparatus according to a sixth embodiment of the present invention.

FIG. 17 is a diagram for explaining a method of converting from no oversampling to double oversampling.

FIG. 18 is a diagram illustrating a configuration example of the smoothing device illustrated in FIG. 16;

FIG. 19 is a diagram showing a spectrum of a signal and a spectrum of noise converted from no oversampling to double oversampling by switching timing.

FIG. 20 is a diagram illustrating an operation example of the smoothing device illustrated in FIG. 18;

FIG. 21 is a diagram illustrating a configuration of a spread spectrum receiving apparatus according to a seventh embodiment of the present invention.

FIG. 22 is a diagram illustrating an operation example of the second cyclic integrator illustrated in FIG. 21;

FIG. 23 is a diagram showing a configuration of a spread spectrum receiving apparatus according to an eighth embodiment of the present invention.

FIG. 24 is a diagram showing a configuration of a ninth embodiment of a spread spectrum receiving apparatus according to the present invention.

FIG. 25 is a diagram illustrating a configuration of a spread spectrum receiving apparatus according to a tenth embodiment of the present invention.

FIG. 26 shows an output example of a conventional matched filter.

FIG. 27 is a diagram for explaining the operation of cyclic integration.

FIG. 28 shows a conventional matched filter and a conventional cyclic integrator.

FIG. 29 is a diagram showing a configuration of a conventional matched filter.

FIG. 30 is a diagram showing a configuration of a conventional cyclic integrator.

[Explanation of symbols]

Reference Signs List 1 matched filter, 2 interpolation device, 2a first interpolation device, 2b second interpolation device, 2c third interpolation device, 2d fourth interpolation device, 3 cyclic integrator, 3a first cyclic integrator, 3b A second cyclic integrator, a 4-pass detector, a 5 sample device, 5a a first sample device,
5b 2nd sample device, 6 sample timing control device, 7 smoothing device, 8 signal demodulator, 11 input register, 12 reference code register, 13 adder, 1
4 Multipliers, 21a, 21b, 21c, 21d, 21e
Delay device, 22a, 22b, 22c adder, 23a,
23b, 23c coefficient unit, 24 adder, 25 selector, 31, 35 adder, 32, 36 memory, 33,
37 address generator, 34 power value calculator, 71 delay unit, 72a, 72b, 72c adder, 73a, 73
b, 73c Coefficient unit, 74 adder, 111 register, 112 writing control device.

Claims (10)

[Claims] 1. A spread spectrum receiver for synchronizing the timing of a received spread signal using a matched filter, comprising: a matched filter without oversampling for performing a correlation operation between a received spread signal and a reference code; Interpolating means for interpolating at double (N is an integer of 1 or more) oversampling timing. 2. The apparatus according to claim 1, further comprising a cyclic integration means for cyclically integrating the output of the matched filter coherently without oversampling between the matched filter and the interpolation means, wherein the interpolation means outputs the output of the cyclic integration means. 2. The spread spectrum receiving apparatus according to claim 1, wherein interpolation is performed at N times oversampling timing. 3. A spread spectrum receiver for synchronizing the timing of a received spread signal using a matched filter, comprising: a matched filter without oversampling for performing a correlation operation between a received spread signal and a reference code; First cyclic integration means for performing coherent cyclic integration without samples, first interpolation means for interpolating the output of the first cyclic integration means at double oversampling timing, and power output of the first interpolation means. A second cyclic integration means for performing a cyclic integration, and a second interpolation means for interpolating the output of the second cyclic integration means at M times (M is an integer of 2 or more) oversampling timing. And a path detecting means for detecting a timing of a signal from an output of the second interpolating means. Apparatus. 4. A second path detector for detecting a signal timing from an output of the second cyclic integration means, replacing the second interpolation means and the path detection means connected to the second cyclic integration means. Means for multiplying the output of L (L is an integer of 1 or more) second cyclic integration means before and after the timing detected by the second path detection means by M times (M is an integer of 4 or more) oversampling timing The spread spectrum receiving apparatus according to claim 3, further comprising: a third interpolation unit that performs interpolation by: 5. The second interpolation means interpolates the output of the second cyclic integration means at four times oversampling timing, and further outputs L signals before and after the timing detected by the path detection means (L is 1 The output of the second interpolating means of
4. The spread spectrum receiving apparatus according to claim 3, further comprising third interpolation means for performing interpolation at M-times (M is an integer of 4 or more) oversampling timing. 5. 6. A spread spectrum receiving apparatus for synchronizing the timing of a received spread signal by using a matched filter, comprising: a sampling means capable of sampling the received spread signal by N times (N is an integer of 1 or more) oversamples; A sample timing control means for switching a sample timing of the sample means; a matched filter without oversample for performing a correlation operation between the output of the sample means and a reference code; Cyclic integration means for performing cyclic integration in a coherent manner without a sample; smoothing means for smoothing N outputs of the cyclic integration means; and path detecting means for detecting signal timing from the output of the smoothing means. A spread spectrum receiving apparatus characterized by the above-mentioned. 7. A first cyclic integration means, which replaces the cyclic integration means, the smoothing means, and the path detection means, and cyclically integrates the matched filter output coherently without oversampling; First interpolating means for interpolating the output of the cyclic integration means at double oversampling timing, second cyclic integration means for converting the output of the first interpolation means into electric power and cyclically integrating the power, A second interpolating means for interpolating the output of the cyclic integration means at M times (M is an integer of 2 or more) oversampling timing; and a path detecting means for detecting a signal timing from the output of the second interpolating means. The spread spectrum receiving apparatus according to claim 6, comprising: 8. A second path detection unit for detecting a signal timing from an output of the second cyclic integration unit instead of the second interpolation unit and the path detection unit connected to the second cyclic integration unit. Means for multiplying the output of L (L is an integer of 1 or more) second cyclic integration means before and after the timing detected by the second path detection means by M times (M is an integer of 4 or more) oversampling timing The spread spectrum receiving apparatus according to claim 7, further comprising: third interpolation means for interpolating by: 9. The second interpolating means interpolates the output of the second cyclic integration means at quadruple oversampling timing, and outputs L (L is 1) before and after the timing detected by the path detecting means. The output of the second interpolating means of
8. The spread spectrum receiving apparatus according to claim 7, further comprising third interpolation means for interpolating at M-times (M is an integer of 4 or more) oversampling timing. 10. A spread spectrum receiver for synchronizing the timing of a received spread signal using a matched filter, comprising: first sampling means capable of sampling a received spread signal by N times (N is an integer of 1 or more) oversamples; A second sampling means for sampling the output of the first sampling means once every N times; a sample timing control means for switching the number of sample timings of the second sampling means; and an output of the second sampling means. A matched filter without oversampling for performing a correlation operation between the first and second reference codes, a first cyclically integrating means for cyclically integrating the output of the matched filter coherently without oversampling, and an output of the first cyclically integrating means, First interpolating means for interpolating at double oversampling timing, and the output of the first interpolating means A second cyclic integration means for converting to power and performing cyclic integration; a second interpolation means for interpolating an output of the second cyclic integration means at M times (M is 2 or more) oversampling timing; A path detecting means for detecting a signal timing from an output of the interpolating means; a fourth interpolating means for interpolating the first sampling means to K-times (an integer satisfying K> N) oversampling timing; And a signal demodulating means for demodulating the received signal at the timing detected by the detector (4).