JP2006211211A - Data receiving unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data receiving unit performing data demodulation at accurate identification timing without using a plurality of pairs of A/D converters and without increasing a sampling clock speed. <P>SOLUTION: A/D converters 1, 2 convert analog signals to digital signals according to the sampling clocks from a clock generator unit 8. The clock frequency at this time is a normal frequency, not a quadrupled frequency. A filter 3a produces no delay of the sampling clock, while a filter 3b produces a delay of 1/4 sample interval, a filter 3c produces a delay of 2/4 sample interval, and a filter 3d produces a delay of 3/4 sample interval, respectively. Demodulators 4a-4d individually perform demodulation processing by inputting signals of different phases caused by different delays. Demodulation signal estimation calculators 5a-5d and a estimation value comparator 6 calculate each error in the digital signals, and a selector 7 selects and forwards the digital signal of the minimum error as a decoded data. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data receiving apparatus used for digital mobile communication, and more particularly to a data receiving apparatus that inputs an analog IQ orthogonal signal and outputs decoded data of the digital signal.

  2. Description of the Related Art Conventionally, there has been known a data receiving apparatus that performs demodulation while sampling while shifting the phase of an IQ orthogonal signal little by little, selects data with the smallest error, and outputs it as decoded data (see, for example, Patent Document 1). . According to this technique, a data receiving apparatus that performs digital wireless communication performs A / D conversion on a plurality of input signals having different sampling phases, identifies a digital value at a symbol identification point, and decodes data with the least error. Yes. At this time, the symbol identification point is accurately detected to improve the reception quality level.

  FIG. 7 is a block diagram showing an example of a conventional data receiving apparatus that demodulates received data with high resolution. In FIG. 7, the data receiving apparatus inputs a plurality of A / D converters 31 and 32 (four sets in the figure) that perform A / D conversion by inputting an in-phase signal (I signal) and a quadrature signal (Q signal). Used. At this time, the sampling timing of each A / D converter group (31a, 32a), (31b, 32b), (31c, 32c), (31d, 32d) is different by 1/4 of the sampling period. Data having different sampling timings by 1/4 are individually demodulated by four demodulators 33a, 33b, 33c, and 33d. Further, the corresponding discriminators 34a, 34b, 34c, and 34d respectively obtain an error between the demodulated data and a preset discrimination value. Then, the instantaneous error comparator 35 compares the errors of the respective sampling data, and the selector 36 selects the data that minimizes the error and outputs it as decoded data. Note that the sampling timing of each of the A / D converters 31 and 32 is determined by the pulse timing sent from the timing generator 37.

FIG. 8 is a block diagram showing another example of a conventional data receiving apparatus that demodulates received data with high resolution. 8 uses only one set of A / D converters 41 and 42 whose sampling clocks are four times (generally N times) the A / D converters 31 and 32 in the received data of FIG. Sampling. Then, the sampling data is sequentially input to the demodulators 33a, 33b, 33c, and 33d by the data switch 43. The processes after the demodulators 33a, 33b, 33c, and 33d are the same as those in FIG. That is, as in the data receiving apparatus of FIG. 7 or FIG. 8, demodulation is performed while shifting the phase of the input signal little by little and sampling is performed. Data can be decoded with a time accuracy of N times in general.
JP-A-9-233140

  However, when it is desired to improve the time resolution to N times the time accuracy using the conventional data receiving apparatus, it is necessary to use N sets of A / D converters in the data receiving apparatus as shown in FIG. As described above, when a plurality of sets of A / D converters are used, it is necessary to prepare a plurality of A / D converters without variation, and therefore it is extremely difficult to select an A / D converter. Furthermore, the use of a plurality of sets of A / D converters increases the number of parts, causing problems such as an increase in the size and cost of the data receiving apparatus.

  When a data receiving apparatus as shown in FIG. 8 is used, one set of A / D converters is sufficient, but the sampling clock generated by the timing generator 37 needs to be multiplied by N times. However, when the sampling clock is increased N times, if the sampling clock before N times is high, there is a limit to the speed of the sampling clock, so the sampling clock may not be increased N times. Furthermore, since noise may be generated when the data switch 43 switches data of each sampling clock, problems such as a reduction in communication quality level are likely to occur.

  The present invention has been made in view of the above points, and is a data receiving apparatus capable of demodulating data at an accurate identification timing without using a plurality of sets of A / D converters and without increasing the sampling clock. The purpose is to provide.

  A data receiving apparatus according to the present invention is a data receiving apparatus that inputs an analog signal and outputs decoded data of a digital signal, an A / D converter that converts an analog signal into a digital signal based on a sampling clock, and A plurality of digital filters that perform a delay of less than one sample interval in the sampling clock with respect to the digital signal converted by the A / D converter, and a phase corresponding to the delay amount delayed by each of the plurality of digital filters A plurality of demodulators for demodulating different digital signals, and a selector for selecting the digital signal with the least error information from among the digital signals individually demodulated by the plurality of demodulators and outputting them as decoded data The structure to be provided is taken.

  According to the data receiving apparatus of the present invention, high-resolution data demodulation is performed using a plurality of all-pass digital filters that delay by a delay amount less than one sample interval of the sampling clock of the IQ orthogonal signal. This eliminates the need to use a plurality of sets of A / D converters, thereby reducing the size of the data receiving apparatus and reducing the cost. Furthermore, since a plurality of sets of A / D converters are not used, it is not necessary to increase the pulse timing of the sampling clock. As a result, the maximum value of the pulse timing of the clock generator can be effectively used as the sampling clock of the A / D converter.

<< Summary of Invention >>
The data receiving apparatus of the present invention uses a plurality of all-pass digital filters that are delayed by a delay amount less than one sampling interval of the sampling clock, and transmits digital signals having different phases from the respective digital filters to the corresponding demodulator. Accordingly, each demodulator demodulates an individual digital signal, so that high-resolution data demodulation can be performed. With such a configuration, it is not necessary to use a plurality of sets of A / D converters, and it is not necessary to speed up the pulse timing of the sampling clock.

  Hereinafter, some embodiments of a data receiving apparatus according to the present invention will be described in detail with reference to the drawings. Note that in the drawings used in the embodiments, the same components are denoted by the same reference numerals, and redundant description is omitted as much as possible.

Embodiment 1
FIG. 1 is a block diagram showing the configuration of the data receiving apparatus according to Embodiment 1 of the present invention. This data receiving apparatus shows a configuration example in the case of improving the time accuracy by a factor of four. In FIG. 1, the data receiving apparatus includes a set of A / D converters 1, 2, 4 filters 3a, 3b, 3c, 3d, 4 demodulators 4a, 4b, 4c, 4d, and 4 demodulations. The signal evaluation calculators 5a, 5b, 5c, and 5d, the evaluation value comparator 6, the selector 7, and the clock generator 8 are provided.

  The A / D converter 1 receives an analog in-phase signal (I signal) and converts it into a digital I signal, and the A / D converter 2 receives an analog quadrature signal (Q signal) and receives a digital Q signal. Convert to signal. The clock generator 8 generates a clock for operating the AD converters 1 and 2 (that is, a clock for determining sampling timing). The frequency of the clock at this time is not a quadruple frequency but a normal frequency. Filters 3a, 3b, 3c, and 3d are all-pass filters that are delayed by less than one sample interval of the sampling clock. In this case, filter 3a is not delayed at all, filter 3b is delayed by 1/4 sample interval, and filter 3c is The filter 3d is delayed by a 3/4 sample interval while being delayed by a 2/4 sample interval.

  Demodulators 4a, 4b, 4c, and 4d receive signals having different phases due to different delays, and individually perform demodulation processing. The demodulated signal evaluation calculators 5a, 5b, 5c and 5d receive the demodulated signals from the corresponding demodulators 4a, 4b, 4c and 4d and perform power calculation. Alternatively, the demodulated signal evaluation calculators 5a, 5b, 5c, and 5d determine the evaluation value of the demodulated signal by calculating an error between each demodulated signal and a preset identification value. The calculation method for determining the evaluation value may be appropriately changed depending on the modulation method used in the data receiving apparatus.

  The evaluation value comparator 6 compares the evaluation values output by the demodulated signal evaluation calculators 5a, 5b, 5c, and 5d, and the demodulated signal of the system having the best evaluation value (that is, the evaluation value is high). Is sent to the selector 7. The selector 7 selects a demodulated signal of the best system (having the highest evaluation value) notified by the evaluation value comparator 6 and outputs it as decoded data.

  In the data receiving apparatus of FIG. 1, the case where the time accuracy is increased by a factor of 4 has been described. Generally, when the time accuracy is desired to be increased by N times (N is an integer), the AD converter remains as one set. The N filter, the demodulator, and the demodulated signal evaluation calculator may be used as N systems, and the delay amount of the filter may be set by shifting by 1 / N samples by the clock generator.

  Here, a design example of an all-pass filter that delays less than one sample interval of the sampling clock will be described. FIG. 2 is an explanatory diagram showing a design method of an all-pass filter for delaying less than one sample interval applied to the data receiving apparatus of the present invention. The design method of the all-pass filter in FIG. 2 is an FIR (Finite Impulse Response) filter as an example. The FIR filter is a filter in which an output signal when an impulse is input converges to 0 in a finite time.

  As shown in step S1 of FIG. 2, a multiplier output signal that multiplies the signal input to the first-stage delay unit D by the filter coefficient h [0], and an output signal of the first-stage delay unit D is multiplied by the filter coefficient h [1]. Multiplier output signal,..., FIR filter for obtaining output signal y [i] by adding a multiplier output signal multiplied by filter coefficient h [N-1] to the output signal of N-1 stage delay device D Think about what to do.

As shown in step S2, the frequency amplitude characteristic p (f) is flat (i.e., P (f) = 1.0) to a frequency phase characteristic theta and (f) θ (f) = - 2πf (t oft + t d ) Desired frequency characteristic data P (f) and θ (f) are created. However, t _d is the desired delay time to be delayed, t _oft is the delay time corresponding to half the FIR filter length N samples, is the delay time for a large part of the amplitude of the impulse response at the center .

For example, if the sampling frequency for delaying by 1/4 sample interval is _fsmp ,
The desired delay time t _d may be set as the following equation (1).
t _d = (1 / f _smp ) × (1/4) (1)

Next, as shown in step S3, discrete complex frequency characteristic data H [k] is obtained from the frequency amplitude characteristic P (f) and the frequency phase characteristic θ (f) by the following equation (2).
H [k] = P (f) {cos (θ (f)) + jsin (θ (f))}
= Cos (θ (f)) + jsin (θ (f)) (2)
here,
f = (k / N) f _smp (where k ≦ N / 2)
f = [(k−N) / N] f _smp (where k> N / 2)

但し、ｎ＝１，２，…Ｎ−１である。 Next, as shown in step S4, an impulse response h [i] is obtained by performing discrete inverse Fourier transform (IDFT) on the discrete complex frequency characteristic data H [k] using the following equation (3).

However, n = 1, 2,... N-1.

  That is, if the impulse response h [i] is created by performing discrete inverse Fourier transform (IDFT) on the discrete complex frequency characteristic data H [k], the impulse response h [i] becomes the filter coefficient of the FIR filter.

When the impulse response h [i] using a FIR filter with filter coefficients, as well as the desired delay time t _d, is also delay the delay time t _oft corresponding to half the filter length N. Therefore, the filter 3a in the demodulation system in (line demodulators 4a in FIG. 1), the filter (Fig. 1 for delayed a delay time t _oft corresponding to half the filter length N to 0 the desired delay time t _d Equivalent). By doing so, it is possible to obtain a signal delayed by a desired delay time t _d with respect to the demodulation system (system demodulator 4a) to 0 delay time.

FIG. 3 is an explanatory diagram showing an image of a signal that has passed through the FIR filter applied to the data receiving apparatus shown in FIG. That is, FIG. 3 shows an image of the signal after passing through the all-pass filter with a delay of less than one sample interval. It appeared temporal change in the amplitude y ₁ [i] of the output signal of the filter to be delayed a delay time t _oft corresponding to half the filter length N (corresponding to a filter 3a in FIG. 1) is shown in FIG. 3 (a) Assuming that the analog signal before sampling is an envelope signal having an amplitude y ₁ [i] of the output signal, as shown in FIG.

Further, as shown in FIG. 3 (b), the signal obtained by delaying by a desired delay time t _d with respect to the sampling period of the delay time t _oft only the output signal delayed corresponding to half the filter length N is dashed It becomes like this. _Accordingly, dashed _(t oft + _{t d)} by filtering the delayed ((filter 3b in FIG. 1, 3c, temporal change in the amplitude _{y 2} [i] of the output signal of corresponding to the 3d) Figure 3 (c) 3C, the temporal change in the amplitude y ₂ [i] of the output signals of the filters 3b, 3c, and 3d in FIG. It has an amplitude of at delayed by a desired delay time t _d with respect to the temporal change of ₁ [i].

<< Embodiment 2 >>
Next, as a second embodiment of the present invention, a data receiving apparatus in a CDMA (Code Division Multiple Access) system using a plurality of correlators will be described. FIG. 4 is a block diagram showing the configuration of a CDMA data receiving apparatus using a plurality of correlators in Embodiment 2 of the present invention. The data receiving device of the second embodiment shown in FIG. 4 includes a set of A / D converters 1 and 2, a clock generator 8, four filters 3a, 3b, 3c, 3d, four correlators 11a, 11b, 11c, 11d, a delay profile calculator 12, a path searcher 13, a selector 14, and a data despreader 15.

  In FIG. 4, a pair of A / D converters 1 and 2 and a clock generator 8 are elements having the same functions as those in the first embodiment shown in FIG. Further, the filters 3a, 3b, 3c, 3d also have a function of generating a delay similar to that in FIG. The correlators 11a, 11b, 11c, and 11d have a function for obtaining a correlation value for obtaining a delay profile. The delay profile calculator 12 has a function of calculating a delay profile with high time resolution by combining the output signals of the correlators 11a, 11b, 11c, and 11d. The path searcher 13 has a function of determining effective fingers from the delay profile. The selector 14 has a function of selecting data corresponding to valid finger timing. The data despreader 15 has a function of performing despreading at effective finger timing and then performing RAKE.

  In the data receiving apparatus shown in FIG. 4, when each filter 3a, 3b, 3c, 3d transmits a delayed signal to the corresponding correlator 11a, 11b, 11c, 11d, the delay profile calculator 12 A delay profile with high time resolution is calculated by combining the output signals of the devices 11a, 11b, 11c, and 11d. The path searcher 13 determines a valid finger from the calculated delay profile, and the selector 14 selects data corresponding to a valid finger timing. As a result, the data despreader 15 performs despreading at the effective finger timing and outputs decoded data. Since the data receiving apparatus performs timing detection with high accuracy in this way, it is possible to suppress degradation of decoded data.

<< Embodiment 3 >>
In the third embodiment of the present invention, a data receiving apparatus in the CDMA system using only one correlator will be described. FIG. 5 is a block diagram showing the configuration of a CDMA data receiving apparatus using one correlator in Embodiment 3 of the present invention. The data receiving device of the third embodiment shown in FIG. 5 differs from the data receiving device of the second embodiment shown in FIG. 4 in that one correlator 11 is used and a high-accuracy peak detector 16 is provided. It is only used.

  In the data receiving apparatus of FIG. 5, the filter filters 3a, 3b, 3c, and 3d generate delays similar to those in FIG. One correlator 11 determines a correlation value for obtaining a delay profile. The delay profile calculator 12 calculates a delay profile from the correlation value obtained by the correlator 11. In the delay profile calculator 12, unlike the case of the second embodiment in FIG. 4, a highly accurate delay profile is not created. The path searcher 13 determines an effective finger from the delay profile. The high-accuracy peak detector 16 predicts a peak position less than one sample interval by using the delay profile data of three samples near the effective finger position. The operation of the high-accuracy peak detector 16 will be described later.

  The selector 14 selects data corresponding to the effective finger timing and the high-accuracy peak detection result. The data despreader 15 despreads the signal output from the selector and then RAKEs it. By adopting such a configuration, the delay profile calculation amount can be reduced as compared with the data receiving apparatus of FIG. In this configuration, the result of the high-accuracy peak detector 16 may be filtered.

Next, the operation of the high-accuracy peak detector 16 in FIG. 5 will be described. FIG. 6 is an operation explanatory diagram of the high-accuracy peak detector 16 shown in FIG. First, in step S11, to prepare the profile value _P 1, _{P 3} with its longitudinal profile value _{P 2} of path positions enabled by the path searcher 13. Next, in step S12, a difference between profile values before and after the peak is obtained. That is, (P ₂ −P ₁ ) in step S 11 is set as the profile value difference P _{2, and} (P ₃ −P ₂ ) in step S 11 is set as the profile value difference P ₃ .

Next, in step S13, linear interpolation difference _{P 2} and _{P 3} of the profile values. Then, in step S14, the place where the profile value is 0 and the true peak position A when the difference P ₂ and P ₃ of the profile values were linearly interpolated. Further, in step S15, the above steps S11 to S14 are repeated by the number of valid paths. In this way, the maximum value of the profile can be detected by detecting the point where the difference value of the profile becomes zero. In this way, the high-accuracy peak detector 16 predicts a peak position less than one sample interval using the three-sample delay profile data near the effective finger position.

  As described above, the data receiving apparatus of the present invention uses a set of A / D converters and can demodulate data with accurate identification timing according to the speed of a normal sampling clock. It can be used effectively for equipment.

1 is a block diagram showing a configuration of a data receiving device according to Embodiment 1 of the present invention. Explanatory drawing which shows the design method of the all-pass filter which delays less than 1 sample interval applied to the data receiver of this invention Explanatory drawing which shows the image of the signal which passed the FIR filter applied to the data receiver shown in FIG. FIG. 3 is a block diagram showing a configuration of a data receiving apparatus based on a CDMA system using a plurality of correlators in Embodiment 2 of the present invention. FIG. 9 is a block diagram showing a configuration of a CDMA data receiving apparatus using one correlator in Embodiment 3 of the present invention. Operational explanatory diagram of the high-accuracy peak detector shown in FIG. Block diagram showing an example of a conventional data receiving apparatus that demodulates received data with high resolution Block diagram showing another example of a conventional data receiving apparatus that demodulates received data with high resolution

Explanation of symbols

1, 2 A / D converters 3a, 3b, 3c, 3d Filters 4a, 4b, 4c, 4d Demodulator 5a, 5b, 5c, 5d Demodulated signal evaluation calculator 6 Evaluation value comparator 7, 14 Selector 8 Clock generation Apparatus 11, 11a, 11b, 11c, 11d Correlator 12 Delay profile calculator 13 Path searcher 15 Data despreader 16 High precision peak detector

Claims (5)

A data receiving device that inputs an analog signal and outputs decoded data of a digital signal,
An A / D converter that converts the analog signal into the digital signal based on a sampling clock;
A plurality of digital filters for performing a delay of less than one sample interval in the sampling clock with respect to the digital signal converted by the A / D converter;
A plurality of demodulators that demodulate digital signals having different phases according to the delay amount delayed by each of the plurality of digital filters;
A selector that selects the digital signal with the least error information from the respective digital signals demodulated individually by the plurality of demodulators and outputs the digital signal as the decoded data;
A data receiving apparatus comprising: When the plurality of digital filters is N units,
Each of the N digital filters performs delay of the accumulated delay amount by sequentially integrating the delay amount obtained by dividing the sampling clock by less than one sample interval by N with reference to the digital filter having the delay amount of zero. The data receiving apparatus according to claim 1, wherein When the plurality of digital filters is four,
The first digital filter has a delay amount of zero, the second digital filter has a delay amount of less than 1/4 sample interval, the third digital filter has a delay amount of less than 2/4 sample interval, and the fourth digital filter has a delay amount 3. The data receiving apparatus according to claim 2, wherein the delay is performed for each of the quantities less than 3/4 sample intervals.   4. The data receiving device according to claim 1, wherein the plurality of digital filters are all-pass digital filters.   The data receiving apparatus according to claim 1, wherein the analog signal is an IQ orthogonal signal.

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