JP5447080B2 - Semiconductor package and semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor package and a semiconductor device.

  In order to cool a semiconductor integrated circuit (LSI) element in an electronic device, for example, a computer, a heat spreader, a heat sink or the like as a heat dissipation element is bonded to the heat dissipation surface of the LSI element, and a blower is disposed near the heat dissipation element to dissipate heat. Air is sent to the element to diffuse heat. In this case, a surface on which no electrode pad for solder connection is formed is selected as the heat dissipation surface of the LSI element.

  In recent years, LSI circuits tend to increase in heat generation due to high integration and high functionality of LSI circuits. With this trend, large heat spreaders and heat sinks have been adopted, and structures that make their shapes complicated. Or make it. This has a great influence on the mounting technology of equipment equipped with LSI elements.

  On the other hand, there is also a method of dissipating heat to the joint surface side of the LSI element with the circuit board. For example, it is known to use a metal core board instead of a resin circuit board.

  There is also known a structure in which a part of a heat pipe is connected to a heat sink, or a metal core substrate in which a metal plate is sandwiched inside a resin circuit board is used, thereby improving the cooling efficiency of the LSI element.

  Further, a structure in which a semiconductor integrated circuit chip is attached to a concave portion on the surface of an internal hollow metal package in which a working fluid is sealed is known, and a plurality of grooves are formed in the hollow portion. In this case, the surface without the electrode pad of the semiconductor integrated circuit chip is bonded to the metal package. In addition, a wiring board is attached around the recess of the metal package, and the terminals of the wiring board and the semiconductor integrated circuit chip are connected to each other by wire bonding.

JP 2004-47897 A JP 2002-335057 A JP 2004-172425 A JP 2002-15640 A JP-A-5-198713 JP 2007-123547 A

  According to the cooling structure of the semiconductor element as described above, two substrates such as a structure in which the semiconductor element and the interposer are connected through solder (solder), and a structure in which the interposer and the wiring board are connected through solder. It is difficult to efficiently cool the heat staying in the space between.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package and a semiconductor device capable of efficiently cooling the heat accumulated in the gap between the upper and lower substrates connected via solder, or the gap between the semiconductor element and the substrate. Is to provide.

According to one aspect, a first substrate having a first electrode pad formed on one surface, a second substrate having a second electrode pad formed on one surface, and the first substrate. A solder bump that joins the first electrode pad and the second electrode pad with one surface facing one surface of the second substrate, and a gap between the first substrate and the second substrate. A radiator having an opening hermetically sealed from, a groove and a protrusion formed on at least one of the one surface of the first substrate and the one surface of the second substrate, the first substrate, and the A semiconductor package having a second substrate and a refrigerant sealed in a space defined by the heat radiator is provided.
According to another aspect, a semiconductor element in which a first electrode pad is formed on one surface, a circuit wiring board in which a second electrode pad is formed on one surface, the one surface of the semiconductor element, and a circuit wiring substrate A solder bump that joins the first electrode pad and the second electrode pad with the one surface facing each other, and an opening that seals and surrounds a gap between the semiconductor element and the second circuit wiring board from a side surface. A semiconductor device comprising: a heat dissipating body, grooves and protrusions formed on the one surface of the circuit wiring board, and a refrigerant sealed in a space defined by the semiconductor element, the circuit wiring board, and the heat dissipating body. Is provided.
It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.

According to the present invention, grooves and protrusions are formed on at least one of the opposing surfaces of the first substrate and the second substrate to which the electrode pads are bonded via the solder bumps, and the first substrate and the second substrate are formed. The refrigerant is enclosed in a space defined by the substrate and the heat radiator on the outer periphery thereof.
The refrigerant is guided toward the solder bumps in the gap between the first and second substrates by capillary action in the grooves and protrusions.
On the other hand, heat generated from the semiconductor element mounted on the first substrate is transmitted to the gap between the first substrate and the second substrate mainly through the electrode pads and the solder bumps. The liquid refrigerant existing in the gap is guided around the electrode pad and the solder bump by capillary action in the groove.
The coolant guided by the capillary phenomenon evaporates and vaporizes in the electrode pads and the solder bumps and the periphery thereof, so that the solder bumps are deprived of heat and cooled. The vaporized refrigerant is cooled and liquefied by the heat radiating body at the outer peripheral portion having a low temperature, is again led to the inside of the gap between the first and second substrates through the groove and the protrusion, and is evaporated again there. Repeat these cycles.
In addition, according to the present invention, a groove and a protrusion are formed on the circuit wiring board side of the facing surface of the semiconductor element and the circuit wiring board to which the electrode pads are bonded via the solder bumps. And the refrigerant | coolant is enclosed with the space divided by the thermal radiation body of those outer periphery.
The heat generated in the semiconductor element is transmitted through the electrode pads and the solder bumps to evaporate the refrigerant in the space between the semiconductor element and the circuit wiring board. In this case, the refrigerant is guided from the heat radiating body to the gap between the semiconductor element and the circuit wiring board by capillary action in the grooves and protrusions. In addition, the vaporized refrigerant is cooled and liquefied by the heat dissipating member on the outer peripheral portion, is again led to the inside of the gap between the semiconductor element and the circuit wiring board through the grooves and protrusions, and is evaporated again. repeat.
As described above, in the gap between the substrates or in the gap between the semiconductor element and the circuit wiring board, the heat transferred from the semiconductor element via the electrode pad and the solder bump vaporizes the refrigerant in the gap, and the gap The temperature rise of the semiconductor element is suppressed, and further, the temperature rise of the semiconductor element is suppressed.

1A to 1C are cross-sectional views (parts 1 to 3) showing a mounting substrate forming step in the semiconductor package according to the first embodiment of the present invention. 1D and 1E are cross-sectional views (Nos. 4 and 5) showing a mounting substrate forming step in the semiconductor package according to the first embodiment of the present invention. FIGS. 1F and 1G are cross-sectional views (Nos. 6 and 7) showing a mounting substrate forming step in the semiconductor package according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment of the present invention. FIG. 3A is a plan view of a mounting substrate in the semiconductor package according to the first embodiment of the present invention, and FIG. 3B is a plan view showing a state in which the upper substrate in FIG. 3A is removed. FIG. 4 is an explanatory view showing the heat exchange action in the mounting substrate of the semiconductor package according to the first embodiment of the present invention. 5A to 5D are cross-sectional views (Nos. 1 to 4) showing a process of forming electrode pads, grooves and protrusions applied to the mounting substrate of the semiconductor package according to the first embodiment of the present invention. FIG. 5E to FIG. 5G are cross-sectional views (Nos. 5 to 7) showing steps of forming electrode pads, grooves and protrusions applied to the mounting substrate in the semiconductor package according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view showing another example of the mounting substrate of the semiconductor package according to the first embodiment of the present invention. FIG. 7 is a sectional view showing another arrangement example of the semiconductor elements mounted on the semiconductor package according to the first embodiment of the present invention. FIG. 8 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. It is a top view which shows another example of an electrode pad.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the drawings, similar components are given the same reference numerals.
(First embodiment)
1A to 1G are cross-sectional views illustrating a process of forming a semiconductor package according to the first embodiment of the present invention.
First, two interposers used for a semiconductor package will be described. The interposer is a circuit board that converts the position of the metal pad on one side to the position of the metal pad on the opposite side.

  A first interposer 1 shown in FIG. 1A includes, for example, a silicon substrate 2 having a thickness of about 200 μm, and a plurality of first electrode pads 3 formed on the first surface of the silicon substrate 2 at a pitch of, for example, 50 μm to 200 μm. have. On the second surface of the silicon substrate 2, a plurality of second electrode pads 4 are formed, for example, at a pitch of about 2 mm. The first electrode pad 3 and the second electrode pad 4 are connected by wiring (not shown), vias (not shown), etc. formed in the silicon substrate 2.

  Solder bumps 5 are bonded to the surface of the second electrode pad 4. The solder bump 5 is made of lead-free solder, for example, a tin / silver / copper (Sn—Ag—Cu) alloy having a melting point of 217 ° C.

  The second interposer 11 shown in FIG. 1B includes an insulating substrate 12 made of, for example, a glass epoxy resin having a thickness of about 2 mm, and a plurality of third electrode pads 13 formed on the first surface. ing. The third electrode pad 13 is formed at a position facing the second electrode pad 4 in a state where the first interposer 1 is overlaid on the insulating substrate 12.

Furthermore, a fourth electrode pad 14 is formed on the second surface of the second interposer 11. The third electrode pad 13 and the fourth electrode pad 14 are electrically connected through a via 15 in a via hole 15 a formed in the insulating substrate 12.
In addition, by forming wiring (not shown) and vias (not shown) inside the insulating substrate 12,
The third electrode pad 13 and the fourth electrode pad 14 may be electrically connected.

  As a method of forming the via 15, a method of heating after filling the via hole 15a with a conductive paste or a method of forming a metal film, for example, a Cu film on the inner surface of the via hole 15a by electroless plating or electrolytic plating is adopted. May be.

A metal film 18 having a plurality of fine grooves 16 and protrusions 17 is formed on the first surface of the insulating substrate 12 of the second interposer 11 except for the third electrode pad 13 and its peripheral region. . That is, the upper portion of the metal film 18 has an uneven shape, the width of the protrusion 17 is about 40 μm, the width of the groove 16 is about 40 μm, and the height of the protrusion 17 is about 40 μm, for example.
The protrusion 17 extends continuously or intermittently from the third electrode pad 13 toward the outside. A method for forming the groove 16 and the protrusion 17 will be described later.

Next, as shown in FIG. 1C, the solder paste 6 is formed on the third electrode pad 13 of the second interposer 11 by screen printing. Note that a flux may be formed instead of the solder paste 6.
Thereafter, the first surface of the second interposer 11 and the second surface of the first interposer 1 are made to face each other. Further, the first interposer 1 is pressed from the first surface side, and the first solder bumps 5 are pressed against the solder paste 6 to come into contact with the third electrode pads 13.

  Subsequently, the second interposer 11 and the first interposer 1 thereon are placed in a reflow furnace, and the solder bumps 5 are melted at a temperature, for example, about 20 ° C. higher than the melting point of the first solder bumps 5 in that state. Later, return to room temperature.

As a result, as shown in FIG. 1D, the solder bump 5 on the second electrode pad 4 of the first interposer 1 is bonded to the third electrode pad 13 on the second interposer 11.
Next, as shown in FIG. 1E, the second and third solder bumps 22 and 24 joined to the respective electrode pads 21a and 23a of the first semiconductor element 21 and the second semiconductor element 23 are connected to the first semiconductor element 21 and the second semiconductor element 23, respectively. Bonded to the first electrode pad 3 on the interposer 1.

  The second and third solder bumps 22 and 24 are made of a material having a melting point lower than that of the first solder bump 5 below the first interposer 1, for example, an Sn—In—Bi alloy having a melting point of 206 ° C. to 214 ° C. It is preferable to form.

  In order to join the second and third solder bumps 22 and 24 to the first electrode 3, first, solder paste or flux is applied onto the first electrode pad 3 of the first interposer 1. Thereafter, an underfill layer 25 is formed by a screen printing method in a region where the first and second semiconductor elements 21 and 23 are placed in the first interposer 1. Further, the second and third solder bumps 22 and 24 of the first and second semiconductor elements 21 and 23 are pressed against and penetrate the underfill layer 25 and are brought into contact with the first electrode pad 3. A thermosetting resin such as an epoxy resin is used as the underfill layer.

Thereafter, the first and second interposers 1 and 11 and the first and second semiconductor elements 21 and 23 are placed in a reflow furnace and heated. The heating temperature in this case is set to a height at which the underfill layer 25 is thermally cured and the second and third solder bumps 22 and 24 are melted. Thereafter, the underfill layer 25 and the second and third solder bumps 22 and 24 are cooled, so that the second and third solder bumps 22 and 24 are bonded to the first electrode pad 3.
A semiconductor integrated circuit is formed in each of the first and second semiconductor elements 21 and 22.

  Next, as shown in FIG. 1F, the first and second interposers 1 and 11 are formed in an opening 31a formed in a region closer to the center of the frame-like radiator 31 formed of a metal such as copper or aluminum. Fit. Thereby, the clearance gap between the 1st, 2nd interposer 1 and 11 is enclosed by the heat radiator 31 from the circumference | surroundings.

  A lateral groove 32 communicating with the gap between the first and second interposers 1 and 11 is formed on the inner peripheral surface of the opening 31a surrounding the first and second interposers 1 and 11 in the heat radiator 31. Yes. The bottom surface of the lateral groove 32 is formed at a position that is substantially flush with or above the first surface of the second interposer 11. In addition, the lower surface of the radiator 31 has a shape that protrudes from the second surface of the second interposer 11 beyond the second electrode pad 14.

  Further, a liquid supply path 33 is formed in the heat radiating body 31 so as to communicate with a part of the lateral groove 32 from the side surface. A plurality of heat radiation fins 34 are formed on the outer surface, for example, the upper surface, of the heat radiator 31.

  Subsequently, the boundary between the radiator 31 and the first and second interposers 1 and 11 is sealed using a sealing material 31b, for example, solder. In this case, the solder is preferably formed of a material having a melting point lower than that of the first, second, and third solder bumps 5, 22, and 24, for example, an Sn—In—Bi alloy.

  Next, as shown in FIG. 1G, a working fluid 35 serving as a refrigerant is supplied from the open end of the liquid supply path 33 on the side surface of the radiator 31. The supply amount of the working fluid 35 is an amount that fills the narrow groove 16 existing in the gap between the first and second interposers 1 and 11 and secures a space in the gap.

As the working fluid 35, a fluid having a boiling point of, for example, 100 ° C. or less, for example, HFC-365 or HFC-7000 which is a hydrochlorofluorocarbon used as an alternative chlorofluorocarbon, or a hydrocarbon such as butane or pentane which is an organic solvent. Use system fluid.
After that, the opening end of the liquid supply path 33 on the side surface of the radiator 31 is sealed with a plug 36, thereby preventing the working fluid 35 from leaking and disappearing due to volatilization.

  Next, as shown in FIG. 2, the first and second interposers 1 and 11 are attached on the circuit board 37. In the circuit board 37, wirings, vias, etc. (not shown) are formed, a fifth electrode pad 38 is formed on the upper surface of the circuit board 37, and a fifth electrode pad 38 is formed on the fifth electrode pad 38. 4 solder bumps 39 are formed. The fourth solder bump 39 is preferably formed of a material having a melting point lower than that of the first to third solder bumps 5, 22, 24, for example, an SnZn alloy having a melting point of about 199 ° C.

  In order to attach the first and second interposers 1 and 11 onto the circuit board 37, first, solder paste or flux is applied to the surface of the fourth electrode pad 14 of the second interposer 11. Thereafter, the fourth electrode pad 14 and the fourth solder bump 39 are aligned, and the fourth solder bump 39 is melted and joined to the fourth electrode pad 14.

  As a result, the semiconductor integrated circuits in the first and second semiconductor elements 21 and 23 have the first to fifth electrode pads 3, 4, 13, 14 and the first to fourth solder bumps 5, 22, 24. , 39, etc., to the wiring in the circuit board 37.

A semiconductor device in which the first and second semiconductor elements 21 and 23 are mounted on the package substrate having the first and second interposers 1 and 11 as described above has a planar structure as shown in FIG. 3A, for example. Further, the upper surface of the second interposer 1 has a planar structure as shown in FIG. 3B.
In FIG. 3A, reference numerals 7 and 8 indicate semiconductor elements other than the first and second semiconductor elements 21 and 23, and reference numeral 9 indicates other electronic components.

  In the semiconductor device as described above, a voltage is supplied to the semiconductor integrated circuits in the first and second semiconductor elements 21 and 23 mounted on the semiconductor package substrate having the first and second interposers 1 and 11, The semiconductor integrated circuit is operated by transmitting and receiving the signal. As a result, the temperatures of the first and second semiconductor elements 21 and 23 change according to the operating state of the semiconductor integrated circuit.

  In FIG. 2, when the amount of heat generated by the first and second semiconductor elements 21 and 23 increases, the heat passes through the second and third solder bumps 22 and 24 and the first electrode pad 3, and the first interposer 1. Is transmitted in.

  Further, the heat transmitted to the first interposer 1 is transmitted to the second electrode pad 4, the first solder bump 5, and the third electrode pad 13 through wiring, vias, etc. in the silicon substrate 2.

  In addition, at the bottom of the gap between the first and second interposers 1 and 11 where the second electrode pads 4, the first solder bumps 5, and the third electrode pads 13 are arranged, the working fluid 35 contains a large number of fine fluids. It is guided by the capillary phenomenon in the groove 16 and supplied to the periphery of the third electrode pad 14, the first solder bump 5, and the second electrode pad 4.

  Therefore, as shown in FIG. 4, the heat transferred from the first interposer 1 to the third electrode pad 13 and the first solder bump 5 is transferred to the first solder bump 5, the third electrode pad 13 and the The working fluid 35 is heated and evaporated by the surrounding protrusions 17.

  The vaporized working fluid 35 travels through the space between the first interposer 1 and the second interposer 11 and moves to the lateral groove 32 of the radiator 31 at the outer peripheral portion having a low temperature. The moved gas is cooled and liquefied by heat exchange in the lateral groove 16 in the heat dissipating body 31 having a large number of heat dissipating fins 34.

  The liquefied working fluid 35 flows down to the bottom of the lateral groove 32, and is again guided to the surfaces of the third electrode pad 13 and the first solder bump 5 by capillary action in a large number of narrow grooves 16.

  As described above, the working fluid 35 repeats vaporization and liquefaction and circulates in the space defined by the gap between the first and second interposers 1 and 11 and the lateral groove 32 around the second interposer 1, 11. The heat transmitted to the electrode pad 4, the first solder bump 5, and the third electrode pad 13 is dissipated to the outside through the refrigerant and the heat radiator 31.

  Further, since the working fluid 35 takes away the latent heat of vaporization on the surface of the first solder bump 5, the third electrode pad 13, and the narrow groove 16, the first solder bump 5, the third electrode pad 13, and the narrow groove 16. Temperature drops. Thereby, the temperature of the gap between the first and second interposers 1 and 11 is lowered, and the temperature distribution of the gap is made uniform. Further, when the first solder bump 5 and the third electrode pad 13 are cooled, a local temperature rise of the first and second semiconductor elements 21 and 23 thermally connected to them, that is, a hot spot is obtained. Is suppressed.

Further, in the system-in-package in which the chip-like first and second semiconductor elements 21 and 23 are mounted on the package substrate, the temperature variation between the first and second semiconductor elements 21 and 23 is suppressed. Thus, the temperature distribution can be averaged.
Furthermore, even if the heights of the first and second semiconductor elements 21 and 23 are different, the temperature rise can be suppressed and the problem of component mounting does not occur.

  Further, even if a structure in which the first and second semiconductor elements 21 and 23 are mounted on the first interposer 1 face-up is adopted, the heat dissipation effect is enhanced. In addition, since a metal layer for heat transfer is not formed in the first and second interposers 1 and 11, the degree of freedom of wiring in the interposers 1 and 11 is increased, and high integration of semiconductor integrated circuits is supported. can do.

Next, a method for forming the metal film 18 having the narrow groove 16 and the protrusion 17 and the third electrode pad 13 will be described with reference to FIGS. 5A to 5G.
First, as shown in FIG. 5A, a 0.3 μm thick Ti layer 18a and a 0.25 μm thick first Cu layer 18b are electrolessly formed as seed layers on the upper surface of the insulating substrate 12 in which the vias 15 are formed. It is formed by a plating method.

Subsequently, as shown in FIG. 5B, a photoresist is applied on the first Cu layer 18b, and a resist pattern 19 is formed by exposing and developing the photoresist. The resist pattern 19 includes a first opening 19a having a diameter of about 200 μm to 300 μm that exposes a region where the third electrode pad 13 is to be formed, and a stripe shape having a width of about 40 μm that exposes a region where the protrusion 17 is to be formed. The second opening 19b. The periphery of the first opening 19 a is covered with a resist pattern 19. A plurality of second openings 19b are formed at intervals of about 40 μm.
A via 15 is formed in the insulating substrate 12 below the first opening 19a.

  Next, as shown in FIG. 5C, the Ti layer 18a and the first Cu layer 18b are used as plating electrodes, and are formed on the Cu layer 18b exposed from the first and second openings 19a and 19b of the resist pattern 19. The Ni layer 18c and the second Cu layer 18d are sequentially formed by electrolytic plating. The thickness of the Ni layer 18c is, for example, 4 μm, and the thickness of the second Cu layer 18d is, for example, about 40 μm.

The Ti layer 18 a, the first Cu layer 18 b, the Ni layer 18 c, and the second Cu layer 18 d formed on the insulating substrate 12 in this way are used as the metal film 18.
Thereafter, as shown in FIG. 5D, the resist pattern 19 is removed.

Next, as shown in FIG. 5E, a photoresist 20 is applied, and this is exposed and developed to form an opening 20a around the region where the third electrode pad 13 is to be formed.
Subsequently, as shown in FIG. 5F, after etching the Cu layer 18b with a solution containing hydrogen peroxide and sulfuric acid through the opening 20a, the Ti layer 18a is etched with a hydrofluoric acid / nitric acid containing solution through the opening 20a. The upper surface of the second interposer 11 is exposed.

  Thereafter, as shown in FIG. 5G, the photoresist 20 is removed. As a result, the metal film of the Ti layer 18a, the first Cu layer 18b, the Ni layer 18c, and the second Cu layer 18d left in the shape of islands in the region above the via 15 in the exposed metal film 18 is converted into a third layer. The electrode pad 13 is used. Further, the Ti layer 18a, the Cu layer 18b, the Ni layer 18c, and the Cu layer 18d left in the other regions in a convex shape are used as the protrusions 17, and the recesses between the protrusions 17 are used as the narrow grooves 16.

  Incidentally, the first Cu layer 18b and Ti layer 18a may be etched without using the photoresist 20 shown in FIG. 5F. However, when the first Cu layer 18b is etched, the second Cu layer 18d is as thin as the first Cu layer 18b, but there is no particular problem. In this case, the protrusion 17 is not connected via the lower metal film 18, but a capillary phenomenon due to the narrow groove 17 occurs.

FIG. 6 is a cross-sectional view showing another example of the semiconductor device as described above. The metal film 18 having the narrow groove 16 and the protrusion 17 is formed on the second surface (lower side in the figure) of the first interposer 1. It has the structure formed in.

  Thereby, the working fluid 35 liquefied in the region near the heat radiating fin 34 in the horizontal groove 32 of the radiator 31, that is, the upper surface of the horizontal groove 32, can be guided to the gap between the first and second interposers 1 and 12 by the narrow groove 16. It becomes easy. In this case, the liquefied working fluid 35 falls from the narrow groove 16 to the second interposer 11 and flows on the second interposer 11. Further, the working fluid 35 guided to the narrow groove 16 is vaporized by the heat of the second and third electrode pads 4 and 13 and the first solder bump 5 and its peripheral region and moves to the heat radiator 31.

FIG. 7 is a cross-sectional view showing still another example of the semiconductor device.
In FIG. 7, third to seventh semiconductor elements 41 a to 41 e stacked in the height direction, that is, three-dimensionally, are stacked on the first surface of the first interposer 1. Among them, electrode pads are formed on the upper and lower surfaces of the third to sixth semiconductor elements 41a to 41d, and the upper and lower electrode pads are connected to each other via solder bumps 42b to 42d. The solder bumps 42a to 42e are made of the same material as the second and third solder bumps 22 and 24 described above.

Solder bumps 42 a bonded to the electrode pads on the lower surface of the third semiconductor element 41 a disposed at the bottom are connected to the first electrode pads 3.
The upper surface of the seventh semiconductor element 41e disposed at the top is a heat radiating surface, and a heat sink 42 having heat radiating fins 43a is bonded thereon. In addition, an electrode pad is formed on the lower surface of the seventh semiconductor element 41e, and is connected to the electrode pad on the upper surface of the sixth semiconductor element 41d via the solder bump 42e therebelow.

  Further, a step 31c extending outward is formed at the lower part of the opening 31a of the heat radiator 31, and a flange 12a formed on the outer peripheral surface of the second interposer 12 is fitted into the step 31c. In addition, a support frame 31d that supports the flange 21a from below is fitted in a lower portion of the step 31c of the radiator 31. Thereby, positioning of the 2nd interposer 12 in opening 31a of heat sink 31 becomes easy.

  According to the semiconductor device having such a structure, the heat generated in the third to seventh semiconductor elements 41 a to 41 e is supplied to the gap between the first interposer 1 and the second interposer 11. In addition to being radiated from the radiator 31 via the heat sink, it can be emitted to the outside via the heat sink 43.

(Second Embodiment)
FIG. 8 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. In FIG. 8, the same reference numerals as those in FIG. 2 denote the same elements.

In FIG. 8, a plurality of first electrode pads 52 are formed on the lower surface of a semiconductor element 51 having a semiconductor integrated circuit. In addition, a plurality of second electrode pads 54 are formed on the upper surface of the circuit wiring board 53 disposed to face the semiconductor element 51.
The planar shape of the circuit wiring board 53 is the same as the planar shape of the semiconductor element 51. The second electrode pad 54 is formed at a position overlapping the first electrode pad 52 in a state where the outer peripheral edges of the circuit wiring board 53 and the semiconductor element 51 coincide with each other when viewed from above.

  Further, in the upper surface of the printed circuit board 53 except for the second electrode pad 54 and its surrounding region, a metal film 18 having a plurality of fine grooves 16 and protrusions 17 is formed as in the first embodiment. Has been.

  The protrusion 17 extends continuously or intermittently from the second electrode pad 54 toward the outside. The method for forming the grooves 16 and the protrusions 17 in the metal film 18 is the same as the method shown in the first embodiment. The width of the groove 16 is, for example, about 40 μm, the width of the protrusion 17 is, for example, about 40 μm, and the height of the protrusion 17 is, for example, about 40 μm.

  The semiconductor element 51 is arranged so that the outer peripheral edge thereof overlaps with the outer peripheral edge of the circuit wiring board 53. In such a state, the first electrode pad 52 and the second electrode pad 54 are connected via the solder bumps 55. Are joined together. The solder bump 55 is made of lead-free solder, for example, a SnAgCu alloy having a melting point of 217 ° C.

The semiconductor element 51 and the circuit wiring board 53 connected by the solder bumps 55 are fitted in a sealed state in an opening 56 a formed near the center of the radiator 56.
A lateral groove 57 that leads to a gap between the semiconductor element 51 and the circuit wiring board 53 is formed on the inner peripheral surface of the opening 56 a of the radiator 56. The lower surface of the lateral groove 57 is formed at or above a position that is substantially flush with the lower surface of the circuit wiring board 53. The radiator 56 is made of a metal such as copper or aluminum.

  A liquid supply path 58 is formed in the radiator 56 from a part of the lateral groove 57 to the outer peripheral surface of the radiator 56. A plurality of heat radiation fins 59 are formed on the outer surface, for example, the upper surface, of the heat radiator 56.

  The boundary between the radiator 56 and the semiconductor element 51 and the boundary between the radiator 56 and the circuit wiring board 53 are sealed with a sealing material 60, for example, solder. The solder is preferably formed of a material having a melting point lower than that of the solder bump 55, for example, a SnInBi alloy.

  From the side opening end of the liquid supply path 58 of the radiator 56, the working fluid 35 serving as a refrigerant is supplied to the gap between the semiconductor element 51 and the circuit wiring board 53 through the lateral groove 57. The supply amount of the working fluid 35 is set to an amount in which a space exists between the semiconductor element 51 and the circuit wiring board 53 and fills the narrow groove 16 at room temperature.

  As the working fluid 35, a fluid having a boiling point of, for example, 100 ° C. or less, for example, the same liquid as shown in the first embodiment is used. The open end of the liquid supply path 58 on the side surface of the radiator 56 is sealed with a plug 61.

  In the semiconductor device as described above, the semiconductor integrated circuit is operated by supplying power to the semiconductor element 51 and transmitting and receiving signals. Thereby, the temperature of the semiconductor element 51 changes according to the operation state of the semiconductor integrated circuit.

  When the amount of heat generated by the semiconductor element 51 increases, the heat is transmitted to the solder bump 55 and the first and second electrode pads 52 and 54 that exist in the gap between the semiconductor element 51 and the circuit wiring board 53.

  At the bottom of the gap, the working fluid 35 is guided by capillarity in the large number of narrow grooves 16 and supplied to the periphery of the second electrode pad 54 and the solder bump 55, so that the second electrode is supplied from the circuit wiring board 53. The heat transmitted to the pad 54 and the solder bump 55 heats the working fluid 35 and evaporates it.

The vaporized working fluid 35 travels through the space between the semiconductor element 51 and the circuit wiring board 53 and moves to the lateral groove 57 of the radiator 56 at the outer peripheral portion having a low temperature. The gas of the moved working fluid 35 is cooled and liquefied by heat exchange in the lateral groove 57 in the heat radiator 56 having a large number of heat radiation fins 59.

  The liquefied working fluid 35 flows down to the bottom of the lateral groove 57 and is again guided to the surfaces of the second electrode pad 54 and the solder bump 55 by capillary action in the numerous narrow grooves 16.

  Thus, in the space defined by the gap between the semiconductor element 51 and the circuit wiring board 53 and the lateral groove 57 around the gap, the working fluid 35 repeats vaporization and liquefaction and circulates. It is discharged to the outside through the working fluid 35 and the heat radiator 56.

  Further, the working fluid 35 takes away latent heat of evaporation in the solder bumps 55, the second electrode pads 54, the narrow grooves 16 and their peripheral regions, thereby cooling the gap between the semiconductor element 51 and the circuit wiring board 53. Thereby, the internal temperature of the semiconductor element 51 is lowered, the temperature distribution of the semiconductor element 51 is made uniform, and the occurrence of hot spots is suppressed.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It should be construed without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. Although embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the present invention.

Reference Signs List 1 interposer 2 silicon substrate 3 first electrode pad 4 second electrode pad 5 solder bump 11 interposer 12 insulating substrate 13 third electrode pad 14 fourth electrode pad 15 via 16 narrow groove 17 protrusion 18 metal films 21 and 22 Semiconductor elements 23 and 24 Solder bumps 31 Radiator 31a Opening 32 Horizontal groove 33 Liquid supply path 34 Radiation fin 35 Working fluid 36 Plug 37 Circuit board 38 Fifth electrode pad 39 Solder bumps 41a to 41e Semiconductor element 43 Heat sink 51 Semiconductor element 52 , 54 Electrode pad 55 Solder bump 56 Radiator 57 Horizontal groove

Claims (5)

A first substrate having a first electrode pad formed on one surface;
A second substrate having a second electrode pad formed on one surface;
A solder bump for bonding the first electrode pad and the second electrode pad with the one surface of the first substrate facing the one surface of the second substrate;
A radiator having an opening that seals and surrounds a gap between the first substrate and the second substrate from a side;
Grooves and protrusions formed on at least one of the one surface of the first substrate and the one surface of the second substrate;
A refrigerant sealed in a space defined by the first substrate, the second substrate, and the radiator;
A semiconductor package.   The semiconductor package according to claim 1, wherein a lateral groove that communicates with a gap between the first substrate and the second substrate is formed on an inner peripheral surface of the opening of the heat radiator.   The semiconductor package according to claim 1, wherein at least one of a via and a wiring is formed on the first substrate and the second substrate.   3. The third electrode pad connected to the electrode pad of the semiconductor element via a bump is formed on the other surface of the first substrate. 3. 2. The semiconductor package according to item 1. A semiconductor element having a first electrode pad formed on one surface;
A circuit wiring board having a second electrode pad formed on one surface;
A solder bump for bonding the first electrode pad and the second electrode pad with the one surface of the semiconductor element and the one surface of the circuit wiring board facing each other;
A radiator having an opening that seals and surrounds a gap between the semiconductor element and the second circuit wiring board from a side;
Grooves and protrusions formed on the one surface of the circuit wiring board;
A refrigerant sealed in a space defined by the semiconductor element, the circuit wiring board, and the radiator;
A semiconductor device.

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