JP2007141887A - Semiconductor device and printed wiring board employing it - Google Patents

Semiconductor device and printed wiring board employing it Download PDF

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Publication number
JP2007141887A
JP2007141887A JP2005329245A JP2005329245A JP2007141887A JP 2007141887 A JP2007141887 A JP 2007141887A JP 2005329245 A JP2005329245 A JP 2005329245A JP 2005329245 A JP2005329245 A JP 2005329245A JP 2007141887 A JP2007141887 A JP 2007141887A
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semiconductor element
semiconductor device
wiring board
printed wiring
substrate
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Japanese (ja)
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Yuichi Kurashina
優一 倉科
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Sony Corp
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Sony Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To dissipate heat from a heat generating component while sustaining a uniform clearance between a semiconductor device and a printed wiring board without increasing the thickness. <P>SOLUTION: A semiconductor device 2 stacked on the first semiconductor element 3 of an insulating substrate 4 mounting the first semiconductor element 3 comprises a substrate 8, a plurality of bumps 10 formed on one side of the substrate 8 opposing the first semiconductor element 3 and being brought into contact with the upper surface 3a of the first semiconductor element 3, and a second semiconductor element 9 mounted on the other side of the substrate 8. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

プリント配線板に実装される半導体装置に関し、詳しくは絶縁基板上に複数の半導体チップを積層させてモジュール化された半導体装置に関する。   The present invention relates to a semiconductor device mounted on a printed wiring board, and more particularly to a semiconductor device modularized by stacking a plurality of semiconductor chips on an insulating substrate.

従来よりプリント配線板においては、ＣＳＰ（Chip Size Package）やＢＧＡ（Ball Grid Aray）といった半導体パッケージを用いてフリップチップ実装する際には、例えば図４に示すように、半導体パッケージ５０の実装面に設けられたはんだボール５１を、クリームはんだ等が印刷されたプリント配線板５２のランド５３に搭載し、リフローはんだ付けされることにより行われていた。   Conventionally, when a printed wiring board is flip-chip mounted using a semiconductor package such as CSP (Chip Size Package) or BGA (Ball Grid Aray), for example, as shown in FIG. The solder balls 51 provided are mounted on lands 53 of a printed wiring board 52 on which cream solder or the like is printed, and are reflow soldered.

ここで、プリント配線板５２の半導体パッケージ５０の実装領域に半導体チップ５４が実装されている場合、この半導体チップ５４より生ずる熱は、これら半導体パッケージ５０及び半導体チップ５４間の空間において、はんだボール５１側に逃げるしかない。また、リフロー投入温度は、半導体パッケージ５０のインタポーザ基板５５のガラス転移温度を超えるため、図５に示すように、半導体パッケージ５０に反りが発生してプリント配線板５２と半導体パッケージ５０とのクリアランスを均一に確保できず、また、はんだボール５１との接続不良を引き起こすおそれがあり、品質信頼性に影響を及ぼすおそれがある。さらに、半導体チップ５４の動作時における発熱がプリント配線板５２の配線パターンを伝達し、発熱温度がプリント配線板の動作品質に影響する可能性もある。   Here, when the semiconductor chip 54 is mounted in the mounting region of the semiconductor package 50 on the printed wiring board 52, the heat generated from the semiconductor chip 54 is solder balls 51 in the space between the semiconductor package 50 and the semiconductor chip 54. There is no choice but to escape to the side. Further, since the reflow charging temperature exceeds the glass transition temperature of the interposer substrate 55 of the semiconductor package 50, the semiconductor package 50 is warped and the clearance between the printed wiring board 52 and the semiconductor package 50 is increased as shown in FIG. Uniformity cannot be ensured, and there is a possibility that poor connection with the solder ball 51 may occur, which may affect quality reliability. Further, heat generated during operation of the semiconductor chip 54 may transmit the wiring pattern of the printed wiring board 52, and the heat generation temperature may affect the operation quality of the printed wiring board.

かかる半導体チップが発生した熱の放熱に留意したプリント配線板としては、特開２００２−２７０７４３号公報（特許文献１）に示されるように、基板内に放熱用ヒートシンク部がコア層内に設置された構造や、特開２００１−２５７４８９号公報（特許文献２）に示されるように発熱部品上にヒートシンクを接触させた構造がある。   As a printed wiring board in consideration of heat dissipation of the heat generated by such a semiconductor chip, as shown in Japanese Patent Laid-Open No. 2002-270743 (Patent Document 1), a heat sink for heat dissipation is installed in a core layer in a substrate. And a structure in which a heat sink is brought into contact with a heat-generating component, as disclosed in Japanese Patent Application Laid-Open No. 2001-257489 (Patent Document 2).

しかし、基板内に放熱用ヒートシンク部を設置した構造のプリント配線板を用いることは不可能ではないが、プリント配線板の厚みが増してしまい、小型化、薄型化の要請を満足させることは困難となる。また、ヒートシンクを積層させる構造でも、同様に、プリント配線板の厚みが問題となる。さらに、プリント配線板及び電子機器の小型化、薄型化に伴い、ファンなどの空冷手段を搭載することや発熱部品上に送風が流れるスペースを確保することは困難である。   However, it is not impossible to use a printed wiring board with a heat sink for heat dissipation in the board, but the thickness of the printed wiring board increases, making it difficult to satisfy the demand for miniaturization and thinning. It becomes. Similarly, the thickness of the printed wiring board becomes a problem even in a structure in which heat sinks are stacked. Furthermore, with the miniaturization and thinning of printed wiring boards and electronic devices, it is difficult to mount an air cooling means such as a fan or to secure a space for air flow on a heat-generating component.

特開２００２−２７０７４３号公報JP 2002-270743 A 特開２００１−２５７４８９号公報Japanese Patent Laid-Open No. 2001-257489

そこで、本発明は、ＣＳＰ等の半導体装置やプリント配線板の厚みを増すことなく、発熱部品の十分な放熱を行い、また半導体装置とプリント配線板とのクリアランスを均一に保持することができる半導体装置及びプリント配線板を提供することを目的とする。   Accordingly, the present invention provides a semiconductor capable of sufficiently radiating heat-generating components without increasing the thickness of a semiconductor device such as a CSP or a printed wiring board and maintaining a uniform clearance between the semiconductor device and the printed wiring board. An object is to provide a device and a printed wiring board.

上述した課題を解決するために、本発明にかかる半導体装置は、第１の半導体素子が実装された絶縁基板の該第１の半導体素子上に積層される半導体装置において、基板と、該基板の上記第１の半導体素子と対向する一面に形成され、上記第１の半導体素子の上面に当接される複数のバンプと、上記基板の他面に実装される第２の半導体素子とを有するものである。   In order to solve the above-described problems, a semiconductor device according to the present invention includes a substrate, a semiconductor device stacked on the first semiconductor element of the insulating substrate on which the first semiconductor element is mounted, and the substrate. One having a plurality of bumps formed on one surface facing the first semiconductor element and in contact with the upper surface of the first semiconductor element, and a second semiconductor element mounted on the other surface of the substrate It is.

また、本発明にかかるプリント配線板は、第１の半導体素子が実装された絶縁基板の該第１の半導体素子上に半導体装置が積層されるプリント配線板において、上記半導体装置は、基板と、該基板の上記第１の半導体素子と対向する一面に形成され、上記第１の半導体素子の上面に当接される複数のバンプと、上記基板の他面に実装される第２の半導体素子とを有するものである。   Moreover, the printed wiring board according to the present invention is a printed wiring board in which a semiconductor device is stacked on the first semiconductor element of an insulating substrate on which the first semiconductor element is mounted. The semiconductor device includes: a substrate; A plurality of bumps formed on one surface of the substrate facing the first semiconductor element, and in contact with the upper surface of the first semiconductor element; and a second semiconductor element mounted on the other surface of the substrate; It is what has.

本発明にかかる半導体装置及びプリント配線板によれば、第１の半導体素子の表面に複数のバンプが接することにより、実質的に第１の半導体素子の表面積を増加させることとなるため、バンプがヒートシンクとして機能し、第１の半導体素子の熱をより効率的に放熱させることができる。   According to the semiconductor device and the printed wiring board according to the present invention, since the plurality of bumps are in contact with the surface of the first semiconductor element, the surface area of the first semiconductor element is substantially increased. It functions as a heat sink and can dissipate the heat of the first semiconductor element more efficiently.

以下、本発明が適用された半導体装置及びプリント配線板について、図面を参照しながら詳細に説明する。本発明が適用されたプリント配線板１は、表面にＬＳＩベアチップや、ＢＧＡ、ＣＳＰといった半導体パッケージが実装されるとともに、これら半導体素子３の上にさらに半導体装置２が積層されるものである。そして本発明では、プリント配線板１に実装されたこれら半導体素子３の発熱を半導体装置２によって効率よく放熱するものである。   Hereinafter, a semiconductor device and a printed wiring board to which the present invention is applied will be described in detail with reference to the drawings. The printed wiring board 1 to which the present invention is applied has a semiconductor package such as an LSI bare chip, BGA, or CSP mounted on the surface, and a semiconductor device 2 is further stacked on the semiconductor element 3. In the present invention, heat generated by the semiconductor elements 3 mounted on the printed wiring board 1 is efficiently radiated by the semiconductor device 2.

図１に示すように、プリント配線板１は、絶縁基板４として例えばガラスエポキシ樹脂銅貼積層板等のリジット基板が用いられ、印刷やフォトエッチング等により配線パターンや半導体素子３が実装される実装部５が形成されている。実装部５には、はんだクリームが印刷された後、半導体素子３が搭載され、リフローはんだ付けされることにより実装される。また、実装部５の近傍には、半導体装置２をプリント配線板１上に積層させるはんだボール７が搭載されるランド部６が複数形成されている。   As shown in FIG. 1, the printed wiring board 1 is a mounting in which a rigid substrate such as a glass epoxy resin copper-clad laminate is used as an insulating substrate 4, and a wiring pattern or a semiconductor element 3 is mounted by printing or photoetching. Part 5 is formed. After the solder cream is printed on the mounting portion 5, the semiconductor element 3 is mounted and mounted by reflow soldering. A plurality of land portions 6 on which solder balls 7 for laminating the semiconductor device 2 on the printed wiring board 1 are mounted are formed in the vicinity of the mounting portion 5.

この実装部５に実装される半導体素子３は、上述したＬＳＩベアチップや各種半導体パッケージが用いられる。これら半導体素子３は、駆動されることにより発熱し高温となるため、安定した動作を確保し、かつ発熱によって周囲の部材に与える悪影響を抑えるために放熱を必要とする。   As the semiconductor element 3 mounted on the mounting unit 5, the LSI bare chip and various semiconductor packages described above are used. Since these semiconductor elements 3 generate heat and become high temperature when driven, they require heat radiation to ensure stable operation and to suppress adverse effects on the surrounding members due to the heat generation.

半導体素子３上に積層される半導体装置２は、インタポーザ基板８と、インタポーザ基板８の表面８ａに実装された半導体素子９と、インタポーザ基板８の下面８ｂに形成された複数のバンプ１０とを有する。インタポーザ基板８は、リジットな絶縁基板が用いられ、表面８ａには導電層を解して半導体素子９が実装され、下面８ｂにも導電層を解してバンプ１０が複数形成されている。   The semiconductor device 2 stacked on the semiconductor element 3 includes an interposer substrate 8, a semiconductor element 9 mounted on the surface 8 a of the interposer substrate 8, and a plurality of bumps 10 formed on the lower surface 8 b of the interposer substrate 8. . As the interposer substrate 8, a rigid insulating substrate is used, and a semiconductor element 9 is mounted on the front surface 8a by breaking the conductive layer, and a plurality of bumps 10 are formed on the lower surface 8b by breaking the conductive layer.

バンプ１０は、金属突起からなり、インタポーザ基板８の下面８ｂに形成されている。このバンプ１０は、導電層１１上に形成されたプリント配線板１に実装された半導体素子３の表面３ａに直に接触することにより、半導体素子３に発生した熱を放熱させるものである。すなわち、バンプ１０は、半導体装置２がプリント配線板１の半導体素子３上に積層されることにより、半導体素子３の表面３ａに接触され、実質的に半導体素子３の表面積を増加させることとなるため、ヒートシンクとして機能し、半導体素子３の熱をより効率的に放熱させることができる。   The bumps 10 are made of metal protrusions and are formed on the lower surface 8 b of the interposer substrate 8. The bumps 10 radiate heat generated in the semiconductor element 3 by directly contacting the surface 3 a of the semiconductor element 3 mounted on the printed wiring board 1 formed on the conductive layer 11. In other words, the bump 10 is brought into contact with the surface 3 a of the semiconductor element 3 when the semiconductor device 2 is laminated on the semiconductor element 3 of the printed wiring board 1, thereby substantially increasing the surface area of the semiconductor element 3. Therefore, it functions as a heat sink, and the heat of the semiconductor element 3 can be radiated more efficiently.

したがって、かかる半導体装置２が積層されたプリント配線板は、半導体装置２の積層時におけるリフロー加熱による半導体素子３の温度上昇や、半導体素子３の駆動時における過剰な温度上昇を抑えることができ、半導体装置２の熱によるはんだボール７を介したプリント配線板１と半導体装置２との接続不良を防止し、また半導体装置２のインタポーザ基板８がガラス転移温度まで上昇することによる反りの発生を防止することができる。したがって、プリント配線板１は、半導体装置２とのクリアランスも均一に保持することができる。さらに、プリント配線板１は、半導体素子３の熱を配線パターンを通じて放熱するものではないため、熱による伝達特性等の影響を抑えることができる。   Therefore, the printed wiring board on which the semiconductor device 2 is laminated can suppress an increase in the temperature of the semiconductor element 3 due to reflow heating when the semiconductor device 2 is laminated, and an excessive temperature rise when the semiconductor element 3 is driven. Connection failure between the printed wiring board 1 and the semiconductor device 2 via the solder balls 7 due to heat of the semiconductor device 2 is prevented, and warpage due to the interposer substrate 8 of the semiconductor device 2 rising to the glass transition temperature is prevented. can do. Therefore, the printed wiring board 1 can maintain a uniform clearance from the semiconductor device 2. Furthermore, since the printed wiring board 1 does not dissipate the heat of the semiconductor element 3 through the wiring pattern, the influence of heat transfer characteristics and the like can be suppressed.

このような半導体装置２は、以下のように形成される。先ず、ガラスエポキシ樹脂銅貼積層板等のリジットな基板からなるインタポーザ基板８に配線層を形成する。配線層は、内層及び外層パターンを印刷やフォトリソグラフィー、メッキ等の公知の技術を用いて形成され、また設計に応じて複数の配線層が積層されてなる。これにより、インタポーザ基板８は、表面に半導体素子９が実装される実装部１２が形成され、下面８ｂにバンプ１０が形成される導電層１１及びはんだボール７と接続されるランド部１３が形成される。   Such a semiconductor device 2 is formed as follows. First, a wiring layer is formed on the interposer substrate 8 made of a rigid substrate such as a glass epoxy resin copper-clad laminate. The wiring layer is formed by using a known technique such as printing, photolithography, or plating on the inner layer and outer layer patterns, and a plurality of wiring layers are laminated according to the design. Thereby, the interposer substrate 8 has a mounting portion 12 on which the semiconductor element 9 is mounted on the surface, and a conductive layer 11 on which the bumps 10 are formed and a land portion 13 connected to the solder balls 7 on the lower surface 8b. The

次いで、この導電層１１上に、フォトリソグラフィー技術によりバンプ１０の形成パターンが形成されたレジストを貼り付け、導電性ペーストを印刷する。ここで、導電性ペーストには、銀ペーストや、銅ペースト、カーボンペースト等が用いられる。次いで、ウェットバック法で導電性ペーストを加熱溶融させることによりバンプ１０が形成された後、レジストを剥離する。   Next, a resist on which the formation pattern of the bumps 10 is formed by photolithography is pasted on the conductive layer 11, and a conductive paste is printed. Here, a silver paste, a copper paste, a carbon paste, or the like is used as the conductive paste. Next, after the bumps 10 are formed by heating and melting the conductive paste by a wet back method, the resist is peeled off.

なお、バンプ１０は、バンプ１０の形成パターンを有するメタルスクリーン板を導電層１１上に当てて導電性ペーストを印刷し、加熱溶融させて形成するようにしてもよい。また、バンプ１０は、導電層１１上にパターニングされたレジストを貼着した後、メッキ法により、銅メッキや金メッキ、銀メッキ等の金属メッキを析出させ、リフローによって形成させてもよい。さらに、バンプ１０として金スタッドバンプを用いる場合には、Ａｕワイヤーを導電層１１上に溶接し切断して形成する。また、バンプ１０のサイズや形成エリア、密度等は、半導体素子３の種類や大きさ、放熱効率等を考慮してケースバイケースに定められる。なおバンプ１０を高密度に連続して形成させることにより、半導体装置２は、剛性を高めることができる。   The bump 10 may be formed by applying a metal screen plate having a bump 10 formation pattern on the conductive layer 11, printing a conductive paste, and heating and melting the paste. The bumps 10 may be formed by reflow after depositing a patterned resist on the conductive layer 11 and then depositing metal plating such as copper plating, gold plating, or silver plating by a plating method. Further, when a gold stud bump is used as the bump 10, an Au wire is welded and cut on the conductive layer 11. In addition, the size, formation area, density, and the like of the bump 10 are determined on a case-by-case basis in consideration of the type and size of the semiconductor element 3, the heat dissipation efficiency, and the like. In addition, the semiconductor device 2 can increase rigidity by continuously forming the bumps 10 at a high density.

その後、インタポーザ基板８は、表面８ａに形成された実装部１２にはんだクリームが印刷され、半導体素子９が実装される。そして半導体素子９が、表面８ａに形成された外層パターンと接続された後、パッケージングされることにより半導体装置２が完成する。   Thereafter, the solder paste is printed on the mounting portion 12 formed on the surface 8a of the interposer substrate 8, and the semiconductor element 9 is mounted. Then, after the semiconductor element 9 is connected to the outer layer pattern formed on the surface 8a, the semiconductor device 2 is completed by packaging.

また、プリント配線板１は、ガラスエポキシ樹脂銅貼積層板等のリジットな基板からなる絶縁基板４に配線層が形成される。配線層は、内層及び外層パターンをスクリーン印刷やフォトリソグラフィー、メッキ等の公知の技術を用いて形成され、また設計に応じて複数の絶縁基板が積層され配線層が多層化される。これにより絶縁基板の最外層には、半導体素子３が実装される実装部５と、はんだボール７が実装されるランド部６が形成される。そして、実装部５及びランド部６にはんだクリームが塗布され、それぞれ半導体素子３及びはんだボール７がリフローはんだ付けにより実装される。   In the printed wiring board 1, a wiring layer is formed on an insulating substrate 4 made of a rigid substrate such as a glass epoxy resin copper-clad laminate. The wiring layer is formed by using a known technique such as screen printing, photolithography, plating, etc. for the inner layer and outer layer patterns, and a plurality of insulating substrates are laminated according to the design to make the wiring layer multilayer. As a result, a mounting portion 5 on which the semiconductor element 3 is mounted and a land portion 6 on which the solder ball 7 is mounted are formed on the outermost layer of the insulating substrate. And solder cream is apply | coated to the mounting part 5 and the land part 6, and the semiconductor element 3 and the solder ball 7 are mounted by reflow soldering, respectively.

次いで、図２に示すように、半導体素子３及びはんだボール７上に半導体装置２が積層される。このとき、半導体素子３の表面３ａにはインタポーザ基板８の下面８ａに形成されたバンプ１０が接する。また、インタポーザ基板８の下面８ｂに形成されたランド部１３には、予めはんだクリームが塗布されており、このランド部１３にはんだボール７が接する。   Next, as shown in FIG. 2, the semiconductor device 2 is stacked on the semiconductor element 3 and the solder ball 7. At this time, the bump 10 formed on the lower surface 8 a of the interposer substrate 8 contacts the surface 3 a of the semiconductor element 3. Solder cream is applied in advance to the land portion 13 formed on the lower surface 8 b of the interposer substrate 8, and the solder ball 7 contacts the land portion 13.

このように、プリント配線板１に実装された半導体素子３の表面３ａ上に、複数のバンプ１０が接して半導体装置２が積層されることにより、バンプ１０によって半導体素子３の熱を効率よく放出し、半導体素子３やプリント配線板１の加熱による半導体装置２や半導体素子３の誤動作、あるいは半導体装置２の変形を防止することができる。すなわち、半導体素子３の表面に複数のバンプ１０が接することにより、実質的に半導体素子３の表面積を増加させることとなるため、バンプ１０がヒートシンクとして機能する。したがって、半導体装置２の積層時や半導体素子３の駆動時等における半導体素子３の熱や、半導体装置２の積層時におけるリフロー加熱による熱を、より効率的に放熱させることができる。   As described above, the semiconductor device 2 is stacked on the surface 3 a of the semiconductor element 3 mounted on the printed wiring board 1 by contacting the bumps 10, so that the heat of the semiconductor element 3 is efficiently released by the bumps 10. In addition, malfunction of the semiconductor device 2 and the semiconductor element 3 due to heating of the semiconductor element 3 and the printed wiring board 1 or deformation of the semiconductor device 2 can be prevented. That is, the bumps 10 function as a heat sink because the surface area of the semiconductor element 3 is substantially increased by contacting the bumps 10 with the surface of the semiconductor element 3. Therefore, the heat of the semiconductor element 3 when the semiconductor device 2 is stacked or when the semiconductor element 3 is driven, and the heat due to reflow heating when the semiconductor device 2 is stacked can be radiated more efficiently.

したがって、プリント配線板１は、半導体素子３の異常加熱による誤動作を防止することができる。また半導体装置２は、インタポーザ基板８がガラス転移温度まで加熱されることなく、その平坦性を確保し、またプリント配線板１の絶縁基板４とのクリアランスを一定に保つことができる。さらに、プリント配線板１は、ヒートシンクを積層させ、あるいは絶縁基板内に形成するものではないため、全体の厚みを抑えつつ、放熱構造を有し、かつ半導体素子の高密度化を図ることができる。   Therefore, the printed wiring board 1 can prevent malfunction due to abnormal heating of the semiconductor element 3. Further, the semiconductor device 2 can ensure the flatness of the interposer substrate 8 without being heated to the glass transition temperature, and can keep the clearance of the printed wiring board 1 from the insulating substrate 4 constant. Furthermore, since the printed wiring board 1 is not formed by laminating heat sinks or being formed in an insulating substrate, the printed wiring board 1 has a heat dissipation structure and can increase the density of semiconductor elements while suppressing the overall thickness. .

また、半導体装置２は、図３に示すように、バンプ１０とインタポーザ基板８に形成された導電層１４とをバイア１５（図３（ａ））やメッキスルーホール１６（図３（ｂ））によって接続させることにより、より放熱効果を高めることができる。導電層１４は、インタポーザ基板８の表面８ａや内部に形成され、バイア１５やメッキスルーホール１６を介してバンプ１０に伝達された半導体素子３の熱が伝達される。したがって、かかる構成を備えることにより、プリント配線板１は、バンプ１０以外にも放熱の経路を増やすことができることから、より放熱効果を高めることができる。   Further, as shown in FIG. 3, the semiconductor device 2 connects the bumps 10 and the conductive layer 14 formed on the interposer substrate 8 with vias 15 (FIG. 3A) and plated through holes 16 (FIG. 3B). By making the connection, the heat dissipation effect can be further enhanced. The conductive layer 14 is formed on or inside the surface 8 a of the interposer substrate 8, and the heat of the semiconductor element 3 transmitted to the bumps 10 through the vias 15 and the plated through holes 16 is transmitted. Therefore, by providing such a configuration, the printed wiring board 1 can increase the heat dissipation path in addition to the bumps 10, and thus can further enhance the heat dissipation effect.

本発明が適用されたプリント配線板を示す断面図である。It is sectional drawing which shows the printed wiring board to which this invention was applied. 本発明が適用された半導体装置及びプリント配線板を示す断面図である。It is sectional drawing which shows the semiconductor device and printed wiring board to which this invention was applied. 半導体装置の他の例を示す断面図である。It is sectional drawing which shows the other example of a semiconductor device. 従来のプリント配線板を示す断面図である。It is sectional drawing which shows the conventional printed wiring board. 反りが発生した従来のプリント配線板を示す断面図である。It is sectional drawing which shows the conventional printed wiring board in which curvature generate | occur | produced.

符号の説明Explanation of symbols

１ プリント配線板、２ 半導体装置、３ 半導体素子、４ 絶縁基板、５ 実装部、６ ランド部、７ はんだボール、８ インタポーザ基板、９ 半導体素子、１０ バンプ、１１ 導電層、１２ 実装部、１３ ランド部 DESCRIPTION OF SYMBOLS 1 Printed wiring board, 2 Semiconductor device, 3 Semiconductor element, 4 Insulating board, 5 Mounting part, 6 Land part, 7 Solder ball, 8 Interposer board, 9 Semiconductor element, 10 Bump, 11 Conductive layer, 12 Mounting part, 13 Land Part

Claims (4)

第１の半導体素子が実装された絶縁基板の該第１の半導体素子上に積層される半導体装置において、
基板と、該基板の上記第１の半導体素子と対向する一面に形成され、上記第１の半導体素子の上面に当接される複数のバンプと、上記基板の他面に実装される第２の半導体素子とを有する半導体装置。 In the semiconductor device stacked on the first semiconductor element of the insulating substrate on which the first semiconductor element is mounted,
A substrate, a plurality of bumps formed on one surface of the substrate facing the first semiconductor element, and in contact with an upper surface of the first semiconductor element; and a second mounted on the other surface of the substrate. A semiconductor device having a semiconductor element. 上記バンプは、上記基板に設けられたビアにより、該基板に形成された他の導電層と接続されていることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the bump is connected to another conductive layer formed on the substrate by a via provided in the substrate. 上記バンプは、金属メッキ、導電ペースト印刷あるいはスタッドバンプ工法のいずれか一つの方法により形成されることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the bump is formed by any one of metal plating, conductive paste printing, or stud bump method. 第１の半導体素子が実装された絶縁基板の該第１の半導体素子上に半導体装置が積層されるプリント配線板において、
上記半導体装置は、基板と、該基板の上記第１の半導体素子と対向する一面に形成され、上記第１の半導体素子の上面に当接される複数のバンプと、上記基板の他面に実装される第２の半導体素子とを有するプリント配線板。 In a printed wiring board in which a semiconductor device is stacked on the first semiconductor element of the insulating substrate on which the first semiconductor element is mounted,
The semiconductor device is mounted on a substrate, a plurality of bumps formed on one surface of the substrate facing the first semiconductor element, and in contact with the upper surface of the first semiconductor element, and on the other surface of the substrate. Printed circuit board having a second semiconductor element.
JP2005329245A 2005-11-14 2005-11-14 Semiconductor device and printed wiring board employing it Withdrawn JP2007141887A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009054684A (en) * 2007-08-24 2009-03-12 Powertech Technology Inc Semiconductor pop device
JP2013042025A (en) * 2011-08-18 2013-02-28 Fujitsu Semiconductor Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009054684A (en) * 2007-08-24 2009-03-12 Powertech Technology Inc Semiconductor pop device
JP2013042025A (en) * 2011-08-18 2013-02-28 Fujitsu Semiconductor Ltd Semiconductor device

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