JP5441216B2 - 半導体装置及びデータ処理システム - Google Patents

半導体装置及びデータ処理システム Download PDF

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Publication number
JP5441216B2
JP5441216B2 JP2010038857A JP2010038857A JP5441216B2 JP 5441216 B2 JP5441216 B2 JP 5441216B2 JP 2010038857 A JP2010038857 A JP 2010038857A JP 2010038857 A JP2010038857 A JP 2010038857A JP 5441216 B2 JP5441216 B2 JP 5441216B2
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Japan
Prior art keywords
address
input
information
terminal
external
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Expired - Fee Related
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JP2010038857A
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English (en)
Japanese (ja)
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JP2011175445A5 (enExample
JP2011175445A (ja
Inventor
政明 平野
久仁彦 西山
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Renesas Electronics Corp
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Renesas Electronics Corp
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Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2010038857A priority Critical patent/JP5441216B2/ja
Priority to US13/033,641 priority patent/US8291124B2/en
Publication of JP2011175445A publication Critical patent/JP2011175445A/ja
Priority to US13/618,369 priority patent/US8543735B2/en
Publication of JP2011175445A5 publication Critical patent/JP2011175445A5/ja
Priority to US14/011,336 priority patent/US9298657B2/en
Application granted granted Critical
Publication of JP5441216B2 publication Critical patent/JP5441216B2/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Dram (AREA)
JP2010038857A 2010-02-24 2010-02-24 半導体装置及びデータ処理システム Expired - Fee Related JP5441216B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2010038857A JP5441216B2 (ja) 2010-02-24 2010-02-24 半導体装置及びデータ処理システム
US13/033,641 US8291124B2 (en) 2010-02-24 2011-02-24 Semiconductor device and data processing system having a reduced number of terminals allocated for externally accessed address
US13/618,369 US8543735B2 (en) 2010-02-24 2012-09-14 Semiconductor device and data processing system having reduced number of terminals allocated for externally accessed address
US14/011,336 US9298657B2 (en) 2010-02-24 2013-08-27 Semiconductor device and data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010038857A JP5441216B2 (ja) 2010-02-24 2010-02-24 半導体装置及びデータ処理システム

Publications (3)

Publication Number Publication Date
JP2011175445A JP2011175445A (ja) 2011-09-08
JP2011175445A5 JP2011175445A5 (enExample) 2012-09-20
JP5441216B2 true JP5441216B2 (ja) 2014-03-12

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JP2010038857A Expired - Fee Related JP5441216B2 (ja) 2010-02-24 2010-02-24 半導体装置及びデータ処理システム

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US (3) US8291124B2 (enExample)
JP (1) JP5441216B2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6294732B2 (ja) * 2014-03-31 2018-03-14 株式会社メガチップス データ転送制御装置及びメモリ内蔵装置
JP6517549B2 (ja) * 2015-03-13 2019-05-22 東芝メモリ株式会社 メモリコントローラ、記憶装置、データ転送システム、データ転送方法、及びデータ転送プログラム
US20240020787A1 (en) * 2020-11-12 2024-01-18 Sony Semiconductor Solutions Corporation Imaging element, imaging method, imaging device, and image processing system

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55108052A (en) * 1979-02-09 1980-08-19 Usac Electronics Ind Co Ltd Data processing system
US4754435A (en) 1985-02-14 1988-06-28 Nec Corporation Semiconductor device having a memory circuit
JPH06251168A (ja) * 1993-03-01 1994-09-09 Oki Lsi Tekunoroji Kansai:Kk Ｅｐｒｏｍ内蔵マイコンのアドレス生成回路
US20020116595A1 (en) * 1996-01-11 2002-08-22 Morton Steven G. Digital signal processor integrated circuit
EP1122688A1 (en) * 2000-02-04 2001-08-08 Texas Instruments Incorporated Data processing apparatus and method
US6785781B2 (en) * 2000-04-20 2004-08-31 International Business Machines Corporation Read/write alignment scheme for port reduction of multi-port SRAM cells
DE60132817T2 (de) 2001-01-31 2009-02-05 Hitachi, Ltd. Datenverarbeitungssystem und datenprozessor
US20040193835A1 (en) * 2003-03-31 2004-09-30 Patrick Devaney Table lookup instruction for processors using tables in local memory
DE10355583A1 (de) * 2003-11-28 2005-07-07 Advanced Micro Devices, Inc., Sunnyvale Gemeinsame Nutzung eines Speichers in einer Zentralsteuerung
US7230876B2 (en) * 2005-02-14 2007-06-12 Qualcomm Incorporated Register read for volatile memory
US7613060B2 (en) * 2007-05-21 2009-11-03 Micron Technology, Inc. Methods, circuits, and systems to select memory regions
US8850103B2 (en) * 2009-08-28 2014-09-30 Microsoft Corporation Interruptible NAND flash memory

Also Published As

Publication number Publication date
US20130073831A1 (en) 2013-03-21
US20130346634A1 (en) 2013-12-26
JP2011175445A (ja) 2011-09-08
US8543735B2 (en) 2013-09-24
US20110208878A1 (en) 2011-08-25
US8291124B2 (en) 2012-10-16
US9298657B2 (en) 2016-03-29

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