JP5434547B2 - Method for forming a plurality of patterns using a reticle - Google Patents

Description

The present invention relates to patterning of semiconductor lithography. In particular, the present invention relates to a pattern forming method for forming a plurality of identical patterns on a silicon wafer.

In the industrial field such as semiconductors, a pattern transfer method using lithography is used as a mass production technique. This is an excellent technique for forming many identical patterns on a wafer. As a lithography pattern transfer method, there is a method of performing pattern formation using a stepper. A reticle pattern is projected onto a wafer mainly through a reticle in which a pattern is formed of a metal such as Cr on transparent quartz using i-line or g-line (ultraviolet light). Thus, a pattern is formed on the wafer by photoreacting the projected portion of the resist.

At this time, in order to form two or more patterns, a plurality of reticles are prepared, and the number of exposure processes corresponding to the type of pattern is performed. In this method, as the number of patterns increases, the number of reticles and the number of stepper processes increase accordingly. An increase in the number of reticles and the number of stepper treatments complicates the manufacturing process and causes an increase in manufacturing cost.

In order to suppress such an increase in the number of reticles or the number of stepper processes, for example, Patent Document 1 discloses a technique for exposing a desired chip pattern to a reticle having a plurality of chip patterns using an aperture aperture. It is disclosed. In this method, there is one chip pattern in one exposure region, and one chip pattern is formed by one exposure. Patent Document 2 discloses a technique in which a plurality of types of patterns are formed on a reticle and the illumination range of the reticle is changed using a blind to perform screen composition. However, since this method is a method for obtaining a driving offset amount of a reticle blind or the like, it is only necessary to form a pattern one after another on the entire substrate, and another pattern is reexposed on the exposed chip pattern area. There is no. In these methods, when forming one chip pattern by forming two or more patterns, the number of reticles and the number of stepper processes cannot be reduced.

JP-A-8-55795 JP-A-9-223653

An object of the present invention is to provide a pattern forming method and a pattern forming apparatus capable of forming a plurality of different patterns with a small number of reticles in semiconductor lithography.

According to an embodiment of the present invention, in a method of forming a chip pattern having a plurality of different patterns on a resist on a wafer, using a reticle in which the plurality of different patterns are arranged in a plurality of regions, Each having a predetermined width in a first direction and a second direction orthogonal to the first direction, including a plurality of the patterns formed linearly and intermittently in the first direction, A plurality of chip patterns formed in parallel with the first direction and the second direction, the plurality of regions having a first region and a second region different from the first region; An axis in which a cleavage plane of the wafer and a plane forming the pattern of the wafer are orthogonal to each other, the first direction or the second direction in the first region, or the first direction in the second region or Second Direction Metropolitan different way, selecting the first region from said plurality of regions, said plurality of regions other than the portion of the first region is shielded by a blind, a portion of the first region by irradiating light to the light shielding, the first pattern formed in the resist, to select the second region from said plurality of regions, said plurality of regions other than the portion of the second region by the blind Then, a pattern forming method is provided in which a second pattern is formed on the resist by irradiating a part of the second region with light.

A first region is selected from the plurality of regions, the reticle is arranged so that the alignment mark of the reticle and the alignment mark of the wafer coincide with each other, and the plurality of regions other than the first region are blinded. Shielding the light, irradiating the first region with light, forming a pattern on the resist, selecting a second region different from the first region from the plurality of regions, and aligning the alignment mark of the reticle and the The reticle is arranged so as to coincide with the alignment mark of the wafer, the plurality of regions other than the second region are shielded from light by the blind, light is irradiated to the second region, and a pattern is formed on the resist. It may be formed.

The reticle may have a plurality of the alignment marks.

A light shielding region may be formed between the first region and the second region, and the first region and the second region may be disposed on the reticle at a predetermined interval.

According to one embodiment of the present invention, in a method of forming a chip pattern having a plurality of patterns on a resist on a wafer, a reticle in which a plurality of different patterns are arranged in a plurality of regions is used, and the plurality of regions are included in the plurality of regions. Each having a predetermined width in a first direction and a second direction orthogonal to the first direction, including a plurality of the patterns formed linearly and intermittently in the first direction, A plurality of chip patterns formed in parallel with the first direction and the second direction, the plurality of regions having a first region and a second region different from the first region; An axis in which a cleavage plane of the wafer and a plane forming the pattern of the wafer are orthogonal to each other, the first direction or the second direction in the first region, or the first direction in the second region or Second direction But differently, selects the first region from said plurality of regions, said plurality of regions other than the first region is shielded by a blind, by irradiating light to the first region, the resist to form a first chip pattern patterns, select the second region from said plurality of regions, said plurality of regions other than the second region shielded by a blind, a light to said second region Is provided to form a second chip pattern pattern on the resist.

The chip pattern in the first region may coincide with a pattern obtained by rotating the chip pattern in the second region by 90 °.

According to the present invention, a plurality of different patterns can be formed with a small number of reticles in semiconductor lithography.

The schematic diagram which shows the pattern formation method of this invention which concerns on one Embodiment. It is a schematic diagram of the reticle 100 of the present invention according to an embodiment, (a) shows an overview, (b) shows an example of a pattern. The schematic diagram of the stepper 700 of this invention which concerns on one Embodiment. The schematic diagram of the positioning method of this invention which concerns on one Embodiment. It is the figure which showed the correction | amendment method of the deviation | shift of this invention which concerns on one Embodiment, (a) shows the range of deviation, (b) is a schematic diagram which shows a coping method. The schematic diagram which shows the light-shielding area | region of the reticle 300 of this invention which concerns on one Embodiment. (A) shows a conventional chip pattern arrangement, and FIG. 7 (b) is a schematic diagram showing a chip pattern arrangement of the present invention according to an embodiment. It is a schematic diagram of the reticle 100 of the present invention according to an embodiment, (a) shows an overview, (b) shows an example of a pattern. The schematic diagram explaining the method of forming the pattern of this invention which concerns on one Embodiment. The schematic diagram which shows the chip pattern arrangement | positioning of this invention which concerns on one Embodiment. The schematic diagram explaining the method of forming the pattern of this invention which concerns on one Embodiment. FIG. 10 is a schematic diagram of a projection exposure method using a conventional reticle.

Hereinafter, a method for forming a plurality of patterns and a pattern forming apparatus using a reticle according to the present invention will be described with reference to the drawings. However, the method for forming a plurality of patterns and the pattern forming apparatus using the reticle of the present invention can be implemented in many different modes, and are limited to the description of the embodiments and examples shown below. It is not something. Note that in the drawings referred to in this embodiment mode and examples, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
FIG. 12 is a schematic diagram showing a projection exposure method using a conventional reticle for forming a pattern on a wafer using a stepper. Irradiation light 951 is irradiated to one reticle 901 on which one kind of pattern is formed, and pattern 911 is projected and exposed to a silicon wafer 921 having a resist layer formed on the upper surface. In this conventional method, the number of reticles and the number of stepper processes increase in response to the type of pattern as described above.

In the field of manufacturing CPUs (Central Processing Units) and semiconductor memories, where miniaturization of products is always required, finer and more complicated pattern formation is required, and a reticle for pattern formation that meets the requirements whenever the design is changed. Is required. On the other hand, in the field of MEMS (Micro Electro Mechanical Systems), there are many cases where a simple and large pattern is formed as compared with those fields, and the size of the pattern to be formed is relatively large, such as several tens to several hundreds of μm. There are many. Further, in the field of MEMS, there is relatively little demand for constantly pursuing miniaturization, and the size of products is not miniaturized year by year as in other fields. Focusing on such differences in pattern formation requirements, a more efficient pattern formation method was studied.

FIG. 1 is a schematic view showing a method for forming a plurality of patterns according to the present invention of Embodiment 1. As shown in FIG. For example, when the chip pattern 200 is exposed to a resist on a silicon wafer, the chip pattern 200 includes a pattern 201 and a pattern 203. Therefore, a reticle on which a pattern that matches the chip pattern 200 is formed or a pattern 201 and a pattern 203 are used. Are combined with the respective formed reticles. The reticle 100 according to the present embodiment of the present embodiment has a first unit region 101 including a pattern corresponding to the pattern 201 and a second unit region 103 including a pattern corresponding to the pattern 203 in one reticle.

Here, the reticle 100 will be described in detail. 2A and 2B are schematic diagrams of a reticle 100 according to the present invention of Embodiment 1, wherein FIG. 2A is a schematic diagram, and FIG. 2B is a diagram illustrating an example of a pattern. The reticle 100 includes, for example, a first unit region 101 in which a pattern 111 is formed, a second unit region 103 in which a pattern 113 that is not related to the pattern 111 is formed, and a third unit formed by rotating the pattern 113 by 90 °. The unit region 105 and the fourth unit region 107 in which a pattern obtained by slightly moving the pattern 113 in the X-axis direction (second direction) is formed. Note that the first unit region 101, the second unit region 103, the third unit region 105, and the fourth unit region 107 shown in this embodiment are merely examples, and may have any pattern. Good.

Each unit area is shielded by the light shield 121 so that each unit area is separated. The light shield 121 is formed not only in the region of FIG. 2A but also around the pattern 111 so as to form each pattern of FIG. 2B, for example, the pattern 111 one by one. As a material of the reticle 100, transparent quartz or the like generally used for a reticle can be used. Moreover, a well-known material can be used for the light-shielding body 121, for example, chromium can be used. In the present embodiment, an example in which one reticle 100 has four unit regions has been described. However, the present invention is not limited to this. In addition, the pattern of the reticle 100 used in the present invention may be appropriately formed according to the negative resist application or the positive resist application.

When the chip pattern 200 is formed using the reticle 100, a part of the first unit area 101 of the reticle 100 including the pattern 111 corresponding to the pattern 201 is specified, and the other areas are shielded by the light shielding area 221. To expose. Subsequently, a part of the second unit area 103 including the pattern 113 corresponding to the pattern 203 may be specified, and the other areas may be exposed by being shielded by the light shielding area 223. In this way, a desired chip pattern can be formed by exposing only a part of a reticle region having a desired pattern and combining a plurality of these patterns.

FIG. 3 is a schematic view showing a stepper 700 according to the present invention of Embodiment 1. As shown in FIG. The stepper 700 includes, for example, a light source 701, an elliptical mirror 703 that is a dimming unit, a reflecting mirror 705, a wavelength selection filter 707, and a fly-eye integrator 709, a blind 711 that is an opening / closing unit, and a reflecting mirror 713 that is a light guide unit. And a lens system 715, a projection optical system 717, a stage 719 that is a position adjusting unit, and a drive control system 751.

Light emitted from the light source 701 is guided to the wavelength selection filter 707 by the elliptical mirror 703 and the reflection mirror 705, adjusted to a desired wavelength by the wavelength selection filter 707, and uniformized by the fly eye integrator 709. The uniformed light is applied to the reticle 531 by opening and closing the blind 711. When a pattern is projected and exposed to the resist 3 coated on the upper surface of the silicon wafer 1, the light is guided to the reticle 100 through the reflecting mirror 713 and the lens system 715, and the light not blocked by the reticle 100 is projected into the projection optical system. The resist 3 on the silicon wafer 1 is irradiated through 717. Thereby, the pattern formed on the reticle 100 is projected and exposed on the resist 3. The stage 719 on which the silicon wafer 1 is mounted can be moved in two horizontal directions (the X-axis direction (second direction) and the Y-axis direction (first direction) orthogonal to each other) and can be rotated in the horizontal direction. The exposure position of the silicon wafer 1 is adjusted.

For example, when the pattern 201 is exposed, the irradiation light 791 is irradiated only to a part of the plurality of patterns 111 formed in the first unit region 101 of the corresponding reticle 100. The drive control system 751 controls the position and shape of the opening by controlling the blind 711 so that the light shielding region 221 is formed on the reticle 100 as shown in FIG. In general, the blind 711 is a combination of two L-shaped light shielding plates, and the shape and size of the rectangular opening are changed by moving the light shielding plate in the horizontal direction. The blind 711 of the present invention according to this embodiment can irradiate the irradiation light 791 with a desired shape and size onto a desired region of the reticle 100 by the drive control system 751. The blind 711 is not limited to the combination of two L-shaped light shielding plates, and other combinations of the shape and the number of light shielding plates may be used.

As described above, according to the method for forming a plurality of patterns and the pattern forming apparatus of the present invention according to the present embodiment, using a single reticle in which a plurality of different patterns are formed in a plurality of regions, only a desired region is used. By irradiating irradiation light and combining a plurality of different patterns, there is an excellent effect that a desired pattern can be formed on the resist on the silicon wafer. The method and apparatus for forming a plurality of patterns according to the present invention can impart versatility to a reticle by forming a pattern as a template, and can reduce the number of reticles necessary for forming a resist pattern. Thereby, it is possible to reduce the time and cost required for manufacturing the reticle. In particular, it is effective for speeding up and cost reduction at the prototype stage of the product. Further, the multiple pattern forming method and pattern forming apparatus of the present invention according to the present embodiment are particularly effective in the field of high-mix low-volume production such as MEMS because it is not necessary to prepare a reticle for each product to be manufactured. It is.

(Embodiment 2)
In the second embodiment, means for improving the accuracy of the multiple pattern forming method described in the first embodiment will be described. FIG. 4 is a schematic diagram showing an alignment method when forming a pattern according to the present invention according to the present embodiment. An alignment mark 31 is attached to the silicon wafer 1 coated with a resist, and an alignment mark 331 is also attached to the reticle 300.

By aligning the alignment mark 31 and the alignment mark 331 when forming a pattern, the reticle 300 and the silicon wafer 1 can be accurately aligned at an arbitrary position. A desired pattern can be formed at an arbitrary position on the silicon wafer 1 by designating and exposing a region having a desired pattern on the reticle 300 after alignment.

By the way, when a general stepper designates an irradiation area of a reticle, a blind opening area may be displaced. FIG. 5A is a diagram showing a shift area. When a blind is opened so as to irradiate light to an arbitrary area of the reticle 300, the area 351 becomes a shift range and cannot be used for pattern formation. When one type of pattern is formed with one reticle, such a shift is unlikely to be a problem, but in the method for forming a plurality of patterns according to the present invention, it is a problem because a fine irradiation area is specified.

As a countermeasure for such a shift, as shown in FIG. 5B, a pattern is formed on the reticle 300 so that the space between the pattern area 301 and the pattern area 303 is larger than the shift area. FIG. 6 is a schematic diagram showing the light shielding region 321 of the reticle 300 according to the present embodiment. When irradiating the pattern area 301 with light, a shift may occur such that the blind area opens outside the opening area 341. For this reason, the light shielding region 321 may be formed outside the opening region 341. The light shielding region 321 may be formed outside the pattern region 301 with a width of 200 μm or more. The light shielding region 321 can be made of commonly used chromium.

As described above, according to the means for improving the accuracy of the method for forming a plurality of patterns of the present invention according to the present embodiment, it is possible to accurately expose a resist in a desired region of a reticle onto a resist. As a result, a multi-pattern forming method and a pattern forming apparatus having both high versatility and high accuracy are provided.

(Embodiment 3)
In the first and second embodiments, the method for forming a plurality of patterns has been described in detail. In the third embodiment, an example in which the above pattern formation is applied to a product will be described. FIG. 7A shows a conventional chip pattern arrangement, and FIG. 7B is a schematic diagram showing a chip pattern arrangement according to the pattern forming method of the present invention according to the third embodiment.

In semiconductor lithography, in order to obtain desired electrical characteristics, a pattern is generally formed so that the plane orientation is aligned. For example, when a linear pattern 811 as shown in FIG. 7A is continuously formed on a (100) plane silicon wafer, and such a chip pattern 801 is continuously formed in the same direction. When the pattern coincides with the cleavage plane 850 having the <110> plane orientation, the silicon wafer is likely to break along the pattern. The alternate long and short dash line indicates the direction of the pattern 811 that coincides with the cleavage plane 830 at that time.

In particular, in the bulk MEMS field, a plurality of identical patterns having deep holes and grooves are often formed in a silicon wafer as compared with a semiconductor element such as a memory. Since the depths of the holes and grooves to be formed are several tens of μm to several hundreds of μm, breakage tends to occur along the open surface of the silicon wafer. For this reason, when forming the same pattern in multiple numbers on a silicon wafer, the pattern formation method which does not raise | generate a fracture | rupture is desired.

On the other hand, in bulk MEMS, it is not always necessary to align the sides. Therefore, the present inventors have deliberately tried to shift the plane orientation of a silicon wafer which is not normally performed in pattern formation by semiconductor lithography. As shown in FIG. 7B, the chip pattern arrangement 400 in which the chip pattern 403 and the chip pattern 405 are formed in a checkered pattern is effective as a method for preventing such breakage of the silicon wafer.

More specifically, the chip pattern arrangement 400 includes, for example, a chip pattern 403 including a pattern in which patterns 411 etched in a first direction 411a and a second direction 411b with a predetermined depth are formed in a straight line. The chip pattern 403 obtained by rotating the chip pattern 403 by 90 ° is repeatedly formed in the first direction 411a and the second direction 411b.

Examples of the pattern 411 include a comb-tooth portion having a comb-tooth structure, a plurality of channels arranged in one direction, and a beam portion of a sensing device. The silicon wafer may be a bare silicon wafer or an SOI (Silicon on Insulator) substrate.

At this time, a line 433 virtually connecting the pattern 411 formed intermittently in the chip pattern 403 as a straight line coincides with the first direction 411a. Further, a line 435 obtained by virtually connecting the intermittently formed pattern 411 in the chip pattern 405 as a straight line does not coincide with the first direction 411a, and forms an angle of 90 °. In the present embodiment, as shown in FIG. 7, the chip pattern 405 adjacent to the chip pattern 403 is arranged by rotating the chip pattern 403 by 90 °. In such a checkered pattern arrangement, the lines 433 and 435 are orthogonal to each other, so that no virtual line that continuously coincides with the axis 850 is generated over the entire silicon wafer. Therefore, the wafer is less likely to break.

FIG. 8 shows a pattern of the reticle 100 in the present embodiment. In the second unit region 103 of the reticle 100, a pattern in which a pattern 113 having a predetermined width in the first direction 113a and the second direction 113b is intermittently formed in a straight line is formed in the first direction 111a and the second direction. It is repeatedly formed in the direction 111b. In the third unit region 105, a pattern obtained by intermittently forming a pattern obtained by rotating the pattern 113 by 90 ° linearly in the second direction 113b is repeatedly formed in the first direction 111a and the second direction 111b. Yes. Further, in the fourth unit region 107, a pattern obtained by moving the pattern 113 by a predetermined distance dX in the second direction is intermittently formed linearly in the first direction 113a, and the pattern is formed in the first direction 111a and the first direction. It is formed repeatedly in two directions 111b.

A line 133 that virtually connects the pattern 113 formed intermittently in the chip pattern 103 as a straight line coincides with the first direction 113a. In addition, a line 135 that virtually connects the pattern 113 that is intermittently formed in the chip pattern 105 as a straight line does not coincide with the first direction 113a, and forms an angle of 90 °. Further, a line 137 that virtually connects the intermittently formed pattern 113 in the chip pattern 107 as a straight line coincides with the first direction 113a, but the arrangement of the pattern 113 moves a predetermined distance dX in the second direction. Therefore, there is a slight deviation in the second direction from the line 133 that virtually connects the patterns 113 of the chip pattern 103 as straight lines.

In the present embodiment, in order to form a chip pattern arrangement 400 as shown in FIG. 7B, the second unit region 103 and the third unit region 105 of the reticle 100 are used and arranged adjacent to each other. By irradiating the reticle on the wafer as described above, the axis in which the cleaved surface of the wafer and the surface on which the pattern of the wafer is formed are orthogonal to each other in the first direction in the first region of the wafer or in the adjacent second region A plurality of chip patterns can be formed so as to be different from the first direction.

FIG. 9 is a schematic diagram for explaining a method of forming the above-described pattern. First, as shown in the upper diagram of FIG. 9A, a chip pattern arrangement 410 that is a part of the chip pattern arrangement 400 is formed. As shown in the lower diagram of FIG. 9A, exposure is performed by shielding the light shielding area 421 with a blind so that only the second unit area 103 on which the pattern 113 of the reticle 100 corresponding to the chip pattern 403 is formed is irradiated with light. . Next, in order to form the chip pattern 405 shown in the upper part of FIG. 9B, as shown in the lower part of FIG. 9B, the third unit region 105 in which a pattern obtained by rotating the pattern 113 of the reticle 100 by 90 ° is formed. In order to irradiate only the light, the light shielding region 423 is shielded by the blind and exposed. In this way, the chip pattern arrangement 400 can be formed with only one reticle by adjusting the blind so that only a desired region is sequentially opened.

Further, although an example in which one region is selected and irradiated in order to form one chip pattern has been described, the method for forming a plurality of patterns of the present embodiment is not limited to this, and one region is formed. One chip pattern may be formed by selecting and irradiating a partial region in which a plurality of patterns are formed.

As described above, according to the method for forming a plurality of patterns of the present invention according to the present embodiment, by using a plurality of patterns formed on one reticle, by combining and exposing patterns in a desired region. Thus, it becomes possible to form a pattern that is difficult to break on the wafer.

(Embodiment 4)
In the third embodiment, the method of forming a pattern such as a checkered pattern is described in order to prevent the silicon wafer from being broken by the coincidence with the cleavage plane of the continuous pattern. However, in this embodiment, another pattern formation is performed. A method will be described.

FIG. 10 is a schematic diagram showing a chip pattern arrangement 500 of the present invention according to the fourth embodiment. In the chip pattern arrangement 500, for example, a chip pattern 503 including a pattern in which a pattern 511 etched in a first direction 511a and a second direction 511b with a predetermined depth is formed linearly, and a chip pattern Chip patterns 507 obtained by shifting 503 in the second direction 511b by the distance dX are alternately formed in the first direction 511a. In such an arrangement, since the virtual line 533 in the pattern direction of the pattern 503 and the virtual line 537 in the pattern direction of the pattern 507 do not match, the continuity of the pattern over the entire silicon wafer is lost. The fracture due to the coincidence with the cleaved surface axis 850 is less likely to occur.

FIG. 11 is a schematic diagram for explaining a method of forming the above-described pattern. As an example using the reticle 100 described in the third embodiment, first, as shown in FIG. 11A, light is applied only to the second unit region 103 in which the pattern 113 of the reticle 100 corresponding to the pattern 503 is formed. In order to irradiate the light, the light shielding region 521 is shielded from light by the blind and exposed. Next, as shown in FIG. 11B, only the fourth unit region 107 on which the pattern obtained by moving the pattern 113 of the reticle 100 by a predetermined distance dX in the second direction to form the pattern 507 is formed. In order to irradiate light, the light shielding region 523 is shielded by the blind and exposed. In this way, by adjusting the blind so that only a desired region is sequentially opened, the chip pattern arrangement 500 can be formed with only one reticle.

Further, although an example in which one region is selected and irradiated in order to form one chip pattern has been described, the method for forming a plurality of patterns of the present embodiment is not limited to this, and one region is formed. One chip pattern may be formed by selecting and irradiating a partial region in which a plurality of patterns are formed.

As described above, according to the method for forming a plurality of patterns of the present invention according to the present embodiment, by using a plurality of patterns formed on one reticle, by combining and exposing patterns in a desired region. Thus, it becomes possible to form a pattern that is difficult to break on the wafer.

Reference Signs List 1 silicon wafer 3 resist 31 alignment mark 100 reticle 101 first unit area 103 second unit area 105 third unit area 107 fourth unit area 111 pattern 113 pattern 113a first direction 113b second direction 121 light shield 133 virtual Straight line 135 Virtual line 137 Virtual line 200 Chip pattern 201 Pattern 203 Pattern 221 Shading area 223 Shading area 300 Reticle 301 Pattern area 303 Pattern area 331 Alignment mark 351 Deviation range 400 Chip pattern arrangement 403 Pattern 405 Pattern 410 One Chip pattern 411 pattern 411a first direction 411b second direction 421 light shielding area 423 light shielding area 433 virtual line 435 virtual line 500 chip pattern arrangement 50 3 pattern 507 pattern 511 pattern 511a first direction 511b second direction 521 light shielding area 523 light shielding area 533 virtual line 537 virtual line 700 stepper 701 light source 703 elliptical mirror 705 reflecting mirror 707 wavelength selection filter 709 fly eye integrator 711 Blind 713 Reflector 715 Lens system 717 Projection optical system 719 Stage 751 Drive control system 791 Irradiation light 800 Chip pattern group 801 Chip pattern 811 Pattern 830 Virtual line 850 Cleaved surface 901 Reticle 911 Chip pattern 921 Silicon wafer 951 Irradiation light

Claims (6)

In a method of forming a chip pattern having a plurality of different patterns on a resist on a wafer,
Using a reticle in which the plurality of different patterns are arranged in a plurality of regions,
The plurality of regions each have a predetermined width in a first direction and a second direction orthogonal to the first direction, and are formed in a straight line and intermittently in the first direction. A plurality of chip patterns formed in parallel to the first direction and the second direction,
The plurality of regions include a first region and a second region different from the first region,
The axis at which the cleavage plane of the wafer and the plane forming the pattern of the wafer are orthogonal to each other, the first direction or the second direction in the first region, or the first direction in the second region Or so that the second direction is different,
Wherein said plurality of regions a first select an area, the plurality of areas other than the part of the first region is shielded by a blind, by radiating light to a portion of said first region, said Forming a first pattern on the resist;
Wherein said plurality of regions a second region is selected, the plurality of areas other than the part of the second region is shielded by a blind, by radiating light to a portion of the second region, the A pattern forming method comprising forming a second pattern on a resist. A first region is selected from the plurality of regions, the reticle is arranged so that the alignment mark of the reticle and the alignment mark of the wafer coincide with each other, and the plurality of regions other than the first region are blinded. Shielding the light, irradiating the first region with light, forming a pattern on the resist,
A second region different from the first region is selected from the plurality of regions, the reticle is arranged so that the alignment mark of the reticle and the alignment mark of the wafer coincide with each other, and other than the second region The pattern forming method according to claim 1, wherein the plurality of regions are shielded by a blind, and the second region is irradiated with light to form a pattern on the resist. The pattern forming method according to claim 2, wherein the reticle has a plurality of the alignment marks. A light-shielding region is formed between the first region and the second region, and the first region and the second region are arranged on the reticle at a predetermined interval. Item 4. The pattern forming method according to any one of Items 1 to 3. In a method of forming a chip pattern having a plurality of patterns on a resist on a wafer,
Using a reticle with multiple different patterns in multiple areas,
The plurality of regions each have a predetermined width in a first direction and a second direction orthogonal to the first direction, and are formed in a straight line and intermittently in the first direction. A plurality of chip patterns formed in parallel to the first direction and the second direction,
The plurality of regions include a first region and a second region different from the first region,
The axis at which the cleavage plane of the wafer and the plane forming the pattern of the wafer are orthogonal to each other, the first direction or the second direction in the first region, or the first direction in the second region or the second and the direction, differently, selecting the first region from said plurality of regions, said plurality of regions other than the first region is shielded by a blind, a light to the first region , To form a first chip pattern pattern on the resist,
Wherein said plurality of regions a second region is selected, the plurality of areas other than the second region shielded by a blind, by irradiating light to the second region, the second chip to the resist A pattern forming method comprising forming a pattern pattern. Wherein the chip pattern of the first region, the pattern forming method according to claim 1 or 5 coincides with the second of the chip pattern is rotated 90 ° pattern area.

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