JP5433156B2 - Memory control circuit - Google Patents

Description

  The present invention relates to a memory control circuit.

In recent electronic devices equipped with a CPU (Central Processing Unit) and a memory, a memory control circuit may be provided between the CPU and the memory so that the CPU can smoothly access the memory (for example, Patent Document 1). Or refer to Patent Document 2). Access to the memory is generally performed in synchronization with a clock signal output from the memory control circuit to the memory. Therefore, it is possible to increase the access speed by increasing the frequency of the clock signal when the memory control circuit accesses the memory.
JP 2007-66118 A JP 2007-305073 A

  By the way, in a general electronic device, when a large-capacity memory is used, the memory and the memory control circuit are often integrated separately. For this reason, it is difficult to increase the frequency of the clock signal when accessing the memory due to the influence of the parasitic capacitance between the terminals generated when the memory and the memory control circuit are connected. Further, in order to increase the access speed from the memory control circuit to the memory without increasing the frequency of the clock signal, for example, parallel access instead of serial access may be performed. However, in order for the memory control circuit to perform parallel access, the number of terminals required for the memory and each integrated circuit of the memory control circuit is increased as compared with the case of serial access. The problem arises that becomes large.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a memory control circuit capable of speeding up access to a memory and suppressing an increase in mounting area.

In order to achieve the above object, the memory control circuit of the present invention is capable of serial access and receives first access data for accessing a memory that can be accessed in parallel using a terminal used for serial access. A serial data processing circuit for outputting the first access data serially; a second access data for accessing the memory; a parallel data processing circuit for outputting the second access data in parallel; When the first instruction signal for instructing serial access to the memory is input, the first access data from the serial data processing circuit is serially output to the memory capable of serial access, Second instruction signal for instructing parallel access to the memory If There being input to said memory is capable of parallel access, the comprising: a selection circuit for outputting the second access data from the parallel data processing circuit in parallel, wherein the serial data processing circuit, a predetermined The first access data is serially output in synchronization with a rising edge or a falling edge of a clock signal having a period, and the parallel data processing circuit is configured so that the clock signal does not become an integral multiple of a half period of the clock signal. A delay circuit that outputs a delayed clock signal that has been delayed; and a parallel output circuit that outputs the second access data in parallel in synchronization with both rising and falling edges of the delayed clock signal; The selection circuit is serially input when the first instruction signal is input. The first access data to be received in synchronization with the rising edge or the falling edge of the clock signal, and the first access data from the serial data processing circuit to the rising edge or the falling edge of the clock signal. The memory capable of serially outputting in synchronization with an edge and receiving the second access data input in parallel in synchronization with both edges of the clock signal when the second instruction signal is input In addition, the second access data from the parallel data processing circuit is output in parallel in synchronization with both edges of the delayed clock signal .

  It is possible to provide a memory control circuit capable of increasing the access speed to the memory and suppressing an increase in mounting area.

At least the following matters will become apparent from the description of this specification and the accompanying drawings.
FIG. 1 is a diagram showing a system LSI (Large Scale Integration) 10 according to an embodiment of the present invention.
The system LSI 10 is a circuit that executes access to the memory 11, and includes a CPU 20, a memory control circuit 21, an address bus 22, a data bus 23, a control bus 24, and terminals 300 to 305.

  The memory 11 is a non-volatile memory such as a flash memory, for example, and stores a program executed by the CPU 20 and data used in various processes of the CPU 20. In addition, the memory 11 according to the present embodiment is capable of serial access. For example, when the CPU 20 reads a program stored in the memory 11 and high-speed access is required, a terminal used for serial access is set. Can be used for parallel access.

  Specifically, when the memory 11 is serially accessed, the terminal 400 is an input terminal to which a control signal SCS for enabling the memory 11, that is, an accessible state is input. The terminal 401 is an input terminal to which the clock signal SCLK is input. The terminal 402 serves as an input terminal to which data SO for accessing the memory 11 is input. The terminal 403 is an input terminal to which a control signal SWP for making the memory 11 in a writable state is input. The terminal 404 is an input terminal to which a control signal SHOLD for allowing the memory 11 to accept data is input. The terminal 405 serves as an output terminal from which data read from the memory 11 in accordance with the data SO input to the terminal 402 is output as data SI. On the other hand, when the memory 11 is accessed in parallel, the terminal 400 is an input terminal to which a control signal PCS for enabling the memory 11, that is, an accessible state is input. The terminal 401 is an input terminal to which the clock signal PCLK is input. Terminals 402 to 405 receive address data for the memory 11 as data PIO [0] to PIO [3], and data read according to the address data is output as data PIO [0] to PIO [3]. I / O terminal. That is, in the memory 11 of the present embodiment, when the terminals 402 to 404 functioning as input terminals when serially accessed and the terminal 405 functioning as an output terminal are accessed in parallel, data PIO [0] -PIO [3] are changed to input / output terminals capable of input / output.

  Further, when the memory 11 of this embodiment is serially accessed and the command for causing the memory 11 to access the memory 11 in parallel is input as the data SO from the memory control circuit 21, the memory 11 can be accessed in parallel. When a command for serially accessing the memory 11 is input as data PIO [0] to PIO [3] from the memory control circuit 21 while the memory 11 is being accessed in parallel, the memory 11 can be serially accessed. And Note that the memory 11 of the present embodiment is in a serial accessible state when activated.

  The CPU 20 controls the memory control circuit 21 that accesses the memory 11 via the address bus 22, the data bus 23, and the control bus 24, and is stored in the memory 11 that is output from the memory control circuit 21 via the data bus 23. It is a circuit that performs various processes based on the data and programs. In the present embodiment, the clock signal HCLK is output from the CPU 20 to the memory control circuit 21 as a bus clock.

  The memory control circuit 21 is a circuit that performs serial access or parallel access to the memory 11 in accordance with an instruction from the CPU 20. Specifically, when the memory control circuit 21 in this embodiment performs serial access, the memory control circuit 11 sends the control signal SCS, the clock signal SCLK, the data SO, and the control signals SWP and SHOLD to the terminals 300 to 304. Output each one. Further, the memory control circuit 21 receives data SI read from the memory 11 according to the data SO from the terminal 305. On the other hand, when the memory control circuit 21 in this embodiment performs parallel access, the memory control circuit 21 outputs the control signal PCS and the clock signal PCLK from the terminals 300 and 301, respectively, and the address data for the memory 11 is the data PIO [ 0] to PIO [3] are output to the terminals 302 to 305, respectively. In addition, data read from the memory 11 according to the address data is received as data PIO [0] to PIO [3] from the terminals 302 to 305, respectively. In the following embodiment, the state in which the memory control circuit 21 can serially access the memory 11 is referred to as a serial mode, and the state in which the memory control circuit 21 can access the memory 11 in parallel is referred to as a parallel mode. In this embodiment, when the control signal SCS or the control signal PCS becomes “L”, the memory 11 is enabled, that is, accessible, and when the control signal SCS or the control signal PCS becomes “H”, the memory 11 11 is in a disabled state, that is, an inaccessible state.

  The address bus 22 includes, for example, an address for the memory 11 when data stored in the memory 11 is read, and an address for various registers for setting a memory control circuit 21 described later to a serial mode or a parallel mode. As output from the CPU 20. In this embodiment, the address data HADDR output from the CPU 20 is 32-bit data, and the address bus 22 is a 32-bit bus.

  For example, data for various registers for setting the memory control circuit 21 to the serial mode or the parallel mode is output from the CPU 20 to the data bus 23 as write data HWDATA. Further, the memory control circuit 21 outputs the data read from the memory 11 in the serial mode as the first read data HRDATA1. In the parallel mode, data read from the memory 11 is output as second read data HRDATA2. In the present embodiment, each of the write data HWDATA, the first read data HRDARA1, and the second read data HRDATA2 is 32-bit data, and the data bus 23 is a 96-bit bus.

  In the control bus 24, a first slave selection signal HSEL1 for selecting various registers included in the memory control circuit 21 as a slave from the CPU 20 operating as a master in the present embodiment, and a memory 11 for selecting the memory 11 as a slave. A second slave selection signal HSEL2 (control signal) is output. Further, a transfer signal HWRITE indicating whether the memory 11 is read or written is output from the CPU 20 to the control bus 24. In addition, the memory control circuit 21 outputs an interrupt signal INT indicating that data transmission / reception has ended between the memory control circuit 21 and the memory 11. In the present embodiment, the first slave selection signal HSEL1, the second slave selection signal HSEL2, the transfer signal HWRITE, and the interrupt signal INT are each 1 bit, and the control bus 24 is a 4-bit bus.

  FIG. 2 is a diagram illustrating an embodiment of the memory control circuit 21. The memory control circuit 21 includes a bus interface 30, an address decoder 31, a first setting register 32, a control register 33, a change register 34, a status register 35, a clock generation circuit 36, a serial data processing circuit 37, a parallel data processing circuit 38, a memory An interface 39 (selection circuit) is included.

  The bus interface 30 is a circuit that executes transmission / reception of various data between the CPU 20 and each circuit in synchronization with the clock signal HCLK. Specifically, of the input 32-bit address data HADDR, lower 24 bits [23: 0] data that can be specified by the CPU 20 in this embodiment are output to the address decoder 31 and the parallel data processing circuit 38. . In the following, in this embodiment, the least significant bit is the 0th bit, and the lower mth bit to the lower nth bit are described as [n: m]. Further, the bus interface 30 outputs the write data HWDATA to the first setting register 32, the control register 33, the change register 34, the status register 35, and the serial data processing circuit 37, and the transfer signal HWRITE as an address decoder 31 and serial data processing. The first slave selection signal HSEL1 and the second slave selection signal HSEL2 are output to the address decoder 31 and the parallel data processing circuit 38, respectively. Further, the bus interface 30 outputs an interrupt signal INT, first read data HRDATA1, and second read data HRDATA2 input from the status register 35, the serial data processing circuit 37, and the parallel data processing circuit 38 to the CPU 20, respectively.

  The address decoder 31 is a circuit for decoding input address data HADDR [23: 0] and selecting each circuit in the memory control circuit 21. Further, the address decoder 31 selects a write access or a read access as an access to each circuit from the input transfer signal HWRITE. When the transfer signal HWRITE is “1”, write access is performed, and when the transfer signal HWRITE is “0”, read access is performed. The address decoder 31 of the present embodiment, based on the address data HADDR [23: 0], the first setting register 32, the control register 33, the change register 34, the status register 35, the second setting register 50, the transmission FIFO (First- In First-Out) 51 and reception FIFO 52 can be selected. Further, the address decoder 31 of this embodiment latches and decodes the address data HADDR [23: 0] in synchronization with the slave selection signal HSEL1.

  The first setting register 32 stores 6-bit setting data DSET used when the clock generation circuit 36 generates a clock signal based on the write data HWDATA, and the memory interface 39 in either the serial mode or the parallel mode. Stores setting data MODE to correspond to the mode. In the present embodiment, the setting data MODE is “0” when the memory interface 39 is compatible with the serial mode, and the setting data MODE is “1” when the memory interface 39 is compatible with the parallel mode. Note that the setting data MODE set to “0” corresponds to the first instruction signal in the present invention, and the setting data MODE set to “1” corresponds to the second instruction signal in the present invention.

  In the control register 33, based on the write data HWDATA, the enable data EN1 for causing the serial data processing circuit 37 to transmit data for accessing the memory 11 and the parallel data processing circuit 38 for accessing the memory 11 are provided. The enable data EN2 for transmitting data and the enable data EN3 for causing the parallel data processing circuit 38 to transmit data for changing the memory 11 from a parallel accessible state to a serial accessible state are stored. In the present embodiment, it is assumed that the serial data processing circuit 37 can transmit data for accessing the memory 11 only when the enable data EN1 is “1”. Similarly, the parallel data processing circuit 38 can transmit data for accessing the memory 11 only when the enable data EN2 is “1”. Further, only when the enable data EN3 is “1”, the parallel data processing circuit 38 can transmit data for enabling the parallel accessible memory 11 to be serially accessed.

  The change register 34 stores change data EDATA for changing the memory 11 from a parallel accessible state to a serial accessible state based on the write data HWDATA. The change data EDATA in the present embodiment is 24-bit data. When the change data EDATA is stored in the change register 34, the change data EDATA is output to the parallel data processing circuit 38.

  The status register 35 is output from the serial data processing circuit 37, and is output from the parallel data processing circuit 38 and data END 1 indicating whether the serial data processing circuit 37 has completed transmission / reception of data to / from the memory 11. The data END2 indicating whether or not the parallel data processing circuit 38 has completed the transmission of the change data EDATA, the data END1CLR for clearing the data END1 in the serial data processing circuit 37, and the data END2 in the parallel data processing circuit 38 Data END2CLR for clearing is stored. Further, the status register 35 of the present embodiment outputs an interrupt signal INT to the bus interface 30 based on the stored data END1 and END2. Specifically, when the serial data processing circuit 37 completes data transmission / reception with the memory 11, the serial data processing circuit 37 sets the data END1 to “1”, and when data transmission / reception has not been completed, END1 is set to “0”. Similarly, the parallel data processing circuit 38 sets the data END2 to “1” when the transmission of the change data EDATA is completed, and sets the data END2 to “0” when the transmission is not completed. The state register 35 in this embodiment outputs “1” as the interrupt signal INT to the bus interface 30 when either of the data END1 and END2 is “1”, and when both of the data END1 and END2 are “0”. Then, “0” is output to the bus interface 30 as an interrupt signal. Further, when the data END1 becomes “1” indicating completion of data transmission / reception and the CPU 20 confirms that the interrupt signal INT is “1”, the CPU 20 writes the data END1 to the status register 35 to set it to “0”. Access. Specifically, the CPU 20 writes data END1CLR for setting the transfer signal HWRITE to “1” and the data END1 to “0” as the write data HWDATA in the status register 35. As a result, the data END1CLR is output from the status register 35 to the serial data processing circuit 37, and the data END1 in the serial data processing circuit 37 becomes “0”. Similarly, when the data END2CLR is stored in the status register 35 in the parallel data processing circuit 38, the data END2 in the parallel data processing circuit 38 also becomes “0”.

  As illustrated in FIG. 3, the clock generation circuit 36 generates a clock signal NSFCLK for operating the serial data processing circuit 37 from the clock signal HCLK based on the setting data DSET stored in the first setting register 32, a parallel signal. This circuit generates clock signals SFCLK, NSFCLK, PARCLK, DSFCLK, and DNSFCLK for operating the data processing circuit 38, and includes buffer circuits 100 and 101, inverters 102 and 103, and delay circuits 110 and 111. The delay circuits 110 and 111 correspond to the delay circuit in the present invention.

  The buffer circuit 100 is a circuit that outputs an output signal having the same phase as the phase of the input signal. Therefore, in this embodiment, the clock signal SFCLK having the same phase as the clock signal HCLK is output from the buffer circuit 100.

  The inverter 102 is a circuit that inverts and outputs the phase of the input signal. In the present embodiment, a clock signal NSFCLK obtained by inverting the clock signal HCLK is output.

  As illustrated in FIG. 4, the delay circuit 110 is a circuit that delays the clock signal NSFCLK based on the upper 3 bits [5: 3] data of the 6-bit setting data DSET and outputs the delayed signal as the clock signal PARCLK. It includes buffer circuits 700 to 706, inverters 710 to 713, AND circuits 720 to 733, and NOR circuits 740 to 746. The buffer circuit 700 is a circuit that delays the input clock signal NSFCLK and outputs it to the buffer circuit 701. Each of the buffer circuits 701 to 706 is a circuit that delays and outputs an input clock signal, similarly to the buffer circuit 700. In the present embodiment, it is assumed that the buffer circuits 700 to 706 are designed so that the delay times in the buffer circuits 700 to 706 are equal. Therefore, from the buffer circuits 700 to 706 of the present embodiment, clock signals obtained by delaying the clock signal NSFCLK by seven ways are output. The inverter 710, the AND circuits 720 and 721, and the NOR circuit 740 generate either the clock signal NSFCLK or the clock signal obtained by delaying the clock signal NSFCLK by the buffer circuit 700 in accordance with the level of the input setting data DSET [3]. It is a circuit that inverts and outputs. Specifically, when the setting data DSET [3] is “0”, the clock signal NSFCLK is output from the AND circuit 720 and “0” is output from the AND circuit 721. Therefore, from the NOR circuit 740, A clock signal obtained by inverting the clock signal NSFCLK is output. When the setting data DSET [3] is “1”, the AND circuit 720 outputs “0”, and the AND circuit 721 outputs the clock signal delayed by the buffer circuit 700, so that the NOR circuit 740 is output. From this, a clock signal obtained by inverting the clock signal delayed by the buffer circuit 700 is output. In the present embodiment, AND circuits 722, 723, NOR circuit 741, AND circuits 724, 725, NOR circuit 742, AND circuits 726, 727, NOR circuit 743, AND circuits 728, 729, NOR circuit 744, and AND Since the circuits 730 and 731 and the NOR circuit 745, the AND circuits 732 and 733, and the NOR circuit 746 have the same configuration as the above-described AND circuits 720 and 721 and the NOR circuit 740, they operate in the same manner. Therefore, for example, when the setting data DSET [5: 3] are all “0”, the clock signal NSFCLK is output from the inverter 713 as the clock signal PARCLK. When all the setting data DSET [5: 3] are “1”, the clock signal output from the buffer circuit 706 is output from the inverter 713 as the clock signal PARCLK. As a result, the delay circuit 110 illustrated in FIG. 4 can set eight delays based on the setting data DSET [5: 3], including the case where the clock signal NSFCLK is not delayed.

  The delay circuit 111 is a circuit that delays the clock signal HCLK based on the lower 3 bits [2: 0] data of the 6-bit setting data DSET, and is similar to the delay circuit 110. In this embodiment, the buffer circuit 101 is the same as the buffer circuit 100, and the inverter 103 is the same as the inverter 102. Therefore, the clock signal DSFCLK obtained by delaying the clock signal HCLK by the delay circuit 111 is output from the buffer circuit 101, and the clock signal DNSFCLK obtained by inverting the clock signal DSFCLK is output from the inverter 102. As will be described in detail later, the clock signal PARCLK is used when the parallel data processing circuit 38 transmits data to the memory 11, and the clock signals DSFCLK and DNSFCLK are used when the parallel data processing circuit 38 receives data from the memory 11. Used for. In the present embodiment, the delay time delayed by the delay circuit 110 is set as a delay time TA, and the delay time delayed by the delay circuit 111 is set as a delay time TB. The delay time TA is a delay time set so that the memory 11 can acquire the output data from the memory interface 39 at the time of parallel access. The delay time TB is a delay time that is set so that the memory interface 39 can acquire output data from the memory 11 in parallel access. In this embodiment, the range in which the delay can be set is one cycle of the clock signal HCLK. That is, the delay time TA can be set in eight different delays by combining the upper 3 bits of the setting data DSET within a range of one cycle of the clock signal HCLK. Further, the delay time TB can be set in eight different delays by combining the lower 3 bits of the setting data DSET within a range of one cycle of the clock signal HCLK.

  The serial data processing circuit 37 outputs control signals SCS, SWP, SHOLD, data SO (first access data), and clock signal NSFCLK to the memory 11 for serial access to the memory 11 based on the enable data EN1. The control signal SCLKEN is output to the memory interface 39, and the first read data HRDATA1 is output to the bus interface 30 based on the data SI from the memory interface 39. The serial data processing circuit 37 of this embodiment includes a second setting register 50, a transmission FIFO 51, a reception FIFO 52, and a serial control circuit 53.

  The second setting register 50 is a circuit for setting control signals SWP and SHOLD output to the memory interface 39 based on the write data HWDATA and the transfer signal HWRITE. In the present embodiment, it is assumed that the control signals SWP and SHOLD are set so that the memory 11 can accept input data.

  The transmission FIFO 51 stores data for accessing the memory 11 based on the write data HWDATA and the transfer signal HWRITE. When the enable data EN1 of the control register 33 becomes “1”, the stored data is used as data SO. It is a circuit that outputs to the interface 39. In the present embodiment, the data stored in the transmission FIFO 51 is, for example, command data indicating access contents, address data for the memory 11, and write data for writing to the memory 11. Since the address for the memory 11 in this embodiment is 24 bits, the address data stored in the transmission FIFO 51 is also 24 bits.

  The reception FIFO 52 is a circuit that receives data SI read from the memory 11 in response to an instruction from the CPU 20 and outputs the data SI to the bus interface 30 as first read data HRDATA1. Note that the transmission FIFO 51 and the reception FIFO 52 in this embodiment operate in synchronization with the clock signal NSFCLK from the clock generation circuit 36, for example.

  The serial control circuit 53 causes the data stored in the transmission FIFO 51 to be transmitted based on the enable data EN1, and the control signals SCS, SCLKEN and the data END1 indicating whether the transmission FIFO 51 or the reception FIFO 52 has completed data transmission / reception. Is a circuit that generates Specifically, when transmitting data to the memory 11, the CPU 20 sets the transfer signal HWRITE to “1” and performs writing to the transmission FIFO 51. After the write data HWDATA is written in the transmission FIFO 51 as transmission data, the CPU 20 writes the control data 33 so that the enable data EN1 becomes “1”. When the enable data EN1 becomes “1”, the serial control circuit 53 sets the control signals SCS and SCLKEN to “L” and “H”, respectively, for a predetermined period necessary for transmitting the data of the transmission FIFO 51, and the transmission FIFO 51 Send the data. In this embodiment, data is output from the memory 11 at the same timing as the transmission data of the transmission FIFO 51 and stored in the reception FIFO 52. The serial control circuit 53 sets the data END1 to “1” after a lapse of a predetermined period required for transmission and reception, that is, when transmission and reception are completed. Then, after the CPU 20 confirms the interrupt signal INT, the CPU 20 reads the reception FIFO 52. That is, the CPU 20 sets the transfer signal HWRITE to “0”, and acquires the data in the memory 11 stored in the reception FIFO 52 as the first read data HRDATA1.

  The parallel data processing circuit 38, based on the enable data EN2 and EN3, the address data HADDR [23: 0], and the second slave selection signal HSEL2, to control the memory 11 in parallel, the control signal PCS, the clock signal NSFCLK, The control signal PCLKEN for outputting the clock signal NSFCLK to the memory 11 and the 4-bit data POUT (second access data) are output, and the second read data is based on the 4-bit data PIN from the memory interface 39. This circuit outputs HRDATA2 to the bus interface 30. Specifically, when the enable data EN2 becomes “1”, the parallel data processing circuit 38 outputs the address data HADDR [23: 0] for the memory 11 in parallel to the memory interface 39 as the data POUT, and the memory interface 39 The data PIN [3: 0] input in parallel is output to the bus interface 30 as the second read data HRDATA2. In addition, when the enable data EN3 becomes “1”, the parallel data processing circuit 38 receives the change data EDATA for changing the memory 11 from the parallel accessible state to the serial accessible state as data POUT [3: 0]. To the memory interface 39 in parallel. The parallel data processing circuit 38 of the present embodiment includes a transmission circuit 60 (parallel output circuit), a reception circuit 61 (data output circuit), and a parallel control circuit 62.

  As illustrated in FIG. 5, the transmission circuit 60 outputs 24-bit address data HADDR [23: 0] or 24-bit change data EDATA as data POUT sequentially in units of 4 bits in synchronization with the clock signal PARCLK. And includes a latch circuit 120, selectors 121 and 122, a data distribution circuit 123, a pulse generation circuit 124, data shift circuits 125 and 126, and a data output circuit 127. Note that the transmission circuit 60 of the present embodiment outputs the data POUT in synchronization with both edges of the clock signal PARCLK in order to transmit the data POUT at high speed.

  When the second slave selection signal HSEL2 for reading out the data stored in the memory 11 by the CPU 20 selecting the memory 11 as a slave is “H”, the latch circuit 120 receives the 24-bit address data HADDR [ 23: 0]. Note that data from the latch circuit 120 in the present embodiment is referred to as data LD1.

  The selector 121 outputs the data LD1 as output data when the enable data EN3 is “1”, and outputs 24 bits “0” as output data when the enable data EN3 is “0”.

  The selector 122 outputs 24-bit address data HADDR [23: 0] when the enable data EN2 is “1”, and outputs the output data from the selector 121 when the enable data EN3 is “0”.

  The data distribution circuit 123 is a circuit that distributes input 24-bit data to 12 bits each. In the present embodiment, data input to the data distribution circuit 123 is data D1. Further, the data distribution circuit 123 according to the present embodiment outputs D1 [23:20, 15:12, 7: 4], which is 12-bit data among the data D1 [23: 0], to the data shift circuit 125. , D1 [19:16, 11: 8, 3: 0], which is 12-bit data, is output to the data shift circuit 126. In the present embodiment, 12-bit data output from the data distribution circuit 123 to the data shift circuit 125 is referred to as data D2, and 12-bit data output to the data shift circuit 126 is referred to as data D3.

  When the enable data EN3 becomes “1” or the second slave selection signal HSEL2 becomes “H” and the clock signal SFCLK rises, the pulse generation circuit 124 takes in the data D2 from the data distribution circuit 123. For this purpose, a pulse signal LP1 is generated. In addition, when the enable data EN3 becomes “1” or the second slave selection signal HSEL2 becomes “H” and the clock signal NSFCLK rises, the pulse generation circuit 124 causes the data shift circuit 126 to output the data D3 from the data distribution circuit 123. Is generated as a pulse signal LP2. In the present embodiment, the pulse signals LP1 and LP2 output from the pulse generation circuit 124 are set to “H” for one period of each of the clock signals SFCLK and NSFCLK.

  The data shift circuit 125 is a circuit that takes in the input 12-bit data D2 based on the pulse signal LP1 and sequentially outputs it in units of 4 bits in synchronization with the clock signal NSFCLK. As illustrated in FIG. 200, a latch circuit 201, data selection circuits 202 and 203, and a data generation circuit 204.

  The selector 200 outputs data D2 as data D4 when the pulse signal LP1 is “H”, and outputs 12-bit data output from the data generation circuit 204 as data D4 when the pulse signal LP1 is “L”. To do.

  The latch circuit 201 latches the data D4 in synchronization with the rising edge of the clock signal NSFCLK and outputs it as 12-bit data D5.

  The data selection circuit 202 selects the lower 8 bits [7: 0] of the 12-bit data D5 and outputs it to the data generation circuit 204.

  The data selection circuit 203 selects the upper 4 bits [11: 8] of the 12-bit data D5 and outputs it to the data output circuit 127. Note that the data of the upper 4 bits [11: 8] of the data D5 in the present embodiment is referred to as data D6.

  The data generation circuit 204 is a circuit that combines the data whose 4 bits are “0” and the 8-bit data D5 [7: 0] output from the data selection circuit 202 and outputs the combined data as 12-bit data. Note that the data generation circuit 204 of the present embodiment, when generating 12-bit data, sets the data in which the 4 bits are “0” to be the lower 4 bits of the 8-bit data D5 [7: 0]. It is assumed that 12-bit data is generated.

  Therefore, when the pulse signal LP1 is “H”, the data shift circuit 125 of this embodiment latches the input data D2 in synchronization with the clock signal NSFCLK, and synchronizes the upper 4 bits of the data D2 with the clock signal NSFCLK. Will be output. On the other hand, when the pulse signal LP1 is “L”, the data shift circuit 125 outputs the 4-bit data from the most significant bit among the 12-bit data latched before the pulse signal LP1 becomes “L”. The data is sequentially output in synchronization with the. In this embodiment, since data having 4 bits of “0” is input to one input of the data generation circuit 204, 12-bit data latched before the pulse signal LP1 becomes “L”. After all are output, data whose 4 bits are “0” continues to be output in synchronization with the clock signal NSFCLK.

  The data shift circuit 126 has the same configuration as that of the data shift circuit 125. The data shift circuit 126 takes in the input 12-bit data based on the pulse signal LP2, and forms 4-bit data D7 in synchronization with the clock signal SFCLK. This circuit outputs sequentially. In the present embodiment, the data shift circuit 125 sequentially outputs data D6 in synchronization with the rising edge of the clock signal NSFCLK, and the data shift circuit 126 sequentially outputs data D7 in synchronization with the rising edge of the clock signal SFCLK. . Since the phase of the clock signal NSFCLK is inverted from the phase of the clock signal SFCLK, the data D6 and the data D7 are sequentially input to the data output circuit 127 every 4 bits with a half cycle shift.

  The data output circuit 127 is a circuit that outputs data D6 as data POUT when the clock signal PARCLK is “H”, and outputs data D7 as data POUT when the clock signal PARCLK is “L”. The clock signal PARCLK in the present embodiment is set so that the delay time TA with respect to the clock signal NFSCLK is, for example, a quarter cycle. Therefore, the data output circuit 127 sequentially outputs the data D6 and D7 in synchronization with both the rising edge and the falling edge of the clock signal PARCLK.

  Here, the operation of the transmission circuit 60 will be described with reference to the timing chart of FIG. Here, a case where the address data HADDR [23: 0] is transmitted by the transmission circuit 60, that is, a case where the enable data EN2 and EN3 are “1” and “0”, respectively, will be described as an example. In FIG. 7, the address data HADDR [23] to HADDR [0] are described as A23 to A0, respectively.

  When the second slave selection signal HSEL2 becomes “H” at time T1, the latch circuit 120 latches the input address data HADDR [23: 0] and outputs it to the selector 122 as data LD1. Since the enable data EN2 is “1” from the selector 122, the address data HADDR [23: 0] is output. Then, the data distribution circuit 123 outputs HADDR [23:20, 15:12, 7: 4] as data D2 to the data shift circuit 125, and HADDR [19:16, 11: 8, 3: 0] as data. D3 is output to the data shift circuit 126. When the rising edge of the clock signal NSFCLK is input to the latch circuit 201 at time T2, the latch circuit 201 latches the data D2, and therefore, the address data HADDR [23: 20] is output. At time T3, since the clock signal PARCLK input to the data output circuit 127 becomes “H”, each bit of the address data HADDR [23:20] is output as data POUT. At time T4, similarly to time T2, the data shift circuit 126 outputs address data HADDR [19:16], which is the upper 4 bits of data D3. At time T5, as in time T3, each bit of the address data HADDR [19:16] is output as data POUT. Hereinafter, from time T6 to time T10, the data output circuit 127 synchronizes with the clock signal PARCLK and addresses data HADDR [15:12], HADDR [11: 8], HADDR [7: 4], HADDR [3: 0] Are sequentially output.

  Note that the memory 11 of the present embodiment stores the address at the designated address when the falling edge of the clock signal NSFCLK is input at time T11 after the address for the memory 11 is transmitted from the transmission circuit 60 at time T10. The output of the recorded data is started. If the data read from the memory 11 in this embodiment is 16 bits, the first 4 bits of the 16 bits are output in response to the fall of the clock signal NSFCLK input at time T11. Assume that 4 bits are sequentially output in synchronization with the edge of NSFCLK.

  The receiving circuit 61 illustrated in FIG. 8 receives the 4-bit data PIN output from the memory interface 39 as the read data of the memory 11 and transmits it to the CPU 20 as the 32-bit second read data HRDATA2 as the bus interface 30. And includes a pulse generation circuit 130, a delay circuit 131, data conversion circuits 132 and 133, and a read data generation circuit 134. In the present embodiment, the read data read by designating the address for the memory 11 as described above is 16 bits, and both the rising edge and falling edge of the clock signal NSFCLK are input. Each time four bits are output. In the present embodiment, the read data output from the memory 11 is delayed due to the influence of the terminals 302 to 305, 402 to 405, etc., and input as data PIN. Therefore, in the present embodiment, the data PIN is received by the clock signals DSFCLK and DNSFCLK obtained by delaying the clock signals SCLK and NSCLK in the clock generation circuit 36 so that the data PIN input with a delay can be received. . In the present embodiment, for example, it is assumed that the clock signal HCLK is delayed by the delay time TB so that both edges of the clock signal DSFCLK enter a period in which read data is output.

  The pulse generation circuit 130 is based on the second slave selection signal HSEL2 and the clock signal SFCLK, and the pulse signal LP3 for the data conversion circuit 132 to acquire 4-bit data PIN sequentially input to the data conversion circuit 132; This is a circuit that outputs a pulse signal LP4 for converting the data PIN acquired by the data conversion circuit 132 into 16-bit data.

  The delay circuit 131 delays the pulse signals LP3 and LP4, and the data conversion circuit 133 acquires the pulse signal LP5 for the data conversion circuit 133 to acquire 4-bit data PIN sequentially input to the data conversion circuit 133. This is a circuit that outputs a pulse signal LP6 for converting the processed data PIN into 16-bit data.

  The data conversion circuit 132 is a circuit that receives sequentially input 4-bit data PIN and converts it into 16-bit data. The data generation circuits 210 and 214, selectors 211 and 215, data selection circuit 213, and latch circuit 212 , 216.

  The data generation circuit 210 is a circuit that generates 12-bit data D11 from the 8-bit data D10 output from the data selection circuit 213 and the 4-bit data PIN. In the data generation circuit 210 in the present embodiment, among the 12-bit data D11 to be generated, the data PIN is the lower 4 bits [3: 0] and the data D10 is the upper 8 bits [11: 4]. It is assumed that data D11 is generated.

  When the pulse signal LP3 is “H”, the selector 211 outputs the data D11 as data D12 to the latch circuit 212, and when the pulse signal LP3 is “L”, the selector 211 latches the data D13 from the latch circuit 212 as it is as data D12. This is a circuit that outputs to the circuit 212.

  The latch circuit 212 is a circuit that latches the input 12-bit data D12 in synchronization with the rising edge of the clock signal DSFCLK and outputs it as 12-bit data D13.

  The data selection circuit 213 is a circuit that outputs the lower 8 bits [7: 0] of the 12-bit data D13 output from the latch circuit 212 to the data generation circuit 210 as data D10.

  Therefore, when the data PIN is continuously input to the latch circuit 212 in synchronization with the clock signal DSFCLK during the period in which the pulse signal LP3 is “H”, the 12-bit storage area [11: 0] in the latch circuit 212 The data PIN input earlier in time is held in the storage area [7: 4], and the data PIN input later in time is held in the storage area [3: 0]. When new data PIN is input to the latch circuit 212, the data PIN input earlier in time is held in the storage area [11: 8], and the data PIN input later in time is stored in the storage area [7. : 4], and the new data PIN is held in the storage area [3: 0]. Note that during the period in which the pulse signal LP3 is “L”, the latch circuit 212 continues to hold the data D13 regardless of the clock signal DSFCLK.

  The data generation circuit 214 is a circuit that generates 16-bit data D14 from the 12-bit data D13 from the latch circuit 212 and the 4-bit data PIN. In the present embodiment, of the 16-bit data D14, the data D14 is generated such that the data D13 is the upper 12 bits and the data PIN is the lower 4 bits.

  The selector 215 outputs data D14 as data D15 when the pulse signal LP4 is “1”, and outputs data D16 output from the latch circuit 216 when the pulse signal LP4 is “0”.

  The latch circuit 216 is a circuit that latches input 16-bit data D15 in synchronization with the rising edge of the clock signal DSFCLK and outputs the data as 16-bit data D16.

  Therefore, the data conversion circuit 132 of the present embodiment holds the input data PIN up to 16 bits in the latch circuit 216 in synchronization with the clock signal DSFCLK, and outputs the data PIN to the read data generation circuit 134 as data D16.

  Similar to the data conversion circuit 132, the data conversion circuit 133 is a circuit that converts input 4-bit data PIN into 16-bit data based on the pulse signals LP5 and LP6 and the clock signal DNSFCLK and outputs the converted data. , Data generation circuits 220 and 224, selectors 221 and 225, a data selection circuit 223, and latch circuits 222 and 226. Note that the data conversion circuit 133 in this embodiment has the same configuration as the data conversion circuit 132, and the data generation circuits 220 and 224, the selectors 221 and 225, the data selection circuit 223, and the latch circuits 222 and 226 are data It corresponds to the generation circuits 210 and 214, the selectors 211 and 215, the data selection circuit 213, and the latch circuits 212 and 216. In the present embodiment, data output from the latch circuit 222 is data D17, and data output from the latch circuit 226 is data D18.

  The read data generation circuit 134 is a circuit that generates 32-bit read data HRDATA2 from the 16-bit data D16 and D18 from the data conversion circuits 132 and 133.

  Here, the details of the operation of the receiving circuit 61 in the present embodiment will be described with reference to the timing chart of FIG. It is assumed that read data output from the memory after the address for the memory 11 is designated by the transmission circuit 60 described above is input to the reception circuit 61 of the present embodiment. That is, time T11 in FIG. 9 is the same as time T11 in FIG. 7 described above, and a period TD (first time) has elapsed since the falling edge of the clock signal NSFCLK at time T11 was input to the memory 11. It is assumed that the data PIN is input to the receiving circuit 61 at time T12. In the present embodiment, since the clock signal NSFCLK is input to the memory 11, 16-bit read data is output from the memory 11 at the respective timings of both edges of the clock signal NSFCLK. After the falling edge of the clock signal NSFCLK is input, 4-bit data PIN is sequentially input to the receiving circuit 61 with a half cycle delay. In FIG. 9, data [15] to [0] of the input 16-bit read data are described as 15 to 0, respectively. In addition, the pulse generation circuit 130 according to the present embodiment outputs a pulse signal LP3 that is “H” for two periods of the clock signal SFCLK at time T11 in response to the second slave selection signal HSEL2 input at time T1. I decided to. Further, in the pulse generation circuit 130 of this embodiment, the pulse signal LP3 becomes “H” and the period of the one cycle of the clock signal DSFCLK is “H” from time T14 when the falling edge of the clock signal DSFCLK is input twice. A pulse signal LP4 is output. Further, the delay circuit 131 of the present embodiment delays the aforementioned pulse signals LP3 and LP4 by a half cycle of the clock signal HCLK and outputs them as pulse signals LP5 and LP6. Further, in the present embodiment, the data conversion circuits 132 and 133 capture 8 bits each of the input 16-bit data. Note that the latch circuits 212, 216, 222, and 226 in this embodiment are reset when activated, for example, and 12 bits of “0” are stored therein.

  First, data acquired by the data conversion circuit 132 will be described. At time T13, since the pulse signal LP3 is “H”, the data [15] to [12] are latched by the latch circuit 212 as data D13 in synchronization with the rising edge of the clock signal DSFCLK. At time T15, since the pulse signal LP4 is “H”, the last 4-bit data [7] to [4] fetched by the data conversion circuit 132 and the latch circuit 212 are already latched [15]. To [12] are latched by the latch circuit 216 in synchronization with the rising edge of the clock signal DSFCLK and output as data D16.

  Next, data acquired by the data conversion circuit 133 will be described. Also in the data conversion circuit 133, the data [11] to [8] are latched by the latch circuit 221 at time T14, and the data [11] to [8] and [3] to [0] are stored at time T17. It is latched by the latch circuit 226.

  At time T17, the read data generation circuit 133 receives 16-bit data D16 including data [15] to [12] and [7] to [4] from the data conversion circuit 132, and [ 11] to [8] and [3] to [0] are combined with 16-bit data D18 to generate 32-bit second read data HRDATA2. In the present embodiment, the data read from the memory 11 is 16 bits. However, even if the data read from the memory 11 is 32 bits by using the receiving circuit 61 in the present embodiment, the second read is performed. Data HRDATA2 can be converted.

  The parallel control circuit 62 illustrated in FIG. 10 is a circuit that outputs the control signals PCS, PCLKEN, and data END2 based on the clock signal HCLK, the second slave selection signal HSEL2, and the enable data EN3. The initial value setting circuit 140, A counter 141 is included.

  The initial value setting circuit 140 outputs a count value corresponding to the second slave selection signal HSEL2 or the enable data EN3 as an initial value of the counter 141 when either the second slave selection signal HSEL2 or the enable data EN3 becomes “H”. Circuit.

  In the present embodiment, when the second slave selection signal HSEL2 becomes “H”, the transmission circuit 60 transmits the address data HADDR and indicates a predetermined period for the reception circuit 61 to receive the read data corresponding to the address data HADDR. The first count value is output to the counter 141. When the enable data EN3 becomes “H”, a second count value indicating a predetermined period for the transmission circuit 60 to transmit the conversion data EDATA is output. In the present embodiment, the first count value is 8 (decimal number), for example, and the second count value is 5, for example.

  The counter 141 sets the count value output from the initial value setting circuit 140 based on the clock signal HCLK, and down-counts the count value in synchronization with the clock signal HCLK, and outputs the control signals PCS, PCLKEN, and the data END2 It is a circuit to output. In this embodiment, when the second slave selection signal HSEL2 and the enable data EN3 are “L”, the control signals PCS, PCLKEN, and data END2 are “H”, “L”, and “L”, respectively. . Here, when the second slave selection signal HSEL2 becomes “H” and the first count value is set in the counter 141, the control signal PCLKEN becomes “L” when the count value becomes “1” (decimal number). When the count value becomes “0” (decimal number), the control signal PCS is set to “H”. Further, when the enable data EN3 becomes “H” and the second count value is set in the counter 141, when the count value becomes “1” (decimal number), the control signal PCLKEN becomes “L” and the count value Becomes “0” (decimal number), the control signal PCS is set to “H” and the data END2 is set to “H”. Further, the counter 141 according to the present embodiment resets the data END2 to “0” when the data END2CLR is input.

  The memory interface 39 illustrated in FIG. 11 makes the serial data processing circuit 37 accessible to the memory 11 when the setting data MODE is “0”, and the parallel data processing circuit 38 when the setting data MODE is “1”. Is configured to include a selector 230 to 240, a buffer circuit 250 to 255, and an AND circuit 260. Note that the selectors 230 to 240 in this embodiment are the same as the selector 121 of the transmission circuit 60, and the buffer circuits 250 to 255 are the same as the buffer circuit 100 in the clock generation circuit 36. The memory interface 39 according to the present embodiment transmits and receives data based on the clock signal NSFCLK output from the clock generation circuit 36.

  First, a case where the setting data MODE is “0”, that is, a case where the serial data processing circuit 37 can access the memory 11 will be described. Since the control signal SCS is output from the selector 230, the control signal SCS is output from the terminal 300 to the memory 11. Since the clock signal NSFCLK and the control signal SCLKEN from the selector 231 are output to the AND circuit 260, when the control signal SCLKEN is “H”, the clock signal NSFCLK is output from the terminal 301 to the memory 11, and the control signal When SCLKEN is “L”, “L” is similarly output to the memory 11. Since the selectors 233, 235, and 237 output the control signals SO, SWP, and SHOLD, the control signals SO, SWP, and SHOLD are output to the memory 11 from the terminals 302 to 304, respectively. Further, since the data SI from the memory 11 is input to the selector 238, the data SI is output to the serial data processing circuit 37. Since “0” is output from each of the selectors 232, 234, 236, and 239, the data PIN [0] to [3] are each “0”. Since the setting data MODE input to the selector 238 is “0”, the terminal 305 operates as an input terminal to which data SI is input.

  Next, a case where the setting data MODE is “1”, that is, a case where the parallel data processing circuit 38 can access the memory 11 will be described. Since the control signal PCS is output from the selector 230, the control signal PCS is output from the terminal 300 to the memory 11. Since the clock signal NSFCLK and the control signal PCLKEN from the selector 231 are output to the AND circuit 260, when the control signal PCLKEN is “H”, the clock signal NSFCLK is output from the terminal 301 to the memory 11, and the control signal When PCLKEN is “L”, “L” is similarly output to the memory 11. Since the selectors 233, 235, 237, and 240 output the data POUT [0] to [3], the data POUT [0] to [3] are output from the terminals 302 to 305 to the data PIO [0] to PIO [0]. [3] is output to the memory 11, respectively. Since the data PIO [0] to [3] from the memory 11 corresponding to the data POUT [0] to [3] are input to the selectors 232, 234, 236 and 239, the data PIO [0] to [3] ] Are output to the parallel data processing circuit 38 as data PIN [0] to [3]. Since the output from the selector 238 is “0”, the data SI is eventually “0”.

  Therefore, when the setting data MODE is “0”, the memory interface 39 according to the present embodiment has the control signal SCS from the serial data processing circuit 37, the clock signal NSFCLK according to the control signal SCLKEN, the data SO, and the control signals SWP, SHOLD. Are output to the terminals 300 to 304, and the data SI input to the terminal 305 is output to the serial data processing circuit 37. On the other hand, when the setting data MODE is “1”, the control signal PCS from the parallel data processing circuit 38 and the clock signal NSFCLK corresponding to the control signal PCLKEN are output to the terminals 300 and 301, respectively, and the 4-bit data POUT is output to the terminal. 302 to 305 are output as 4-bit data PIO. Further, the 4-bit data PIO input to the terminals 302 to 305 is output to the parallel data processing circuit 38 as 4-bit data PIN.

<< Read Operation for Memory 11 in Serial Mode >>
As an example of the case where the memory control circuit 21 is serially accessing the memory 11, an operation when the memory control circuit 21 reads data stored in the memory 11 will be described with reference to the flowchart shown in FIG. 12. Here, it is assumed that the memory 11 is in a state where, for example, the system LSI 10 is activated and serial access is possible. First, the CPU 20 sets the first setting register 32 so that the setting data MODE of the first setting register 32 becomes “0” (S200). Then, the CPU 20 stores the read command and the address for the memory 11 in the transmission FIFO 51 in order to execute the reading to the memory 11, and controls the second setting register 50 to cause the memory 11 to execute the reading. The signals SWP and SHOLD are set to “0” (S201). Thereafter, the CPU 20 sets the enable data EN1 of the control register 33 to “1” in order to transmit the data stored in the transmission FIFO 51 to the memory 11 (S202). When the reception FIFO 52 receives the data stored at the address for the memory 11 and the reception FIFO 52 completes the reception (S203: YES), the serial control circuit 52 sets the data END1 stored in the status register 35 to “1”. Therefore, the interrupt signal INT output from the status register 35 becomes “1” (S204). The CPU 20 acquires the data stored in the reception FIFO 52 as the first read data HRDATA1, and sets the enable data EN1 to “0” (S205). In the present embodiment, the CPU 20 can repeatedly read the data stored in the memory 11 by repeating the above-described steps S201 to S205. Note that the data END1 of the status register 33 of the present embodiment is changed to “0” after a lapse of a predetermined period after the data END1 becomes “1”. In step 205, the data END1 is changed to “0”. It is designed to be done.

  Here, an operation for the CPU 20 to change the memory 11 from a serial accessible state to a parallel accessible state will be described. Note that the memory 11 in this embodiment is changed to a state in which parallel access is possible when a command for changing to parallel access is input in the case of serial access. Therefore, in order to make the memory 11 accessible in parallel in this embodiment, after storing a command for enabling parallel access in step 201 instead of a command and address for reading, steps 203 to 205 are performed. Should be executed.

<< Read Operation for Memory 11 in Parallel Mode >>
As an example of the case where the memory control circuit 21 is accessing the memory 11 in parallel, the operation when the memory control circuit 21 reads the data stored in the memory 11 is shown in the flowchart shown in FIG. This will be described with reference to a timing chart. Note that the case where the memory control circuit 21 performs parallel access to the memory 11 is a case where high-speed access is required, for example, when the CPU 20 reads a program stored in the memory 11. 14 is the same as the times T1 to T11 in FIG. 7, and the times T11 to T17 are the same as the times T11 to T17 in FIG. Here, it is assumed that the memory 11 is in a state where parallel access is possible.

  The CPU 20 sets the first setting register 32 to set the setting data MODE and the delay times TA and TB of the delay circuits 110 and 111 in the clock generation circuit 36 (S300). Specifically, the setting data MODE is set to “1”, and the delay time TA is set so that the clock signal PARCLK is delayed by ¼ period with respect to the clock signal NFSCLK. Further, the delay time TB is set so that both edges of the clock signal DSFCLK enter a period in which read data is output. Note that the delay time TB in this embodiment is determined from the above-described delay time TD between the terminals and a period in which read data is output from the memory 11, that is, a period corresponding to the cycle of the clock signal NSFCLK. Then, the CPU 20 sets the enable data EN2 of the control register 33 to “1” so that the memory control circuit 21 can access the memory 11 in parallel (S301). At time T1, the CPU 20 outputs a second slave selection signal HSEL2 and address data HADDR for the memory 11 in order to read data from the memory 11 (S302). When the second slave selection signal HSEL2 is output, the parallel control circuit 62 of the present embodiment outputs the control signal PCS to “L” from time T4 to T18 based on the first count value set in the counter 141 described above. ", And the control signal PCLKEN is set to" H "from time T4 to T16. In this embodiment, when the CPU 20 outputs the second slave selection signal HSEL2 and the address data HADDR at time T1, the transmission circuit 60 outputs the address data from time T3 to time T10 as shown in FIG. Will be. Since the memory interface 39 of this embodiment outputs the 4-bit data PO output from the transmission circuit 60 as data PIO, the address data HADDR is output at the same timing as shown in FIG. . Further, the memory 11 in the present embodiment receives the data PIO input at the timing when the control signal PCS becomes “L” and the data PIO input in synchronization with both edges of the clock signal PCLK. . Therefore, the memory 11 of the present embodiment receives the address data HADDR that is input from time T3 to time T10. The memory 11 of the present embodiment outputs read data for the address data HADDR as data PIO when the falling edge of the clock signal PCLK is input at time T11 after receiving the address data HADDR. The data PIO output from the memory 11 is delayed from the time T11 by a delay time TD due to the influence of the terminal and the like, and is output from the memory interface 39 as data PIN. As described above, the receiving circuit 61 that receives the data PIN can receive the data PIN using the clock signals DSFCLK and DNSFCLK. As a result, the data read from the memory 11 is transferred from the receiving circuit 61 at time T17. 2 read data HRDATA2. Then, the CPU 20 acquires the second read data HRDATA2 in synchronization with the rising edge of the clock signal HCLK at time T18 (S303). Further, in the present embodiment, when the CPU 20 continues the data reading operation with respect to the memory 11 (S304: YES), the process proceeds to step S302 again, and an address for the memory 11 is designated. On the other hand, when the CPU 20 finishes the data reading operation with respect to the memory 11 (S304: NO), the CPU 20 sets the enable data EN2 of the control register 33 to “0” (S305), and the parallel data processing circuit 37 enters the memory 11. Inaccessible state.

<< When parallel accessible memory 11 is serially accessible >>
Here, a case where the memory 11 in a parallel accessible state is changed to a serial accessible state will be described with reference to the flowchart shown in FIG. Here, it is assumed that the memory control circuit 21 has already executed step S300 shown in FIG. 13 and supports the parallel mode. First, the CPU 20 stores the change data EDATA in the change register 34 (S400). Then, the CPU 20 sets the enable data EN3 of the control register 33 to “1” (S401). When the enable data EN3 becomes “1”, the control signals PCS and PCLKEN output from the parallel control circuit 62 are based on the second count value set in the counter 141, from time T4 to time T11 and T100, respectively. “L”, “H”. Further, since the selector 121 in the transmission circuit 60 outputs the change data EDATA, as a result, the change data EDATA is output as the data POUT at the same timing as the address data HADDR shown in FIG. Therefore, the change data EDATA is output from the memory interface 39 to the memory 11. When the change data EDATA is received, the memory 11 of the present embodiment is changed from a parallel accessible state to a serial accessible state. When the change data EDATA is transmitted (S402: YES), the parallel control circuit 62 stores “1” in the data END2 of the status register 35. Therefore, the interrupt signal INT output from the status register 35 is “1” (S403). Then, the CPU 20 sets the enable data EN3 to “0” (S404), so that the parallel data processing circuit 37 cannot access the memory 11.

  The memory 11 in the present embodiment is a memory that can read data in accordance with input address data when accessed in parallel. For example, address data input when accessed in parallel. Depending on the situation, a memory capable of writing data may be used. At that time, the memory control circuit 21 of the present embodiment can write the data to the memory 11 at high speed by transmitting the write data HWDATA in the same manner as the address data HADDR.

  In the system LSI 10 of the present embodiment configured as described above, when the memory control circuit 21 supports the serial mode, the serial data processing circuit 37 accesses the memory 11 by outputting the data SO to the terminal 402. To do. When the memory control circuit 21 supports the parallel mode, the parallel data processing circuit 38 accesses the memory 11 by outputting 4-bit data POUT to the terminals 402 to 405. Of the terminals 403 to 405 from which the parallel data processing circuit 38 outputs data POUT, terminals 403 and 404 are terminals for outputting the control signals SWP and SHOLD when the serial data processing circuit 37 performs serial access. The memory 11 is a terminal for outputting data SI to the serial data processing circuit 37. Therefore, the memory control circuit 12 in the present embodiment can increase the access speed to the memory 11 while suppressing an increase in mounting area.

   In addition, when the address data HADDR [23: 0] for parallel access to the memory 11 is input to the transmission circuit 60 in the present embodiment, the address data HADDR [23: 0] is sent to the data shift circuits 125 and 126 by 12. The data is latched bit by bit and sequentially output as 4-bit data POUT. Therefore, when parallel access is performed, for example, the address data HADDR [23: 0] is stored in a register to which an address is assigned and is output as data POUT. In this embodiment, the CPU 20 sets the address of the register described above. Since it is not necessary to perform a designated process, the memory 11 can be accessed at a higher speed.

  In addition, when the second slave selection signal HSEL2 input at the time of parallel access becomes “H”, the transmission circuit 60 of the present embodiment latches the address data HADDR [23: 0] and outputs it as data POUT. Therefore, as compared with the case where the address HADDR output to the address bus 22 is latched by the bus clock, power consumption can be reduced because the address HADDR latch is limited to the necessary timing when accessed in parallel.

  In this embodiment, the data POUT output from the parallel data processing circuit 38 is address data for the memory 11. For example, when the memory 11 is a writable memory, the data POUT is written to the memory 11. Therefore, the write data may be output to the terminals 402 to 405 as the data POUT following the address data. With this configuration, the memory control circuit 21 of the present embodiment can write data to the memory 11 at high speed while suppressing an increase in mounting area.

  Further, when the memory control circuit 21 of the present embodiment is compatible with the parallel mode, the parallel data processing circuit 38 transmits the address data to the memory 11 to transfer the data stored in the memory 11 to the terminals 402 to 405. Can be received as data PIN and output as second read data HRDATA2. Therefore, the memory control circuit 21 of the present embodiment can read data stored in the memory 11 at high speed while suppressing an increase in mounting area.

  In the receiving circuit 61 according to the present embodiment, the data conversion circuits 132 and 133 latch the data stored in the memory 11, and the read data generation circuit outputs the second read data HRDATA2. Therefore, compared with the case where the data PIN input to the receiving circuit 61 is stored in, for example, a register to which an address is assigned and is output as the second read data HRDATA2, in this embodiment, the CPU 20 designates the address of the register. Since it is not necessary to perform the process, the data can be read at a higher speed.

  In addition, the data output circuit 127 in the transmission circuit 60 of the present embodiment has 4 bits of data D6 input in synchronization with the rising edge of the clock signal NSFCLK and 4 input in synchronization with the rising edge of the clock signal SFCLK. For example, by selecting the bit data D7 at the logical level of the clock signal PARCLK obtained by delaying the clock signal NSFCLK by ¼ period by the setting data DSET, the 4-bit data D7 synchronized with both edges of the clock signal PARCLK is selected. Data POUT is output. Therefore, the transmission circuit 60 according to the present embodiment can transmit the data POUT at a higher speed than the case where the data POUT is output in synchronization with a single edge of the clock signal, for example. Data can be transmitted at high speed.

  In the present embodiment, data read from the memory 11 is input as data PIN to the receiving circuit 61 with a delay time TD from the time T11 as illustrated in FIG. The period of the input data PIN changes according to the cycle of the clock signal NSFCLK. The receiving circuit 61 of this embodiment receives data PIN using clock signals DSFCLK and DNSFCLK obtained by delaying the clock signal HCLK by a delay time TB corresponding to the delay time TD and the cycle of the clock signal NSFCLK. Therefore, the receiving circuit 60 according to the present embodiment can receive the data PIN at a higher speed than when receiving the data PIN at one edge of the clock signal, for example. Speed can be increased.

  In addition, the said Example is for making an understanding of this invention easy, and is not for limiting and interpreting this invention. The present invention can be changed and improved without departing from the gist thereof, and the present invention includes equivalents thereof.

1 is a diagram illustrating a system LSI 10 according to an embodiment of the present invention. 2 is a diagram illustrating an embodiment of a memory control circuit 21. FIG. 3 is a diagram illustrating an embodiment of a clock generation circuit 36. FIG. FIG. 3 is a diagram illustrating an embodiment of a delay circuit 110. 2 is a diagram illustrating an embodiment of a transmission circuit 60. FIG. FIG. 3 is a diagram illustrating an embodiment of a data shift circuit 125. 3 is a timing chart for explaining the operation of a transmission circuit 60. 6 is a diagram illustrating an embodiment of a reception circuit 61. FIG. 6 is a timing chart for explaining the operation of the reception circuit 61. FIG. 6 is a diagram illustrating an embodiment of a parallel control circuit 62. FIG. 3 is a diagram illustrating an embodiment of a memory interface 39. 4 is a flowchart for explaining a read operation with respect to a memory 11 in a serial mode. 4 is a flowchart for explaining a read operation with respect to a memory 11 in a parallel mode. 4 is a timing chart for explaining a read operation with respect to a memory 11 in a parallel mode. 6 is a timing chart for explaining an operation when the memory 11 in a parallel accessible state is changed to a serial accessible state.

Explanation of symbols

10 System LSI
11 Memory 20 CPU
21 memory control circuit 30 bus interface 31 address decoder 32 first setting register 33 control register 34 change register 35 status register 36 clock generation circuit 37 serial data processing circuit 38 parallel data processing circuit 50 second setting register 51 transmission FIFO
52 Receive FIFO
53 Serial Control Circuit 60 Transmission Circuit 61 Reception Circuit 62 Parallel Control Circuit 300 to 305 Terminal

Claims (3)

Serial data processing that allows serial access and receives first access data for accessing a memory that can be accessed in parallel using a terminal used for serial access, and outputs the first access data serially Circuit,
A parallel data processing circuit for inputting second access data for accessing the memory and outputting the second access data in parallel;
When the first instruction signal for instructing serial access to the memory is input, the first access data from the serial data processing circuit is serially output to the memory capable of serial access; Selection of outputting the second access data from the parallel data processing circuit in parallel to the memory capable of parallel access when a second instruction signal for instructing parallel access to the memory is input Circuit,
Equipped with a,
The serial data processing circuit includes:
The first access data is serially output in synchronization with a rising edge or falling edge of a clock signal having a predetermined period,
The parallel data processing circuit includes:
A delay circuit that outputs a delayed clock signal obtained by delaying the clock signal by a predetermined time that is not an integral multiple of a half cycle of the clock signal;
A parallel output circuit for outputting the second access data in parallel in synchronization with both rising and falling edges of the delayed clock signal;
Including
The selection circuit includes:
When the first instruction signal is input, the serial data processing circuit is connected to the memory capable of receiving the first access data input serially in synchronization with a rising edge or a falling edge of the clock signal. The first access data from the first access data is serially output in synchronization with the rising edge or falling edge of the clock signal, and the second access data input in parallel when the second instruction signal is input Output the second access data from the parallel data processing circuit in parallel in synchronization with both edges of the delayed clock signal to the memory capable of receiving the synchronization in synchronization with both edges of the clock signal.
A memory control circuit. The memory control circuit according to claim 1 ,
Each of the first access data and the second access data is:
Including write instruction data for instructing writing to the memory and write data for the memory;
A memory control circuit. The memory control circuit according to claim 1 ,
Each of the first access data and the second access data is:
Read instruction data for instructing reading from the memory to the processing circuit,
The selection circuit includes:
When the first instruction signal is input, first read data read serially from the memory according to the read instruction data is serially output to the serial data processing circuit, and the second instruction signal is A predetermined second time shorter than a half cycle of the clock signal after a predetermined first time from each of a rising edge and a falling edge of the clock signal in a predetermined cycle according to the read instruction data, The second read data read in parallel from the memory is output in parallel to the parallel data processing circuit,
The serial data processing circuit includes:
The first read data serially output from the selection circuit is received in synchronization with a rising edge or a falling edge of the clock signal, and the processing circuit outputs the first read data so that it can be read.
The parallel data processing circuit includes:
A delayed clock obtained by delaying the clock signal for a time corresponding to the first time and the second time so that the timing of the rising edge and the falling edge enters a period in which the second read data is output from the memory. A delay circuit for outputting a signal;
The second read data output in parallel from the selection circuit is received in synchronization with both rising and falling edges of the delayed clock signal from the delay circuit, and the second read data is received from the delay circuit. A data output circuit readable by the processing circuit;
Including,
A memory control circuit.

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