JP2013120587A - Serial transfer device and serial transfer method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve data transfer performance by simplifying a configuration of a device and preventing complication of a logic circuit.SOLUTION: A serial transfer device 1 includes: shared memory 3 capable of random access storing parallel data; a serial transfer unit 2 which converts between the parallel data and serial data, and transmits/receives data between an external device and a shared memory 3; and a DMA control circuit 20 which controls so that the serial transfer unit 2 transmits/receives the data by a DMA transfer. The serial transfer unit 2 includes: a plurality of serial transmission/reception circuits 10 which transmits/receives the serial data for the external device; a memory control circuit 30 which controls access for the shared memory 3 by the plurality of serial transmission/reception circuits 10; and a cyclic counter 40 which cyclically outputs a predetermined value by synchronizing a predetermined synchronization signal. The plurality of serial transmission/reception circuits 10 transmits/receives the serial data for the external device according to an output value from the cyclic counter 40.

Description

  The present invention relates to a serial transfer device and a serial transfer method, and more particularly to a transfer device and a transfer method when DMA (direct memory access) transfer is used.

  Conventionally, when data transfer is performed between a memory provided in a transfer device and an external peripheral device, serial transfer is performed using DMA transfer in which data transfer is performed without using a central processing unit (CPU). Data transfer is performed (for example, Patent Document 1). In this case, a shift register is provided to convert parallel data from the memory into serial data and transfer it to the peripheral device, and to convert serial data from the peripheral device into parallel data and transfer it to the memory. .

  Recently, serial transfer devices capable of transferring serial data to and from a plurality of peripheral devices have been put into practical use. Such a serial transfer device is provided with a plurality of serial ports corresponding to a plurality of serial interfaces and a shift register corresponding to each serial port. The serial transfer device is provided with a shared memory for use in data transmission between a plurality of shift registers, and a plurality of serial transmission / reception circuits having the above-described shift register and a function for controlling serial data transfer. .

  When data is transmitted to a plurality of peripheral devices by such a serial transfer device, the data transmitted by each serial transmission / reception circuit is read from the shared memory, and when data is received, the received data is supplied to the supply memory. Write to.

  However, if a plurality of serial transmission / reception circuits access the supply memory at the same time, there is a risk of contention. In order to avoid such competition, various methods have been proposed in recent years, and specifically, the following first to fourth methods have been proposed.

  As shown in FIG. 14, for example, in the first method, in the serial transfer device 100 including the serial transfer unit 200, the shared memory 300, and the CPU 400, serial transmission / reception circuits 110A, 110B, and 110C provided in the serial transfer unit 200 are used. ,..., 110N and the memory control circuit 130 are provided with buffers 150A, 150B, 150C,... 150N that hold data, and an arbitration circuit 140 that determines the priority of each serial transmission / reception circuit 110 is provided. Is the method.

  When data is transmitted in the serial transfer device 100, the parallel data read from the shared memory 300 in advance is held in the buffers 150A, 150B, 150C,... 150N so that the data does not run out during transmission. .

  When data is received, serial data received by the serial transmission / reception circuits 110A, 110B, 110C,... 110N is converted into parallel data, and then stored in the buffers 150A, 150B, 150C,. And wait until the shared memory 300 becomes accessible. As a result, data overflow due to waiting for access to the shared memory 300 is prevented.

  Here, the priority order of access to the shared memory 300 is determined by the arbitration circuit 140, and access to the shared memory 300 is permitted to the serial transmission / reception circuit having a higher priority order. As a result, contention for access to the shared memory 300 can be prevented.

  For example, as shown in FIG. 15, the second method uses a serial transfer device 100 ′ composed of a serial transfer unit 200 ′, a shared memory 300, and a CPU 400, and the serial transfer unit 200 shown in FIG. This is a method excluding 150C,.

  When data transmission / reception is performed in the serial transfer device 100 ′, the priority order is determined by the arbitration circuit 140, and the predetermined serial transmission / reception circuit occupies the shared memory 300 until transmission or reception of data is completed, and other serial transmission / reception circuits. The circuit cannot access the shared memory 300. When transmission or reception by a predetermined serial transmission / reception circuit is completed, transmission or reception of data by another serial transmission / reception circuit is executed according to the order determined by the arbitration circuit 140. In the second method, as shown in FIG. 16, serial transmission / reception circuits 110A, 110B, 110C,... 110F execute data transmission or reception in order.

  The third method, for example, as described in Patent Document 2, is a method in which only a single serial transmission / reception circuit is used for serial transmission / reception of a plurality of ports. In this method, as in the second method, data transmission or reception is executed in order for each port.

  The fourth method is a method in which a special circuit called an interconnection matrix is provided between a port and a buffer as described in, for example, Patent Document 3, and all ports perform transmission or reception uniquely.

Japanese Patent Laid-Open No. 2-73445 Japanese Patent Laid-Open No. 8-194462 JP-A-9-502828

  However, in the first method, since it is necessary to provide a buffer corresponding to each serial transmission / reception circuit, there is a problem that hardware increases, and there is a possibility that the cost may increase, and design / manufacturing may become impossible.

  In addition, an arbitration circuit that determines the priority of each serial transmission / reception circuit is required to prevent contention of access to the shared memory by each serial transmission / reception circuit, which complicates the logic circuit and makes it difficult to ensure quality during design. There is a problem that an increase in design man-hours and a long design period occur.

  In the second and third methods, a predetermined serial transmission / reception circuit or port occupies the shared memory, and data is transmitted / received in order for each serial transmission / reception circuit or each port. Therefore, the serial transmission / reception circuit or port other than the serial transmission / reception circuit or port that transmits / receives data is in a standby state, which requires time for data transfer as a whole device, and there is a problem that the data transfer performance deteriorates. .

  In the fourth method, data transfer is performed with all ports in the transmission state, and when the transfer is completed, data transfer is performed with all ports in the reception state. The operation cannot be set arbitrarily for each port. For this reason, there is a problem that the data transfer performance deteriorates because the transfer standby state increases, such as the reception standby state during transmission execution and the transmission standby state during reception execution.

  Therefore, the present invention has been made in view of the problems in the above-described conventional technology, and while simplifying the configuration of the device while preventing an increase in hardware, the complexity of the logic circuit is prevented, and the data An object of the present invention is to provide a serial transfer device and a serial transfer method capable of improving transfer performance.

  To achieve the above object, the present invention performs a random access shared memory for storing parallel data, converts the parallel data and serial data, and transmits / receives data between an external device and the shared memory. A serial transfer device comprising: a serial transfer circuit; and a DMA transfer control circuit for controlling data transmission / reception by the serial transfer circuit by DMA transfer, wherein the serial transfer circuit transmits / receives serial data to / from the external device A plurality of serial transmission / reception circuits, a memory control circuit that controls access to the shared memory by the plurality of serial transmission / reception circuits, and a circulation counter that cyclically outputs a predetermined value in synchronization with a predetermined synchronization signal And the plurality of serial transmission / reception circuits are the circulation counters And performing transmission and reception of the serial data to said external device in response to the output value.

  According to the present invention, since serial data is transmitted / received to / from an external device in accordance with the output value from the circulation counter, transmission / reception operations by a plurality of serial transmission / reception circuits can be performed in parallel, and data transfer performance can be improved. It becomes possible to improve.

  In the serial transfer device, the plurality of serial transmission / reception circuits can perform transmission / reception operations when a unique circuit number is set in advance and the value output from the circulation counter matches the circuit number.

  In the serial transfer device, the DMA transfer control circuit causes the plurality of serial transmission / reception circuits to receive data from the external device at different timings for each serial transmission / reception circuit in accordance with the value of the circulation counter. At the same time, the data transmission operation to the external device by the plurality of serial transmission / reception circuits can be controlled to be executed at different timings for each serial transmission / reception circuit in accordance with the value of the circulation counter. As a result, it is possible to prevent contention between the write operation and the read operation with respect to the shared memory.

  In the serial transfer device, the serial transfer circuit can perform a write operation on the shared memory when the serial data received from the external device reaches an accessible amount of the shared memory. This prevents overflow of received data during the serial data receiving operation and allows the receiving operation to be continued.

In the serial transfer device, the serial transfer circuit can perform a read operation from the shared memory before the amount of serial data transmitted to the external device reaches the amount read from the shared memory.
As a result, it is possible to prevent a shortage of transmission data during the serial data transmission operation and to continue the transmission operation.

  Further, the present invention performs conversion between parallel data stored in the shared memory and serial data for transmission / reception to / from an external device by a plurality of serial transmission / reception circuits, and transmits / receives data between the external device and the shared memory. Serial transfer method using DMA transfer, wherein the serial transmission and reception corresponding to the output value according to an output value from a cyclic counter that cyclically outputs a predetermined value in synchronization with a predetermined synchronization signal A serial circuit transmits and receives the serial data to and from the external device. In the present invention, a plurality of transmission / reception operations with respect to an external device can be performed in parallel as in the above-described invention, and the data transfer performance can be improved.

  As described above, according to the present invention, it is possible to simplify the configuration of the apparatus while preventing an increase in hardware, prevent the complexity of the logic circuit, and improve the data transfer performance.

1 is a block diagram showing a first embodiment of a serial transfer device according to the present invention. It is a block diagram which shows an example of a structure of a serial transmission / reception circuit. It is a block diagram which shows an example of a structure of a DMA control circuit. It is a block diagram which shows an example of a structure of a memory control circuit. 6 is a timing chart for explaining the timing at which the memory control circuit accesses the shared memory. It is a flowchart for demonstrating the flow of a process of a serial transmission / reception circuit. It is a timing chart for demonstrating the case where data are transmitted in a single serial transmission / reception circuit. It is a timing chart for demonstrating the case where a single serial transmission / reception circuit receives data. It is a timing chart for demonstrating an example in case all the serial transmission / reception circuits transmit / receive data. It is a timing chart for demonstrating the other example when all the serial transmission / reception circuits transmit / receive data. It is a timing chart for demonstrating the other example when all the serial transmission / reception circuits transmit / receive data. It is a basic diagram for demonstrating access with respect to a shared memory. It is a block diagram which shows 2nd Embodiment of the serial transfer apparatus which concerns on this invention. It is a block diagram which shows an example of a structure of the conventional serial transfer apparatus. It is a block diagram which shows the other example of a structure of the conventional serial transfer apparatus. It is a timing chart for demonstrating the data transfer by the conventional serial transmission / reception circuit.

  Next, an embodiment for carrying out the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a first embodiment of a serial transfer device according to the present invention. This serial transfer device 1 exchanges data with peripheral devices (hereinafter referred to as “external devices”) provided outside. A serial transfer unit 2 that performs transmission / reception, a shared memory 3 that holds serial transfer data and can be randomly accessed, and controls each unit, and various types of DMA control circuits (described later) provided in the serial transfer unit 2 CPU 4 for writing the above command.

  The serial transfer unit 2 includes a plurality of serial transmission / reception circuits 10A, 10B, 10C,... 10N, a DMA control circuit 20, a memory control circuit 30, and a circulation counter 40. The serial transmission / reception circuits 10A, 10B, 10C,. 10N and the memory control circuit 30 are connected by a bus. The serial transmission / reception circuits 10A, 10B, 10C,..., 10N have the same functions, and are described as “serial transmission / reception circuit 10” unless they need to be distinguished in the following description.

  The serial transmission / reception circuit 10 is connected to an external device via a serial interface. The serial transmission / reception circuit 10 converts parallel data read from the shared memory 3 via the memory control circuit 30 into serial data when transmitting data to an external device. The serial transmission / reception circuit 10 converts the received serial data into parallel data when data is received from an external device.

  The DMA control circuit 20 is connected to the CPU 4 via the CPU bus 6 and controls each serial transmission / reception circuit 10 based on a write command supplied from the CPU 4 via the CPU bus 6. The memory control circuit 30 is connected to the shared memory 3 via the memory bus 5 and controls data read (Read) and write (Write) to the shared memory 3 based on a request received from each serial transmission / reception circuit 10 via the bus. To do.

  The circulation counter 40 generates a circulation counter signal that is a control signal for synchronizing the operation timing of each serial transmission / reception circuit 10. This cyclic counter signal is a signal whose value cyclically changes in accordance with the timing of the serial clock (CLK) that is the operation timing of the entire serial transfer unit 2.

  Next, detailed configurations of the serial transmission / reception circuit 10, the DMA control circuit 20, and the memory control circuit 30 will be described with reference to FIGS. As shown in FIG. 2, the serial transmission / reception circuit 10 includes a shift register 11 that performs mutual conversion between parallel data and serial data, a serial control circuit 12 that controls operations of the shift register 11 and an IO buffer 13 described later, and an external device. An IO buffer 13 for transmitting / receiving data to / from the circuit, a circuit number clamp logic unit 14 for setting a unique number for the serial transmission / reception circuit 10, and buffers 15A to 15C.

  The shift register 11 converts Read data, which is parallel data supplied from the shared memory 3 via the memory control circuit 30, into serial data based on a data load signal and a data shift signal described later supplied from the serial control circuit 12. It is converted into certain output data and supplied to the IO buffer 13. The shift register 11 converts the input data, which is serial data supplied from the external device via the IO buffer 13, into the write data, which is parallel data, based on the data load signal and the data shift signal. 30.

  Based on the transfer control signal supplied from the DMA control circuit 20 and the cyclic counter signal supplied from the circulation counter 40, the serial control circuit 12 shifts the data load signal for loading the read data in the shift register 11 and the shift The register 11 is shifted to generate a data shift signal for converting parallel data into serial data and outputting the serial data, and supplies the generated data to the shift register 11. Details of the transfer control signal will be described later.

  The serial control circuit 12 generates an IO control signal for controlling the input / output direction of the IO buffer 13 and supplies the IO control signal to the IO buffer 13. Further, the serial control circuit 12 generates a read request signal indicating a read request to the shared memory 3, a write request signal indicating a write request, and a memory address signal indicating an address to be accessed by the shared memory 3, and sends it to the memory control circuit 30. To supply. Furthermore, the serial control circuit 12 generates an enable signal, a transfer clock (CLK) signal, and an input / output mode signal that are control signals for controlling the external device. The various generated control signals are supplied to the external device via the buffers 15A to 15C.

  The IO buffer 13 controls the data input / output direction based on the IO control signal supplied from the serial control circuit 12. When transmitting data to an external device, the IO buffer 13 outputs the output data (serial data) supplied from the shift register 11 as input / output data. When receiving data from an external device, the IO buffer 13 supplies input / output data supplied from the external device to the shift register 11 as input data (serial data).

  The circuit number clamp logic unit 14 is preset with a number unique to the serial transmission / reception circuit 10, generates a circuit number clamp signal indicating the unique number, and supplies the circuit number clamp signal to the serial control circuit 12.

  As shown in FIG. 3, the DMA control circuit 20 includes an address decoder 21, AND gates 22A,..., 22N and control registers 23A,.

  The address decoder 21 decodes a CPU address indicating an address of a later-described control register 23A,..., 23N supplied from the CPU 4 and outputs the decoded CPU address to the AND gates 22A,.

  AND gates 22A,..., 22N are provided corresponding to the number of serial transmission / reception circuits 10. The AND gates 22A,..., 22N calculate the logical product of the output signal supplied from the address decoder 21 and the CPU write pulse supplied from the CPU 4 and indicating a CPU data write pulse to be described later. , 23N is generated corresponding to the address indicated by.

  The control registers 23A,..., 23N are provided corresponding to the number of serial transmission / reception circuits 10. The control registers 23A,..., 23N are based on CPU data indicating write data from the CPU 4 and write signals supplied from the AND gates 22A,. The control information including the information regarding is held, and the transfer control signal including the control information is supplied to the corresponding serial transmission / reception circuit 10.

  As shown in FIG. 4, the memory control circuit 30 includes selectors 31a to 31d, an address register 32a, a read register 32b, a write register 32c, a write enable register 32d, a read enable register 32e, buffers 33A to 33C, and buffers 34A and 34B. Prepare.

  The selector 31a selects a predetermined memory address signal from each memory address signal supplied from each serial transmission / reception circuit 10, and supplies it to the address register 32a. The selector 31b selects predetermined write data from each write data supplied from each serial transmission / reception circuit 10, and supplies it to the write register 32c.

  The selector 31c selects a predetermined write request signal from each write request signal supplied from each serial transmission / reception circuit 10, and supplies it to the write enable register 32d. The selector 31d selects a predetermined Read request signal from each Read request signal supplied from each serial transmission / reception circuit 10, and supplies it to the Read enable register 32e.

  The address register 32a holds an address for accessing the shared memory 3 indicated by the memory address signal supplied from the selector 31a, and supplies the held address to the shared memory 3 via the buffer 33A. The Read register 32b holds the Read data supplied from the shared memory 3 via the buffer 33B, and supplies it to the serial transmission / reception circuit 10 that outputs a Read enable signal described later. The write register 32c is supplied from the selector 31b, holds write data for writing to the shared memory 3, and supplies the held write data to the shared memory 3 via the buffer 33C.

  The write enable register 32d holds the write request signal supplied from the selector 31c as a write enable signal for accessing the shared memory 3, and supplies the held write enable signal to the shared memory 3 via the buffer 34A. . The Read enable register 32e holds the Read request signal supplied from the selector 31d as a Read enable signal for accessing the shared memory 3, and supplies the held Read enable signal to the shared memory 3 via the buffer 34B. .

Next, the operation of the serial transfer device 1 having the above configuration will be described. First, a schematic operation of the entire serial transfer device 1 will be described with reference to FIG. In the serial transfer device 1, when the CPU 4 makes a data transmission request to the DMA control circuit 20, each serial transmission / reception circuit 10 accesses the shared memory 3 via the memory control circuit 30 and reads parallel data.
The serial transmission / reception circuit 10 converts the read parallel data into serial data and transmits the serial data to the connected external device.

  When the CPU 4 requests the DMA control circuit 20 to receive data, each serial transmission / reception circuit 10 receives serial data from an external device and converts it into parallel data. Then, the serial transmission / reception circuit 10 writes the converted parallel data into the shared memory 3 via the memory control circuit 30.

  At this time, the transmission / reception timing of serial data in each serial transmission / reception circuit 10 is controlled by the value indicated by the circulation counter signal output from the circulation counter 40. The serial transmission / reception circuit 10 corresponding to the circulation counter value Start transmission and reception.

  Next, the operation of the DMA control circuit 20 will be described with reference to FIGS. As shown in FIG. 1, during data transmission, a command (CPU data, CPU write pulse and CPU address in FIG. 3) for starting transmission of serial data from the CPU 4 is supplied to the DMA control circuit 20 via the CPU bus 6. Then, the DMA control circuit 20 decodes the CPU address by the address decoder 21. Then, the CPU data is written to the control registers 23A,..., 23N corresponding to the serial transmission / reception circuit 10 that performs data transmission in synchronization with the CPU write pulse by the AND gates 22A,.

  The control registers 23A,..., 23N hold control information including information relating to a transfer valid flag, a transmission / reception mode, and a transfer size indicating a data size to be transferred. The held control information is supplied to the serial transmission / reception circuit 10 as a transfer control signal.

  Next, the operation of the memory control circuit 30 will be described with reference to FIG. 1, FIG. 4, and FIG. When a write request signal that is a write request to the shared memory 3 is supplied from the serial transmission / reception circuit 10, the memory control circuit 30 selects the memory address signal supplied from the serial transmission / reception circuit 10 that has output the write request by the selector 31a. The address register 32a is loaded. Further, the memory control circuit 30 selects the write data supplied from the serial transmission / reception circuit 10 that has output the write request by the selector 31b, and loads the write data into the write register 32c. Further, the memory control circuit 30 calculates a logical sum of the write request signal supplied from the serial transmission / reception circuit 10 by the selector 31c and loads the logical sum into the write enable register 32d.

  Then, the memory control circuit 30 asserts the write enable signal output from the write enable register 32d, and writes the write data output from the write register 32c to the address output from the address register 32a in the shared memory 3. .

  On the other hand, when a Read request signal that is a read request to the shared memory 3 is supplied from the serial transmission / reception circuit 10, the memory control circuit 30 uses the selector 31a to receive the memory address signal supplied from the serial transmission / reception circuit 10 that has output the read request. Select and load into address register 32a. Further, the memory control circuit 30 calculates a logical sum with the selector 31d with respect to the Read request signal supplied from the serial transmission / reception circuit 10, and loads it into the Read enable register 32e.

  Then, the memory control circuit 30 asserts the Read enable signal output from the Read enable register 32e, reads the Read data from the address output from the address register 32a in the shared memory 3, and loads it into the Read register 32b. Read data is supplied to the serial transmission / reception circuit 10.

  FIG. 5 is a timing chart showing the timing at which the memory control circuit 30 accesses the shared memory 3. “Serial CLK” is a clock used for serial transfer. “MEM CLK” is a clock of the memory control circuit 30 and is set to be faster than the serial CLK. In this example, the frequency is set to twice the frequency of the serial CLK.

  “MEM address” indicates the type of address loaded in the address register 32a. In this example, “Write address” indicates a write address, and “Read address” indicates a read address.

  “MEM Read enable” is a signal indicating whether or not reading to the shared memory 3 is valid, and indicates that this signal is valid from the falling edge to the rising edge. “MEM Write Enable” is a signal indicating whether or not writing to the shared memory 3 is valid, and indicates that this signal is valid from the falling edge to the rising edge. “MEM Read data” indicates the timing for reading data from the shared memory 3, and “MEM Write data” indicates the timing for reading data from the shared memory 3.

  That is, in this example, the timing at which writing or reading is valid is synchronized with the waveform of the serial CLK, and the period from timing T1 to T3 is the timing for writing data to the shared memory 3, and from timing T3 to T5 The period until is the timing for reading data from the shared memory 3.

  Note that the system clock for operating the entire serial transfer device 1 is a signal different from the serial CLK, and although not particularly shown, the same signal may be used for the system clock and the serial CLK.

  Next, transmission and reception operations in the serial transmission / reception circuit 10 will be described with reference to a flowchart shown in FIG. In the following, for ease of explanation, a case where transmission and reception operations are performed by any one of the plurality of serial transmission / reception circuits 10A, 10B, 10C,. .

  First, based on the value of the transfer valid flag included in the transfer control signal supplied from the memory control circuit 30, it is determined whether or not to transfer data (step S1). The transfer valid flag is information whose value is “1” when data transfer is performed. If the value of the valid flag is “1” (step S1: Yes), the process proceeds to step S2. On the other hand, when the value of the valid flag is other than “1” (step S1: No), the process returns to step S1, and the presence / absence of data transfer is determined again based on the value of the valid flag.

  Next, in step S2, it is determined whether the operation mode is the transmission mode or the reception mode based on the information indicating the transmission / reception mode included in the transfer control signal. When the operation mode is “transmission mode” (step S2: transmission), the process proceeds to step S3, where the circulation counter signal supplied from the circulation counter 40 and the circuit supplied from the circuit number clamp logic unit 14 are processed. Based on the number clamp signal, it is determined whether or not the two signals match (step S3).

  When it is determined that the circulation counter signal and the circuit number clamp signal match (step S3: Yes), the process proceeds to step S4. When it is determined that they do not match (step S3: No), again, It is determined whether or not the circulation counter signal and the circuit number clamp signal match.

  In step S4, the read request signal is asserted and the memory address signal is output by the serial control circuit 12 of FIG. Then, the data load signal is asserted, and the shift register 11 is loaded with one word in the read data (parallel data).

  In step S5, the data shift signal is asserted by the serial control circuit 12, and the shift register 11 is shifted by 1 bit and output as output data (serial data). At this time, an IO control signal is supplied from the serial control circuit 12 to the IO buffer 13, and the IO buffer 13 transmits output data from the shift register 11 to the external device. Also, an enable signal for the external device is asserted by the serial control circuit 12 and transmitted to the external device together with the input / output mode signal indicating the output mode and the transfer CLK signal.

  Next, it is determined whether or not the last 1 bit of one word in the Read data loaded in the shift register 11 has been output (step S6). If it is determined that the last 1 bit has not been output (step S6: No), the process returns to step S5, the next 1 bit is output, and thereafter, until the last 1 bit is output. The process of step S5 is performed.

  On the other hand, when it is determined that the last one bit has been output (step S6: Yes), the process proceeds to step S7, and information indicating the transfer size included in the transfer control signal supplied from the memory control circuit 30 Whether or not the data transfer for the transfer size has been completed is determined based on the actual number of transferred data (step S7). When it is determined that the transfer size matches the number of transfer data (step S7: Yes), a series of processing ends.

  If it is determined that the transfer data number is smaller than the transfer size and the transfer size and the transfer data number do not match (step S7: No), the process returns to step S4, and the read data from the shared memory 3 is read. The next one word of data is loaded.

  On the other hand, when the operation mode is “reception mode” in step S2 (step S2: reception), the process proceeds to step S8, where the circulation counter signal supplied from the circulation counter 40 and the circuit number clamp logic unit Whether the two signals match is determined based on the circuit number clamp signal supplied from 14 (step S8).

  When it is determined that the circulation counter signal and the circuit number clamp signal match (step S8: Yes), the process proceeds to step S9, and when it is determined that they do not match (step S8: No), again, It is determined whether or not the circulation counter signal and the circuit number clamp signal match.

  In step S9, the enable signal for the external device is asserted by the serial control circuit 12 of FIG. 2, and is transmitted to the external device together with the input / output mode signal indicating the input mode and the transfer CLK signal. Also, an IO control signal is supplied from the serial control circuit 12 to the IO buffer 13, and the IO buffer 13 supplies input data (serial data) from an external device to the shift register 11. The data shift signal is asserted by the serial control circuit 12, the shift register 11 is shifted by 1 bit, and input data (serial data) is input.

  Next, in step S10, it is determined whether or not the transfer of input data for one word has been completed. If it is determined that the data transfer for one word has been completed (step S10: Yes), the process proceeds to step S11, the write request signal is asserted by the serial control circuit 12, and the memory address signal is output. Write data (parallel data) is output from the shift register 11.

  On the other hand, if it is determined in step S10 that the data transfer for one word has not been completed (step S10: No), the process returns to step S9, and the next 1 bit is input.

  Next, based on the information indicating the transfer size included in the transfer control signal supplied from the memory control circuit 30 and the number of actually transferred data, it is determined whether or not the data transfer for the transfer size has been completed. (Step S12). If it is determined that the transfer size matches the number of transfer data (step S12: Yes), a series of processing ends. On the other hand, when it is determined that the number of transfer data is smaller than the transfer size and the transfer size does not match the number of transfer data (step S12: No), the process returns to step S9.

  FIG. 7 shows an example of a timing chart when data is transmitted in the single serial transmission / reception circuit 10. In this example, a case where the circuit number of the serial transmission / reception circuit 10 is “1” and data of two words is transmitted will be described.

  In this example, the value of the circulation counter signal output from the circulation counter 40 and the value of the circuit number clamp signal output from the circuit number clamp logic unit 14 are timings for the circulation counter determination process shown in step S3 of FIG. Since they match at T2, at the next timing T3, data reading processing for one word from the shared memory 3 in step S4 is performed.

  At the next timings T4 to T19, serial data D0 to D7 based on the read data for one word are output. At this time, the final 1-bit determination process in step S6 and the transfer end determination process for the data size are performed at timing T17. In this example, data for two words is transmitted, and at this point in time, data for the second word is not transmitted, so the process returns to step S4.

  Then, at the timing T19, the data reading process for the next second word is performed, and at the timings T20 to T35, serial data D8 to D15 based on the read second word data are output. At this time, the final 1-bit determination process in step S6 and the transfer end determination process for the data size are performed at timing T33. In this example, since data transmission for two words has been performed at this time, a series of processing ends at timing T36.

  FIG. 8 shows an example of a timing chart when data is received by a single serial transmission / reception circuit 10. In this example, the value of the circulation counter signal output from the circulation counter 40 and the value of the circuit number clamp signal output from the circuit number clamp logic unit 14 are timings for the circulation counter determination process shown in step S8 of FIG. Since they coincide at T2, the input processing of the serial data D0 to D7 in step S9 is performed at timings T4 to T19.

  At this time, the end processing of one word transfer is performed at timing T19, the writing processing of the parallel data for one word converted from the serial data in step S11 to the shared memory 3 is performed, and the data size corresponding to the data size in step S12 is performed. A transfer end determination process is performed. In this example, data for two words is received, and at this time, data for the second word has not been received, so the process returns to step S9.

  Then, at timings T20 to T35, input processing of serial data D8 to D15 corresponding to the next second word data is performed. A one-word transfer end process is performed at timing T35, a one-word parallel data converted from serial data is written to the shared memory 3, and a transfer end determination process for the data size is performed. In this example, since data reception for two words has been performed at this time, a series of processing ends at timing T36.

  Next, a case where all the serial transmission / reception circuits 10 transmit / receive data will be described. Hereinafter, a case where data transmission / reception is performed using six serial transmission / reception circuits 10A to 10F will be described as an example, and a case where the circuit numbers in the serial transmission / reception circuits 10A to 10F are “1” to “6” will be described. .

  First, as a first example, a case where serial transmission / reception circuits 10A to 10C transmit data for two words and serial transmission / reception circuits 10D to 10F receive data for two words will be described with reference to FIG. .

  As illustrated in FIG. 9, the serial transmission / reception circuit 10 </ b> A starts operating at a timing T <b> 2 when the value of the circulation counter signal output from the circulation counter 40 becomes “1”. Then, the serial transmission / reception circuit 10A reads parallel data for one word from the shared memory 3 at timing T3, and transmits serial data D0 to D7 obtained by converting the read parallel data at timings T4 to T19.

  Here, the timing T18 is a timing for transmitting the last one bit when transmitting serial data for one word. In this example, data for two words is transferred. Therefore, the serial transmission / reception circuit 10A accesses the shared memory 3 again at the next timing T19, reads the next one word of parallel data, and converts the read parallel data at the timing T20 to T35. -D15 is transmitted.

  At this time, since the timing T34 is a timing for transmitting the last one bit of the serial data of the second word, the serial transmission / reception circuit 10A ends the data transfer at the timing T36.

  Further, the serial transmission / reception circuit 10B starts operation at timing T4 when the value of the circulation counter signal becomes “2”, and parallel data for one word from the shared memory 3 is received at timing T5 in the same manner as the serial transmission / reception circuit 10A. Read, serial data D0 to D7 are transmitted at timings T6 to T21.

  Here, the timing T20 is a timing for transmitting the last one bit when serial data for one word is transmitted. In this example, data for two words is transferred. Therefore, the serial transmission / reception circuit 10B accesses the shared memory 3 again at the next timing T21, reads the parallel data for the next one word, and transmits the serial data D8 to D15 at the timings T22 to T37.

  At this time, since the timing T36 is a timing for transmitting the last one bit of the serial data of the second word, the serial transmission / reception circuit 10B ends the data transfer at the timing T38.

  Further, the serial transmission / reception circuit 10C starts operation at timing T6 when the value of the circulation counter signal becomes “3”, and in parallel with the serial transmission / reception circuits 10A and 10B, parallel processing for one word from the shared memory 3 is performed at timing T7. Data is read and serial data D0 to D7 are transmitted at timings T8 to T23.

  Here, the timing T22 is a timing for transmitting the last one bit when transmitting serial data for one word, and in this example, data for two words is transferred. Therefore, the serial transmission / reception circuit 10C accesses the shared memory 3 again at the next timing T23, reads the next one word of parallel data, and transmits the serial data D8 to D15 at the timings T24 to T39.

  At this time, since the timing T38 is a timing for transmitting the last one bit of the serial data of the second word, the serial transmission / reception circuit 10C ends the data transfer at the timing T40.

  On the other hand, the serial transmission / reception circuit 10D starts operating at timing T8 when the value of the circulation counter signal becomes “4”, and receives serial data D0 to D7 at timings T10 to T25. Here, the timing T25 is a timing for receiving the last one bit in the serial data for one word, and the data for one word is prepared by receiving the last one bit. Therefore, the serial transmission / reception circuit 10D accesses the shared memory 3 at timing T26 and writes parallel data for one word obtained by converting serial data.

  Furthermore, in this example, since data for two words is received, serial data D8 to D15 corresponding to the next second word are received at timings T26 to T41. Timing T41 is a timing for receiving the last 1 bit in the serial data corresponding to the second word. By receiving the last 1 bit, data for one word is prepared. Therefore, the serial transmission / reception circuit 10D accesses the shared memory 3 at timing T42, writes parallel data for one word obtained by converting serial data, and ends the data transfer.

  Further, the serial transmission / reception circuit 10E starts operation at timing T10 when the value of the circulation counter signal becomes “5”, and serial data D0 to D7 are received at timings T12 to T27, similarly to the serial transmission / reception circuit 10E. Here, the timing T27 is a timing for receiving the last 1 bit in the serial data for one word, and the data for one word is prepared by receiving the last 1 bit. Therefore, the serial transmission / reception circuit 10E accesses the shared memory 3 at the timing T28, writes the parallel data for one word obtained by converting the serial data, and at the timing T28 to T43, the serial corresponding to the next second word. Data D8 to D15 are received.

  The timing T43 is a timing for receiving the last 1 bit in the serial data corresponding to the second word. Since the last 1 bit is received, data for one word is prepared. At time T44, the shared memory 3 is accessed, parallel data for one word converted from serial data is written, and the data transfer is completed.

  Further, the serial transmission / reception circuit 10F starts operation at the timing T12 when the value of the circulation counter signal becomes “6”, and receives the serial data D0 to D7 at the timings T14 to T29 similarly to the serial transmission / reception circuits 10D and 10E. To do. Here, the timing T29 is a timing for receiving the last 1 bit in the serial data for 1 word, and the data for 1 word is prepared by receiving the last 1 bit. Therefore, the serial transmission / reception circuit 10F accesses the shared memory 3 at the timing T30, writes parallel data for one word obtained by converting the serial data, and at the timing T30 to T45, the serial corresponding to the next second word. Data D8 to D15 are received.

  The timing T45 is a timing for receiving the last 1 bit in the serial data corresponding to the second word. Since the last 1 bit is received, data for one word is prepared. At time T46, the shared memory 3 is accessed, parallel data for one word converted from serial data is written, and the data transfer is completed.

  Next, as a second example, FIG. 10 shows a case where the serial transmission / reception circuits 10A, 10C, and 10E transmit data for two words and the serial transmission / reception circuits 10B, 10D, and 10F receive data for two words. The description will be given with reference.

  Also in the second example, data transmission / reception is performed in each serial transmission / reception circuit 10 as in the first example described above. Here, as shown in FIG. 10, the serial transmission / reception circuit 10B accesses the shared memory 3 and writes parallel data for one word at timing T22 because data for one word is prepared at timing T21. On the other hand, the serial transmission / reception circuit 10C transmits the last one bit of the serial data at timing T22, accesses the shared memory 3 at the next timing T23, and reads the data of the next second word.

  At this time, since the timings T22 and T23 are the same timing when considered in the timing unit of the circulation counter 40, the serial transmission / reception circuits 10B and 10C access the shared memory 3 at the same time. Then, since the write operation is performed by the serial transmission / reception circuit 10B and the read operation is performed by the serial transmission / reception circuit 10C at the timing T23, the contention with the shared memory 3 does not occur.

  The same applies to timings T26 and T27 in which access to the shared memory 3 is simultaneously performed by the write operation by the serial transmission / reception circuit 10D and the read operation by the serial transmission / reception circuit 10E.

  Next, as a third example, a case where data having a different transfer size is transmitted / received for each serial transmission / reception circuit 10 will be described with reference to FIG. In this example, the serial transmission / reception circuits 10A to 10C transmit data, the serial transmission / reception circuits 10D to 10F receive data, the serial transmission / reception circuit 10B has three words, the serial transmission / reception circuit 10D has four words, and the others. Assume that the serial transmission / reception circuits 10A, 10C, 10E, and 10F transfer data for one word.

  In this case, data transmission / reception by the serial transmission / reception circuits 10A to 10F is performed in the same manner as in the first and second examples described above.

  After completion of the transfer, the serial transmission / reception circuit 10A accesses the shared memory 3 at the timing T35 when the circulation counter value from the circulation counter 40 becomes “1”, and transmits the serial data D0 to D7 at the timing T36. At this time, the serial transmission / reception circuit 10B continues to transmit the serial data D0 to D23. However, since access to the shared memory 3 is performed at timing T37, contention for access to the shared memory 3 by the serial transmission / reception circuits 10A and 10B. Does not occur.

  Further, the serial transmission / reception circuit 10E starts receiving serial data from the timing T44 when the circulation counter value from the circulation counter 40 becomes “6” after the transfer is completed, and the parallel data shared memory obtained by converting the serial data at the timing T60. 3 is written. At this time, the serial transmission / reception circuit 10D continues to transfer data. However, since access to the shared memory 3 is performed at timing T58, there is no contention for access to the shared memory 3 by the serial transmission / reception circuits 10D and 10E.

  Next, access to the shared memory 3 in the third example will be described with reference to the memory map shown in FIG. In FIG. 12, “h” described immediately after the numerical value of the address indicates that the numerical value immediately before is in hexadecimal notation.

  In the memory map shown in FIG. 12, for example, the serial transmission / reception circuit 10A uses addresses “0100h” to “0200h” and increments the address by 1 for each access when transferring data for one word.

  Similarly, the serial transmission / reception circuit 10B uses addresses “0200h” to “0300h”, and the serial transmission / reception circuit 10C uses addresses “0300h” to “0400h”. The serial transmission / reception circuit 10D uses addresses “0400h” to “0700h”, and the serial transmission / reception circuit 10E uses addresses “0700h” to “0800h”. Further, the serial transmission / reception circuit 10F uses addresses “0800h” to “0900h”.

  Here, the serial transmission / reception circuit 10D has a large memory area because the amount of data to be transferred is larger than that of other serial transmission / reception circuits. Thus, a memory map can be arbitrarily configured according to the amount of data transferred by each serial transmission / reception circuit 10.

  As described above, according to the first embodiment, since the plurality of serial transmission / reception circuits are operated in parallel according to the value of the circulation counter, the data transfer performance can be improved. In addition, when operating serial transmission / reception circuits in parallel, contention between the write operation and read operation to the shared memory can be prevented, and transmission / reception by a plurality of serial transmission / reception circuits can be arbitrarily set. The waiting time can be reduced, and the data transfer performance can be improved.

  Furthermore, in order to prevent contention for the shared memory, the buffer provided in each serial transmission / reception circuit that has been conventionally required can be omitted. Thereby, the hardware of the apparatus can be reduced. Furthermore, since transmission / reception operations by a plurality of serial transmission / reception circuits are controlled based on the circulation counter, the conventionally provided arbitration circuit can be omitted, and the logic circuit can be simplified.

  Next, a second embodiment of the serial transfer device according to the present invention will be described. In the serial transfer device 1 ′ according to the second embodiment, the shared memory 3 is configured by a dual port RAM so that it can be accessed by two memory buses 5 </ b> A and 5 </ b> B.

  The serial transfer unit 2 ′ includes memory control circuits 30 </ b> A and 30 </ b> B instead of the memory control circuit 30 in the first embodiment, and controls, for example, half of the plurality of serial transmission / reception circuits 10. Thereby, since simultaneous access of two systems to the shared memory 3 is permitted, data transmission / reception by the two systems can be performed simultaneously.

  The serial transmission / reception circuit 10 assigned to the memory control circuits 30A and 30B may be set according to the transfer data length, for example. Specifically, for example, the serial transmission / reception circuit 10 having a long transfer data length is assigned to the memory control circuit 30A, and the serial transmission / reception circuit 10 having a short transfer data length is assigned to the memory control circuit 30B. May be.

  Further, since the addresses of the shared memory 3 accessed by the serial transmission / reception circuits 10 are mutually exclusive, a limited operation such as the same address access of the dual port RAM is not performed.

  As described above, according to the second embodiment, two memory control circuits are provided and the shared memory can be accessed in two systems, so that two systems can access the shared memory simultaneously. .

  In addition, since two systems can simultaneously access the shared memory, the overall data transfer performance can be improved even when the number of serial transmission / reception circuits increases. Specifically, for example, assuming that the earliest data transfer start is the 0th cycle, the latest data transfer start cycle can be shortened to half that of the prior art.

  Although the first and second embodiments of the present invention have been described above, the present invention is not limited to the above-described configuration, and various modifications are possible within the scope of the invention described in the claims. It is. For example, the data width of the shared memory 3 may be widened and the data for one access may be 2 words or more.

1, 1 'serial transfer device 2, 2' serial transfer unit 3 shared memory 4 CPU
5 (5A, 5B) Memory bus 6 CPU bus 10 (10A, 10B, 10C, 10D, 10E, 10F,..., 10N) Serial transmission / reception circuit 11 Shift register 12 Serial control circuit 13 IO buffer 14 Circuit number clamp logic unit 15 (15A, 15B, 15C) Buffer 20 DMA control circuit 21 Address decoder 22 (22A,..., 22N) AND gate 23 (23A,..., 23N) Control register 30 (30A, 30B) Memory control circuit 31 (31a, 31b, 31c, 31d) Selector 32a Address register 32b Read register 32c Write register 32d Write enable register 32e Read enable register 33 (33A, 33B, 33C) Buffer 34 (34A, 34B) Buffer 4 Circulation counter

Claims (6)

Randomly accessible shared memory for storing parallel data, a serial transfer circuit that converts the parallel data and serial data, and transmits and receives data between the external device and the shared memory, and data by the serial transfer circuit A DMA transfer control circuit for controlling the transmission / reception of data to be performed by DMA transfer,
The serial transfer circuit is
A plurality of serial transmission / reception circuits for transmitting / receiving serial data to / from the external device;
A memory control circuit for controlling access to the shared memory by the plurality of serial transmission / reception circuits;
A circulation counter that cyclically outputs a predetermined value in synchronization with a predetermined synchronization signal;
The serial transfer device, wherein the plurality of serial transmission / reception circuits perform transmission / reception of the serial data to / from the external device in accordance with an output value from the circulation counter.   2. The plurality of serial transmission / reception circuits are set with a unique circuit number in advance, and perform a transmission / reception operation when a value output from the circulation counter matches the circuit number. Serial transfer device.   The DMA transfer control circuit performs a data reception operation from the external device by the plurality of serial transmission / reception circuits at different timings for each of the serial transmission / reception circuits according to the value of the circulation counter, and the plurality of serial transmission / reception circuits. 3. The serial according to claim 1, wherein a transmission operation of data to the external device by the transmission / reception circuit is controlled to be executed at a different timing for each serial transmission / reception circuit according to a value of the circulation counter. Transfer device.   The serial transfer circuit performs a write operation on the shared memory when serial data received from the external device reaches an accessible amount of the shared memory. 3. The serial transfer device according to 3.   5. The serial transfer circuit performs a read operation from the shared memory before an amount of serial data to be transmitted to the external device reaches an amount read from the shared memory. The serial transfer device according to any one of the above. Conversion between parallel data stored in the shared memory and serial data for transmission / reception to / from an external device is performed by a plurality of serial transmission / reception circuits, and data transmission / reception between the external device and the shared memory is performed using DMA transfer. A serial transfer method to perform,
In accordance with an output value from a circulation counter that cyclically outputs a predetermined value in synchronization with a predetermined synchronization signal, the serial transmission / reception circuit corresponding to the output value transmits / receives the serial data to / from the external device. A serial transfer method characterized by the above.

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