JP4799137B2 - Bus system - Google Patents

Description

  The present invention relates to a bus system in which bus connection is performed using register slice means.

  In recent years, the miniaturization of processes has progressed, and the circuit scale built in LSI has reached tens of millions of gates.

  On the other hand, various problems have become prominent due to the influence of miniaturization of the device size. Among them, an increase in wiring delay inside the LSI is an important problem.

  As a system that is greatly affected by the wiring delay inside the LSI, there is a system bus that connects modules by wiring.

  Today, as a system bus inside LSI, for example, AMBA (version 2.0) specified by British ARM or AHB which is one of the buses in the standard is an industry standard (for example, see Patent Document 1). . AMBA is an abbreviation for “Advanced Microcontroller Bus Architecture”, and AHB is an abbreviation for “Advanced High-Performance Bus”.

  The AHB has a so-called shared bus structure, and a plurality of bus masters and a plurality of slaves are connected by a single bus structure. This bus structure is composed of elements such as an address decoder, a multiplexer, and a demultiplexer. Since this is a shared bus, the same signal wiring is routed over a long distance inside the LSI so that all masters or all slaves can observe the same bus signal.

  Since the AHB has such a configuration, as described above, it is difficult to increase the operating frequency at present when the wiring delay has become a problem.

  Therefore, AMBA version 3.0 has been formulated by ARM as a new bus standard, and AXI defined therein is drawing attention as a candidate for the next generation system LSI standard bus. AXI (Advanced eXtensible Interface) is an interface that defines a point-to-point connection between an initiator and a target, not a shared bus structure like AHB.

  In the AXI protocol, addresses, commands, and data are separated into different channels, and are transmitted by a simple two-wire handshake using a Valid signal and a Ready signal for each channel.

  That is, one transfer is established in a cycle in which both the Valid signal asserted by the initiator and the Ready signal asserted by the target are asserted simultaneously.

  AXI is a protocol specification and does not specify the implementation of the bus connection network. Usually, realization with a crossbar structure, a multilayer structure, or the like is assumed. ARM supplies the PrimeCell PL300 with a multilayer structure as its IP (Intellectual Property) core.

  As described above, since the AXI protocol transfers between two points according to a simple handshake, a latch mechanism called “register slice” can be inserted between the two points. This register slice is inserted when the delay time between the two points is long and the required operating frequency cannot be achieved.

  For example, when the path delay between the target and the initiator is 2 ns and the operating frequency is 800 MHz (1 period = 1.25 ns), the delay value is divided into about 1 ns by inserting a register slice between the two points. be able to. Accordingly, it is possible to achieve a necessary operating frequency.

  On the other hand, a disadvantage of inserting a register slice is that a delay of one cycle occurs due to the latch. Note that the signal propagation direction is not only one direction from the initiator to the target, but also the response signal (Ready signal) direction from the target to the initiator. For this reason, the timing of handshaking cannot be achieved simply by latching each signal with a single-stage flip-flop (FF).

  That is, both the initiator and the target receive the signal output one cycle before on the other side.

  In order to solve this problem, for example, a register slice may be configured using two stages of FFs. However, when a two-stage FF is used, the disadvantage is that the circuit scale increases and the latency increases.

  Therefore, the above-described demerit can be eliminated by using two stages of half latches using the positive and negative phases of the clock instead of the FF.

  FIG. 1 shows an example in which a register slice is constituted by a half latch. In FIG. 1, the left side is the initiator side signal, and the right side is the target side signal. The half latch shown in FIG. 1 is in a transparent state when the EN input is 1.

  FIG. 2 shows a timing chart of the register slice. In FIG. 2, the hatched portion represents the holding operation of the half latch. That is, the timing of EN = 0.

  As can be seen from FIG. 2, when the Ready signal from the target is deasserted, the timing of handshaking is generated by masking the data holding operation.

  FIG. 3 shows an example of a system configured using such a register slice. The arrow in the figure is one channel, and five channels are defined in the AXI protocol.

  As described above, the register slice has an effect of improving the operating frequency by dividing the path delay between two points, but there is an increase in latency as a drawback. In particular, in a system that requires high-speed operation, register slices need to be placed in multiple stages, but the latency deteriorates according to the number of stages.

In particular, from the viewpoint of power consumption, etc., even in a system that does not always operate at the highest operating frequency but takes the optimum operating frequency as required, register slices are inserted as necessary at the highest operating frequency. There is a need. Therefore, it is conceivable to improve the latency by bypassing the register slice when the operating frequency of the system is low.
JP 2004-178570 A

  However, there is a problem to be considered when attempting to change bypass and non-bypass of the register slice at the same time when changing the operating frequency of the system.

  In other words, if a new register slice to be bypassed holds valid commands and data, it must wait for the commands and data to reach the target and shift to the bypass state. .

  The simplest way to solve this problem is to provide a special waiting period for operating frequency switching, as is done elsewhere for normal operating frequency switching. Then, after waiting for the frequency to be changed by handshaking, the frequency is switched.

  Specifically, in the case of a register slice, it is prohibited to newly issue a bus transfer command to all masters, and it is confirmed that the slave has processed all the commands that have already been issued. Then, after confirming, the frequency is changed and the master is allowed to issue a new bus transfer command.

  This ensures that valid commands present in the register slice are flushed, and that no problem occurs even when the bypass state is entered.

  However, in the above-described method, all issued commands must be processed from when the system operating frequency switching is instructed to when the operating frequency is actually switched. Therefore, there is a problem that it takes too much time especially when register slices are inserted in multiple stages.

  Furthermore, it is necessary to perform this handshake explicitly as system control, and the problem is that the mechanism for switching the operating frequency becomes complicated.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to perform a dynamic operation frequency switching operation of a system with a simple configuration and at high speed.

The present invention has, on a bus connecting between the initiator and the target, a bus system having a plurality of latching means, at least one of said plurality of latching means includes a bypass means for bypassing the latching operation, Receiving a bypass selection signal for selecting whether or not to bypass the latch operation from the initiator side, and transmitting the bypass selection signal to the target side latch means; and the latch according to the bypass selection signal And determining means for determining whether to bypass the operation.

According to the present invention, when switching the operating frequency of the system, it is not necessary to provide a waiting time required for flash register slice is bypassed, it becomes possible to perform the bypass switching of the register slice seamlessly.

  The best mode for carrying out the invention will be described below in detail with reference to the drawings.

  FIG. 4 is a diagram illustrating a configuration of a register slice in the present embodiment. In FIG. 4, reference numeral 401 denotes a bypass signal transmission unit that receives a bypass signal from the initiator and transmits the bypass signal to the target side. The bypass signal transmission unit 401 does not simply transmit a bypass signal. That is, it has a function of notifying that a bypass signal has been received to a bypass state transition unit, which will be described later, and transmitting the bypass signal after the bypass state transition unit is permitted to transmit the bypass signal.

  A bypass state transition unit 402 is a state machine that controls transition between the bypass state and the non-bypass state. When the bypass signal reception notification is received from the bypass signal transmission unit 401, the internal state is changed according to the value of the signal. Transition. Details of this state transition will be further described later with reference to FIG.

  Reference numeral 403 denotes a response suppression unit. When a bypass transition instruction signal is received from the bypass state transition unit 402, the reception response signal (Ready signal) is maintained in the deasserted state by the response suppression signal.

  A reset unit 404 receives a reset signal from the bypass state transition unit 402 and resets a half latch 421 described later.

  Reference numerals 410 to 413 and 420 to 422 denote half latches which hold transmission data when the EN terminal is 1 and hold output data when the EN terminal is 0. In particular, the half latch 421 is a half latch that includes a reset terminal and is reset by a reset signal from the reset unit 404.

  FIG. 5 is a diagram illustrating state transitions in the bypass state transition unit 402 illustrated in FIG. 4. First, the transition from the non-bypass state to the bypass state will be described.

  In the present embodiment, the initial state is placed in a non-bypass state. In this state, when a bypass signal reception notification is received and the signal indicates a transition from the non-bypass state to the bypass state, the state transits to the bypass transition state. While in this state, the bypass state transition unit 402 asserts the bypass transition instruction signal to the response suppression unit 403. When this signal is asserted, the response suppression unit 403 sets the response suppression signal, which is the output signal, to “0”. As a result, the Ready signal for the initiator becomes “0”, the Valid signal from the initiator is masked, and new valid data is not captured.

  Next, the condition that the Valid signal held in the half latch 411 is “0”, the Valid signal held in the half latch 421 is “0” or “1”, and the Ready signal from the target is “1” is satisfied. Wait until you do. Thereafter, when this condition is satisfied and there is no valid data to be held inside, the state transits to the bypass state. At the same time, the bypass state transition unit 402 gives a bypass signal transmission permission to the bypass signal transmission unit 401. During this state, the bypass state transition unit 402 continues to assert the register bypass signal. This register bypass signal is a signal for fixing the signal value of the EN terminal in all the half latches to “1”. As a result, all the half latches become transparent. As a result, the register slice is bypassed.

  Next, the transition from the bypass state to the non-bypass state will be described.

  When in the bypass state, when a bypass signal reception notification is received and the signal indicates a transition from the bypass state to the non-bypass state, the state transits to the non-bypass transition state. At the same time, the bypass state transition unit 402 gives a bypass signal transmission permission to the bypass signal transmission unit 401. In this state, the register slice shifts to a non-bypass state, and the bypass state transition unit 402 deasserts the register bypass signal described above and asserts a reset signal to the reset unit 404. Since this state unconditionally transits to the non-bypass state, the reset signal is asserted for only one cycle period.

  Here, taking the system shown in FIG. 6 as an example, the operation of the register slice and the transition between the bypass and non-bypass states will be described in more detail using the timing chart shown in FIG.

  FIG. 6 is a diagram illustrating an example of a system configuration in the present embodiment. As shown in FIG. 6, three register slices 603, 604, and 605 are inserted between one master 601 and one slave 602. Here, the register slices 603 and 605 can be switched between a bypass state and a non-bypass state. The register slice 604 is always in a non-bypass state, and a bypass signal input from the initiator side is transmitted to the target side after a delay of one cycle.

  In the timing chart shown in FIG. 7, only the command channel from the master to the slave will be described as an example for simplicity of explanation.

First, the case where the system operating frequency is changed from the higher side to the lower side will be described. In the first cycle shown in FIG. 7, the register slice 603-60 5, operating in all non-bypassed state. By switching to the low system operating frequency side, the master 601 asserts a bypass signal in cycle 3 to switch the register slices 603 and 605 to the bypass state.

  When the register slice 603 receives the bypass signal, the ready signal is first deasserted in cycle 4 in accordance with the state transition shown in FIG. Next, when a handshake with the register slice 604 is established at the end of the cycle 4, the register slice 603 shifts to a bypass state in the cycle 5, and asserts a bypass signal output.

  In cycle 5, the register slice 604 also receives the bypass signal. However, since the register slice 604 remains in the non-bypass state, the bypass signal output is asserted in cycle 6 after one cycle, and other operations remain the same as before. .

  In cycle 6, when the register slice 605 receives the bypass signal, the register slice 605 operates to deassert the ready signal in cycle 7 according to the state transition shown in FIG.

  However, cycle 7 is a cycle in which a ready signal is originally deasserted in a normal handshake operation of a register slice. That is, at the beginning of cycle 7 even after receiving the bypass signal, two stages of valid commands (cmd-2 and cmd-3) are held in the register slice.

  In cycle 7 and cycle 8, there are no valid commands held in the register slice 605 when two handshakes are established with the slave 602. Then, in cycle 9, the register slice 605 enters the bypass state and asserts the bypass signal output.

  It should be noted here that when the frequency is lowered, the timing constraint between paths is satisfied even if the register slice is in a bypass state or a non-bypass state. That is, in the series of operations described above, the actual operating frequency can be switched at any timing. For example, switching may be performed in cycle 2, and cycle 5 or cycle 11 may be used.

  Next, a case where the system operating frequency is changed from the low side to the high side will be described. In this case, the master 601 deasserts the bypass signal in cycle 13 to switch the register slices 603 and 605 to the non-bypass state by switching to the higher system operating frequency.

  When the register slice 603 receives the bypass signal, the register slice 603 transits to the non-bypass state in the cycle 14 according to the state transition shown in FIG. At the same time, the half latch 421 is reset and the bypass signal output is deasserted.

  In cycle 14, register slice 604 also receives the bypass signal, but register slice 604 remains in the non-bypass state, deasserts the bypass signal output in cycle 15 after one cycle, and other operations remain as before. is there.

  Then, when the register slice 605 receives the bypass signal, the register slice 605 transits to the non-bypass state in the cycle 17 in accordance with the state transition shown in FIG. At the same time, the half latch 421 is reset and the bypass signal output is deasserted.

  As described above, when the system operating frequency is increased, the timing constraint between paths cannot be satisfied even if a part of the register slice is in the bypass state. However, since it is guaranteed that all register slices are in the non-bypass state when the bypass signal reaches the slave, the operating frequency is switched with this.

  Needless to say, the present invention is not limited to the above-described embodiment, and other modifications and improvements are possible.

  For example, in the present embodiment, the register slice is configured using a half latch, but of course, the present invention is not limited to this.

  For example, a negative edge triggered flip-flop and a positive edge triggered flip-flop may be used. Moreover, you may comprise only using positive edge triggered flip-flop. In that case, what is necessary is just to comprise so that another path may be detoured using MUX as a bypass route.

  That is, the present invention is not limited to the specific forms shown in the above-described embodiments, and covers all modifications that do not depart from the spirit and scope of the present invention in the appended claims. It should be understood that you are thinking.

  According to the present embodiment, when switching the system operating frequency, it is not necessary to provide a waiting period required for flushing the register slice to be bypassed, and the register slice bypass switching can be performed seamlessly. As a result, the switching operation of the system operating frequency can be performed easily and at high speed.

  A recording medium recording software program codes for realizing the functions of the present embodiment is supplied to a system or apparatus, and a computer (CPU or MPU) of the system or apparatus reads the program codes stored in the recording medium. Execute. It goes without saying that the object of the present invention can also be achieved by this.

  In this case, the program code itself read from the recording medium realizes the functions of the above-described embodiment, and the recording medium storing the program code constitutes the present invention.

  As a recording medium for supplying the program code, for example, a flexible disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

  In addition, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also the following cases are included. That is, when the OS (operating system) running on the computer performs part or all of the actual processing based on the instruction of the program code, and the functions of the above-described embodiments are realized by the processing.

  Further, the program code read from the recording medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer. After that, based on the instruction of the program code, the CPU of the function expansion board or function expansion unit performs part or all of the actual processing, and the function of the above-described embodiment is realized by the processing. Needless to say.

It is a figure which shows the example which comprised the register slice by the half latch. FIG. 2 is a diagram showing a timing chart of the register slice shown in FIG. 1. It is a figure which shows an example of the system comprised using the register slice shown in FIG. It is a figure which shows the structure of the register slice in this embodiment. It is a figure which shows the state transition in the bypass state transition part 402 shown in FIG. It is a figure which shows an example of a structure of the system in this embodiment. It is a figure which shows an example of the operation timing of the system in this embodiment.

Explanation of symbols

401 Bypass signal transmission unit 402 Bypass state transition unit 403 Response suppression unit 404 Reset unit 410 Half latch 411 Half latch 412 Half latch 413 Half latch 420 Half latch 421 Half latch 422 Half latch 601 Master 602 Slave 603 Register slice 604 Register slice 605 Register slice

Claims (8)

On the bus which connects between the initiator and the target, a bus system having a plurality of latching means,
At least one of the plurality of latch means is
Bypass means for bypassing the latch operation;
A transmission means for receiving a bypass selection signal for selecting whether or not to bypass the latch operation from the initiator side, and transmitting the bypass selection signal to the latch means on the target side ;
A bus system comprising: determining means for determining whether or not to bypass the latch operation according to the bypass selection signal.   2. The bus system according to claim 1, wherein when a transition is made from a non-bypass state to a bypass state in response to the bypass selection signal, the state is shifted to the bypass state when handshaking with the target side is completed. . The determining means determines whether or not to bypass the latch operation based on a bypass selection signal received by the transmitting means. After the handshaking with the transmitting means of the latch means on the target side is established, the transmitting means The bus system according to claim 1, wherein the bypass selection signal is transmitted. The plurality of latch means shifts from the non-bypass state to the bypass state in response to the bypass selection signal when the handshaking with the target side is completed when the operating frequency of the system is increased. Item 4. The bus system according to any one of Items 1 to 3. When the operating frequency of the system is lowered, the plurality of latch means shift from the non-bypass state to the bypass state in response to the bypass selection signal regardless of the end of handshaking with the target side. The bus system according to any one of claims 1 to 4. Wherein when the bypass select signal by delaying output bus system according to any one of claims 1 to 5, characterized in that output with a the handshaking with the target side is complete. 7. The bus system according to claim 1, wherein at least one of the plurality of latch means maintains a non-bypass state regardless of the bypass selection signal. The plurality of latch means perform handshaking based on a Valid signal that is asserted to the target side and a Ready signal that is asserted from the target side,
The bus system according to any one of claims 1 to 7, wherein the plurality of latch means further include a reset means for resetting a flip-flop that holds a Valid signal asserted to the target side.

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