JP5428214B2 - Semiconductor wafer manufacturing method, semiconductor wafer, and semiconductor wafer crystal evaluation method - Google Patents

Description

  The present invention relates to a technique for evaluating crystal defects in a semiconductor wafer.

  Conventionally, a silicon wafer (a typical semiconductor wafer) is manufactured by flattening the surface of a wafer obtained by slicing a silicon single crystal ingot through a grinding process or a polishing process with high accuracy. (Note that each manufacturing process of such a silicon wafer is disclosed in detail in, for example, Patent Document 1), but all of the single crystal ingots are crystallized prior to manufacturing a silicon wafer as a product. Quality evaluations such as crystal defects caused by growth have been made.

And the silicon wafer (evaluation wafer) used for the quality evaluation of this silicon single crystal ingot is manufactured in the same manufacturing process as that for manufacturing a silicon wafer (product wafer) as an actual product. ing.
JP 2006-1000079 A

  FIG. 6 shows a typical manufacturing process for manufacturing a product wafer. Generally, a product wafer is sliced from a silicon single crystal ingot S110, and a double-sided grinding process in which the front and back surfaces (both sides) of the wafer sliced in the slicing step S110 are simultaneously subjected to rough grinding and flattened. S120, a single-sided grinding step S130 in which the front and back surfaces of the wafer obtained in the double-sided grinding step S120 are subjected to fine grinding in order one by one and flattened, and the front and back surfaces of the wafer obtained in the single-sided grinding step S130 are mirrored. The double-side polishing step S140 to be processed and the single-side polishing step S150 for polishing the surface of the wafer (the main surface on which the device is formed) obtained in the double-side polishing step S140 to finish the mirror surface are manufactured in this order. It is like that.

  However, since the manufacturing process of the evaluation wafer is complicated as in the case of the product wafer, it takes time to manufacture the evaluation wafer, and it takes several days to manufacture and evaluate the evaluation wafer. For this reason, the single crystal ingot must be stored for a long period of time before the evaluation is completed, but enormous costs are required to secure a space for the storage and to manage dust storage in the storage space.

Also, the equipment for manufacturing the evaluation wafer is usually prepared separately from the equipment for manufacturing the product wafer, and the manufacturing process of the evaluation wafer is as complex as the product wafer. In addition, the equipment for manufacturing the evaluation wafer is very expensive.
In addition, there is a strong demand not only for evaluation wafers but also for facilitating shortening of manufacturing time and manufacturing cost by making it possible to further simplify equipment and processes for manufacturing product wafers. In particular, in the double-side polishing step S140, mirror polishing must be performed until mechanical processing damage generated in the slicing step S110 and the grinding steps S120 and S130 is removed, which requires a long time and increases manufacturing costs. It is a big factor.

  The present invention has been devised in view of such problems, and can simplify the manufacture of semiconductor wafers and promote the reduction of manufacturing time and the reduction of manufacturing costs. An object of the present invention is to provide a semiconductor wafer manufacturing method, a semiconductor wafer, and a semiconductor wafer crystal evaluation method capable of reducing the time and cost required for evaluation.

In order to achieve the above object, a method for producing a semiconductor wafer according to claim 1 of the present invention is a method for producing a semiconductor wafer for producing an evaluation wafer for performing quality evaluation of a single crystal ingot, Slicing step of slicing the wafer from a single crystal ingot, and single wafer etching for rotating the wafer sliced in the slicing step and injecting an etching solution onto the surface of the rotated wafer to etch the surface of the wafer And a grinding process for grinding and flattening the surface of the wafer as a process immediately before the single wafer etching process. In the grinding process, a # 1000 to # 8000 grinding wheel is used. grinding the surface of the該枚wafer etching process, and set the uneven surface of the wafer as a reference after processing of the etching Comparing the concavo-convex shape of the surface of the wafer before the etching treatment with the concavo-convex shape of the surface of the wafer serving as a reference after the etching treatment, calculating the etching amount at each point of the wafer, the etching amount The surface of the wafer is etched so that

The method for producing a semiconductor wafer according to the present invention is the above-described method for producing a semiconductor wafer. In the grinding step, the wafer set in a carrier plate holder is divided into an upper surface plate and a lower surface plate to which the grinding wheel is attached. The carrier plate is moved in a planetary motion with the sun gear and the internal gear, and at the same time, the upper surface plate and the lower surface plate are rotated in a relative direction to grind both surfaces of the wafer. It is preferable .
The method for producing a semiconductor wafer according to the present invention may comprise a polishing step for polishing the surface of the etched wafer to provide a mirror finish as the next step of the single wafer etching step in the method for producing a semiconductor wafer. preferable.

The semiconductor wafer of the present invention is preferably manufactured by the method for manufacturing a semiconductor wafer described above .
Crystal evaluation method of a semiconductor wafer of the present invention is preferably provided with an evaluation step of evaluating crystal defects of a semiconductor wafer produced by the method of manufacturing the semiconductor wafer.

  According to the present invention, focusing on the high controllability of surface treatment by single wafer etching, by incorporating the single wafer etching process into the semiconductor wafer manufacturing method, the conventional grinding process and polishing process are not required. However, the surface of the semiconductor wafer can be satisfactorily mirror-finished, and in particular, the surface treatment of the wafer can be performed to the extent that crystal defects can be detected for evaluation. In other words, crystal defects caused by crystal growth of single crystal ingots are difficult to detect accurately unless mechanical damage on the wafer surface caused by the slicing process or grinding process is removed and the wafer surface is not mirror-finished. However, according to single wafer etching, processing damage in the wafer can be reduced, and the wafer surface can be satisfactorily mirror-finished, so that at least single wafer etching can be performed to produce an evaluation wafer. Can do. Therefore, it is possible to simplify the manufacture of a semiconductor wafer, particularly an evaluation wafer, reduce the time and cost required for manufacturing, and reduce the time and cost required for evaluation.

Hereinafter, embodiments of the present invention and related inventions will be described with reference to the drawings.
[First Embodiment]
1 to 3 show a manufacturing method and related apparatus for semiconductor wafer of the first embodiment according to the related inventions of the present invention, FIG. 1 is a flow chart of the manufacturing process, Figure 2 is used in the manufacturing process FIG. 3 is a schematic view of a single-side polishing apparatus used in the manufacturing process.

In the present embodiment, description will be made assuming that a silicon wafer, which is a typical semiconductor wafer used as an evaluation wafer, is manufactured.
In the present embodiment, as shown in FIG. 1, an evaluation wafer (silicon wafer) for quality evaluation of a silicon single crystal ingot (single crystal ingot) includes a slicing step S10 for slicing the wafer from the silicon single crystal ingot. The single-wafer etching step S20 for single-wafer etching the wafer sliced in the slicing step S10, and the single-side polishing step S30 for mirror-finishing the wafer etched in the single-wafer etching step S20 are manufactured in this order. It has become so. The evaluation wafer manufactured by the manufacturing method including the slicing step S10, the single wafer etching step S20, and the single-side polishing step S30 is subjected to an appropriate evaluation method (for example, Cu decoration) in the evaluation step subsequent to the single-side polishing step S30. Method), the crystal defects of the wafer are evaluated.

Each of the above steps will be described in detail below.
《Slicing process》
In the slicing step S10, a predetermined number of evaluation wafers are sliced from the silicon single crystal ingot by a slicing device (slicing means) such as a wire saw or an inner peripheral blade. The number and thickness of the evaluation wafers can be set according to the type of evaluation method.

<< Etching process >>
The etching step S20 is performed by a single wafer etching apparatus 1 as shown in FIG. This single wafer etching apparatus 1 includes a wafer rotating device (wafer rotating means) 10, a wafer temperature adjusting device (wafer temperature adjusting means) 20, an etching solution supply device (etching solution supply unit) 30, and a rinsing solution supply. The apparatus (rinsing liquid supply means) 40, a wafer surface shape measuring device (wafer surface shape measuring means) 50, and a control device (control means) 60 are provided.

  The wafer rotation device 10 includes a disk-shaped chuck (support means) 11 that supports a wafer, a rotating shaft 12 connected to the central portion of the chuck 11, and a chuck 11 connected to the rotating shaft 12 via the rotating shaft 12. And a rotation driving device (rotation driving means) 13 such as a motor for rotating the motor. Here, the chuck 11 is formed in a disc shape along the shape of the wafer, but may have a plate shape other than the disc shape. That is, the chuck 11 is not particularly limited as long as it can stably support the wafer.

  The wafer temperature adjusting device 20 has a plurality of temperature control elements 21 a and 21 b provided on the surface side of the chuck 11. The temperature control elements 21a and 21b are controlled by the control device 60, and can control the etching reaction rate at each position on the wafer surface by changing the temperature at each position on the wafer surface. Specifically, each of the temperature control elements 21a and 21b is concentric with the wafer rotation center on the upper surface of the chuck 11, and has a circular center portion 11a corresponding to the wafer center side position and an outer side of the center portion 11a. It arrange | positions corresponding to the position with the annular outer peripheral part 11b to a periphery, respectively. The temperature control elements 21a and 21b are set by the control device 60 so that the heat generation amount is set for each of the parts 11a and 11b.

The etchant supply device 30 faces the wafer supported by the chuck 11, and a nozzle 31 that jets the etchant toward the wafer, and an etchant supply unit 32 that stores the etchant and supplies the etchant to the nozzle 31. And a nozzle moving device (nozzle moving means) 33 that moves the position of the nozzle 31 and a nozzle injection state adjusting device (nozzle injection state adjusting means) 34 that adjusts the injection state of the nozzle 31. As an etching solution, a mixed acid solution in which HF (hydrofluoric acid), HNO ₃ (nitric acid), and H ₃ PO ₄ (phosphoric acid) are mixed at a predetermined ratio is used. However, the composition and mixing ratio of the etching solution are not limited to this.

  The nozzle moving device 33 includes a nozzle base portion 33a that supports the nozzle 31 and a guide portion 33b that guides the nozzle base portion 33a so as to be movable and restricts the position and movement of the nozzle base portion 33a in the in-plane direction. . Specifically, the guide portion 33b guides the nozzle base portion 33a so that the nozzle 31 moves in the wafer radial direction through the rotation center of the wafer. The guide portion 33b is supported by a support portion (not shown) so as to be rotatable in the wafer surface direction around the wafer rotation center, and the guide member 33b is rotated in the wafer surface direction, whereby the nozzle 31 is rotated. Can be moved in the wafer plane direction.

The nozzle injection state adjusting device 34 is provided in the nozzle base 33a, and although not shown in detail, an angle adjusting device (angle adjusting means) for adjusting the angle of the nozzle 31 with respect to the nozzle base 33a and a wafer at the nozzle tip portion. A height adjusting device (height adjusting means) for adjusting the height position from the nozzle and an injection switching device (injection switching means) for switching between injection and non-injection of the etching solution from the nozzle 31.
The rinsing liquid supply device 40 faces the wafer supported by the chuck 11, and rinses the nozzle 41 for injecting a rinsing liquid such as pure water toward the wafer, and storing the rinsing liquid and supplying the rinsing liquid to the nozzle 41. The liquid supply unit 42 and an injection switching device (injection switching means) (not shown) that switches between injection and non-injection of the rinse liquid from the nozzle 41 are provided.

The wafer surface shape measuring apparatus 50 measures the surface shape of the wafer by a non-contact type laser reflection method or a capacitance method.
The control device 60 includes a storage unit 61, a calculation unit 62, and a command unit 63, controls the number of rotations of the rotation driving device 13 of the wafer rotation device 10 and sets the number of wafer rotations. The temperature control elements 21a and 21b of the temperature setting device 20 are controlled to set the wafer temperatures of the respective portions 11a and 11b, the etching solution supply unit 32 is set to set the supply amount of the etching solution, and the nozzle is moved. The position of the nozzle 31 and the injection state are set by controlling the device 33 and the nozzle injection state adjusting device 34. Further, when the control device 60 performs etching so as to be in a predetermined state, the control device 60 stops the supply of the etching solution and supplies the rinsing solution to clean the etching solution on the wafer surface. The injection switching device and the injection switching device of the rinse liquid supply device 40 are controlled.

  Specifically, the storage unit 61 stores a first storage unit 61a that stores a concavo-convex shape (reference concavo-convex shape) on the wafer surface that is a reference after the etching process, and a second storage unit that stores a correspondence relationship between the wafer rotation speed and the etching state. A storage unit 61b, a third storage unit 61c that stores the correspondence between the wafer temperature and the etching state, a fourth storage unit 61d that stores a correspondence between the etching solution supply amount and the etching state, the position of the nozzle 31 and the etching It has a fifth storage unit 61e for storing the correspondence relationship with the state, and a sixth storage unit 61f for storing the correspondence relationship between the nozzle 31 injection angle and the etching state. These correspondences are obtained in advance by measurement.

  Here, the reference concavo-convex shape is set to the wafer surface shape before the single-side polishing step S30 defined by the processing characteristics in the single-side polishing step S30 with respect to the surface shape of the evaluation wafer to be finally manufactured. ing. Specifically, in the single-side polishing step S30, sagging is likely to occur at the peripheral portion, so that the reference uneven shape is set so that the center portion becomes concave by compensating for the sagging that occurs, In order to prevent sagging, the reference uneven shape is set so that the peripheral edge is raised.

  The computing unit 62 is input with the concavo-convex shape of the wafer surface immediately before the etching process measured by the wafer surface shape measuring device 50, and reads the reference concavo-convex shape from the first storage unit 61a. And the surface uneven | corrugated shape before an etching process and a reference | standard uneven | corrugated shape are compared, and the etching amount (in-plane machining allowance distribution) in each point of a wafer is calculated. Further, the etching state for each parameter (wafer rotation speed, wafer temperature, etching solution supply amount, nozzle position, nozzle movement pattern, spray angle) is read from the second storage unit 61b to the sixth storage unit 61f, and the read data is based on the read data. The parameters are set such that the above in-plane machining allowance distribution is obtained, and the settings are output to the command unit 63.

  The command unit 63 controls each device 10, 20, 30, 40 by sending a command to each device 10, 20, 30, 40 based on the setting of each parameter input from the calculation unit 62. For example, a command to set the wafer rotation speed to 600 rpm is sent to the wafer rotation device 10, and the nozzle position is set to 0, 15, 35, 60, 90, from the wafer center to the nozzle moving device 33 of the etching solution supply device 30. A command for movement such as 120, 135, and 150 mm is sent.

《Single-side polishing process》
Next, the single-side polishing step S30 will be described. The single-side polishing step S30 is performed by a single-side polishing apparatus 7 as shown in FIG. This single-side polishing apparatus 7 includes a nozzle 71 for supplying a polishing liquid (abrasive), a polishing head 73 for detachably holding a polishing plate 72 to which a wafer is bonded by wax, and a polishing surface plate to which a polishing cloth 74a is attached. 74, and a polishing head 73 mounted with a wafer via a polishing plate 72 is pressed against the polishing surface plate 74, and a polishing liquid is supplied from the nozzle 71 in a state where pressure is applied to the wafer. By rotating at least one of the polishing surface plate 74 and the wafer surface (main surface) becomes a mirror surface, the surface is polished in a mechanochemical combination. Although the case where the wafer is mirror-polished using the polishing plate 72 bonded with wax is described here, the wafer may be directly held on the polishing head 73 by vacuum suction. Further, the number of wafers to be processed may be a single wafer processing method for processing one by one or a multiple processing method for simultaneously processing a plurality of wafers.

  In the single-side polishing step S30, the allowance for one side (one side) of the wafer surface is set to about 0.3 μm to 2.0 μm. Thereby, the mirror surface of the wafer surface can be further mirrored, and the evaluation accuracy of crystal defects on the wafer surface can be further improved. Here, the case where only one side of the wafer is polished has been described, but if necessary, the front and back surfaces of the wafer may be mirror-polished one by one in order, or a double-side polishing apparatus may be used instead of the single-side polishing apparatus. It is possible to finish mirror polishing within the range of the setting allowance.

<< Evaluation process >>
The wafer after the above-described single-side polishing step S30 is evaluated for a predetermined wafer quality item that is normally performed. For example, evaluation of minute defects on the wafer surface by a known Cu decoration method, and evaluation of specific resistance value, oxygen concentration, minority carrier lifetime, surface photovoltaic power, BMD density, etc. in the wafer using various known methods . Thereby, the quality of a single crystal ingot can be evaluated.

Since the semiconductor wafer manufacturing method and the apparatus used in the manufacturing method of the first embodiment according to the related invention of the present invention are as described above, there are the following operations and effects.
Focusing on the high controllability of surface treatment by single wafer etching, by incorporating the single wafer etching step S20 into the evaluation wafer manufacturing method, evaluation can be performed without going through a grinding step or double-side polishing step as in the past. Therefore, the surface quality of the wafer can be maintained to such an extent that crystal defects can be detected.

  In other words, the present inventors paid attention to the surface roughness of the wafer after the single wafer etching, and that the wavelength roughness component of 10 μm or less on the wafer surface after the single wafer etching is less than that after the double-side polishing processing. Confirmed experimentally. In other words, since the fine roughness is removed by single wafer etching and the wafer surface can be made into a mirror surface state, even if the double-side polishing process that has been conventionally required is omitted, the product wafer that has been conventionally implemented It was confirmed that an evaluation result of the same level as the evaluation result using can be obtained. Moreover, since single-wafer etching is chemical processing, processing damage such as processing distortion due to mechanical processing such as a slicing process can be removed with almost no processing damage due to single-wafer etching itself, which is conventionally required. It was also confirmed that the grinding process can be omitted.

Therefore, by incorporating at least the single wafer etching step S20, the manufacturing process of the evaluation wafer can be simplified, and the time and cost for evaluation can be reduced.
Further, by changing the nozzle position in the wafer radial direction, it is possible to satisfactorily set the machining allowance in the regions 11a and 11b divided in the wafer radial direction.
Further, since the single wafer etching of this embodiment is a spin type, the wafer surface liquid distribution is controlled corresponding to the surface shape of the wafer before the etching process, and the machining allowance at each point on the wafer surface is accurately controlled. In addition, a high degree of processing freedom can be obtained. Further, since a mixed acid solution composed of HF, HNO ₃ and H ₃ PO ₄ is used, there are advantages of high-speed processing and low surface roughness.

  In addition, a predetermined number of evaluation wafers are sliced to evaluate an evaluation wafer, that is, a single crystal ingot, and a product wafer is manufactured by slicing the entire single crystal ingot only for single crystal ingots that have been selected based on the evaluation. As a result, it is possible to turn a long time-consuming operation of slicing the entire single crystal ingot into a wafer with a wire saw or the like to an actual product wafer manufacturing process. As a result, compared to storing the entire single crystal ingot in the state of being sliced into a wafer, the handling of the single crystal ingot is improved, and the device that requires the most care and must maintain its cleanliness. Since the wafer surface, which is the area, is not exposed in the ingot state and can be stored without exposing the front and back surfaces of the wafer to the air, the requirement for cleanliness in the storage space is reduced, and the construction and maintenance costs for the storage space are reduced. Can be reduced. Further, since the wafer is not sliced, the storage space can be saved.

Furthermore, at the same time that the pulled single crystal is cut into an ingot, it is also possible to slice the evaluation wafer with a wire saw that is used to cut the pulled single crystal into an ingot (that is, the slicing step is referred to as an ingot processing step). It is possible to make the same process), and the working time can be greatly reduced.
[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIGS. 4 and 5.

4 and 5 show a semiconductor wafer manufacturing method and related apparatus according to the second embodiment of the present invention. FIG. 4 is a flowchart of the manufacturing process, and FIG. 5 is double-side grinding used in the manufacturing process. It is a schematic diagram of an apparatus. The same members and the like as those of the second embodiment will be described with the same reference numerals as those of the first embodiment.
In the second embodiment, as shown in FIG. 4, the evaluation wafer is manufactured in a process in which a double-side grinding process S15 is further added to the manufacturing process of the first embodiment. That is, a slicing step S10 for slicing an evaluation wafer from a single crystal ingot, a double-sided grinding step (flattening step) S15 for grinding and flattening both surfaces of the wafer sliced in the slicing step S10, and a double-sided grinding step The wafer is manufactured through a single wafer etching step S20 for etching the wafer ground in S15 and a single side polishing step S30 for polishing the wafer etched in the single wafer etching step S20. And the defect in a crystal | crystallization is evaluated with the wafer for evaluation manufactured with such a manufacturing method.

The apparatus used in the slicing step S10, the single wafer etching step S20, and the single-side polishing step S30 is the same as that in the first embodiment.
《Double-sided grinding process》
The newly added double-side grinding step S15 will be described. The double-side grinding step S15 is performed by a double-side grinding apparatus 8 as shown in FIG.

  The double-side grinding apparatus 8 meshes with a sun gear 81 and an internal gear 82, and supplies a carrier plate 83 on which a wafer is set in the holder, an upper surface plate 84 and a lower surface plate 85 to which grinding wheels are attached, and abrasive grains. And a nozzle 86. Then, the double-side grinding device 8 holds both surfaces of the wafer set in the holder so as to be sandwiched between the upper surface plate 84 and the lower surface plate 85, supplies abrasive grains from the nozzle 86, the sun gear 81, the internal gear 82, Thus, the carrier plate 83 is caused to make a planetary motion, and at the same time, the upper surface plate 84 and the lower surface plate 85 are rotated in relative directions, whereby both surfaces of the wafer are mechanically ground. As a grinding wheel to be used, a resinoid grinding wheel or a metal bond grinding wheel is desirable, and it is desirable to use a grinding wheel of # 1000 to # 8000.

  In the double-side grinding step S15, if the thickness of the processing damage layer remaining on the wafer surface after double-side grinding is large, the amount of wafer etching in the subsequent etching step S20 and the amount of wafer polishing in the single-side polishing step S30 increase. Therefore, the productivity is lowered and the manufacturing cost is increased. For this reason, it is effective to perform double-side grinding so that the thickness of the processing damage layer on the wafer surface during double-side grinding is 2 μm or less.

Note that the double-side grinding device 8 shown in FIG. 5 is an example, and the front and back surfaces of the wafer may be ground in order using a single-side grinding device, or the front and back surfaces of the wafer may be ground simultaneously using a double-side grinding device. You may make it do.
Since the semiconductor wafer manufacturing method and the apparatus used for the manufacturing method according to the second embodiment of the present invention are configured as described above, the same operations and effects as those of the first embodiment are achieved. In addition, fine roughness is removed by single-wafer etching, the wafer surface that has undergone the double-side grinding step S15 can be made into a mirror surface state, and processing damage can be sufficiently reduced by single-wafer etching, which is conventionally required. Even if the double-side polishing step that has been performed is omitted, an evaluation result equivalent to the evaluation result using a product wafer that has been conventionally performed can be obtained.
[Others]
As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment, A various deformation | transformation is possible in the range which does not deviate from the meaning of this invention.

  For example, in each of the embodiments described above, the single wafer etching apparatus 1 includes the wafer temperature adjustment apparatus 20 having a plurality of temperature control elements 21 a and 21 b provided on the surface side of the chuck 11. The present invention is not limited to the provision of the wafer temperature adjusting device 20, and any device may be provided as long as the etching reaction distribution can be set in a desired state in the in-plane direction of the wafer. That is, instead of the wafer temperature adjusting device 20 in each of the above embodiments, an etching reaction operating device capable of operating the etching reaction for each position of the wafer and setting the etching reaction distribution in the in-plane direction of the wafer is used for the wafer. You may provide the apparatus which has wafer irradiation means, such as an infrared lamp or a laser oscillator which irradiates a heat | fever or light, and the wafer irradiation setting means which sets the irradiation position and irradiation amount of a wafer irradiation means. These wafer irradiation means and wafer irradiation setting means are connected to the control device 60 so that a desired etching reaction distribution is inputted. When the wafer irradiation means is an infrared lamp, the wafer irradiation setting means can be positioned between the lamp and the wafer to limit the irradiation area and the irradiation time. When the means is a laser oscillator, the wafer irradiation setting means can be a control provided in the oscillator so as to control the laser irradiation position.

  In each of the above embodiments, in addition to the etching reaction operation device such as the wafer temperature adjusting device 20, the etching solution temperature setting device (etching solution temperature setting means) for setting the temperature of the etching solution and the mixing ratio of the etching solution are changed. An etching solution mixture ratio changing device (etching solution mixture ratio changing means) may be provided, or an etching reaction temperature control device and an etching solution mixture ratio changing device may be provided without an etching reaction operation device. good.

In each of the above embodiments, only a predetermined number of evaluation wafers are sliced from the silicon single crystal ingot in the slicing step S10. However, the entire ingot may be sliced into a wafer.
Moreover, in the said 2nd Embodiment, you may replace double-sided grinding process S15 with a single-sided grinding process (flattening process). That is, it suffices that at least one surface of the wafer be ground before the single wafer etching step S20. At this time, it is preferable that the allowance for one surface of the surface be 10 μm or less.

  Moreover, in each said embodiment, although the typical silicon wafer was demonstrated as a semiconductor wafer, of course, you may apply this invention to the semiconductor wafer which consists of materials other than silicon.

It is a flowchart which shows the manufacturing method of the semiconductor wafer of 1st Embodiment which concerns on the related invention of this invention. It is a schematic diagram which shows the single wafer etching apparatus used with the manufacturing method of the semiconductor wafer of 1st Embodiment which concerns on the related invention of this invention. It is a schematic diagram which shows the single-side polish apparatus used with the manufacturing method of the semiconductor wafer of 1st Embodiment which concerns on the related invention of this invention. It is a flowchart which shows the manufacturing method of the semiconductor wafer which concerns on 2nd Embodiment of this invention. It is a schematic diagram which shows the double-sided grinding apparatus used with the manufacturing method of the semiconductor wafer which concerns on 2nd Embodiment of this invention. It is a flowchart which shows the manufacturing method of the conventional semiconductor wafer.

Explanation of symbols

1 Single wafer etching equipment 7 Single-side polishing equipment 8 Double-side grinding equipment

Claims (5)

A method for manufacturing a semiconductor wafer, for manufacturing a wafer for evaluation for performing quality evaluation of a single crystal ingot,
Slicing the wafer from the single crystal ingot;
A single wafer etching step in which the wafer sliced in the slicing step is rotated, and an etching solution is sprayed onto the surface of the rotated wafer to etch the surface of the wafer;
As a step immediately before the single wafer etching step, a grinding step of grinding and planarizing the surface of the wafer,
In the grinding step, the surface of the wafer is ground using a grinding wheel of # 1000 to # 8000 ,
In the single wafer etching step, the uneven shape of the surface of the wafer to be a reference after the etching process is set, and the uneven shape of the surface of the wafer before the etching process and the reference after the etching process are set. Comparing the uneven shape of the surface of the wafer, calculating the etching amount at each point of the wafer, and etching the surface of the wafer so as to be the etching amount Manufacturing method. In the grinding step, the wafer set in a carrier plate holder is held so as to be sandwiched between an upper surface plate and a lower surface plate to which the grinding wheel is attached, and the carrier plate is held by a sun gear and an internal gear. 2. The method of manufacturing a semiconductor wafer according to claim 1, wherein both surfaces of the wafer are ground by causing planetary motion and simultaneously rotating the upper surface plate and the lower surface plate in a relative direction . As a next step in該枚wafer etching process, the etched characterized by comprising a polishing step of mirror finishing by polishing the surface of the wafer, method for manufacturing a semiconductor wafer according to claim 1 or 2, wherein. A semiconductor wafer manufactured by the method for manufacturing a semiconductor wafer according to any one of claims 1 to 3 . Characterized by comprising an evaluation step of evaluating crystal defects of a semiconductor wafer produced by the method for producing a semiconductor wafer according to any one of claim 1 to 3 crystal evaluation method of a semiconductor wafer.

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