JP5426130B2 - Semiconductor device having storage node and method of forming the same - Google Patents

Description

  The present invention relates to a semiconductor device and a method for forming the same, and more particularly, to a semiconductor device having storage nodes spaced apart from each other on one side of a bit line pattern on an active region and a method for forming the semiconductor device (Semiconductor Devices Having Storage Nodes). and Methods Of Forming The Same).

  Typically, semiconductor devices have been manufactured while continuously reducing design rules to improve integration. The semiconductor device may include an active region, a gate pattern, a bit line pattern, and a storage node. In this case, the sizes of the active region, the gate pattern, the bit line pattern, and the storage node can be reduced according to the reduced design rule. Further, the active region is disposed obliquely on the semiconductor substrate with respect to the gate pattern or the bit line pattern in order to increase the degree of integration per unit area with respect to the design rule before shrinking. The gate pattern and the bit line pattern are sequentially disposed on the active region. The storage node is disposed at the edge of the active region exposed between the gate pattern and the bit line pattern. As a result, the semiconductor device can have a reduced design rule and improve the degree of integration.

  However, the semiconductor device has a reduced design rule, and cannot have a structure that greatly increases the share of the gate pattern, the bit line pattern, and the storage node on the active region arranged obliquely. This is because the gate pattern, the bit line pattern and the storage node are overlapped with the active region while ignoring the alignment system of the semiconductor photo equipment moving horizontally and vertically along the row and column of the semiconductor substrate. That is, the gate pattern, the bit line pattern and the storage node cannot be preferably aligned with the active region while avoiding an electrical short between them. Therefore, the gate pattern, the bit line pattern, and the storage node are arranged to have a low share on the active region in order to avoid an electrical short between them. The active region may have an undesirable electrical interaction with the gate pattern, the bit line pattern, and the storage node. Accordingly, the active region, the gate pattern, the bit line pattern, and the storage node deteriorate the electrical characteristics of the semiconductor device with the reduced design rule.

  The semiconductor device having the active region, the word line, the bit line, and the storage node was disclosed by Je-Min Park according to Patent Document 1. According to Patent Document 1, the active region is disposed obliquely on a semiconductor substrate with respect to a word line or a bit line. The word line and the bit line are sequentially disposed on the active region so as to intersect each other at a right angle. The bit line is disposed through a central region of the active region so that the bit line can be electrically connected to the active region. The storage node is disposed at the edge of the active region exposed to the word line and the bit line.

  However, Patent Document 1 sometimes provides a semiconductor device that cannot cope with a design rule that is continuously reduced. This is because the semiconductor device has word lines and bit lines that intersect at right angles on the active region. That is, the word line and the bit line can have a large share on the active region arranged obliquely. In addition, since the active region is disposed obliquely with respect to the word line or the bit line, the area exposed to the word line and the bit line can be further reduced in accordance with the design rule that is continuously reduced. As a result, the storage node may not be electrically connected to the active region in an appropriate manner according to a design rule that continuously reduces.

Hereinafter, the present invention that can solve the above-described problems of the prior art and has technical features superior to those of the prior art will be described.
US Pat. No. 7,183,603

  A technical problem to be solved by the present invention is to provide a semiconductor device having storage nodes that are spaced apart from one side of a bit line pattern at different distances on an active region.

  Another technical problem to be solved by the present invention is to increase the share on the active region regardless of the continuous reduction of the design rule, and to separate the bit line pattern from one side of the active region at different distances from each other. Another object of the present invention is to provide a method for forming a semiconductor device having a storage node.

  As a means for solving the technical problem, the present invention provides a semiconductor device having storage nodes spaced apart from one side of a bit line pattern on a selected active region, and a method of forming the same. .

  A semiconductor device according to an aspect of the present invention includes an active region disposed on a semiconductor substrate. The active region has first to third regions located in order from one side to the other side. An inactive region is disposed on the semiconductor substrate so that the active region can be defined. A gate pattern partially buried in the active region and the inactive region is disposed. The gate pattern is positioned between the first and second regions and between the second and third regions so as to intersect the active region at a right angle, and passes through the active region and the inactive region. . A bit line pattern is disposed on the gate pattern and intersects the gate pattern at a right angle. The bit line pattern overlaps with the inactive region and is electrically connected to the second region through a predetermined region. An interlayer insulating film is disposed to cover the gate pattern and surround the bit line pattern. The interlayer insulating film exposes the bit line pattern. A storage node is disposed on the interlayer insulating film and electrically connected to the first and third regions. The storage node overlaps with the first region and the inactive region through a selected one, and overlaps with the third region, the inactive region, and the bit line pattern through the rest.

  According to a selected embodiment of the present invention, one selected from the storage node can contact the bit line pattern in the third region.

  According to a selected embodiment of the present invention, the semiconductor device includes the active region, the gate pattern, the bit line pattern, the node contact, and the storage node in a row and a column of the semiconductor substrate. ) At each of the intersections.

  According to selected embodiments of the present invention, two adjacent active regions in a selected row of the semiconductor substrate may be opposed to each other through the first to third regions. In addition, two adjacent active regions in a selected row of the semiconductor substrate may be opposed to each other through the first and third regions.

  According to selected embodiments of the present invention, the gate pattern may be disposed along each of the rows at the intersection of the row and column of the semiconductor substrate. The bit line pattern may be disposed along each of the columns. The gate pattern and the bit line pattern may intersect at a right angle at the intersection.

  According to selected embodiments of the present invention, at the intersection of the row and column of the semiconductor substrate, the bit line pattern is adjacent to the two adjacent ones along the selected row of the semiconductor substrate. Located in the inactive areas between the active areas.

  According to the remaining embodiment of the present invention, at the intersection of the row and the column of the semiconductor substrate, the storage node has two adjacent bit lines located around the active region in one selected active region. Each can be partially overlapped with the pattern.

  According to another embodiment of the present invention, at the intersection of the row and column of the semiconductor substrate, the storage node is adjacent to the two active regions in the selected one active region. They are arranged to face each other diagonally so as to be defined between the bit line patterns.

  According to the remaining embodiment of the present invention, at the intersection of the row and the column of the semiconductor substrate, storage nodes between the two adjacent bit line patterns are disposed on the active region in a zigzag manner.

  According to the remaining embodiment of the present invention, at the intersection of the row and the column of the semiconductor substrate, the storage nodes adjacent to each other between three adjacent bit line patterns have different active regions in one direction. Between the three adjacent bit line patterns corresponding to two from one active region, which is arranged diagonally between the three adjacent bit line patterns and selected in the other direction perpendicular to the direction. Are arranged diagonally.

  A method for forming a semiconductor device according to an aspect of the present invention includes forming an inactive region in a semiconductor substrate. The inactive region is formed to define an active region. Two gate patterns are formed in the active region and the inactive region so as to intersect the active region at a right angle. A first interlayer insulating film is formed on the active region so as to cover the gate pattern. A bit line pattern is formed on the first interlayer insulating layer and intersects the gate pattern at a right angle. The bit line pattern is formed on the inactive region around the active region, and is electrically connected to the active region between the gate patterns through the first interlayer insulating film. A second interlayer insulating film is formed on the first interlayer insulating film so as to cover the bit line pattern. Overlying the active region, the inactive region, and the bit line pattern around the gate pattern through the first and second interlayer insulating films, and electrically connected to the active region around the gate pattern To form a storage node.

  According to selected embodiments of the present invention, forming the gate pattern includes forming a molding hole corresponding to the gate pattern in the semiconductor substrate, and forming a gate insulating film in the molding hole. And forming a gate located on the gate insulating film and partially filling the molding hole, filling the molding hole on the gate, and the active region and the inactive region. Forming a gate capping pattern protruding from the main surface of the substrate. In this case, the gate is formed using a conductive material.

  According to a selected embodiment of the present invention, forming the bit line pattern includes forming a bit line contact hole in the first interlayer insulating film, and forming a bit line contact filling the bit line contact hole. Forming a bit line conductive film and a bit line capping film so as to cover the bit line contact, and exposing the first interlayer insulating film to the bit line capping film and the bit line conductive film. And sequentially etching. In this case, the bit line contact hole is formed to expose the active region between the gate patterns. The bit line contact is formed using a conductive material. The bit line pattern may be in contact with the bit line contact through a predetermined region of the pattern.

  According to selected embodiments of the present invention, the step of electrically connecting the storage node with the active region around the gate pattern forms a node contact hole in the first and second interlayer insulating films. Forming a node contact filling each of the node contact holes; and contacting the storage node with the node contact. In this case, the bit line contact hole is formed between the node contact hole. The node contact hole is formed to expose the active region around the gate pattern. The node contact is formed using a conductive material.

  According to selected embodiments of the present invention, one of the storage nodes may contact one selected from the node contact and the bit line pattern.

  According to selected embodiments of the present invention, further comprising positioning the active region, the gate pattern, the bit line pattern, the node contact and the storage node at each intersection of a row and a column of the semiconductor substrate. Can be included.

  According to selected embodiments of the present invention, the active regions disposed along one selected row of the semiconductor substrate have the same center and the same area, and are formed in order horizontally. The active regions arranged along one selected row of the semiconductor substrate have the same center and the same area, and are formed in order vertically.

  According to selected embodiments of the present invention, at the intersection of the row and column of the semiconductor substrate, the gate pattern is formed along each of the rows. The bit line pattern is formed along each of the columns. The gate pattern and the bit line pattern are formed to intersect at right angles from the intersection.

  According to the remaining embodiment of the invention, at the intersection of the row and column of the semiconductor substrate, the bit line pattern is the two adjacent actives along the selected row of the semiconductor substrate. Formed in the inactive regions between the regions.

  According to the remaining embodiment of the present invention, at the intersection of the row and the column of the semiconductor substrate, the storage node is one selected active region and two adjacent regions located around the active region. It is formed so as to partially overlap the bit line pattern.

  According to still another embodiment of the present invention, at the intersection of the row and the column of the semiconductor substrate, the storage node is the selected one active region, and the two active regions are located around the active region. As defined between adjacent bit line patterns, they are formed to face each other diagonally.

  According to the remaining embodiment of the present invention, at the intersection of the row and the column of the semiconductor substrate, a storage node between the two adjacent bit line patterns is formed on the active region in a zigzag manner.

  According to the remaining embodiments of the present invention, at the intersection of the row and the column of the semiconductor substrate, the storage nodes adjacent to each other between three adjacent bit line patterns have different active regions in one direction. The three adjacent bit lines are formed diagonally between the three adjacent bit line patterns, and the three adjacent regions correspond to each other from the one active region selected in the other direction perpendicular to the direction. Diagonal lines are formed between bit line patterns.

  By means for solving the technical problem, the present invention presents a method for increasing the share of the semiconductor pattern on the active region despite the continuous reduction of the design rule. To this end, the present invention provides a gate pattern positioned on the active region and orthogonal to the active region, a bit line pattern positioned on the inactive region while intersecting the gate pattern at a right angle, and the gate pattern and the bit line pattern. A storage node located on the active region between can be provided. Accordingly, the present invention can increase the alignment margin of the active region and the storage node through the gate pattern and the bit line pattern as compared with the prior art.

  Aspects of the present invention will be described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein, and can be embodied in other forms. Accordingly, the embodiments disclosed herein are provided to complete the disclosure of the invention and to fully convey the spirit of the present invention to those skilled in the art.

  For example, the terms first, second, etc. are used herein to describe a number of components, but the components are not limited to such terms. However, such terms are used to distinguish one component from another. As used herein, “rows and columns” are used to describe a two-dimensional array of semiconductor patterns on a semiconductor substrate. The term “and / or” has one or more relationships and includes all combinations that can be inferred for the listed items. In addition, “top”, “bottom”, “periphery”, “correspondence”, “partial”, “part”, “remaining”, “opposite”, “upward”, etc. The relative terms are used to briefly describe the selected component, the relative relationship of one shape to another component, or the shape shown in the drawings. The use of the technical terms here is for explaining a special aspect and does not limit the present invention.

  Next, a semiconductor device having storage nodes spaced apart from each other by a different distance from one side of the bit line pattern on one selected active region of the present invention will be described in more detail with reference to the accompanying drawings. To do.

  FIG. 1 is a plan view showing a semiconductor device according to the present invention. 2A to 2C are cross-sectional views showing the semiconductor device taken along the cutting lines I-I ', II-II', and III-III 'of FIG. 1, respectively.

  As shown in FIGS. 1 and 2A to 2C, a semiconductor device 115 according to an aspect of the present invention has a gate pattern 34 arranged on a semiconductor substrate 3 along a row of the semiconductor substrate 3, as shown in FIGS. Included. More specifically, two adjacent gate patterns 34 are arranged as shown in FIG. 1 so as to correspond to a selected row of the semiconductor substrate 3. The gate pattern 34 includes a gate 26 and a gate capping pattern 33 as shown in FIG. 2A. A bit line pattern 69 is disposed on the gate pattern 34 as shown in FIGS. 1 and 2A to 2C. The bit line pattern 69 is arranged along a column of the semiconductor substrate 3 as shown in FIG. The bit line pattern 69 is disposed to intersect the gate pattern 34 at a right angle at the intersection of the row and column of the semiconductor substrate 3. Each of the bit line patterns 69 includes a bit line 63 and a bit line capping pattern 66 as shown in FIGS. 2A to 2C. The gate 26 and the bit line 63 are made of a conductive material. The gate capping pattern 33 and the bit line capping pattern 66 are made of an insulating material.

  According to the embodiment of the present invention, the active region 9 is disposed under the gate pattern 34 and the bit line pattern 69 as shown in FIGS. 1 and 2A to 2C. The active regions 9 are arranged so as to correspond to the intersections of the rows and columns of the semiconductor substrate 3 as shown in FIG. The active region 9 is disposed between the bit line patterns 69. Each of the active regions 9 includes first to third regions 9-1, 9-2, and 9-3 from one side to the other side along a selected row of the semiconductor substrate 3. Formed as follows. According to an embodiment of the present invention, two adjacent active regions 9 in a selected row of the semiconductor substrate 3 are opposed to each other through first to third regions 9-1, 9-2, 9-3. To be arranged. In the selected row of the semiconductor substrate 3, two adjacent active regions 9 are arranged to face each other with the first and third regions 9-1 and 9-3 interposed therebetween. The active region 9 is defined by the inactive region 6 as shown in FIGS. 2A to 2C. The inactive region 6 may have an element isolation film. The bit line pattern 69 is disposed on the inactive region 6.

  According to an embodiment of the present invention, the active region 9 is arranged as shown in FIG. 1 so as to correspond to two adjacent gate patterns 34 in one selected from a row of the semiconductor substrate 3. More specifically, the two adjacent gate patterns 34 are formed between the first and second regions 9-1 and 9-2 of the selected one active region 9, and the second and third regions 9-2. 9-3. The gate pattern 34 is disposed in the active region 9 and the inactive region 6 as shown in FIGS. 1 and 2A. Each gate 26 of the gate pattern 34 is buried in the active region 9 and the inactive region 6. Each gate capping pattern 33 of the gate pattern 34 is formed on the gate 26 so as to protrude from the main surfaces of the active region 9 and the inactive region 6 as shown in FIG. 2A. An interlayer insulating film or a gate interlayer insulating film 43 is disposed on the active region 9 and the inactive region 6 so as to cover the gate pattern 34 as shown in FIGS. 2A to 2C.

  Also, as shown in FIGS. 1 and 2A to 2C, according to an embodiment of the present invention, a bit line contact 49 is disposed on the gate interlayer insulating film 43 as shown in FIGS. 2A and 2C. The bit line contact 49 is exposed from the gate interlayer insulating film 43. Each of the bit line contacts 49 is disposed to contact the second region 9-2 of one selected active region 9 between two adjacent gate patterns 34 as shown in FIGS. The bit line contact 49 is made of a conductive material. The bit line contact 49 is disposed in contact with the bit line pattern 69 as shown in FIGS. 2A and 2C. More specifically, each of the bit line patterns 69 protrudes from the inactive region 6 toward the active region 9 in a predetermined region of the pattern 69 so as to contact the bit line contact 49 of FIGS. 1 and 2c. Are arranged as follows. A bit line interlayer insulating film 78 is disposed on the gate interlayer insulating film 43 so as to cover the bit line pattern 69 as shown in FIGS. 2A to 2C. The bit line interlayer insulating layer 78 is disposed to expose the bit line pattern 69. A node contact 99 is disposed on the gate interlayer insulating layer 43 and the bit line interlayer insulating layer 78 as shown in FIGS. 2A to 2C. The node contact 99 may be exposed from the bit line interlayer insulating film 78. The node contact 99 is disposed so as to contact the active region 9. The node contact 99 is made of a conductive material.

  According to an embodiment of the present invention, the node contacts 99 in the selected one active region 9 are located in the first and third regions 9-1 and 9-3 and face each other diagonally as shown in FIG. Placed in. A storage node 103 is disposed on the node contact 99 as shown in FIGS. 1, 2A and 2B. The storage node 103 is arranged to contact the node contact 99. The storage node 103 is made of a conductive material. The storage node 103 in the selected one active region 9 overlaps the first region 9-1 and the inactive region 6 located around the first region 9-1, and the third region 9-3 and It arrange | positions so that the inactive area | region 6 located in the periphery of the said 3rd area | region 9-3 may overlap. The storage node 103 in the selected one active region 9 may contact the bit line pattern 69 located around the selected one active region 9 as shown in FIGS. 2A and 2B.

  According to the selected embodiment of the present invention, the storage node 103 in the selected one active region 9 is connected between two adjacent bit line patterns 69 located around the selected one active region 9. It arrange | positions like FIG. 1 so that it may be demarcated and may mutually oppose diagonally. The storage nodes 103 between the two adjacent bit line patterns 69 are arranged on the active region 9 in a zigzag manner as shown in FIG. The storage nodes 103 adjacent to each other among the three adjacent bit line patterns 69 are diagonally arranged between the three adjacent bit line patterns 69 with different active regions 9 in one direction as shown in FIG. Be placed. The storage nodes 103 adjacent to each other between the three adjacent bit line patterns 69 correspond to two active regions 9 selected in the other direction perpendicular to one direction, corresponding to two each. A diagonal line between two adjacent bit line patterns 69 is arranged as shown in FIG.

  Further, as shown in FIGS. 1 and 2A to 2C, according to an embodiment of the present invention, a dielectric film is formed on the bit line interlayer insulating film 78 so as to cover the bit line pattern 69, the node contact 99, and the storage node 103. 106 and plate 109 are arranged. The dielectric layer 106 is made of silicon oxide, silicon nitride, metal oxide, or a combination thereof. The plate 109 is made of a conductive material. Each of the storage nodes 103 corresponds to a lower electrode of a capacitor. The plate 109 corresponds to the upper electrode of the capacitor. Meanwhile, a bit line spacer 74 made of an insulating material is disposed on the side wall of the bit line pattern 69. The bit line spacer 74 is made of an insulating material. An impurity diffusion region 36 is disposed in the active region 9. The impurity diffusion region 36 is located between the gate patterns 34 and may be in contact with the bit line contact 49 and the node contact 99. The impurity diffusion region 36 may have a conductivity different from that of the semiconductor substrate 3.

  Next, a method of forming a semiconductor device having storage nodes spaced apart from each other by a distance from one side of the bit line pattern on the active region of the present invention will be described with reference to the accompanying drawings.

  3A, 4A, 5A, 6A, 7A, 8A, and 9A are cross-sectional views illustrating a method for forming a semiconductor device along the cutting line I-I 'in FIG. 3B, FIG. 4B, FIG. 5B, FIG. 6B, FIG. 7B, FIG. 8B, and FIG. 9B are cross-sectional views illustrating a method for forming a semiconductor device along the section line II-II 'in FIG. 3C, FIG. 4C, FIG. 5C, FIG. 6C, FIG. 7C, FIG. 8C and FIG. 9C are cross-sectional views illustrating a method for forming a semiconductor device along the section line III-III 'in FIG.

  As shown in FIGS. 1 and 3A to 3C, an inactive region 6 is formed in a semiconductor substrate 3 as shown in FIGS. 3A to 3C according to an embodiment of the present invention. The inactive region 6 is filled with an element isolation film. The element isolation film is formed using one or more insulating films. The inactive region 6 is formed so as to define an active region 9. The active regions 9 are formed along the rows and columns of the semiconductor substrate 3 as shown in FIG. More specifically, the active regions 9 arranged along one selected row of the semiconductor substrate 3 have the same center and the same area, and are formed in order horizontally. The active regions 9 arranged along one selected row of the semiconductor substrate 3 have the same center and the same area, and are formed in order vertically. A pad base film 13 and a pad mask film 16 are formed on the inactive region 6 so as to cover the active region 9 as shown in FIGS. 3A to 3C. The pad base layer 13 and the pad mask layer 16 may be formed using insulating materials having different etching rates.

  According to the embodiment of the present invention, a molding hole 19 is formed in the active region 9 and the inactive region 6 through the pad base film 13 and the pad mask film 16 as shown in FIG. 3A. The molding hole 19 is formed along the row of the semiconductor substrate 3 so as to be perpendicular to the active region 9. Since the molding hole 19 is aligned at right angles to the active region 9, the molding hole 19 is not formed in the active region 9 even in an unstable semiconductor manufacturing process as compared to the case where the molding hole 19 is aligned obliquely with respect to the active region of the prior art. Well aligned. The molding hole 19 is formed to extend from the main surfaces of the active region 9 and the inactive region 6 toward the lower portion of the semiconductor substrate 3. Although not shown in FIGS. 3A to 3C, the molding hole 19 extends through the active region 9 to the inactive region 6. Each of the active regions 9 is formed as shown in FIGS. 1 and 3A so as to have a predetermined width W1 between the molding hole 19 and the inactive region 6 in a selected row of the semiconductor substrate 3. Each of the active regions 9 has a predetermined width W2 in a selected row of the semiconductor substrate 3 and is formed as shown in FIGS. 1 and 3C so as to be surrounded by the inactive region 6.

  As shown in FIGS. 1 and 4A to 4C, according to an embodiment of the present invention, a gate insulating film 23 is formed in a molding hole 19 as shown in FIG. 4A using the pad base film 13 and the pad mask film 16 as a mask. Let The gate insulating film 23 is formed using silicon oxide, silicon oxynitride, and metal oxide. A gate 26 is formed on the gate insulating layer 23 to partially fill the molding hole 19 as shown in FIG. 4A. The gate 26 is formed using metal nitride. A gate capping layer 29 located on the gate 26 and covering the pad base layer 13 and the pad mask layer 16 is formed as shown in FIGS. 4A to 4C. The gate capping layer 29 is formed using an insulating material having the same etching rate as the pad mask layer 16.

  As shown in FIGS. 1 and 5A to 5C, according to an embodiment of the present invention, a chemical mechanical polishing process is performed on the gate capping film 29 and the pad mask film 16 using the pad base film 13 as an etching buffer film. Thus, the gate capping pattern 33 is formed as shown in FIG. 5A. The gate capping patterns 33 are formed on the gates 26, respectively. The gate capping pattern 33 is formed so as to fill the molding hole 19 and protrude from the main surfaces of the active region 9 and the inactive region 6. An etch-back process can be performed instead of the chemical mechanical polishing process. Subsequently, the pad base film 13 is removed using the gate capping pattern 33 as an etching buffer film to expose the semiconductor substrate 3 as shown in FIGS. 5A to 5C. Accordingly, the gate 26 and the gate capping pattern 33 form a gate pattern 34 defined in the molding hole 19 as shown in FIGS. 1 and 5A.

  According to the embodiment of the present invention, the gate pattern 34 is defined in the molding hole 19 and is formed to intersect the active region 9 at right angles along the row of the semiconductor substrate 3. Two adjacent gate patterns 34 along one row of the semiconductor substrate 3 are formed as shown in FIGS. 1 and 5A so as to correspond to one active region 9. An impurity diffusion region 36 is formed in the active region 9 using the gate pattern 34 and the inactive region 6 as a mask. The impurity diffusion region 36 is formed between the gate patterns 34 and between the gate pattern 34 and the inactive region 6. The impurity diffusion region 36 is formed to have conductivity different from that of the semiconductor substrate 3. According to selected embodiments of the present invention, landing pads 39 are formed in the central region of the active region 9 between the gate patterns 34 along the row of the semiconductor substrate 3 as shown in FIGS. 1 and 5A, respectively. The landing pad 39 may be a conductive material. An interlayer insulating film or a gate interlayer insulating film 43 is formed on the active region 9 and the inactive region 6 to cover the gate pattern 34 as shown in FIGS. 5A to 5C. The gate interlayer insulating layer 43 may have an etching rate different from that of the gate capping pattern 33 and the landing pad 39.

  As shown in FIGS. 1 and 6A to 6C, a bit line contact hole 46 is formed in the gate interlayer insulating film 43 as shown in FIGS. 6A and 6C according to an embodiment of the present invention. The bit line contact holes 46 are respectively formed in the central region of the active region 9 between the gate patterns 34 along the row of the semiconductor substrate 3 as shown in FIG. The bit line contact hole 46 is formed to expose the active region 9. When the landing pad 39 of FIG. 5A is formed, the bit line contact hole 46 is formed on the landing pad 39, respectively. Bit line contacts 49 are formed in the bit line contact holes 46 as shown in FIGS. 1, 6A and 6C, respectively. The bit line contacts 49 are formed to contact the impurity diffusion regions 36, respectively. The bit line contact 49 is formed using a conductive material. A bit line conductive film 54 and a bit line capping film 58 are sequentially formed on the gate interlayer insulating film 43 so as to cover the bit line contact 49 as shown in FIGS. 6A to 6C. The bit line conductive layer 54 is formed using a conductive material. The bit line capping layer 58 is formed using an insulating material having the same etching rate as the gate capping pattern 34.

  As shown in FIGS. 1 and 7A to 7C, according to an embodiment of the present invention, the bit line capping film 58 and the bit line conductive film 54 are sequentially etched to expose the gate interlayer insulating film 43. A pattern 69 is formed as shown in FIGS. 7A to 7C. Each of the bit line patterns 69 is formed to have a bit line 63 and a bit line capping pattern 66. The bit line pattern 69 is formed as shown in FIG. 1 so as to intersect the gate pattern 34 at right angles at the intersections of the rows and columns of the semiconductor substrate 3. The bit line pattern 69 is formed on the inactive region 6 between the active regions 9 along the column of the semiconductor substrate 3. Since the bit line pattern 69 is positioned in the inactive region 6 and aligned in parallel with the active region 9, it is unstable compared to the case where the bit line pattern 69 is aligned obliquely with respect to the active region as in the prior art. Even in a semiconductor manufacturing process, the active region 9 can be more exposed. In a selected column of the semiconductor substrate 3, the bit line pattern 69 extends from the inactive region 6 toward the active region 9 in a predetermined region of the pattern 69 as shown in FIGS. Formed. A bit line spacer 74 is formed on the sidewall of the bit line pattern 69 as shown in FIGS. 7A to 7C. The bit line spacer 74 is formed to have the same etching rate as the bit line capping pattern 66.

  According to the embodiment of the present invention, a bit line interlayer insulating film 78 is formed on the gate interlayer insulating film 43 as shown in FIGS. 7A to 7C so as to cover the bit line pattern 69 and the bit line spacer 74. The bit line interlayer insulating film 78 is formed to have the same etching rate as the gate interlayer insulating film 43. A node mask pattern 83 is formed on the bit line interlayer insulating layer 78 as shown in FIGS. 7A and 7C. The node mask pattern 83 is formed to have an etching rate different from that of the bit line interlayer insulating film 78. The node mask pattern 83 is formed along the row of the semiconductor substrate 3. A part of the node mask pattern 83 is formed along the gate pattern 34 as shown in FIGS. 1 and 7A so as to overlap the gate pattern 34. The remainder of the node mask pattern 83 is located between the gate patterns 34 and is formed in the inactive region 6 as shown in FIGS. 1 and 7A. A mask spacer 86 is formed on the sidewall of the node mask pattern 83 as shown in FIGS. 7A and 7C. The mask spacer 86 is formed to have the same etching rate as the bit line capping pattern 66.

  As shown in FIGS. 1 and 8A to 8C, according to an embodiment of the present invention, a bit line interlayer insulating film is formed using the bit line pattern 69, the bit line spacer 74, the node mask pattern 83, and the mask spacer 86 as an etching mask. 78 and the gate interlayer insulating film 43 are sequentially etched to form a node contact hole 93 as shown in FIGS. 8A and 8B. The node contact holes 93 are formed as shown in FIGS. 1, 8A and 8B so as to correspond to each of the active regions 9. More specifically, two adjacent node contact holes 93 are formed so as to face each other selected from the active region 9 diagonally. The node contact hole 93 is formed as shown in FIGS. 8A and 8B so as to expose the bit line pattern 69, the bit line spacer 74 and the active region 9. A node contact film 96 covering the node mask pattern 83 is formed as shown in FIGS. 8A to 8C so as to fill the node contact hole 93. The node contact film 96 is formed using a conductive material.

  As shown in FIGS. 1 and 9A to 9C, according to an embodiment of the present invention, a node mask pattern 83, a mask spacer 86, and a bit line interlayer insulating film are formed using the bit line pattern 69 and the bit line spacer 74 as an etching buffer film. A chemical mechanical polishing process is performed on 78. In the chemical mechanical polishing step, the node contact 99 is formed in the node contact hole 93 as shown in FIGS. 1, 9A and 9B. The node contact 99 is formed in contact with the impurity diffusion region 36 located around the bit line contact 49. A storage node 103 is formed on the node contact 99 as shown in FIGS. 1, 9A and 9B. Since the storage node 103 is aligned with the active region 9 positioned parallel to the bit line pattern 69, the storage node 103 is aligned with a conventional active region positioned obliquely with respect to the bit line pattern 69. Even in an unstable semiconductor manufacturing process, it is preferably aligned with the active region 9. The storage node 103 is formed using a conductive material. The storage node 103 is formed as shown in FIGS. 1, 9A, and 9B so as to overlap the inactive region 6, the active region 9, and the bit line pattern 69. One storage node 103 selected from the active region 9 is formed as shown in FIGS. 9A and 9B so as to partially contact the bit line pattern 69 located around the selected one active region 9. The

  According to the selected embodiment of the present invention, one storage node 103 selected from the active region 9 is defined between the bit line patterns 69 located around the selected one active region 9 and is diagonal to each other. It forms like FIG. 1 so that it may oppose. The storage nodes 103 between two adjacent bit line patterns 69 are formed on the active region 9 in a zigzag manner. The storage nodes 103 adjacent to each other among the three adjacent bit line patterns 69 are diagonally formed between the three adjacent bit line patterns 69 with different active regions 9 in one direction. The storage nodes 103 that are adjacent to each other among the three adjacent bit line patterns 69 correspond to the active regions 9 selected in the other direction perpendicular to one direction, and two storage nodes 103 correspond to each other. A diagonal line is formed between two adjacent bit line patterns 69. Since the storage node 103 partially overlaps with the active region 9 around the gate pattern 69, it is possible to have a process margin that preferably overlaps with the active region 9 even if the design rule is continuously reduced.

  Subsequently, a dielectric film 106 and a plate 109 are formed on the bit line pattern 69, the bit line interlayer insulating film 78, and the node contact 99 so as to cover the storage node 103. The dielectric layer 103 is formed using silicon oxide, silicon nitride, metal oxide, or a combination thereof. The plate 109 is formed using a conductive material. The dielectric layer 106 and the plate 109 together with the storage node form a capacitor. The capacitor may constitute the semiconductor device 115 according to the present invention together with the gate pattern 34 and the bit line pattern 69.

It is a top view which shows the semiconductor device by this invention. FIG. 2 is a cross-sectional view showing a semiconductor device taken along a cutting line I-I ′ in FIG. 1. FIG. 2 is a cross-sectional view showing the semiconductor device taken along section line II-II ′ in FIG. 1. FIG. 3 is a cross-sectional view showing the semiconductor device taken along section line III-III ′ in FIG. 1. FIG. 7 is a cross-sectional view illustrating a method for forming a semiconductor device along the cutting line I-I ′ in FIG. 1. It is sectional drawing explaining the formation method of the semiconductor device by the cutting line II-II 'of FIG. It is sectional drawing explaining the formation method of the semiconductor device by the cutting line III-III 'of FIG. FIG. 7 is a cross-sectional view illustrating a method for forming a semiconductor device along the cutting line I-I ′ in FIG. 1. It is sectional drawing explaining the formation method of the semiconductor device by the cutting line II-II 'of FIG. It is sectional drawing explaining the formation method of the semiconductor device by the cutting line III-III 'of FIG. FIG. 7 is a cross-sectional view illustrating a method for forming a semiconductor device along the cutting line I-I ′ in FIG. 1. It is sectional drawing explaining the formation method of the semiconductor device by the cutting line II-II 'of FIG. It is sectional drawing explaining the formation method of the semiconductor device by the cutting line III-III 'of FIG. FIG. 7 is a cross-sectional view illustrating a method for forming a semiconductor device along the cutting line I-I ′ in FIG. 1. It is sectional drawing explaining the formation method of the semiconductor device by the cutting line II-II 'of FIG. It is sectional drawing explaining the formation method of the semiconductor device by the cutting line III-III 'of FIG. FIG. 7 is a cross-sectional view illustrating a method for forming a semiconductor device along the cutting line I-I ′ in FIG. 1. It is sectional drawing explaining the formation method of the semiconductor device by the cutting line II-II 'of FIG. It is sectional drawing explaining the formation method of the semiconductor device by the cutting line III-III 'of FIG. FIG. 7 is a cross-sectional view illustrating a method for forming a semiconductor device along the cutting line I-I ′ in FIG. 1. It is sectional drawing explaining the formation method of the semiconductor device by the cutting line II-II 'of FIG. It is sectional drawing explaining the formation method of the semiconductor device by the cutting line III-III 'of FIG. FIG. 7 is a cross-sectional view illustrating a method for forming a semiconductor device along the cutting line I-I ′ in FIG. 1. It is sectional drawing explaining the formation method of the semiconductor device by the cutting line II-II 'of FIG. It is sectional drawing explaining the formation method of the semiconductor device by the cutting line III-III 'of FIG.

Explanation of symbols

3 Semiconductor substrate 6 Inactive region 9 Active region 9-1, 9-2, 9-3 First to third regions 26 Gate 33 Gate capping pattern 34 Gate pattern 43 Gate interlayer insulating film 49 Bit line contact 63 Bit line 66 bit Line capping pattern 69 Bit line pattern 78 Bit line interlayer insulating film 99 Node contact 103 Storage node 150 Semiconductor device

Claims (15)

An active region disposed on a semiconductor substrate and having first to third regions located in order from one side to another side;
An inactive region disposed in the semiconductor substrate to define the active region;
The active region and the inactive region are partially buried in the first region and the second region so as to intersect the active region at right angles, and between the second and third regions, respectively. A gate pattern passing through the active region and the inactive region;
A bit line pattern positioned on the gate pattern, intersecting the gate pattern at a right angle, overlapping the inactive region, and electrically connected to the second region through a predetermined region;
An interlayer insulating film covering the gate pattern and surrounding the bit line pattern and exposing the bit line pattern;
The third region, the inactive region, and the bit line are positioned on the interlayer insulating layer and overlap with the first region and the inactive region through a first storage node, and through a second storage node. A storage node electrically connected to the active region so as to overlap the pattern;
Only including,
One selected from the storage node contacts the bit line pattern in the third region;
The active region, the gate pattern, the bit line pattern, the node contact, and the storage node are disposed at intersections of rows and columns of the semiconductor substrate, respectively .
A plurality of adjacent active regions in the semiconductor substrate adjacent to the active region;
Each of the adjacent active regions has first to third regions, and the first to third regions of the active region in the same row of the semiconductor substrate are the first of the active regions adjacent to the active region. 1st to 3rd region, and in the same row of the semiconductor substrate, the 3rd region of the active region is opposed to the 1st region of one active region adjacent to the active region,
At the intersection of the row and column of the semiconductor substrate,
The selected storage node is defined between the bit line pattern and the one adjacent bit line pattern, and is disposed diagonally to each other . The gate pattern is disposed in at least one row of the semiconductor substrate, the bit line pattern is disposed in one column of the semiconductor substrate, and the gate pattern and the bit line pattern are formed in the at least one row and the one line. The semiconductor device according to claim 1 , wherein the semiconductor device intersects at a right angle at an intersection of two columns. The bit line patterns, according to claim 2, wherein the at least partially disposed in said inactive region between one active region where the active region and the neighboring in the same row of said semiconductor substrate Semiconductor device. 4. The semiconductor device according to claim 3 , wherein the first storage node is at least partially disposed on the active region and partially overlaps with one bit line pattern adjacent to the active region. . At the intersection of the row and column of the semiconductor substrate,
The semiconductor device according to claim 1 , wherein the selected storage node is arranged in a zigzag manner on the active region with respect to the adjacent active region. At the intersection of the row and column of the semiconductor substrate,
The storage nodes of adjacent bit line patterns are disposed diagonally to each other with different active regions in one direction and diagonally to each other in a direction perpendicular to the one direction. Item 6. The semiconductor device according to Item 5 . Forming an inactive region in a semiconductor substrate, the inactive region forming an active region; and
Forming two gate patterns in the active region and the inactive region so as to intersect the active region at right angles;
Forming a first interlayer insulating film on the active region so as to cover the gate pattern;
A bit line pattern is formed on the first interlayer insulating layer and intersects the gate pattern at a right angle. The bit line pattern is located on the inactive region around the active region, and Forming an electrical connection with the active region between the gate patterns through an interlayer insulating film;
Forming a second interlayer insulating film on the first interlayer insulating film so as to cover the bit line pattern;
Overlying the active region, the inactive region, and the bit line pattern around the gate pattern through the first and second interlayer insulating films, and electrically connected to the active region around the gate pattern and forming a storage node for viewing including,
Electrically connecting the storage node to the active region around the gate pattern;
A node contact hole is formed in the first and second interlayer insulating films, the node contact hole is formed to expose the active region around the gate pattern, and the bit line contact hole is the node contact hole. A process of forming between,
Forming node contacts that respectively fill the node contact holes, and forming the node contacts using a conductive material;
Contacting the storage nodes with the node contacts, respectively.
The active region, the gate pattern, the bit line pattern, the node contact, and the storage node include a step located at an intersection of a row and a column of the semiconductor substrate;
At the intersection of the row and column of the semiconductor substrate,
The storage node is formed to partially overlap each of two adjacent bit line patterns located around the active region in the selected active region, and the storage node is the selected one A method of forming a semiconductor device, characterized in that two active regions are defined between the two adjacent bit line patterns located around the active region and are opposed to each other diagonally . The step of forming the gate pattern includes:
Forming a molding hole corresponding to the gate pattern in the semiconductor substrate;
Forming a gate insulating film in the molding hole;
Forming a gate located on the gate insulating film and partially burying the molding hole;
Forming a gate capping pattern located on the gate and filling the molding holes, respectively, and projecting from the main surfaces of the active region and the inactive region,
8. The method of forming a semiconductor device according to claim 7 , wherein the gate is formed using a conductive material. The step of forming the bit line pattern includes:
Forming a bit line contact hole in the first interlayer insulating film, and forming the bit line contact hole to expose the active region between the gate patterns;
Forming a bit line contact filling the bit line contact hole;
Forming a bit line conductive film and a bit line capping film to cover the bit line contact;
Etching the bit line capping film and the bit line conductive film in order to expose the first interlayer insulating film,
9. The method of claim 8 , wherein the bit line contact is formed using a conductive material, and the bit line pattern is in contact with the bit line contact through a predetermined region of the pattern. . 8. The method of claim 7 , wherein one of the storage nodes is in contact with one of the node contacts and the bit line pattern. An active region adjacent to the active region in a selected row of the semiconductor substrate is formed horizontally with the same center and the same area as the active region, and in a selected column of the semiconductor substrate. 8. The method of forming a semiconductor device according to claim 7 , wherein the active region adjacent to the active region is formed horizontally while having the same center and the same area as the active region. At the intersection of the row and column of the semiconductor substrate,
The gate pattern is formed along at least one row of the semiconductor substrate, the bit line pattern is formed along one column of the semiconductor substrate, and the gate pattern and the bit line pattern are mutually connected from the intersection. 12. The method of forming a semiconductor device according to claim 11 , wherein the semiconductor device is formed so as to intersect at right angles. At the intersection of the row and column of the semiconductor substrate,
Forming method according to claim 12 wherein the bit line pattern, characterized in that formed in the inactive region between the active regions adjacent the two in the selected one row of the semiconductor substrate . At the intersection of the row and column of the semiconductor substrate,
8. The method of forming a semiconductor device according to claim 7 , wherein a storage node between the two adjacent bit line patterns is formed on the active region in a zigzag manner. At the intersection of the row and column of the semiconductor substrate,
Storage nodes adjacent to each other between three adjacent bit line patterns are formed diagonally with different active regions in one direction and selected from the active regions in the other direction perpendicular to the one direction. 8. The method of forming a semiconductor device according to claim 7 , wherein the two are formed diagonally corresponding to each other.

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