KR20230065203A - Semiconductor device - Google Patents

Abstract

The present disclosure relates to a semiconductor device. In accordance with one embodiment, the semiconductor device includes: a substrate including an active region located between element isolation layers; a word line cross-overlapped with the active region; a bit line cross-overlapped with the active region in a direction different from the word line; a buried contact connected to the active region; a direct contact connecting the active region and the bit line; and a pad connecting the active region and the buried contact and overlapped with in a vertical direction with a part of the active region, wherein the lower surface of the pad is located below the upper surface of the active region and the upper surface of the element isolation layer, and the pad is overlapped in a horizontal direction with at least one part of the active region and the element isolation layer. Therefore, the present invention is capable of reducing parasitic capacitance between the buried contact and the bit line.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The present disclosure relates to semiconductor devices.

As semiconductor devices become increasingly highly integrated, individual circuit patterns are becoming more miniaturized in order to implement more semiconductor devices in the same area. That is, as the degree of integration of semiconductor devices increases, design rules for components of semiconductor devices decrease.

Each structure included in the semiconductor device may be formed through a photo process and an etching process, and a miss-alignment occurring during the photo process and/or the etching process may increase the defect rate of the semiconductor device. there is.

Embodiments are intended to provide a semiconductor device with improved reliability and productivity.

A semiconductor device according to an embodiment includes a substrate including an active region positioned between device isolation layers, a word line crossing and overlapping the active region, a bit line crossing and overlapping the active region in a direction different from the word line, and the A buried contact coupled to an active region, a direct contact coupled between the active region and the bit line, and a pad coupled between the active region and the buried contact and vertically overlapping a portion of the active region A lower surface of the pad is positioned at a level lower than upper surfaces of the active region and upper surfaces of the isolation layer, and the pad overlaps at least a portion of the active region and the isolation layer in a horizontal direction.

An insulating layer positioned between the bit line and the device isolation layer may be further included, and an upper surface of the pad may be positioned at a lower level than an upper surface of the insulating layer.

An upper surface of the pad may be positioned at the same level as a lower surface of the insulating layer.

An upper surface of the pad may be located at a higher level than an upper surface of the active region and an upper surface of the device isolation layer, and the upper surface of the pad may be located between an upper surface of the insulating layer and a lower surface of the insulating layer. there is.

A bit line spacer positioned at a side of the bit line, wherein an upper surface of the pad has a first portion overlapping the buried contact, and is positioned at a level higher than the first portion and overlaps the bit line spacer. and a second part that is located at a level lower than the upper surface of the active region, the second part is located at the same level as the lower surface of the insulating layer, or the second part is located at the same level as the lower surface of the insulating layer. It may be located between the upper surface of the and the lower surface of the insulating layer.

The pad includes a first pad layer and a second pad layer whose side surfaces and bottom surfaces are surrounded by the first pad layer, and the active region includes an ohmic contact portion surrounding the side surface and bottom surface of the first pad layer. And, the pad and the buried contact may include a metal material.

According to an embodiment, a semiconductor device includes a substrate including active regions defined by device isolation layers, word lines crossing and overlapping the active regions, and crossing and overlapping the active regions in a direction different from the word lines. Bit lines, buried contacts connected to the active regions, pads connecting the active regions and the buried contacts, and an insulating layer positioned between the device isolation layer and the bit lines The device isolation layer is positioned between the pads, each of the active regions surrounds a lower surface and a side surface of each of the pads, and is positioned between the device isolation layer and the pads.

An upper surface of each of the pads may be located at a level higher than an upper surface of the active region and an upper surface of the device isolation layer, and may be located at a level between an upper surface of the insulating layer and a lower surface of the insulating layer.

An upper surface of each of the pads may include a first portion located at a level lower than the lower surface of the insulating layer and a second portion located between the upper surface of the insulating layer and the lower surface of the insulating layer.

An upper surface of each of the pads may include a first part positioned at a level lower than the lower surface of the insulating layer and a second part positioned at the same level as the lower surface of the insulating layer.

According to the exemplary embodiments, a sufficient contact area between the active region and the pad connecting the buried contact and the active region may be secured. Accordingly, electrical characteristics of the semiconductor device may be improved. Also, in the semiconductor device according to an exemplary embodiment, since the pad is not formed on the upper surface of the active region and is formed in the pad trench formed in the active region, compared to the case where the pad is positioned on the upper surface of the active region, buried Parasitic capacitance between the contact and the bit line can be reduced.

1 is a layout diagram illustrating a semiconductor device according to an exemplary embodiment.
FIG. 2 is a cross-sectional view taken along line Ⅰ-Ⅰ′ of FIG. 1 .
FIG. 3 is a cross-sectional view taken along line II-II′ of FIG. 1 .
FIG. 4 is an enlarged view of an area R1 of FIG. 2 .
5 is a cross-sectional view illustrating a semiconductor device according to another embodiment.
6 is a cross-sectional view illustrating a semiconductor device according to another exemplary embodiment.
7 is a cross-sectional view taken along line Ⅰ′ of FIG. 1 according to another embodiment.
FIG. 8 is an enlarged view of an area R4 of FIG. 7 .
9 is a cross-sectional view illustrating a semiconductor device according to another exemplary embodiment.
10 to 17A, 18 to 25, 26A, 27A, 28A, and 29A are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment.
17B is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment.
17C is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another exemplary embodiment.
26B, 27B, 28B, and 29B are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment.
30 to 47 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. This invention may be embodied in many different forms and is not limited to the embodiments set forth herein.

In order to clearly describe the present invention, parts irrelevant to the description are omitted, and the same reference numerals are assigned to the same or similar components throughout the specification.

In addition, since the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, the present invention is not necessarily limited to the shown bar. In the drawings, the thickness is shown enlarged to clearly express the various layers and regions. And in the drawings, for convenience of explanation, the thicknesses of some layers and regions are exaggerated.

In addition, when a part such as a layer, film, region, plate, etc. is said to be "on" or "on" another part, this includes not only the case where it is "directly on" the other part, but also the case where another part is in the middle. . Conversely, when a part is said to be "directly on" another part, it means that there is no other part in between. In addition, being "above" or "on" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" or "on" in the opposite direction of gravity. .

In addition, throughout the specification, when a certain component is said to "include", it means that it may further include other components without excluding other components unless otherwise stated.

In addition, throughout the specification, when it is referred to as "planar image", it means when the target part is viewed from above, and when it is referred to as "cross-sectional image", it means when a cross section of the target part cut vertically is viewed from the side.

1 is a layout diagram illustrating a semiconductor device according to an exemplary embodiment. FIG. 2 is a cross-sectional view taken along line Ⅰ-Ⅰ′ of FIG. 1 . FIG. 3 is a cross-sectional view taken along line II-II′ of FIG. 1 . FIG. 4 is an enlarged view of an area R1 of FIG. 2 . 5 is a cross-sectional view illustrating a semiconductor device according to another embodiment. Specifically , FIG. 5 shows an R2 region corresponding to the R1 region of FIG. 2 .

1 to 5 , the semiconductor device 10 according to an exemplary embodiment includes an active region AR defined by an isolation layer 112 and a word line crossing and overlapping the active region AR. (WL), a bit line (BL) crossing and overlapping the active area (AR) in a different direction from the word line (WL), a buried contact (BC) connected to the active area (AR), and a bit with the active area (AR). A direct contact DC connecting the line BL and a pad XP connecting the active region AR and the buried contact BC may be included.

The active region AR may be defined by the device isolation layer 112 positioned in the substrate 100 . A plurality of active regions AR may be positioned in the substrate 100 , and the plurality of active regions AR may be separated from each other by the device isolation layer 112 . Device isolation layers 112 may be positioned on both sides of each active region AR.

The substrate 100 may include a semiconductor material. For example, the substrate 100 may include a group IV semiconductor, a group III-V compound semiconductor, a group II-VI compound semiconductor, and the like. For example, the substrate 100 may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. However, the material of the substrate 100 is not limited thereto and may be variously changed. The substrate 100 may have an upper surface parallel to the first direction (X) and the second direction (Y), and in a third direction (Z) perpendicular to the first direction (X) and the second direction (Y). It can have parallel thickness.

The active region AR may have a rod shape extending along a fourth direction DR4 oblique with respect to the first and second directions X and Y. The fourth direction DR4 may be parallel to the upper surface of the substrate 100 and may be positioned on the same plane as the first direction X and the second direction Y. The fourth direction DR4 may form an acute angle with the first direction X and the second direction Y, respectively. The plurality of active regions AR may extend in parallel directions. The plurality of active regions AR may be spaced apart from each other by a predetermined interval along the fourth direction DR4 and the first direction X. A central portion of one active region AR may be adjacent to an end portion of another active region AR in the first direction X. One end of one active region AR may be adjacent to the other end of another active region AR in the first direction X. However, the shape or arrangement of the active region AR is not limited thereto and may be variously changed.

The substrate 100 may include a cell array area and a peripheral circuit area. The cell array area is an area where a plurality of memory cells are formed, and a plurality of active areas AR may be located in the cell array area. The peripheral circuit area may be positioned to surround the cell array area, and devices driving memory cells may be positioned. In FIGS. 1 to 6 , for convenience, the cell array area is illustrated, and the illustration of the peripheral circuit area is omitted.

The device isolation layer 112 may have a shallow trench isolation (STI) structure having excellent device isolation characteristics. The device isolation layer 112 may be made of silicon oxide, silicon nitride, or a combination thereof. However, the material of the isolation layer 112 is not limited thereto and may be variously changed. The device isolation layer 112 may be formed of a single layer or multiple layers. The device isolation layer 112 may be made of a single material or may include two or more types of insulating materials.

In a cross-sectional view, an upper surface of the active region AR and an upper surface of the device isolation layer 112 may be positioned at substantially the same level. However, it is not limited thereto, and the relationship between the upper surface of the active region AR and the upper surface of the device isolation layer 112 may be variously changed.

The word line WL may extend along the first direction X and may cross the active region AR. The word line WL may overlap the active region AR and may serve as a gate electrode. One word line WL may overlap a plurality of adjacent active regions AR along the first direction X. A semiconductor device according to an exemplary embodiment may include a plurality of word lines WL. The plurality of word lines WL may extend parallel to each other along the first direction X and may be spaced apart from each other at regular intervals along the second direction Y.

Each of the plurality of active regions AR may cross-overlap two word lines WL. Each active region AR may be divided into three parts by two word lines WL. Here, the center of the active region AR positioned between the two word lines WL may be a portion connected to the bit line BL, and the active region AR positioned outside the two word lines WL. ) Both ends may be a portion connected to a capacitor (not shown). The bit line BL may be connected to the active region AR through a direct contact DC. The capacitor may be connected to the active region AR through the landing pad LP and the buried contact BC.

A word line trench WLT may be formed in the substrate 100 , and a word line structure WLS may be positioned in the word line trench WLT. That is, the word line structure WLS may have a form buried in the substrate 100 . A portion of the word line trench WLT may be positioned on the active region AR, and another portion may be positioned on the device isolation layer 112 . The word line structure WLS may include a gate insulating layer 132 , a word line WL positioned on the gate insulating layer 132 , and a word line capping layer 134 positioned on the word line WL. However, the location, shape, and structure of the word line structure WLS are not limited thereto and may be variously changed.

The gate insulating layer 132 may be located in the word line trench WLT. The gate insulating layer 132 may be conformally formed on the inner wall surface of the word line trench WLT.

The gate insulating layer 132 may include silicon oxide, silicon nitride, silicon nitride, a high-k material having a higher dielectric constant than silicon oxide, or a combination thereof. However, the position, shape, and material of the gate insulating layer 132 are not limited thereto and may be variously changed.

The word line WL may be positioned on the gate insulating layer 132 . Side and bottom surfaces of the word line WL may be surrounded by the gate insulating layer 132 . A gate insulating layer 132 is positioned between the word line WL and the active region AR. Therefore, the word line WL may not directly contact the active region AR. The word line WL may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof. However, the position, shape, and material of the word line WL are not limited thereto and may be variously changed.

The word line capping layer 134 may be positioned on the word line WL. The word line capping layer 134 may entirely cover an upper surface of the word line WL. A lower surface of the word line capping layer 134 may contact the word line WL. Side surfaces of the word line capping layer 134 may be covered by the gate insulating layer 132 . The word line capping layer 134 may include silicon oxide, silicon nitride, silicon nitride, or a combination thereof. However, the location, shape, and material of the word line capping layer 134 are not limited thereto and may be variously changed.

The word line WL may be positioned on both sides of the direct contact DC, and the word line WL and the direct contact DC may overlap each other in the third direction Z. An upper surface of the word line WL may be positioned at a lower level than a lower surface of the direct contact DC. A word line capping layer 134 may be positioned between the word line WL and the direct contact DC. Thus, the word line WL and the direct contact DC may be insulated by the word line capping layer 134 . However, the positional relationship between the word line WL and the direct contact DC is not limited thereto and may be variously changed.

The bit line BL may extend along the second direction Y and may cross the active region AR and the word line WL. Here, the bit line BL may vertically cross the word line WL. The bit line BL may be positioned on the word line WL. One bit line BL may overlap a plurality of adjacent active regions AR along the second direction Y. The bit line BL may be connected to the active region AR through a direct contact DC. One bit line BL may be connected to a plurality of adjacent active regions AR along the second direction Y. Each of the plurality of active regions AR may be connected to one bit line BL. A central portion of the active region AR may be connected to the bit line BL. However, this is only an example, and the connection form of the bit line BL and the active region AR may be variously changed. A semiconductor device according to an embodiment may include a plurality of bit lines BL. The plurality of bit lines BL may extend in parallel along the second direction Y and may be spaced apart from each other at regular intervals along the first direction X.

A direct contact trench DCT may be formed in the substrate 100 , and a direct contact DC may be positioned in the direct contact trench DCT. The direct contact trench DCT may be positioned on the active region AR, and the direct contact trench DC may be connected to the active region AR. The direct contact DC may be directly connected to the active region AR. The direct contact DC may overlap the active region AR in the third direction Z. The direct contact DC may include a conductive material. For example, the direct contact DC may include polysilicon doped with impurities or a metal such as W, Mo, Au, Cu, Al, Ni, or Co.

The bit line BL may be positioned on the substrate 100 and the direct contact DC. The bit line BL may include a first conductive layer 151 , a second conductive layer 153 , and a third conductive layer 155 sequentially stacked. The first conductive layer 151, the second conductive layer 153, and the third conductive layer 155 may include a conductive material. For example, the first conductive layer 151 may include polysilicon doped with impurities or a metal such as W, Mo, Au, Cu, Al, Ni, or Co. The second conductive layer 153 may include a metal such as Ti or Ta and/or a metal nitride such as TiN or TaN. The third conductive layer 155 may include a metal such as W, Mo, Au, Cu, Al, Ni, or Co. However, structures and materials of the conductive layers constituting the bit line BL are not limited thereto and may be variously changed.

The bit line BL may directly contact the direct contact DC. The first conductive layer 151 of the bit line BL may contact the side surface of the direct contact DC, and the second conductive layer 153 of the bit line BL may contact the upper surface of the direct contact DC. can The direct contact DC is positioned between the active region AR and the bit line BL, and may electrically connect the active region AR and the bit line BL. That is, the bit line BL may be connected to the active region AR through the direct contact DC. Among the conductive layers constituting the bit line BL, the first conductive layer 151 and the direct contact DC may include the same material. For example, the first conductive layer 151 and the direct contact DC may include polysilicon doped with impurities. However, it is not limited thereto, and the first conductive layer 151 and the direct contact DC may include different materials.

A bit line capping layer 158 may be positioned on the bit line BL. The bit line BL and the bit line capping layer 158 may form a bit line structure BLS. The bit line capping layer 158 may overlap the bit line BL and the direct contact DC in the third direction Z. The bit line BL and the direct contact DC may be patterned using the bit line capping layer 158 as a mask. A planar shape of the bit line BL may be substantially the same as that of the bit line capping layer 158 . The bit line capping layer 158 is illustrated as being in contact with the third conductive layer 155 of the bit line BL, but is not limited thereto. Another layer may be further positioned between the bit line capping layer 158 and the third conductive layer 155 of the bit line BL. The bit line capping layer 158 may include silicon nitride. However, the material of the bit line capping layer 158 is not limited thereto and may be variously changed.

Spacer structures 620 may be positioned on both sides of the bit line structure BLS. The spacer structure 620 may cover side surfaces of the bit line capping layer 158 , the bit line BL, and the direct contact DC. The spacer structure 620 may extend substantially in the third direction Z along the side surface of the bit line structure BLS. At least a portion of the spacer structure 620 may be positioned within the direct contact trench (DCT). In the direct contact trench DCT, the spacer structures 620 may be positioned on both sides of the direct contact trench DC.

The spacer structure 620 may be formed of multiple layers made of a combination of various types of insulating materials. The spacer structure 620 may include a first spacer 621 , a second spacer 623 , a third spacer 625 , and a fourth spacer 627 . However, it is not limited thereto, and the number and structure of layers constituting the spacer structure 620 may be variously changed. The spacer structure 620 may be made of a single layer. In some embodiments, the spacer structure 620 may be formed of an air spacer structure surrounded by spacers and having an air space.

The first spacer 621 may cover side surfaces of the bit line structure BLS and the direct contact DC. Within the direct contact trench DCT, the first spacer 621 may be formed to cover the bottom and side surfaces of the direct contact trench DCT.

The second spacer 623 may be positioned on the first spacer 621 . A lower surface and a side surface of the second spacer 623 may be surrounded by the first spacer 621 . The second spacer 623 may be located in the direct contact trench (DCT). The second spacer 623 may be positioned on the first spacer 621 positioned within the direct contact trench DCT and on the bottom and side surfaces of the direct contact trench DCT.

The third spacer 625 may be formed to fill the direct contact trench DCT. The third spacer 625 may be positioned on both sides of the direct contact DC within the direct contact trench DCT.

The fourth spacer 627 may be positioned on the first spacer 621 , the second spacer 623 , and the third spacer 625 . The fourth spacer 627 may overlap the first spacer 621 along the first direction X, and overlap the second spacer 623 and the third spacer 625 along the third direction Z. can do. The fourth spacer 627 may extend in the third direction (Z) along the side surface of the first spacer 621 . The fourth spacer 627 may extend parallel to the first spacer 621 . A lower surface of the fourth spacer 627 may be surrounded by the second spacer 623 and the third spacer 625 .

The spacer structure 620 may include an insulating material. Each of the first spacer 621 , the second spacer 623 , the third spacer 625 , and the fourth spacer 627 may include the same material. Alternatively, at least some of the first spacer 621 , the second spacer 623 , the third spacer 625 , and the fourth spacer 627 may include different materials.

Each of the first spacer 621 , the second spacer 623 , the third spacer 625 , and the fourth spacer 627 is silicon nitride, silicon nitride oxide, silicon oxide, silicon carbonate, silicon carbonitride, or silicon carbonitride. And it may include at least one of combinations thereof. For example, the first spacer 621 and the third spacer 625 may include silicon nitride, and the second spacer 623 and the fourth spacer 627 may include silicon oxide. However, the material of the spacer structure 620 is not limited thereto and may be variously changed.

An insulating layer 640 may be positioned under the bit line BL. The insulating layer 640 may be positioned between the bit line BL and the device isolation layer 112 . A direct contact DC is positioned between the bit line BL and the active region AR, and the insulating layer 640 may not be positioned. The insulating layer 640 may be positioned on the word line structure WLS. The insulating layer 640 may be positioned between the word line structure WLS and the bit line BL.

The insulating layer 640 may include a first insulating layer 642 , a second insulating layer 644 , and a third insulating layer 646 sequentially stacked. At least some of the first insulating layer 642 , the second insulating layer 644 , and the third insulating layer 646 may have different widths. Widths of the second insulating layer 644 and the third insulating layer 646 may be substantially the same. Widths of the second insulating layer 644 and the third insulating layer 646 may be greater than those of the bit line BL and the bit line capping layer 158 .

A width of the first insulating layer 642 may be different from that of the second insulating layer 644 and the third insulating layer 646 . The width of the first insulating layer 642 may be greater than that of the second insulating layer 644 and the third insulating layer 646 . Accordingly, the width of the first insulating layer 642 may be greater than that of the bit line BL.

A side surface of the first insulating layer 642 may be surrounded by a buried contact BC and a pad XP to be described later. A side surface of the second insulating layer 644 may be surrounded by a buried contact BC, which will be described later. An upper surface of the third insulating layer 646 may be covered by the first spacer 621 , and a side surface of the third insulating layer 646 may be surrounded by a buried contact BC.

A part of the lower surface of the first insulating layer 642 directly contacts the device isolation layer 112, and the other part directly contacts the upper surface of the active region AR positioned on both sides of the device isolation layer 112. can

At least some of the first insulating layer 642 , the second insulating layer 644 , and the third insulating layer 646 may have different thicknesses. For example, the first insulating layer 642 may be thicker than the second insulating layer 644 , and the second insulating layer 644 may be thicker than the third insulating layer 646 .

The insulating layer 640 may include an insulating material. Each of the first insulating layer 642 , the second insulating layer 644 , and the third insulating layer 646 may include an insulating material. For example, the first insulating layer 642 may include silicon oxide. The second insulating layer 644 may include a material having an etch selectivity different from that of the first insulating layer 642 and the third insulating layer 646 . For example, the second insulating layer 644 may include silicon nitride. For example, the third insulating layer 646 may include silicon oxide or silicon nitride. However, the structure, width, thickness, and material of the insulating layer 640 are not limited thereto and may be variously changed.

A buried contact BC may be positioned between the plurality of bit lines BL. A semiconductor device according to an exemplary embodiment may include a plurality of buried contacts BC. The plurality of buried contacts BC may be spaced apart from each other in the first direction X and the second direction Y. For example, a plurality of buried contacts BC may be disposed to be spaced apart from each other in the second direction Y between two adjacent bit lines BL.

In addition, a plurality of buried contacts BC may be disposed to be spaced apart from each other in the first direction X between two adjacent word lines WL. However, the arrangement form of the plurality of buried contacts BC is not limited thereto and may be variously changed.

At least a portion of the buried contact BC may overlap the active region AR in the third direction Z, and another portion may overlap the device isolation layer 112 in the third direction Z. The buried contact BC may be electrically connected to the active region AR through the pad XP. The buried contact BC may directly contact the pad XP. A part of the lower surface of the buried contact BC may directly contact the pad XP, and the remaining part may directly contact the first spacer 621 , the second spacer 623 , and the third spacer 625 . there is.

A spacer structure 620 may be positioned on both side surfaces of the buried contact BC. A spacer structure 620 may be positioned between the buried contact BC and the bit line BL. For example, one side surface of the buried contact BC directly contacts the third spacer 625 and the fourth spacer 627, and the other side surface of the buried contact BC directly contacts the insulating layer 640 and the fourth spacer 625. It may directly contact the spacer 627 . However, this is just one example, and the positional relationship between the buried contact BC and the spacer structure 620 may be variously changed.

The upper surface of the buried contact BC may be located at a lower level than the upper surface of the bit line BL, and the lower surface of the buried contact BC may be located at a higher level than the lower surface of the direct contact DC. there is. However, it is not limited thereto, and the positional relationship between the buried contact BC, the bit line BL, and the direct contact DC may be variously changed.

The buried contact BC may include a conductive material. For example, the buried contact BC may include polysilicon doped with impurities, but is not limited thereto, and the material included in the buried contact BC may be variously changed.

The pad XP is positioned between the active region AR and the buried contact BC, and may electrically connect the active region AR and the buried contact BC. 4 and 5 show that the buried contact BC and the pad XP and the active region AR and the pad XP are in direct contact, but are not limited thereto, and the buried contact BC and the pad Other layers may be further positioned between the (XP) and between the active region (AR) and the pad (XP).

The semiconductor device 10 according to an exemplary embodiment may include a plurality of pads XP. The device isolation layer 112 may be positioned between the plurality of pads XP, and the active region AR may be positioned between the pads XP and the device isolation layer 112 . That is, at least a portion of the pad XP may overlap a portion of the active region AR, the isolation layer 112 , and the insulating layer 640 along one side of the first direction X. In addition, at least a portion of the pad XP may overlap the spacer structure 620 and the direct contact DC along the other side of the first direction X. For example, the pad XP may overlap the first spacer 621 , the second spacer 623 , and the third spacer 625 along the other side of the first direction X. Also, the pad XP may be located at a level between the upper and lower surfaces of the direct contact DC.

A part of the pad XP may overlap the active region AR along the third direction Z, and the remaining part may overlap the device isolation layer along the third direction Z.

At least a portion of a lower surface of the pad XP and at least a portion of a side surface of the pad XP may be surrounded by the active region AR. That is, in cross section, the pad XP may have a shape that penetrates a part of the active region AR and a part of the device isolation layer 112 toward the substrate 100 from the upper surface of the active region AR.

At least a part of one side surface of the pad XP may directly contact the active region AR, and the other part may directly contact the first insulating layer 642 . In addition, at least a portion of the other side surface of the pad XP may directly contact the first spacer 621 . The other side surface of the pad XP may be positioned at substantially the same boundary as the side surface of the direct contact trench DCT. That is, the side surface of the pad XP and the side surface of the direct contact trench DCT may extend along the same boundary in the third direction Z.

An upper surface of the pad XP may directly contact the buried contact BC. An upper surface of the pad XP may be positioned at a higher level than an upper surface of the active region AR and an upper surface of the isolation layer 112 . An upper surface of the pad XP may be positioned at a level between the upper and lower surfaces of the first insulating layer 642 . Also, an upper surface of the pad XP may be positioned at a level between an upper surface and a lower surface of the direct contact DC. The upper surface of the pad XP is at substantially the same level as the upper surfaces of the first spacer 621 , the second spacer 623 , and the third spacer 625 contacting the bottom surface of the buried contact BC. can be located However, the position of the upper surface of the pad XP is not limited thereto and may be variously changed.

For example, as shown in FIG. 5 , the top surface of the pad XP may be positioned at substantially the same level as the top surface of the active region AR and the top surface of the device isolation layer 112 . Also, an upper surface of the pad XP may be positioned at substantially the same level as a lower surface of the first insulating layer 642 .

When the top surface of the pad XP is positioned at substantially the same level as the top surface of the active region AR and the top surface of the device isolation layer 112, the pad XP extends one side in the first direction X. Accordingly, it may non-overlap with the first insulating layer 642 . In addition, one side surface of the pad XP directly contacts the active region AR and may be covered by the active region AR.

At least a portion of the lower surface of the pad XP may directly contact the active region AR, and the remaining portion may directly contact the device isolation layer 112 . The lower surface of the pad XP may be positioned at a lower level than the upper surface of the active region AR and the upper surface of the device isolation layer 112 . Also, a lower surface of the pad XP may be positioned at a higher level than a bottom surface of the direct contact trench DCT.

The pad XP may include a conductive material. For example, the pad XP may include polysilicon doped with impurities or a metal such as W, Mo, Au, Cu, Al, Ni, or Co. However, the structure, shape, arrangement relationship with other components, and material of the pad XP are not limited thereto and may be variously changed.

A landing pad LP may be positioned on the buried contact BC. A semiconductor device according to an embodiment may include a plurality of landing pads LP. The plurality of landing pads LP may be spaced apart from each other in the first direction X and the second direction Y. A plurality of landing pads LP may be arranged in a line along the first direction X. A plurality of landing pads LP may be arranged in a zigzag shape along the second direction Y. For example, they may be alternately arranged on the left and right sides of the bit line BL. However, the arrangement form of the plurality of landing pads LP is not limited thereto and may be variously changed.

The landing pad LP may cover an upper surface of the buried contact BC and may overlap the buried contact BC in the third direction Z. At least a portion of the landing pad LP may overlap the spacer structure 620 in the third direction Z, or may overlap the bit line BL in the third direction Z. An upper surface of the landing pad LP may be positioned at a higher level than an upper surface of the bit line capping layer 158 .

A spacer structure 620 may be positioned on both side surfaces of the landing pad LP. A spacer structure 620 may be positioned between the landing pad LP and the bit line BL and between the landing pad LP and the bit line capping layer 158 . The landing pad LP may be electrically connected to the buried contact BC. The landing pad LP may directly contact the buried contact BC. The landing pad LP is connected to the pad XP through the buried contact BC, and the landing pad LP can be electrically connected to the active region AR.

The landing pad LP may include a metal silicide layer 171 and a conductive layer 173 . The metal silicide layer 171 may be positioned on the buried contact BC, and the conductive layer 173 may be positioned on the metal silicide layer 171 .

The metal silicide layer 171 may directly contact the buried contact BC. The metal silicide layer 171 may entirely cover an upper surface of the buried contact BC. Spacer structures 620 may be positioned on both side surfaces of the metal silicide layer 171 . For example, the metal silicide layer 171 may contact the fourth spacer 627 . The metal silicide layer 171 may include a metal silicide material such as cobalt silicide, nickel silicide, or manganese silicide. However, the shape and material of the metal silicide layer 171 are not limited thereto and may be variously changed. In some embodiments, the metal silicide layer 171 may be omitted.

A lower surface of the conductive layer 173 may contact the metal silicide layer 171 . The conductive layer 173 may include metal, metal nitride, impurity-doped polysilicon, or a combination thereof. For example, the conductive layer 173 may include W. However, the shape and material of the conductive layer 173 are not limited thereto and may be variously changed.

Although omitted in FIG. 2 , other layers may be further positioned between the metal silicide layer 171 and the conductive layer 173 . For example, a conductive barrier layer may be positioned between the metal silicide layer 171 and the conductive layer 173 . The conductive barrier layer may include Ti, TiN, or a combination thereof.

An insulating pattern 660 may be positioned between the plurality of landing pads LP. The insulating pattern 660 may be formed to fill a space between the plurality of landing pads LP. The plurality of landing pads LP may be separated from each other by the insulating pattern 660 .

The insulating pattern 660 may include silicon nitride, silicon nitride, silicon oxide, or a combination thereof. The insulating pattern 660 may be formed of a single layer or multiple layers. For example, the insulating pattern 660 may include a first material layer and a second material layer. Here, the first material layer may include silicon oxide or a low-k material having a low dielectric constant, such as SiOCH and SiOC, and the second material layer may include silicon nitride or silicon nitride. . However, the shape and material of the insulating pattern 660 are not limited thereto and may be variously changed.

Although omitted in FIG. 2 , a capacitor structure may be positioned on the landing pad LP. The capacitor structure can include a first capacitor electrode, a second capacitor electrode, and a dielectric layer positioned between the first capacitor electrode and the second capacitor electrode. The first capacitor electrode may contact the landing pad LP and may be electrically connected to the landing pad LP. The capacitor structure may be electrically connected to the active region AR through the landing pad LP and the buried contact BC.

A semiconductor device according to an embodiment may include a plurality of capacitor structures. A first capacitor electrode may be positioned on each landing pad LP, and a plurality of first capacitor electrodes may be positioned to be separated from each other. The same voltage may be applied to the second capacitor electrodes of the plurality of capacitor structures and may be integrally formed. Dielectric layers of the plurality of capacitor structures may be integrally formed.

According to the semiconductor device 10 according to an exemplary embodiment, the pad XP connecting the buried contact BC and the active region AR is not formed on the upper surface of the active region AR, and the active region AR ), the contact area between the active region AR and the pad XP may be widened. That is, as the pad XP is located in the pad trench formed in the active region AR, at least a portion of the lower surface of the pad XP and at least a portion of the side surface of the pad XP come into contact with the active region AR. can Therefore, as the pad XP is formed on the upper surface of the active region AR, there is a gap between the pad XP and the active region AR compared to the case where only the lower surface of the pad XP contacts the active region AR. The contact area can be widened.

In addition, as the pad XP is formed in the pad trench formed in the active region AR, the pads XP are separated and insulated from each other by the device isolation layer 112 positioned between the adjacent pads XP. Therefore, there is no need to form a separate insulating pattern to separate and insulate the pad XP. As the active region AR is etched in the process of forming a separate insulating pattern, a decrease in the width of the active region AR in the first direction X may be prevented.

In addition, as the pad XP is not formed on the top surface of the active region AR but is formed within the pad trench formed in the active region AR, the buried contact BC and the bit line are connected by the pad XP. Parasitic capacitance between (BL) can be reduced. That is, when the pad XP is located in the pad trench formed in the active region AR, the bit line BL along the first direction X is formed by the thickness of the pad XP along the third direction Z. Since the area of the buried contact BC overlapping with , may decrease, parasitic capacitance between the buried contact BC and the bit line BL may decrease.

Hereinafter, another embodiment of a semiconductor device will be described with reference to FIGS. 6 to 9 . In the following embodiments, the same reference numerals refer to components identical to those of the previously described embodiments, and redundant descriptions will be omitted or simplified, and description will focus on differences.

6 is a cross-sectional view illustrating a semiconductor device according to another exemplary embodiment. Specifically, FIG. 6 shows an R3 region corresponding to the R1 region of FIG. 2 .

According to the embodiment shown in FIG. 6 , unlike the pad XP according to the embodiment shown in FIGS. 4 and 5 , the pad XP_1 includes the first pad layer XP1_1 and the second pad layer XP2_1. can include Also, the active region AR may include a main active region AR_M and an ohmic contact portion AR_OC.

Specifically, the pad XP_1 electrically connecting the buried contact BC and the active region AR includes the first pad layer XP1_1 and the second pad layer XP2_1 positioned on the first pad layer XP1_1. can include

The first pad layer XP1_1 has a width smaller than that of the second pad layer XP2_1 and may conformally surround side and lower surfaces of the second pad layer XP2_1. The first pad layer XP1_1 may directly contact side surfaces and lower surfaces of the second pad layer XP2_1. Top surfaces of the first pad layer XP1_1 and the second pad layer XP2_1 may directly contact the buried contact BC.

6 illustrates that the pad XP_1 includes two layers, but is not limited thereto, and the pad XP_1 further includes another layer between the first pad layer XP1_1 and the second pad layer XP2_1. can do. In addition, another layer may be further positioned between the pad XP_1 and the buried contact BC.

The first pad layer XP1_1 and the second pad layer XP2_1 may include a metal material, a metal nitride, or a combination thereof. For example, the first pad layer XP1_1 may include Ti, TiN, or a combination thereof, and the second pad layer XP2_1 may include a metal such as W or Mo, a metal nitride, or a combination thereof. . However, it is not limited thereto, and the structures, shapes, and materials of the first pad layer XP1_1 and the second pad layer XP2_1 may be variously changed.

An active region AR according to the embodiment shown in FIG. 6 may include a main active region AR and an ohmic contact portion AR_OC positioned on the main active region AR_M. The ohmic contact portion AR_OC may be positioned between the pad XP_1 and the main active region AR_M. That is, the ohmic contact unit AR_OC may be located in an upper region of the active region AR. In other words, the ohmic contact portion AR_OC may be located in the active region AR directly contacting the pad XP_1.

The ohmic contact portion AR_OC may surround at least a portion of a lower surface and at least a portion of a side surface of the pad XP_1. The ohmic contact portion AR_OC may directly contact the bottom and side surfaces of the pad XP_1. An upper surface of the pad XP_1 may be positioned at a higher level than the upper surface of the ohmic contact portion AR_OC, and a lower surface of the pad XP_1 may be positioned at a level lower than the upper surface of the ohmic contact portion AR_OC.

The ohmic contact portion AR_OC may include a metal silicide material such as cobalt silicide or manganese silicide. However, the shape and material of the ohmic contact unit AR_OC are not limited thereto and may be variously changed.

In this embodiment, when the pad XP_1 includes a metal material, the buried contact BC may also include a metal material. For example, the buried contact BC may include a metal such as W, a metal nitride, or a combination thereof. However, the material of the buried contact BC is not limited thereto and may be variously changed.

In FIG. 6 , the pad XP_1 and the buried contact BC are shown as being in direct contact, but the present invention is not limited thereto, and another layer may be further positioned between the pad XP_1 and the buried contact BC.

FIG. 7 is a cross-sectional view taken along line Ⅰ-I' in FIG. 1 according to another embodiment. FIG. 8 is an enlarged view of an area R4 of FIG. 7 . 9 is a cross-sectional view illustrating a semiconductor device according to another exemplary embodiment. Specifically, FIG. 9 shows an R5 region corresponding to the R4 region of FIG. 7 .

Unlike the spacer structure 620 according to the embodiment illustrated in FIGS. 7 to 9 , the spacer structure 620_1 according to the exemplary embodiment illustrated in FIGS. 7 to 9 may further include a fifth spacer 629 . In addition, the pad XP_2 may be positioned to further extend toward the fifth spacer 629 from a contact surface between the pad XP_2 and the buried contact BC.

Referring to FIGS. 7 and 8 , a fifth spacer 629 may be positioned on the third spacer 625 and the fourth spacer 627 . The fifth spacer 629 may overlap the fourth spacer 627 along the first direction (X), and may overlap the third spacer 625 along the third direction (Y). The fifth spacer 629 may extend along the side surface of the fourth spacer 627 in the third direction (Z). The fifth spacer 629 may extend parallel to the first spacer 621 , the second spacer 623 , and the third spacer 625 . A lower surface and a side surface of the fifth spacer 629 may be surrounded by a third spacer 625 .

The fifth spacer 629 is positioned between the fourth spacer 627 and the buried contact BC and between the fourth spacer 627 and the landing pad LP, and is positioned between the buried contact BC and the landing pad LP. ) can come into direct contact with In addition, the fifth spacer 629 covers a part of the side surface of the first insulating layer 642 and the side surfaces of the second insulating layer 644 and the third insulating layer 646, and the second insulating layer 644 and It may directly contact the third insulating layer 646 . A lower surface of the fifth spacer 629 directly contacts the pad XP_2 and the first insulating layer 642 and may be covered by the pad XP_2 and the first insulating layer 642 .

The fifth spacer 629 may include at least one of silicon nitride, silicon nitride, silicon oxide, silicon carbonate, silicon carbonitride, silicon carbonitride, and combinations thereof. For example, the fifth spacer 629 may include silicon nitride.

The pad XP_2 may be positioned to extend along the third direction Z from a contact surface where the buried contact BC and the pad XP_2 contact each other. That is, the pad XP_2 further extends from the contact surface where the buried contact BC and the pad XP_2 contact each other in the third direction Z, and is formed between the buried contact BC and the first insulating layer 642 and It may be positioned between the buried contact BC and the active region AR. One side of the pad XP_2 further extended in the third direction Z from the contact surface where the buried contact BC and the pad XP_2 come into direct contact with the buried contact BC, and the other side of the pad XP_2 is an active area. (AR) and the first insulating layer 642 may be directly contacted. In addition, a side surface of the pad XP_2 may be located at substantially the same boundary as a side surface of the direct contact trench DCT_1.

Accordingly, a lower surface of the buried contact BC may be covered by the pad XP_2 , and a side surface of the buried contact BC may be covered by the pad XP_2 and the fifth spacer 629 .

The top surface XP_S of the pad XP_2 is formed along the third direction Z with the first portion XP_S1 overlapping the buried contact BC and the fifth spacer 629 along the third direction Z. An overlapping second part (XP_2) may be included. The first part (XP_S1) may be located at a lower level than the second part (XP_S2).

Specifically, the first portion XP_S1 may be positioned at a level lower than the lower surface of the first insulating layer 642 . That is, the first portion XP_S1 may be positioned at a level lower than the upper surface of the active region AR and the upper surface of the isolation layer 112 that directly contact the lower surface of the first insulating layer 642 . The first portion XP_S1 may directly contact the buried contact BC.

The second portion XP_S2 may be positioned at a level between the upper and lower surfaces of the first insulating layer 642 . That is, the second portion XP_S2 may be positioned at a higher level than the upper surface of the active region AR and the upper surface of the device isolation layer 112 that directly contact the lower surface of the first insulating layer 642 . The second portion XP_S2 may directly contact the fifth spacer 629 .

In addition, the first part XP_S1 is formed by the upper surface of the first spacer 621 , the upper surface of the second spacer 623 , and the upper surface of the third spacer 625 directly contacting the buried contact BC. They may be located on substantially the same level. However, the arrangement relationship between the pad XP_2 and other components is not limited thereto and may be variously changed.

For example, unlike the embodiment shown in FIG. 8 , in the embodiment shown in FIG. 9 , the second part XP_S2 of the upper surface XP_S of the pad XP_2 is formed on the lower surface and the lower surface of the first insulating layer 642 . They may be located on substantially the same level. That is, the second portion XP_S2 may be positioned at substantially the same level as the upper surface of the active region AR and the upper surface of the isolation layer 112 that directly contact the lower surface of the first insulating layer 642 . there is.

In addition, the second portion XP_S2 may be spaced apart from the fifth spacer 629 along the third direction Z with the first insulating layer 642 interposed therebetween. That is, the second portion XP_S2 may directly contact the lower surface of the first insulating layer 642 and be spaced apart from the fifth spacer 629 . Accordingly, side surfaces of the buried contact BC may be covered by the pad XP_2 , the first insulating layer 642 , and the fifth spacer 629 .

6 to 9 , pads XP_1 and XP_2 connecting the buried contact BC and the active region AR are provided similarly to the semiconductor device 10 according to the exemplary embodiment. As it is not formed on the upper surface of the active region AR but is formed within the pad trench formed in the active region AR, the contact area between the active region AR and the pads XP_1 and XP_2 may be widened. there is.

Hereinafter, a method of manufacturing a semiconductor device will be described with reference to FIGS. 9 to 47 . Hereinafter, the same reference numerals refer to the same components described previously, and redundant descriptions will be omitted or simplified, and the differences will be mainly described.

10 to 17A, 18 to 25, 26A, 27A, 28A, and 29A are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment. 17B is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment. 17C is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another exemplary embodiment. 26B, 27B, 28B, and 29B are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment.

Specifically, FIGS. 10, 12, 14, 16, 18, 20, 22, 24, 26a, 26b, 28a, and 28b are plan views, and FIGS. 11, 13, 15, 17a to 17c, 19, 21, 23, 25 , FIGS. 27A, 27B, 29A, and 29B are cross-sectional views taken along cutting lines of corresponding plan views.

Referring to FIGS. 10 and 11 , trenches for isolating a plurality of devices may be formed in the substrate 100 , and device isolation layers 112 may be formed to fill the trenches. A plurality of active regions AR may be defined by the device isolation layer 112 . A plurality of active regions AR may be positioned in the substrate 100 , and the plurality of active regions AR may be separated from each other by the device isolation layer 112 . Device isolation layers 112 are positioned on both sides of each active region AR.

An upper surface of the active region AR and an upper surface of the device isolation layer 112 may be positioned at substantially the same level. The active region AR may have a rod shape extending along a fourth direction DR4 oblique with respect to the first and second directions X and Y on a plane.

Subsequently, further referring to FIG. 3 together with FIGS. 10 and 11 , after forming a word line trench WLT extending along the first direction X and intersecting the active region AR, the word line trench ( A gate insulating layer 132 extending along the first direction X in the WLT and overlapping the active region AR, a word line WL, and a word line capping layer 134 may be sequentially formed. .

The word line WL extends along the first direction X, and may cross and overlap the active region AR. One word line WL may overlap a plurality of adjacent active regions AR along the first direction X. The plurality of word lines WL may extend parallel to each other along the first direction X and may be spaced apart from each other at regular intervals along the second direction Y.

In plan view, the gate insulating layer 132 may be positioned on a side surface of the word line capping layer 134 , and the word line capping layer 134 may have the same shape as the word line WL.

Next, referring to FIGS. 12 and 13 , a first preliminary insulating layer 642P, a second preliminary insulating layer 644P, and a third preliminary insulating layer 646P may be sequentially stacked on the substrate 100 . .

The first preliminary insulating layer 642P, the second preliminary insulating layer 644P, and the third preliminary insulating layer 646P may constitute the preliminary insulating layer 640P. However, the structure of the preliminary insulating layer 640P is not limited thereto, and may be formed of a single layer, a double layer, or four or more insulating layers.

Also, the thickness of at least one of the thicknesses of the first preliminary insulating layer 642P, the second preliminary insulating layer 644P, and the third preliminary insulating layer 646P may be different. For example, the first preliminary insulating layer 642P may be thicker than the second preliminary insulating layer 644P, and the second preliminary insulating layer 644P may be thicker than the third preliminary insulating layer 646P. However, the thickness of each of the first preliminary insulating layer 642P, the second preliminary insulating layer 644P, and the third preliminary insulating layer 646P is not limited thereto and may be variously changed.

Each of the first preliminary insulating layer 642P, the second preliminary insulating layer 644P, and the third preliminary insulating layer 646P may be made of an insulating material. For example, the first preliminary insulating layer 642P may include silicon oxide. The second preliminary insulating layer 644P may include a material having an etch selectivity different from that of the first preliminary insulating layer 642P. For example, the second preliminary insulating layer 644P may include silicon nitride. For example, the third preliminary insulating layer 646P may include silicon oxide or silicon nitride. However, the material of the preliminary insulating layer 640P is not limited thereto and may be variously changed.

Next, a first hard mask pattern 910 may be formed by forming a first hard mask layer on the preliminary insulating layer 640P and then patterning the first hard mask layer using a photo and etching process.

The first hard mask pattern 910 may have a planar lattice shape. The first hard mask pattern 910 extends in parallel in a first direction (X), and extends in parallel in a horizontal portion 911 spaced at regular intervals along a second direction (Y) and in a second direction (Y). and may include vertical portions 912 spaced at regular intervals along the first direction (X). The horizontal portion 911 and the vertical portion 912 may cross each other on a plane. That is, the vertical portion 912 may be located between the horizontal portions 911 spaced apart in the second direction (Y).

The width of the horizontal portion 911 may be greater than that of the vertical portion 912 . The width of the vertical portion 912 along the first direction X is the width of the upper surface of the active region AR along the first direction X and the width of the isolation layer 112 along the first direction X. It may be greater than the width of the top surface. However, the widths of the horizontal portion 911 and the vertical portion 912 of the first hard mask pattern 910 are not limited thereto and may be variously changed.

The first hard mask material layer may include a material such as spin on coating (SOH), photoresist, or silicon oxide. However, the first hard mask material layer is not limited thereto and may be variously changed.

By patterning the first hard mask layer, the horizontal portion 911 and the vertical portion 912 of the first hard mask pattern 910 may be simultaneously patterned. However, it is not limited thereto, and a method of forming the horizontal portion 911 and the vertical portion 912 of the first hard mask pattern 910 may be variously changed.

For example, the horizontal portion 911 and the vertical portion 912 of the first hard mask pattern 910 may be formed through a separate patterning process. When the horizontal portion 911 and the vertical portion 912 are formed through separate patterning processes, the horizontal portion 911 and the vertical portion 912 may include different materials.

As such, as the horizontal portion 911 and the vertical portion 912 of the first hard mask pattern 910 intersect on a plane, the first hard mask pattern 910 on a plane may have a lattice shape. The hard mask pattern 910 may include a plurality of openings defined by a horizontal portion 911 and a vertical portion 912 . The opening of the first hard mask pattern 910 may expose an upper surface of the third preliminary insulating layer 646P positioned under the first hard mask pattern 910 .

Next, referring to FIGS. 14 and 15 together with FIG. 13 , a third preliminary insulating layer 646P, a second preliminary insulating layer 644P, and a first preliminary insulating layer ( 642P), a portion of the active region AR, and a portion of the isolation layer 112 may be sequentially etched to form the pad trench XPT. In this case, portions of the active region AR and the device isolation layer 112 that do not overlap with the first hard mask pattern 910 along the third direction Z may be etched along the third direction Z.

On a plan view, the pad trench XPT is formed to be spaced apart from each other in the first direction X and the second direction Y, and the pad trench XPT includes the active region AR, the device isolation layer 112, and the gate. The insulating layer 132 may be exposed.

In this case, an interface between the active region AR and the device isolation layer 112 may be located at approximately the center of the pad trench XPT. The active region AR and the device isolation layer 112 may constitute a bottom surface of the pad trench XPT. The isolation layer 112 and the preliminary insulating layer 640P constitute one side of the pad trench XPT, and the active region AR and the preliminary insulating layer 640P constitute the other side of the pad trench XPT. can However, the formation method and shape of the pad trench XPT are not limited thereto and may be variously changed.

Next, referring to FIGS. 16 and 17A , a pad XP may be formed in the pad trench XPT. A lower surface of the pad XP may directly contact the active region AR and the device isolation layer. One side of the pad XP directly contacts the active region AR and the first preliminary insulating layer 642P, and the other side of the pad XP includes the device isolation layer 112 and the first preliminary insulating layer 642P. can come into direct contact with

Forming the pad XP within the pad trench XPT may include forming a pad material layer on the preliminary insulating layer 640P and within the pad trench XPT until the first preliminary insulating layer 642P is exposed. It may include a planarization process step such as an etch back process or chemical mechanical polishing (CMP). Accordingly, the upper surface of the pad XP and the upper surface of the first preliminary insulating layer 642P may be flat. That is, the upper surface of the pad XP and the upper surface of the first preliminary insulating layer 642P may be located at the same level. However, the planarization process step is not limited thereto and may be variously changed. After the planarization process step, the remaining first preliminary insulating layer 642P becomes a first insulating layer 642 to be described later.

For example, as in the embodiment shown in FIG. 17B, after forming a pad material layer on the preliminary insulating layer 640P and in the pad trench XPT, the upper surface of the active region AR and the isolation layer 112 are formed. A planarization process may be performed until the upper surface of the is exposed. Accordingly, the upper surface of the pad XP, the upper surface of the active region AR, and the upper surface of the isolation layer 112 may be flat. That is, the top surface of the pad XP, the top surface of the active region AR, and the top surface of the device isolation layer 112 may be positioned at the same level.

The pad XP may include a conductive material. For example, the second material layer 150b may include polysilicon doped with impurities. However, the method of forming the pad XP, the structure of the pad XP, and the material are not limited thereto and may be variously changed.

For example, as in the embodiment illustrated in FIG. 17C , the pad XP_1 may include a first pad layer XP1_1 and a second pad layer XP2_1 including a metal material. As such, when the pad XP_1 includes a metal material, the active region AR may include the main active region AR and the ohmic contact portion AR_OC positioned on the main active region AR_M. The ohmic contact portion AR_OC may be positioned between the pad XP_1 and the main active region AR_M.

First, a metal layer may be formed on the active region AR positioned on the side surface and bottom surface of the pad trench XPT, and then a heat treatment process may be performed to form the ohmic contact portion AC_OC.

Subsequently, a first pad layer XP1_1 may be conformally formed on the preliminary insulating layer 640 and in the pad trench XPT. That is, the first pad layer XP1_1 may be conformally formed on the bottom and side surfaces of the pad trench XPT.

Subsequently, a second pad layer XP2_1 may be formed on the first pad layer XP1_1. That is, the first pad layer XP1_1 and the second pad layer XP2_1 may be sequentially formed on the insulating layer 640 . In addition, the remaining area of the pad trench XPT remaining after the first pad layer XP1_1 is formed may be filled with the second pad layer XP2_1. Accordingly, the bottom and side surfaces of the second pad layer XP2_1 may be surrounded by the first pad layer XP1_1.

Subsequently, a planarization process may be performed until the first preliminary insulating layer 642P is exposed. Accordingly, the upper surface of the first pad layer XP1_1, the upper surface of the second pad layer XP2_1, and the upper surface of the first preliminary insulating layer 642P may be flat. That is, the top surface of the first pad layer XP1_1 , the top surface of the second pad layer XP2_1 , and the top surface of the first preliminary insulating layer 642P may be positioned at the same level. After the planarization process step, the remaining first preliminary insulating layer 642P becomes a first insulating layer 642 to be described later.

In some embodiments, as shown in FIG. 17B , a planarization process may be performed until the upper surface of the active region AR and the upper surface of the device isolation layer 112 are exposed. Accordingly, the top surface of the first pad XP1_1 , the top surface of the second pad layer XP2_1 , the top surface of the active region AR, and the top surface of the device isolation layer 112 may be flat. That is, the upper surface of the first pad XP1_1, the upper surface of the second pad layer XP2_1, the upper surface of the active region AR, and the upper surface of the isolation layer 112 may be positioned at the same level.

The first pad layer XP1_1 and the second pad layer XP2_1 may include a metal material, a metal nitride, or a combination thereof. For example, the first pad layer XP1_1 may include Ti, TiN, or a combination thereof, and the second pad layer XP2_1 may include a metal such as W or Mo, a metal nitride, or a combination thereof. . However, it is not limited thereto, and the structures, shapes, and materials of the first pad layer XP1_1 and the second pad layer XP2_1 may be variously changed.

Although not illustrated in FIG. 17C , the impurity-doped polysilicon layer and the first pad layer XP1_1 are sequentially and conformally formed in the pad trench XPT, and then the impurity-doped polysilicon layer and the first pad are sequentially formed. A second pad layer XP2_1 may be formed in the remaining region of the pad trench XPT remaining after the layer XP1_1 is formed. In this case, after forming a metal film on the impurity-doped polysilicon layer, a heat treatment process may be performed to form an ohmic contact portion at an interface between the impurity-doped polysilicon layer and the first pad layer XP1_1.

Hereinafter, subsequent process steps will be described based on the embodiment according to FIG. 17A.

Next, referring to FIGS. 18 and 19 , a second insulating layer 644 and a third insulating layer 646 are sequentially formed on the first insulating layer 642 and the pad XP. The first insulating layer 642 , the second insulating layer 644 , and the third insulating layer 646 may form the insulating layer 640 . However, the structure of the insulating layer 640 is not limited thereto, and may be made of a single layer, a double layer, or four or more insulating layers. As described above, the first insulating layer 642 may be the remaining first preliminary insulating layer 642P after the planarization process of the preliminary insulating layer 640P. In addition, the second insulating layer 644 and the third insulating layer 646 may include the same material as the aforementioned second preliminary insulating layer 644P and the third preliminary insulating layer 646P, respectively.

The second insulating layer 644 may cover the upper surface of the first insulating layer 642 and the upper surface of the pad XP. The third insulating layer 646 covers the second insulating layer 644 and may be formed on the second insulating layer 644 . The first insulating layer 642 , the second insulating layer 644 , and the third insulating layer 646 may constitute the insulating layer 640 . However, the structure of the insulating layer 640 is not limited thereto, and may be made of a single layer, a double layer, or four or more insulating layers.

Next, referring to FIGS. 21 and 22 , a direct contact trench (DCT) may be formed by forming a first material layer 150a on the insulating layer 640 and then patterning the first material layer 150a.

Specifically, the second hard mask pattern is formed by sequentially forming the first material layer 150a and the second hard mask layer on the insulating layer 640 and then patterning the second hard mask layer using a photo and etching process. (920).

Subsequently, the first material layer 150a, the third insulating layer 646, the second insulating layer 644, the first insulating layer 642, and the pad XP are formed using the second hard mask pattern 920. can be sequentially etched. When the first insulating layer 642 and the pad XP are etched, the upper surface of the active region AR and the upper surface of the isolation layer 112 of the substrate 100 may be exposed.

Then, the active region AR, the device isolation layer 112, and the pad XP may be etched to form a direct contact trench DCT. In this case, the active region AR may be located at approximately the center of the direct contact trench DCT.

The active region AR and the device isolation layer 112 may constitute a bottom surface of the direct contact trench DCT. The device isolation layer 112 , the pad XP, the insulating layer 640 , and the first material layer 150a may constitute side surfaces of the direct contact trench DCT.

A side surface of the pad XP may be positioned at substantially the same boundary as a side surface of the direct contact trench DCT. That is, the side surface of the pad XP and the side surface of the direct contact trench DCT may extend along the same boundary in the third direction Z. However, the formation method and shape of the direct contact trench (DCT) are not limited thereto and may be variously changed.

The first material layer 150a may include a conductive material. For example, the first material layer 150a may include polysilicon doped with impurities or a metal such as W, Mo, Au, Cu, Al, Ni, or Co.

The second hard mask material layer may include a material such as spin on coating (SOH), photoresist, or silicon oxide. However, the second hard mask material layer is not limited thereto and may be variously changed.

Next, referring to FIGS. 22 and 23 , a second material layer 150b may be formed in the direct contact trench (DCT). A lower surface of the second material layer 150b may contact the active region AR. Side surfaces of the second material layer 150b may contact the first material layer 150a, the second insulating layer 644, the third insulating layer 646, the pad XP, and the isolation layer 112. . The upper surface of the second material layer 150b and the upper surface of the first material layer 150a may be flat. That is, the upper surface of the second material layer 150b and the upper surface of the first material layer 150a may be located on the same level.

Forming the second material layer 150b in the direct contact trench DCT may include forming the second material layer 150b on the first material layer 150a and in the direct contact trench DCT, and then forming the first material layer 150b in the direct contact trench DCT. A planarization process step such as an etch back process or chemical mechanical polishing (CMP) may be included until 150a is exposed.

Accordingly, the upper surface of the first material layer 150a and the upper surface of the second material layer 150b may be flat. That is, the upper surface of the first material layer 150a and the upper surface of the second material layer 150b may be located on the same level. However, the planarization process step is not limited thereto and may be variously changed.

The second material layer 150b may include a conductive material. For example, the second material layer 150b may include polysilicon doped with impurities or a metal such as W, Mo, Au, Cu, Al, Ni, or Co. The second material layer 150b may be made of the same material as the first material layer 150a. A boundary between the first material layer 150a and the second material layer 150b may not be clear.

Next, referring to FIGS. 24 and 25 , a third material layer (not shown), a fourth material layer (not shown), and a fifth material layer are formed on the first material layer 150a and the second material layer 150b. (not shown) may be sequentially laminated.

The third material layer may include a conductive material. For example, the third material layer may include a metal such as Ti or Ta and/or a metal nitride such as TiN or TaN. The fourth material layer may include a conductive material. For example, the fourth material layer may include a metal such as W, Mo, Au, Cu, Al, Ni, or Co. The fifth material layer may include an insulating material. For example, it may include silicon nitride. However, materials of the third material layer, the fourth material layer, and the fifth material layer are not limited thereto and may be variously changed.

Subsequently, the fifth material layer, the fourth material layer, the third material layer, the second material layer 150b, and the first material layer 150a may be patterned. That is, at least a portion of the fifth material layer, the fourth material layer, the third material layer, the second material layer 150b, and the first material layer 150a may be removed by performing a photo and etching process. Through this patterning process, a direct contact (DC) and a bit line structure (BLS) may be formed.

Specifically, the direct contact DC may be formed by patterning the second material layer 150b. The direct contact DC may be located in the direct contact trench DCT. The direct contact DC may be positioned approximately at the center of the direct contact trench DCT. The direct contact DC may be positioned on the active region AR and may be connected to the active region AR.

The bit line structure BLS may be formed by patterning the first material layer 150a, the third material layer, the fourth material layer, and the fifth material layer.

The bit line structure BLS may include a bit line BL and a bit line capping layer 158 .

The bit line capping layer 158 may be formed by patterning the fifth material layer 150e. The bit line BL may include a first conductive layer 151 , a second conductive layer 153 , and a third conductive layer 155 .

The first material layer may be patterned to form the first conductive layer 151 of the bit line BL, and the third material layer may be patterned to form the second conductive layer 153 of the bit line BL. The third conductive layer 155 of the bit line BL may be formed by patterning the fourth material layer.

A second conductive layer 153 may be positioned on the first conductive layer 151 of the bit line BL, a third conductive layer 155 may be positioned on the second conductive layer 153, and a third conductive layer 155 may be positioned on the second conductive layer 153. A bit line capping layer 158 may be positioned on the conductive layer 155 . In addition, the second conductive layer 153 of the bit line BL may be positioned on the upper surface of the direct contact DC.

As the second material layer is removed, the insulating layer 640 located under the second material layer may be exposed.

Next, referring to FIGS. 26A and 27A , a spacer structure 620 may be formed on the bit line structure BLS by using an insulating material.

In the process of forming the spacer structure 620 , the pad XP may be exposed. That is, in plan view, the pad XP covers a portion of the gate insulating layer 132 and may be positioned between the word line capping layers 134 .

First, the first spacer 621 may be formed to have a conformal shape on the bit line structure BLS. The first spacer 621 may cover side surfaces of the bit line structure BLS and the direct contact DC. The first spacer 621 may cover an upper surface of the third insulating layer 646 . The first spacer 621 may cover the bottom and side surfaces of the direct contact trench DCT. Also, the first spacer 621 may cover a side surface of the pad XP.

Subsequently, the second spacer 623 may be conformally formed on the first spacer 621 using an insulating material. By patterning the second spacer 623 , portions of the second spacer 623 positioned on the bottom and side surfaces of the direct contact trench (DCT) may be left, and the remaining portions may be removed. That is, a portion of the second spacer 623 covering the upper surface of the insulating layer 640 may be removed. The thickness of the second spacer 623 may be thicker than that of the first spacer 621 , but is not limited thereto.

Subsequently, a third spacer 625 may be formed on the second spacer 623 using an insulating material. The third spacer 625 may be formed to fill the direct contact trench DCT. That is, the third spacer 625 may be patterned to leave a part of the third spacer 625 positioned in the direct contact trench (DCT), and the remaining part may be removed. That is, a portion of the third spacer 625 covering the upper surface of the insulating layer 640 may be removed.

Next, a fourth spacer 627 may be formed on the first spacer 621 , the second spacer 623 , and the third spacer 625 by using an insulating material. The fourth spacer 627 may be conformally formed on the first spacer 621 , the second spacer 623 , and the third spacer 625 . The fourth spacer 627 may extend along the third direction Z parallel to the first spacer 621 . The fourth spacer 627 may cover the upper surface of the first spacer 621 , the upper surface of the second spacer 623 , and the upper surface of the third spacer 625 . In addition, the fourth spacer 627 may cover the upper surface of the bit line capping layer 158 and the upper surface of the insulating layer 640 . The thickness of the fourth spacer 627 may be thicker than the thickness of the first spacer 621 and the thickness of the second spacer 623, but is not limited thereto.

The first spacer 621 , the second spacer 623 , the third spacer 625 , and the fourth spacer 627 may constitute the spacer structure 620 .

Each of the first spacer 621 , the second spacer 623 , the third spacer 625 , and the fourth spacer 627 is silicon nitride, silicon nitride oxide, silicon oxide, silicon carbonate, silicon carbonitride, or silicon carbonitride. And it may include at least one of combinations thereof. For example, the first spacer 621 and the third spacer 625 may include silicon nitride, and the second spacer 623 and the fourth spacer 627 may include silicon oxide. However, the material of the spacer structure 620 is not limited thereto and may be variously changed.

Subsequently, the fourth spacer 627 may be patterned. An upper surface of the bit line structure BLS may be exposed by removing the fourth spacer 627 positioned on the bit line structure BLS. By removing the fourth spacer 627 positioned between the bit line structures BLS, an upper surface of the pad XP positioned between the bit line structures BLS may be exposed.

In the process of patterning the fourth spacer 627 positioned between the bit line structures BLS, a portion of the first spacer 621, a portion of the second spacer 623, and a portion of the third spacer 625 are formed. can be removed together. In addition, in the process of patterning the fourth spacer 627 positioned between the bit line structures BLS, a portion of the pad XP and a portion of the insulating layer 640 may be removed together. However, a process of patterning the fourth spacer 627 positioned between the bit line structures BLS is not limited thereto and may be variously changed.

For example, after patterning the fourth spacer 627 positioned between the bit line structures BLS, the second insulating layer 644 and the third insulating layer 646 are etched to expose the pad XP. can At this time, a portion of the pad XP and portions of the first spacer 621 , the second spacer 623 , and the third spacer 625 positioned around the pad XP may be removed together. However, the method of forming the spacer structure 620 and the structure of the spacer structure 620 are not limited thereto and may be variously changed.

For example, as in the embodiments shown in FIGS. 26B and 27B , the spacer structure 620_1 may further include a fifth spacer 629 .

Specifically, according to the embodiment shown in FIGS. 26B and 27B, after patterning the fourth spacer 627 as in the embodiment shown in FIG. 5 The spacer 629 may be formed conformally.

The fifth spacer 629 may be conformally formed on the upper surface of the bit line structure BLS, the upper surface of the third spacer 625 , the upper surface of the pad XP_2 , and the side surface of the insulating layer 640 . there is. The fifth spacer 629 may extend parallel to the fourth spacer 627 along the third direction Z. The fifth spacer 629 may be thinner than the fourth spacer 627 and thicker than the first spacer 621 and the second spacer 623 , but is not limited thereto.

The first spacer 621 , the second spacer 623 , the third spacer 625 , the fourth spacer 627 , and the fifth spacer 629 may constitute the spacer structure 620_1 .

The fifth spacer 629 may include at least one of silicon nitride, silicon nitride, silicon oxide, silicon carbonate, silicon carbonitride, silicon carbonitride, and combinations thereof. For example, the fifth spacer 629 may include silicon nitride. However, the material of the fifth spacer 629 is not limited thereto and may be variously changed.

Subsequently, the fifth spacer 629 may be patterned. An upper surface of the bit line structure BLS may be exposed by removing the fifth spacer 629 positioned on the bit line structure BLS. By removing the fifth spacer 629 positioned between the bit line structures BLS, an upper surface of the pad XP_2 positioned between the bit line structures BLS may be exposed.

In the process of patterning the fifth spacer 629 positioned between the bit line structures BLS, a portion of the first spacer 621, a portion of the second spacer 623, and a portion of the third spacer 625 are formed. can be removed together. Also, in a process step of patterning the fourth spacer 627 positioned between the bit line structures BLS, a portion of the pad XP_2 may be removed together. However, a process of patterning the fifth spacer 629 positioned between the bit line structures BLS is not limited thereto and may be variously changed.

As described above, when the spacer structure 620_1 further includes the fifth spacer 629, the shape of the pad XP_2 may be different from the shape of the pad XP according to the embodiment shown in FIG. 27A. . That is, in the process of patterning the fifth spacer 629 positioned between the bit line structures BLS, the fifth spacer 629 positioned on the pad XP_2 serves as a mask, and thus the fifth spacer 629 and A portion of the pad XP_2 overlapping along the third direction Z may remain without being removed. Accordingly, the pad XP_2 may have the same shape as the pad XP_2 according to the exemplary embodiment of FIGS. 7 and 8 .

As such, in the present embodiment, when the fifth spacer 629 is formed on the fourth spacer 627, the same as an oxide film formed on the upper surface of the pad XP before forming the buried contact BC, which will be described later. It is possible to prevent the fourth spacer 627 from being damaged by a cleaning material in a process of cleaning residues or the like.

Next, referring to FIGS. 28A and 29A , a conductive material layer 170 may be formed on the bit line structure BLS. The conductive material layer 170 may be formed between the bit line structures BLS. A region between the bit line structures BLS may be filled with the conductive material layer 170 .

A lower surface of the conductive material layer 170 may contact the pad XP, the first spacer 621 , the second spacer 623 , and the third spacer 625 . At this time, the contact surface where the lower surface of the conductive material layer 170 directly contacts the upper surface of the pad XP is located at a higher level than the upper surface of the active region AR and the upper surface of the isolation layer 112, and the first It may be positioned at a level between the upper and lower surfaces of the insulating layer 642 .

One side of the conductive material layer 170 may directly contact the third spacer 625 and the fourth spacer 627 , and the other side may directly contact the insulating layer 640 and the fourth spacer 627 . However, it is not limited thereto, and according to the embodiments shown in FIGS. 28B and 29B, the contact surface where the lower surface of the conductive material layer 170 and the upper surface of the pad XP_2 directly contact is the upper part of the active region AR. It may be positioned at a level lower than the top surface of the surface and the device isolation layer 112 and positioned at a level lower than the bottom surface of the first insulating layer 642 . Also, a contact surface where the lower surface of the fifth spacer 629 directly contacts the upper surface of the pad XP_2 may be located at a level between the upper and lower surfaces of the first insulating layer 642 .

The conductive material layer 170 may include a conductive material. For example, the conductive material layer 170 may include polysilicon doped with impurities, but is not limited thereto.

Next, the conductive material layer 170 may be patterned to form a buried contact BC as shown in FIG. 2 . The buried contact BC may be electrically connected to the active region AR through the pad XP.

Subsequently, landing pads LP connected to the buried contact BC may be formed, and an insulating pattern 660 separating the landing pads LP may be formed. Although not shown, a capacitor structure may be further formed on the landing pad LP. The capacitor structure may be electrically connected to the active region AR through the landing pad LP and the buried contact BC.

According to the manufacturing method of the semiconductor device according to an exemplary embodiment, the pad trench XPT for forming the pad XP is patterned through a plurality of hard mark patterns by patterning one hard mask pattern having a lattice shape. Compared to , mis-alignment can be prevented from occurring.

In addition, as the pad trench XPT for forming the pad XP is formed with a hard mask pattern made of a single layer, compared to the case where the pad trench XPT is formed with a hard mask pattern made of a plurality of layers, The difficulty of the etching process may be reduced, and thus, the distribution of the pad trench XPT for forming the pad XP may be improved.

In addition, when the pad XP is formed at a level lower than the top surface of the active region AR, compared to the case where the pad XP is formed at a level higher than the top surface of the active region AR, the bit line structure ( The stacking thickness of the material layer for forming the BLS) may be reduced. Accordingly, it is possible to prevent misalignment from occurring by reducing the difficulty of an etching process for forming the bit line structure BLS, and to improve the distribution of diameters of the bit line structure BLS. can do.

Accordingly, according to the method of manufacturing a semiconductor device according to an exemplary embodiment, a semiconductor device having improved productivity and reliability may be provided.

Hereinafter, another embodiment of a semiconductor device will be described with reference to FIGS. 30 to 47 . In the following embodiments, the same reference numerals refer to components identical to those of the previously described embodiments, and redundant descriptions will be omitted or simplified, and description will focus on differences.

30 to 47 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment.

30 is a plan view showing the cell array area of the substrate 100, and illustration of the peripheral circuit area of the substrate 100 is omitted. Hereinafter, the cell array area of the substrate 100 will be mainly described.

Referring to FIGS. 30 and 31 , as described above with reference to FIGS. 10 and 11 , a device isolation layer 112 and an active region AR defined by the device isolation layer 112 are formed on the substrate 100 . After forming, a word line trench WLT extending along the first direction X and intersecting the active region AR is formed, and then extending along the first direction X within the word line trench WLT. and the gate insulating layer 132 overlapping the active region AR, the word line WL, and the word line capping layer 134 may be sequentially formed.

Next, after the insulating layer 640 described above with reference to FIGS. 12 and 13 is formed on the cell array region and the peripheral circuit region of the substrate 100, the insulating layer 640 positioned on the cell array region may be removed. .

32 and 33, a sacrificial layer 910a, a first hard mask layer 910_1, and a second hard mask material layer are sequentially formed on the active region AR and the isolation layer 112. After forming, the second hard mask pattern 920_1 may be formed by patterning the second hard mask layer using a photo and etching process.

The sacrificial layer 910a may cover the active region AR and the isolation layer 112 . The first hard mask layer 910_1 may cover an upper surface of the sacrificial layer 910a.

The second hard mask patterns 920_1 may extend parallel to each other in the second direction (Y) and may be spaced apart from each other at regular intervals along the first direction (X). A width of each of the second hard mask patterns 920_1 may be greater than the width of the top surface of the active region AR and the width of the top surface of the device isolation layer 112 . However, the width of the second hard mask pattern 920_1 is not limited thereto and may be variously changed.

As the second hard mask patterns 920_1 extend in parallel in the second direction (Y) and are spaced apart from each other at regular intervals along the first direction (X), the second hard mask pattern 920_1 is positioned below the second hard mask pattern 920_1. An upper surface of the first hard mask layer 910_1 may be exposed.

Each of the sacrificial layer 910a, the first hard mask layer 910_1, and the second hard mask material layer may include a different material. The second hard mask material layer may include a material having an etch selectivity with that of the first hard mask layer 910_1 . For example, the sacrificial layer 910a includes polysilicon, the first hard mask layer 910_1 includes silicon oxide, and the second hard mask material layer includes a material such as spin on coating (SOH) or photoresist. can include However, a method of forming the sacrificial layer 910a, the first hard mask layer 910_1, and the second hard mask pattern and materials included therein may be variously changed.

Next, referring to FIGS. 34 and 35 , a first hard mask layer 910_1, a sacrificial layer 910a, a portion of the active region AR, and an isolation layer ( 112) may be sequentially etched to form the pad trench XPT_1. In this case, portions of the active region AR and the device isolation layer 112 that do not overlap with the second hard mask pattern 920_1 along the third direction Z may be etched along the third direction Z.

In plan view, the pad trenches XPT_1 may extend parallel to each other along the second direction Y, and may be formed between the first hard mask layers 910_1 while being spaced apart from each other at equal intervals along the first direction X. In plan view, the pad trench XPT_1 may expose the active region AR, the isolation layer 112 , the gate insulating layer 132 , and the word line capping layer 134 .

In this case, a boundary surface between the active region AR and the device isolation layer 112 may be positioned approximately at the center of the pad trench XPT_1. The active region AR and the device isolation layer 112 may constitute a bottom surface of the pad trench XPT_1. The isolation layer 112, the sacrificial layer 910a, and the first hard mask layer 910_1 constitute one side of the pad trench XPT_1, and the active region AR, the sacrificial layer 910a, and the first hard mask layer 910_1 constitute one side of the pad trench XPT_1. The hard mask layer 910_1 may constitute the other side surface of the pad trench XPT_1. However, the formation method and shape of the pad trench XPT_1 are not limited thereto and may be variously changed.

Next, referring to FIGS. 36 and 37 , a pad XP_2 may be formed in the pad trench XPT_1. A lower surface of the pad XP_2 may directly contact the active region AR and the device isolation layer. One side of the pad XP_2 may directly contact the active region AR and the sacrificial layer 910a, and the other side of the pad XP_2 may directly contact the isolation layer 112 and the sacrificial layer 910a. .

In the step of forming the pad XP_2 in the pad trench XPT_1, after forming a pad material layer on the first hard mask layer 910_1 and in the pad trench XPT_1, an etch-back is performed until the sacrificial layer 910a is exposed. It may include a planarization process step such as an etch back process or chemical mechanical polishing (CMP). Accordingly, the upper surface of the pad XP_2 and the upper surface of the sacrificial layer 910a may be flat. That is, the upper surface of the pad XP_2 and the upper surface of the sacrificial layer 910a may be positioned at the same level. However, the planarization process step is not limited thereto and may be variously changed.

Next, referring to FIGS. 38 and 39, an etch back process or chemical mechanical polishing is performed until the upper surface of the active region AR and the upper surface of the isolation layer 112 are exposed. A planarization process such as CMP) may be performed. Accordingly, the upper surface of the pad XP_2, the upper surface of the active region AR, and the upper surface of the isolation layer 112 may be flat. That is, the top surface of the pad XP_2, the top surface of the active region AR, and the top surface of the device isolation layer 112 may be positioned at the same level. However, the planarization process step is not limited thereto and may be variously changed.

Next, referring to FIGS. 40 and 41 , the insulating layer 640, the first material layer 150a, and the third hard mask layer are formed on the pad XP_2, the active region AR, and the isolation layer 112. After forming the third hard mask layer, a third hard mask pattern 930 may be formed by patterning the third hard mask layer using a photo and etching process.

Next, the first material layer 150a, the third insulating layer 646, the second insulating layer 644, and the first insulating layer 642 are sequentially etched using the third hard mask pattern 930. can When the first insulating layer 642 is etched, the upper surface of the active region AR of the substrate 100, the upper surface of the isolation layer 112, and the upper surface of the pad XP_2 may be exposed.

Subsequently, the active region AR, the device isolation layer 112, and the pad XP_2 may be etched to form a direct contact trench DCT_1. In this case, the active region AR may be located at approximately the center of the direct contact trench DCT_1.

The active region AR and the device isolation layer 112 may constitute a bottom surface of the direct contact trench DCT_1. The isolation layer 112 , the pad XP_2 , the insulating layer 640 , and the first material layer 150a may constitute side surfaces of the direct contact trench DCT_1 .

A side surface of the pad XP_2 may be located at substantially the same boundary as a side surface of the direct contact trench DCT_1. That is, the side surface of the pad XP_2 and the side surface of the direct contact trench DCT_1 may extend in the third direction Z along the same boundary. However, the formation method and shape of the direct contact trench DCT_1 are not limited thereto and may be variously changed.

The third hard mask material layer may include a material such as spin on coating (SOH), photoresist, or silicon oxide. However, the third hard mask material layer is not limited thereto and may be variously changed.

Following. Referring to FIGS. 42 and 43 , a second material layer 150b may be formed in the direct contact trench DCT_1. A lower surface of the second material layer 150b may contact the active region AR. A side surface of the second material layer 150b may contact the first material layer 150a , the insulating layer 640 , the pad XP_2 , and the isolation layer 112 . The upper surface of the second material layer 150b and the upper surface of the first material layer 150a may be flat. That is, the upper surface of the second material layer 150b and the upper surface of the first material layer 150a may be located on the same level.

Next, referring to FIGS. 44 and 45 , a direct contact DC and a bit line structure BLS may be formed. Since a method of forming the direct contact DC and the bit line structure BLS is substantially the same as the above description with reference to FIGS. 24 and 25 , a description thereof will be omitted.

Next, referring to FIGS. 46 and 47 , after forming a spacer structure 620_1 using an insulating material on the bit line structure BLS, a fifth spacer 629 positioned between the bit line structures BLS is formed. can be patterned.

Although not illustrated, a conductive material layer 170 may be formed on the bit line structure BLS. The conductive material layer 170 may be formed between the bit line structures BLS.

A method of forming the spacer structure 620_1 on the bit line structure BLS by using an insulating material and then patterning the fifth spacer 629 positioned between the bit line structures BLS and the bit line structure BLS Since the method of forming the conductive material layer 170 thereon is substantially the same as that described above with reference to FIGS. 26A to 29B , differences will be mainly described.

Specifically, in the process of forming the spacer structure 620_1, the pad XP_2 may be exposed. Unlike the embodiment shown in FIG. 26A , in the present embodiment, the pad XP_2 may cover portions of the gate insulating layer 132 and the word line capping layer 134 . Although not shown, as described above with reference to FIGS. 28A to 29B , a process of forming an insulating pattern between the conductive material layers 170 after forming the conductive material layer 170 between the bit line structures BLS. In this step, the pad XP_2 overlapping the word line capping layer 134 may be removed.

Next, the conductive material layer 170 may be patterned to form a buried contact BC as shown in FIG. 7 . The buried contact BC may be electrically connected to the active region AR through the pad XP_2.

Subsequently, landing pads LP connected to the buried contact BC may be formed, and an insulating pattern 660 separating the landing pads LP may be formed. Although not shown, a capacitor structure may be further formed on the landing pad LP. The capacitor structure may be electrically connected to the active region AR through the landing pad LP and the buried contact BC.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the following claims are also included in the scope of the present invention. that fall within the scope of the right.

100: substrate
112: element isolation layer
158: bit line capping layer
620: spacer structure
640: insulating layer
910: first hard mask pattern
920: second hard mask pattern
930: third hard mask pattern
XP: Pad
XPT: Pad Trench
AR: active area
BL: bit line
BLS: bit line structure
WL: word line
WLS: word line structure
BC: buried contact
DC: direct contact
DCT: direct contact trench

Claims (10)

A substrate including an active region positioned between device isolation layers;
A word line crossing and overlapping the active region;
a bit line crossing and overlapping the active region in a direction different from the word line;
a buried contact connected to the active region;
a direct contact connecting between the active region and the bit line; and
a pad connecting the active region and the buried contact and overlapping a portion of the active region in a vertical direction;
a lower surface of the pad is positioned at a level lower than an upper surface of the active region and an upper surface of the isolation layer;
The semiconductor device of claim 1 , wherein the pad overlaps at least a portion of the active region and the isolation layer in a horizontal direction. In paragraph 1,
Further comprising an insulating layer positioned between the bit line and the device isolation layer,
An upper surface of the pad is positioned at a level lower than an upper surface of the insulating layer. In paragraph 2,
An upper surface of the pad is positioned at the same level as a lower surface of the insulating layer. In paragraph 2,
an upper surface of the pad is positioned at a level higher than upper surfaces of the active region and upper surfaces of the device isolation layer;
An upper surface of the pad is positioned between an upper surface of the insulating layer and a lower surface of the insulating layer. In paragraph 2,
Further comprising a bit line spacer positioned on a side of the bit line,
An upper surface of the pad includes a first portion overlapping the buried contact, and
a second portion located at a level higher than the first portion and overlapping the bit line spacer;
The first part is located at a level lower than the upper surface of the active region,
The second part is located at the same level as the lower surface of the insulating layer, or
The second portion is positioned between an upper surface of the insulating layer and a lower surface of the insulating layer. In paragraph 1,
The pad includes a first pad layer and a second pad layer whose side surface and lower surface are surrounded by the first pad layer,
The active region includes an ohmic contact portion surrounding a side surface and a lower surface of the first pad layer,
The pad and the buried contact include a metal material. a substrate including active regions defined by the device isolation layer;
word lines crossing and overlapping the active regions;
bit lines crossing and overlapping the active regions in directions different from those of the word lines;
Buried contacts connected to the active regions;
pads connecting between the active regions and the buried contacts; and
Insulating layers positioned between the device isolation layer and the bit lines,
The device isolation layer is positioned between the pads,
Each of the active regions surrounds a lower surface and a side surface of each of the pads and is positioned between the isolation layer and the pads. In paragraph 7,
An upper surface of each of the pads is located at a level higher than an upper surface of the active region and an upper surface of the isolation layer;
A semiconductor device positioned at a level between an upper surface of the insulating layer and a lower surface of the insulating layer. In paragraph 7,
The upper surface of each of the pads is
A semiconductor device comprising: a first portion located at a level lower than a lower surface of the insulating layer and a second portion located between an upper surface of the insulating layer and a lower surface of the insulating layer. In paragraph 7,
The upper surface of each of the pads is
A semiconductor device comprising: a first portion located at a level lower than the lower surface of the insulating layer and a second portion located at the same level as the lower surface of the insulating layer.

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