JP5424724B2 - Field effect transistor manufacturing method, field effect transistor, display device, and electromagnetic wave detector - Google Patents

Description

  The present invention relates to a method for manufacturing a field effect transistor, a field effect transistor, a display device, and an electromagnetic wave detector.

  2. Description of the Related Art In recent years, flat and thin image display devices (Flat Panel Displays: FPD) have been put into practical use due to advances in liquid crystal and electroluminescence (EL) technologies. In particular, an organic electroluminescent device using a thin film material that emits light when excited by passing an electric current (hereinafter sometimes referred to as “organic EL device”) can emit light with high luminance at a low voltage. Device thinning, lightening, miniaturization, and power saving are expected in a wide range of fields including mobile phone displays, personal digital assistants (PDAs), computer displays, automobile information displays, TV monitors, or general lighting. ing. These FPDs are driven by an active matrix circuit of a field effect transistor (hereinafter sometimes referred to as TFT) using an amorphous silicon thin film or a polycrystalline silicon thin film provided on a glass substrate as an oxide semiconductor layer. Has been.

  On the other hand, in order to further reduce the thickness, weight, and breakage resistance of FPDs, an attempt has been made to use a lightweight and flexible resin substrate instead of a glass substrate. However, the manufacture of the transistor using the above-described silicon thin film requires a relatively high temperature thermal process and is generally difficult to form directly on a resin substrate having low heat resistance. Therefore, development of TFTs using oxide semiconductors that can be formed at low temperatures has been actively conducted. An oxide semiconductor can be formed at room temperature and can be formed on a film, and thus attracts attention as a material for an oxide semiconductor layer in a TFT. In addition, in such a TFT, the oxide semiconductor layer provided in the TFT, the conductive layer including the source electrode, the drain electrode, and the like are protected and electrically insulated and separated in order to protect the oxide semiconductor layer. In general, an insulating layer is provided so as to cover a layer and a region corresponding to the conductive layer. As a layer corresponding to an insulating layer having such a function, Patent Document 1 discloses using silicon oxide (Patent Document 1).

  Here, the TFT is suitably applied to an electromagnetic wave detector that detects an electromagnetic wave such as an X-ray, a display device using a liquid crystal element or an organic EL (electroluminescence) element. When applying a TFT to various devices such as these electromagnetic wave detectors and display elements, it is necessary to electrically connect a part of the conductive layer in the TFT to an element provided in these various devices. For this reason, when the TFT is applied to these various devices, a part of the conductive layer is exposed by processing the insulating layer provided on the conductive layer in the TFT to form a contact hole. Thus, the conductive layer and the various devices are electrically connected through the exposed exposed region.

However, since silicon oxide (SiO ₂ ) used in Patent Document 1 as a constituent material of the insulating layer has acid resistance and alkali resistance, it is necessary to select processing by dry etching. There is a problem of inviting a rise.

  Patent Document 1 discloses a form using a material other than silicon oxide. However, since the insulating layer is processed by an argon milling method, the surface of the conductive layer is damaged during the processing of the insulating layer. There is a problem of receiving. Note that a method using a strongly acidic solution for processing the insulating layer may be considered, but in this method, erosion of the conductive layer may be a problem.

JP 2007-73705 A

  It is an object of the present invention to provide a method for manufacturing a field effect transistor in which erosion and breakage of a conductive layer are suppressed when forming a contact hole in an insulating layer, a field effect transistor, a display device, and an electromagnetic wave detector. And

The above object is achieved by the present invention described below.
That is,
<1> Substrate, gate electrode, gate insulating film, source electrode, drain electrode, pixel electrode, oxide semiconductor layer mainly containing an oxide semiconductor, and inorganic insulation mainly containing an inorganic material A conductive layer forming step of forming a conductive layer including at least one of the source electrode, the drain electrode, and the pixel electrode, and the conductive layer, and An inorganic insulating layer forming step for forming the inorganic insulating layer so as to cover the oxide semiconductor layer; a resist forming step for forming a photoresist film on the inorganic insulating layer formed by the inorganic insulating layer forming step; An exposure process for exposing the photoresist film formed by the resist formation process in a pattern shape, and developing the photoresist film exposed by the exposure process A resist pattern is formed by developing using a solution, and a part of the conductive layer is exposed by removing a region exposed from the resist pattern in the inorganic insulating layer using the developer as an etching solution. And a developing step for producing a field effect transistor.

<2> An electrode layer forming step of forming an electrode layer so as to be electrically connected to the conductive layer partially exposed by the developing step through the exposed region, the electrode layer The method for producing a field-effect transistor as described in <1> above, wherein the electrode layer formed in the forming step contains a metal oxide as a main component.

< 3 > The method for producing a field effect transistor according to <1> or < 2>, wherein the inorganic material is an oxide containing Ga.
< 4 > The method for producing a field effect transistor according to any one of <1> to < 3 >, wherein the inorganic material is amorphous.
< 5 > The method for producing a field effect transistor according to any one of <1> to < 4 >, wherein the etching solution is an alkaline solution.

< 6 > A field effect transistor manufactured by the method for manufacturing a field effect transistor according to any one of <1> to < 5 > above.
< 7 > A display device comprising the field effect transistor manufactured by the method for manufacturing a field effect transistor according to any one of <1> to < 5 >.
< 8 > An electromagnetic wave detector comprising a field effect transistor manufactured by the method for manufacturing a field effect transistor according to any one of <1> to < 5 > above.

According to the method for manufacturing a field effect transistor of the present invention, the conductive layer and the oxide semiconductor layer are formed as insulating layers on the conductive layer including the source electrode, the drain electrode, and the pixel electrode formed by the conductive layer formation step. An inorganic insulating layer containing an inorganic material as a main component is formed so as to cover. This inorganic insulating layer has a function of protecting the oxide semiconductor layer and the conductive layer. And after forming a photoresist film on this inorganic insulating layer and performing exposure in a pattern shape, a resist pattern is formed by developing using a developing solution in a development process. In the developing step, for example, the developer is also used as an etching solution to remove a region exposed from the resist pattern in the inorganic insulating layer, thereby exposing a part of the conductive layer. For this reason, in the development process, the resist pattern is formed using the same liquid as the developer and the etchant, and a contact hole is formed in the inorganic insulating layer.
Thus, according to the method for manufacturing a field effect transistor of the present invention, the contact hole is formed by processing the inorganic insulating layer protecting the conductive layer and the oxide semiconductor layer by wet etching using an etching solution. Therefore, erosion and breakage of the conductive layer during contact hole formation are suppressed.

  According to the present invention, there are provided a method for manufacturing a field effect transistor in which erosion and damage of a conductive layer are suppressed when forming a contact hole in an insulating layer, a field effect transistor, a display device, and an electromagnetic wave detector. .

FIG. 3 is a cross-sectional view schematically showing one configuration of the field-effect transistor of the present embodiment, and is a cross-sectional view along A-A ′ in FIG. 2. It is the top view which showed typically one structure of the field effect transistor of this Embodiment. (A)-(D) It is sectional drawing which showed typically the manufacturing process of the field effect transistor of this Embodiment, (A) is AA 'sectional drawing of FIG. 4, (C) is It is AA 'sectional drawing of FIG. 5, (D) is AA' sectional drawing of FIG. It is the top view which showed typically the manufacturing process of the field effect transistor of this Embodiment. It is the top view which showed typically the manufacturing process of the field effect transistor of this Embodiment. It is the top view which showed typically the manufacturing process of the field effect transistor of this Embodiment. It is the top view which showed typically the manufacturing process of the field effect transistor of this Embodiment. FIGS. 8A to 8C are cross-sectional views schematically showing a manufacturing process of the field effect transistor according to the present embodiment, and FIG. 7A is a cross-sectional view taken along line A-A ′ of FIG. 7. (A)-(B) It is sectional drawing which showed typically the manufacturing process of the field effect transistor of this Embodiment. It is sectional drawing which showed typically the structure of the field effect transistor manufactured by the manufacturing method of the field effect transistor of this Embodiment, and is A-A 'sectional drawing of FIG. It is the top view which showed typically the structure of the field effect transistor manufactured by the manufacturing method of the field effect transistor of this Embodiment. (A)-(B) It is sectional drawing which showed typically the manufacturing process of the field effect transistor of this Embodiment, and is sectional drawing which showed the process different from FIG. It is sectional drawing which showed typically one structure of the display apparatus to which the field effect transistor of this Embodiment is applied. It is sectional drawing which showed typically one structure of the electromagnetic wave detector to which the field effect transistor of this Embodiment is applied.

  An embodiment of a field effect transistor manufacturing method of the present invention and a field effect transistor manufactured by the field effect transistor manufacturing method of the present invention will be described with reference to the drawings.

  As shown in FIGS. 1 and 2, the field effect transistor 10 of this embodiment includes a gate electrode 14 </ b> A, a lower electrode 14 </ b> B, a gate insulating film 16, a conductive layer 20, an oxide semiconductor layer 18 on a substrate 12. The inorganic insulating layer 22 is laminated. The oxide semiconductor layer 18 functions as a channel layer through which electrons or holes move. Part of the conductive layer 20 functions as the source electrode 20A, the drain electrode 20B, and the pixel electrode 20C.

  The field effect transistor 10 of the present embodiment is provided with a transistor element 15 and a capacitor 26. The transistor element 15 includes a gate electrode 14A, a gate insulating film 16, a source electrode 20A, a drain electrode 20B, and an oxide semiconductor layer 18. The capacitor 26 includes a lower electrode 14B, a region facing the lower electrode 14B of the pixel electrode 20C, and the gate insulating film 16. Therefore, the gate insulating film 16 has a function of insulating and isolating the gate electrode 14A, and also has a function as a storage capacitor in the capacitor 26.

For example, when the capacitor 26 is applied to various devices such as a display device and an electromagnetic wave detection device by arranging a plurality of field effect transistors 10 one-dimensionally or two-dimensionally, the field-effect transistors 10 By arranging each pixel region corresponding to a drive unit in the device, the capacitor 26 functions as a capacitor 26 corresponding to each pixel region (drive unit). Specifically, a Tr-1C circuit structure having one field effect transistor 10 and one capacitor in one pixel region, or two field effect transistors 10 and one capacitor in one pixel region. When applied to the various devices such as the 2Tr-1C circuit structure provided, it functions as a capacitor 26 corresponding to each pixel region. A part of the pixel electrode 20 </ b> C functions as an upper electrode corresponding to the lower electrode 14 </ b> B constituting the capacitor 26.
That is, the pixel electrode 20C is a region including a region corresponding to the lower electrode 14B of the capacitor 26 in the conductive layer 20. When the field-effect transistor 10 is applied to the various devices, the pixel electrode 20C It also functions as an electrode that contributes to the definition of the size of the pixel region.

  In this embodiment, the field effect transistor 10 is described as having a configuration including the capacitor 26. However, depending on the configuration and type of various devices to which the field effect transistor 10 is applied, the capacitor 26 may be The structure which does not have may be sufficient. In this case, the lower electrode 14B may be omitted. In this case, the pixel electrode 20C functions as a part of the source electrode 20A or the drain electrode 20B (part of the drain electrode 20B in FIG. 1).

  The inorganic insulating layer 22 is provided so as to cover the conductive layer 20 and the oxide semiconductor layer 18. Thereby, the inorganic insulating layer 22 protects the oxide semiconductor layer 18 and the conductive layer 20 and also achieves electrical insulation.

In the present embodiment, “conductive”, “conductive”, and “electrode” indicate that the volume resistivity is less than 10 ⁻² Ω · cm, and “insulating” and “insulating” Indicates that the volume resistivity is 10 ¹⁰ Ω · cm or more.

  A contact hole 27 is provided in the inorganic insulating layer 22. The contact hole 27 is provided to expose a part of the conductive layer 20 continuously provided on the lower layer side (substrate 12 side) of the inorganic insulating layer 22. When the field effect transistor 10 is applied to various devices such as a display device and an electromagnetic wave detector which will be described later, the conductive layer 20 and various elements in the various devices are electrically connected through the exposed region of the conductive layer 20. Must be connected. For this reason, when the field effect transistor 10 is applied to the various devices described above, the electrode layer 24 is provided on the inorganic insulating layer 22 provided with the contact hole 27 so that the exposed region 21 where the conductive layer 20 is exposed is provided. Thus, the electrode layer 24 and the conductive layer 20 are electrically connected.

  In the present embodiment, the contact hole 27 is provided in a region facing the lower electrode 14B. Therefore, in the present embodiment, the contact hole 27 is provided in the inorganic insulating layer 22, so that the lower electrode 14 </ b> B in the entire region on the upper surface side (surface opposite to the substrate 12) of the conductive layer 20. The region opposite to is exposed from the inorganic insulating layer 22.

  Note that in this embodiment, as described above, the case where the contact hole 27 is provided in a region facing the lower electrode 14B will be described. However, the contact hole 27 includes a portion of the conductive layer 20 that is inorganic. What is necessary is just to be provided so that it may be exposed from the insulating layer 22, and it is not restricted to such a position, What is necessary is just to adjust suitably according to the structure and kind of various apparatuses to which the field effect transistor 10 is applied.

  In the field effect transistor 10 of this embodiment, the oxide semiconductor layer 18 is a bottom contact type in contact with the source electrode 20A and the drain electrode 20B on the lower surface side (substrate 12 side) of the oxide semiconductor layer 18. However, the oxide semiconductor layer 18 may be a top contact type in contact with the source electrode 20A and the drain electrode 20B on the upper surface side (the side opposite to the substrate 12) of the oxide semiconductor layer 18.

  The field-effect transistor 10 configured as described above controls the current flowing through the oxide semiconductor layer 18 by applying a voltage to the gate electrode 14A, and the current between the source electrode 20A and the drain electrode 20B. Is an active element having a function of switching.

  Examples of the material constituting the substrate 12 include glass, inorganic materials such as YSZ (zirconia stabilized yttrium), polyesters such as polyethylene terephthalate, polybutylene phthalate, and polyethylene naphthalate, polystyrene, polycarbonate, polyethersulfone, polyarylate, Examples include organic materials such as polyimide, polycycloolefin, norbornene resin, and poly (chlorotrifluoroethylene). When using the above organic material as the material constituting the substrate 12, select a material excellent in heat resistance, dimensional stability, solvent resistance, electrical insulation, workability, low air permeability, low moisture absorption, etc. It is preferable to do.

  The substrate 12 preferably has flexibility. From the viewpoint of having flexibility, it is preferable to use an organic plastic film in which the organic material is a film. In addition, when the insulating property of the substrate 12 is insufficient, an insulating layer is provided, a gas barrier layer for preventing moisture and oxygen from permeating the substrate 12, the flatness of the film-like plastic substrate, the electrodes and the oxidation. It is good also as a structure which laminated | stacked the undercoat layer etc. for improving adhesiveness with a physical-semiconductor layer.

  The thickness of the substrate 12 is preferably 50 μm or more and 500 μm or less. If the thickness of the substrate 12 is less than 50 μm, it may be difficult for the substrate 12 itself to maintain sufficient flatness. If the thickness of the substrate 12 is larger than 500 μm, it becomes difficult to bend the substrate 12 itself freely, that is, the flexibility of the substrate 12 itself becomes poor.

  Examples of the material constituting the gate electrode 14A and the lower electrode 14B include metals such as Al, Mo, Cr, Ta, Ti, Au, and Ag, alloys such as Al—Nd and APC, tin oxide, zinc oxide, and oxide. Preferable examples include metal oxide conductive films such as indium, indium tin oxide (ITO), and zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or mixtures and alloys thereof. The thickness of the gate electrode 14A is preferably 10 nm or more and 1000 nm or less.

As the gate insulating film 16, an insulator such as SiO ₂ , SiN _x , SiON, Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , HfO ₂ , or a mixed crystal compound containing at least two of these compounds. Is used. A polymer insulator such as polyimide is also used as the gate insulating film 16.

The film thickness of the gate insulating film 16 is preferably 10 nm or more and 10 μm or less. The gate insulating film 16 needs to be thickened to some extent in order to reduce leakage current and increase voltage resistance. However, increasing the thickness of the gate insulating film 16 results in an increase in driving voltage of the field effect transistor 10. Therefore, the thickness of the gate insulating film 16 is preferably 50 nm or more and 1000 nm or less when composed of an inorganic insulator, and 0.5 μm or more and 5 μm or less when composed of a polymer insulator. In particular, it is particularly preferable to use a high dielectric constant insulator such as HfO ₂ for the gate insulating film 16 because the field effect transistor 10 can be driven at a low voltage even if the film thickness is increased.

  As a material constituting the conductive layer 20 (source electrode 20A, drain electrode 20B, pixel electrode 20C), a metal such as Al, Mo, Cr, Ta, Ti, Au, or Ag, an alloy such as Al-Nd, APC, Metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or mixtures and alloys thereof Are preferable. Among these, IZO, ITO, and the like are preferably used because of good ohmic contact with the oxide semiconductor. The thickness of the conductive layer 20 to be formed is preferably 10 nm or more and 1000 nm or less.

The oxide semiconductor layer 18 contains an oxide semiconductor as a main component. Note that the main component indicates that the content is the largest among the constituent components included in the oxide semiconductor layer 18, and preferably 50% by mass or more. Since this oxide semiconductor can be formed at a low temperature, it is preferably formed over the flexible substrate 12.
The oxide semiconductor used for the oxide semiconductor layer 18 is preferably an amorphous oxide containing at least one element selected from the group consisting of In, Zn, Ga, Sn, or Cd, more preferably It is an amorphous oxide containing at least one selected from the group consisting of In, Zn, and Ga.

Specific examples of the amorphous oxide used for the oxide semiconductor layer 18 include InGaO ₃ (ZnO) _m (m is a natural number less than 6), ZnO · Rh ₂ O ₃ , CuGaO ₂ , and SrCu as a composition structure. ₂ O ₂ and oxide semiconductors disclosed in JP-A-2006-165529 can be given.
Among the above, as an amorphous oxide semiconductor used for the oxide semiconductor layer 18, an amorphous oxide semiconductor whose composition in a crystalline state is represented by InGaO ₃ (ZnO) _m (m is a natural number less than 6) is used. Are preferably used. Further, among the amorphous oxide semiconductors whose composition in the crystalline state is represented by InGaO ₃ (ZnO) _m (m is a natural number of less than 6), InGaZnO ₄ is more preferable. An amorphous oxide semiconductor having this composition tends to increase in electron mobility as the electrical conductivity increases.

The electric conductivity of the oxide semiconductor layer 18 is preferably 10 ⁻⁴ Scm ⁻¹ or more and less than 10 ² Scm ⁻¹ , more preferably 10 ⁻¹ Scm ⁻¹ or more and less than 10 ² Scm ⁻¹ . Examples of the method for adjusting the electrical conductivity of the oxide semiconductor layer 18 include a known adjustment method using oxygen defects, an adjustment method using a composition ratio, an adjustment method using impurities, and an adjustment method using an oxide semiconductor material.

  The inorganic insulating layer 22 is a layer mainly composed of an inorganic material and has an insulating property. Since the inorganic insulating layer 22 is a layer containing an inorganic material as a main component, for example, film formation using a sputtering method is possible, and the thickness is uniform (the variation in layer thickness is within ± 10% of the average layer thickness) and thin ( The inorganic insulating layer 22 can be formed preferably (500 nm or less).

  The inorganic insulating layer 22 can be processed by wet etching. That is, the inorganic insulating layer 22 is soluble in the etching solution used when the contact hole 27 is formed. Note that “soluble in this etching solution” preferably means that the dissolution rate of the constituent material of the inorganic insulating layer 22 in the etching solution having a liquid temperature of 25 ° C. is 1 nm / s or more. ing.

  In order to make the inorganic insulating layer 22 soluble in the etching solution, the constituent material of the inorganic insulating layer 22 containing an inorganic material as a main component and the kind of the etching solution (detailed later) may be selected as appropriate.

As a constituent material of the inorganic insulating layer 22, any material satisfying the above characteristics may be used, but Ga ₂ O ₃ which is an oxide containing Ga is preferably used.

By forming the inorganic insulating layer 22 with an oxide containing Ga, as compared with the case where SiO ₂ is used as the inorganic insulating layer 22 as in the prior art, easy processing by wet etching using a less toxic chemical solution. Is realized. Further, since processing by wet etching is possible, erosion and damage of the conductive layer 20 during processing of the inorganic insulating layer 22 (when the contact hole 27 is formed) are suppressed.
In addition, since the inorganic insulating layer 22 is composed of an oxide containing Ga, and the inorganic insulating layer 22 exhibits alkali solubility, an alkaline etching solution is used as an etching solution used for processing the inorganic insulating layer 23. The inorganic insulating layer 23 can be processed without eroding the conductive layer 20 even when a material with low acid resistance (for example, IZO that is suitably used as the conductive layer 20) is used as the conductive layer 20. Can do.

  The constituent material of the inorganic insulating layer 22 is preferably amorphous. Since the constituent material of the inorganic insulating layer 22 is amorphous, the inorganic insulating layer 22 can be satisfactorily soluble in an etching solution used during processing by wet etching described later.

  In the manufacturing process of the field effect transistor 10 in the present embodiment, a developer used for developing the photoresist film 30 (see FIG. 8B, which will be described in detail later) provided on the inorganic insulating layer 23 is used. Used as an etchant for the inorganic insulating layer 22. Therefore, in the present embodiment, a liquid that can be used as a developing solution used for developing the photoresist film 30 is selected as the etching solution used for processing the inorganic insulating layer 22 (details will be described later).

  The layer thickness of the inorganic insulating layer 22 does not hinder the function of protecting the oxide semiconductor layer 18 and the conductive layer 20 (a region other than a region exposed in a process described later), and the electrode layer 24 is formed on the inorganic insulating layer 22. The thickness of the electrode layer 24 and the conductive layer 20 may be any thickness that does not hinder the insulation separation function. For example, the layer thickness of the inorganic insulating layer 22 is desirably 20 nm or more and 500 nm or less, and more desirably 30 nm or more and 100 nm or less.

The field effect transistor 10 composed of the above constituent materials includes a conductive layer formation step, an oxide semiconductor layer formation step, an inorganic insulating layer formation step, a resist formation step, an exposure step, and a development step (resist pattern formation step, processing step). ).
Hereinafter, a method for manufacturing the field-effect transistor 10 composed of the above constituent materials will be described in detail.

(1) Conductive layer forming step In the conductive layer forming step, a stacked body 10A in which a gate electrode 14A and a lower electrode 14B, a gate insulating film 16, and a conductive layer 20 are stacked in this order on a substrate 12 (FIG. 3C )).

  First, as shown in FIGS. 3A and 4, a layer made of a constituent material of the gate electrode 14 </ b> A and the lower electrode 14 </ b> B is formed on the substrate 12 and then patterned to form the gate electrode 14 </ b> A and the lower electrode 14 </ b> B. Including electrode layer 14 is formed. Next, as shown in FIG. 3B, a gate insulating film 16 is formed on the electrode layer 14 including the formed gate electrode 14A and lower electrode 14B. As a method for forming the layer of the gate electrode 14A and the lower electrode 14B on the substrate 12 and the method for forming the gate insulating film 16, a known method is used and is not particularly limited. For example, a printing method, a coating method, or the like is used. We consider the suitability with the materials that make up each layer among the wet methods, vacuum deposition methods, sputtering methods, physical methods such as ion plating methods, chemical methods such as CVD and plasma CVD methods, etc. What is necessary is just to select suitably.

  For example, when ITO is selected as the material constituting the gate electrode 14A and the lower electrode 14B, the method of forming a layer using these constituent materials includes direct current or high frequency sputtering, vacuum deposition, ion plating. Laws are selected. In addition, when an organic conductive compound is selected as the material constituting the gate electrode 14A and the lower electrode 14B, a wet film forming method is selected as the film forming method. Moreover, as a patterning method of the layers by the constituent materials of the gate electrode 14A and the lower electrode 14B, a known method may be used, and for example, photolithography and etching are used.

  Next, a conductive layer (not shown) is formed on the gate insulating film 16 and patterned to form the conductive layer 20 having the source electrode 20A, the drain electrode 20B, and the pixel electrode 20C (FIG. 3 ( C) and FIG. 5).

  A method for forming this conductive layer (the conductive layer 20 before patterning, not shown) is not particularly limited, and is a wet method such as a printing method or a coating method, a vacuum deposition method, a sputtering method, What is necessary is just to select suitably according to the material selected as the electroconductive layer 20 from physical methods, such as ion plating methods, chemical methods, such as CVD and plasma CVD method. For example, when ITO is selected as the conductive layer 20, a direct current or high frequency sputtering method, a vacuum deposition method, or an ion plating method is preferably used. Further, when an organic conductive compound is used as a material for forming the conductive layer 20, the conductive layer 20 is suitably formed by a wet film forming method.

  A known method is used as a patterning method for the formed conductive layer (the conductive layer 20 before patterning). For example, a photolithography method is used on the conductive layer formed on the gate insulating film 16. A resist pattern is formed, and a region of the conductive layer that is not protected by the resist pattern is removed by wet etching. Thus, part of the conductive layer is formed as the source electrode 20A and the drain electrode 20B, and the conductive layer 20 is formed. In addition, a region corresponding to the lower electrode 14B in the conductive layer 20 functions as the pixel electrode 20C.

(2) Oxide Semiconductor Layer Formation Step In the oxide semiconductor layer formation step, as shown in FIGS. 3D and 6, the source electrode 20A and the drain electrode 20B formed in the conductive layer formation step, and the source The oxide semiconductor layer 18 is formed so as to cover between the electrode 20A and the drain electrode 20B.

  In this oxide semiconductor layer forming step, a layer (not shown) of the constituent material of the oxide semiconductor layer 18 is formed on the gate insulating film 16 and the conductive layer 20 and then patterned to form the oxide semiconductor layer 18. To do.

  As a method for forming a layer using the constituent material of the oxide semiconductor layer 18, a vapor-phase film forming method is used with the polycrystalline sintered body of the amorphous oxide semiconductor constituting the oxide semiconductor layer 18 described above as a target. It is preferable to use it. Among vapor deposition methods, sputtering and pulsed laser deposition (PLD) are suitable. Furthermore, the sputtering method is preferable from the viewpoint of mass productivity. The oxide semiconductor layer 18 is formed by controlling the degree of vacuum and the oxygen flow rate by, for example, RF magnetron sputtering deposition. When this method is used, the electrical conductivity of the formed oxide semiconductor layer 18 can be reduced as the oxygen flow rate increases. Note that the formed oxide semiconductor layer 18 is confirmed to be an amorphous film by a known X-ray diffraction method. The film thickness of the oxide semiconductor layer 18 is obtained by stylus type surface shape measurement. The composition ratio is determined by an RBS (Rutherford backscattering) analysis method.

Next, the oxide semiconductor layer 18 is formed as shown in FIGS. 3D and 6 by patterning a layer made of the constituent material of the oxide semiconductor layer 18.
As this patterning method, a known method is used. For example, a resist pattern is formed on the layer made of the constituent material of the oxide semiconductor layer 18 by a photolithography method, and a region not protected by the resist pattern is formed by wet etching. The oxide semiconductor layer 18 may be formed by removing the oxide semiconductor layer 18.

(3) Inorganic insulating layer forming step In the inorganic insulating layer forming step, as shown in FIGS. 7 and 8A, the inorganic insulating layer is covered so as to cover the conductive layer 20 and the oxide semiconductor layer 18 formed in the above step. Layer 23 is formed.
The inorganic insulating layer 23 functions as the inorganic insulating layer 22 provided with the contact hole 27 when it is configured as a field effect transistor 10 by being processed (etched) in a development process or a processing process described later.
As a method for forming the inorganic insulating layer 23, it is preferable to use a vapor phase film forming method with the polycrystalline sintered body of the material constituting the inorganic insulating layer 22 described above as a target. Among vapor deposition methods, sputtering and pulsed laser deposition (PLD) are suitable. Among these, the sputtering method is preferable because of mass productivity and formation of a uniform and thin film. If the inorganic insulating layer 22 is made of an amorphous inorganic material, whether or not the formed inorganic insulating layer 22 is amorphous can be confirmed by a known X-ray diffraction method. Good. Moreover, the film thickness of the inorganic insulating layer 22 is calculated | required by stylus type surface shape measurement.

(4) Resist Forming Step In the resist forming step, as shown in FIG. 8B, a photoresist film 30 is formed on the inorganic insulating layer 23 formed in the inorganic insulating layer forming step.
The photoresist film 30 is formed by applying a photoresist on the inorganic insulating layer 23. The photoresist only needs to have a property of being dissolved in a developer used for developing the photoresist film 30 formed by the photoresist, and is a positive photoresist in which the exposed region is removed by development. Alternatively, it may be a negative photoresist in which the unexposed areas are removed by development.
In this embodiment mode, a mode using a positive photoresist is described as an example.

  As the photoresist, a photosensitive resin composition that is sensitive to radiation such as ultraviolet rays (g rays, i rays), deep ultraviolet rays including excimer lasers, electron beams, ion beams, and X rays is used.

  Specifically, the positive photoresist is preferably a composition containing a quinone diazide compound and an alkali-soluble resin when an alkaline developer is used as the developer. A positive-type photosensitive resin composition containing a quinonediazide compound and an alkali-soluble resin indicates that a quinonediazide group is decomposed by light irradiation with a wavelength of 500 nm or less to generate a carboxyl group, and as a result, the alkali-insoluble state becomes alkali-soluble. Used as a positive photoresist. Since this photosensitive resin composition is remarkably excellent in resolving power, it is used for production of integrated circuits such as IC and LSI. Examples of the quinonediazide compound include naphthoquinonediazide compounds.

(5) Exposure Step In the exposure step, pattern exposure is performed on the photoresist film 30 formed on the inorganic insulating layer 23 by the resist formation step via a photomask, thereby performing pattern exposure. Additional heating is performed to cure the portions that were not irradiated with light.
That is, by this exposure step, as shown in FIG. 8C, the region 30B of the photoresist film 30 that has not been irradiated with light is cured, and the region 30A that has been irradiated with light is uncured (into the developer). A soluble state).

  As light used for pattern exposure to the photoresist film 30 in this exposure step, for example, light sensitive to the photoresist film 30 such as the above-described ultraviolet ray, far ultraviolet ray, electron beam, ion beam, and radiation is used.

(6) Development Step In the development step, the photoresist film 30 that has undergone the exposure step is developed using a developer to form a resist pattern 30B ′ corresponding to the region 30B of the photoresist film 30, and The contact hole 27 is formed by processing the inorganic insulating layer 23 by wet etching using a developing solution as an etching solution.

  Specifically, by developing the photoresist film 30 with a developer, as shown in FIG. 9A, the region in the photoresist film 30 that has been subjected to the above-described exposure step and made soluble in the developer. The region 30A irradiated with light in the case of a positive type photoresist is removed, and the region 30B not irradiated with light in the exposure process is left as a resist pattern 30B ′. As a result, the region 22A of the inorganic insulating layer 23 other than the region (inorganic insulating layer 22) continuously in contact with the resist pattern 30B 'is exposed on the surface.

The developer used for developing the photoresist film 30 also acts as an etchant, and the inorganic insulating layer 23 is processed by wet etching (see FIG. 9B) to form the contact hole 27.
In the present embodiment, as described above, since the inorganic insulating layer 23 is soluble in the developer used for developing the photoresist film 30, the exposure can be performed by using the developer as an etching solution. The etched region 22A is removed by the etching solution, and a contact hole 27 is formed. Further, since the developer is also used as an etching solution, the development of the photoresist film 30 and the wet etching of the inorganic insulating layer 23 can be performed in one step.

  Here, as described above, in the present embodiment, since the developer used for developing the photoresist film 30 is used as the etchant used for wet etching of the inorganic insulating layer 23, the development used in this developing step is used. The liquid may be any liquid as long as the photoresist film 30 can be developed, the inorganic insulating layer 23 can be dissolved, and the conductive layer 20 is insoluble, and the photoresist film 30 and the inorganic insulating layer 23 can be used. , And the constituent material of the conductive layer 20 may be selected as appropriate. The term “insoluble in the conductive layer 20” preferably means that the dissolution rate of the constituent material of the conductive layer 20 in the developer (etching solution) having a liquid temperature of 25 ° C. is 0.2 nm / s or less. ing.

For example, it is assumed that the inorganic insulating layer 23 is made of an alkali-soluble material (for example, Ga ₂ O ₃ ). Further, it is assumed that the material of the photoresist is selected so that a region targeted for removal by pattern exposure in the above exposure step exhibits alkali solubility and a region targeted for remaining exhibits alkali resistance. Further, it is assumed that a material exhibiting alkali resistance is used for the conductive layer 20. In the case of this combination, an alkaline etchant may be used as the developer and etchant used in the development step.

  Note that as the material used for the conductive layer 20, an acid-sensitive material such as amorphous IZO is preferably used, so that the etching solution for the inorganic insulating layer 23 (also used as a developer in this embodiment) is used. ) Is preferably an alkaline etching solution.

  Examples of the alkaline etching solution include sodium hydroxide, potassium hydroxide, sodium carbonate, sodium oxalate, sodium metasuccinate, aqueous ammonia, ethylamine, diethylamine, dimethylethanolamine, tetramethylammonium hydroxide, tetraethylammonium hydroxide. And an aqueous solution containing 1,8-diazabicyclo- [5.4.0] -7-undecene and the like.

  Examples of the development method used in this development step include a dipping method, a spray method, a paddle method, and the like. Further, after development, washing is generally performed with running water.

  Next, the resist pattern 30 </ b> B ′ is peeled off from the inorganic insulating layer 22. The resist pattern 30B ′ may be stripped by any method as long as the resist pattern 30B ′ can be stripped from the protective layer 22B. A method such as ultrasonic wave or ashing is preferably used.

The stripping solution used for dissolving and removing the resist pattern 30B ′ may be any liquid that does not dissolve the inorganic insulating layer 22 and the conductive layer 20 and can dissolve the resist pattern 30B ′. The conductive layer 20 may be selected as appropriate according to the constituent material of the conductive layer 20 and the constituent material of the resist pattern 30B ′. In the present embodiment, for example, a neutral stripping solution is preferably used.
The resist pattern 30B ′ is not necessarily peeled off, and may be left as it is without being peeled off.

  After the development processing, post-baking processing is performed as necessary. Post-baking is a process for the purpose of tapering the shape of the contact hole 27 in the inorganic insulating layer 22 by thermal deformation, and heating (hard baking) is usually performed at about 200 ° C. to 220 ° C. It is carried out continuously or batchwise using heating means such as a hot plate, a convection oven (hot air circulation dryer), a high-frequency heater or the like.

  Since the bottom edge of the contact hole 27 of the inorganic insulating layer 22 can be tapered by the above steps, the bottom edge can be easily tapered as compared with the lift-off method conventionally used when processing the inorganic insulating layer 22. It can be said.

  Note that the taper angle of the bottom peripheral edge of the contact hole 27 of the inorganic insulating layer 22 is easily adjusted by the baking temperature condition during the post baking and the temperature condition of the developer (etching liquid), for example, 30 ° to 80 °. Adjusted to

  Through the above steps, the field effect transistor 10 is manufactured as shown in FIGS.

  In addition, when applying this field effect transistor 10 to the various apparatuses mentioned later, you may provide the electrode layer 24 on this inorganic insulating layer 22 by an electrode layer formation process.

As the film formation method and patterning method of the electrode layer 24, known methods are used. For example, the film formation method and patterning method of the conductive layer 20 may be used.
The constituent material of the electrode layer 24 only needs to have conductivity, and may be appropriately selected according to various devices to which the field effect transistor 10 is applied. For example, Al, Mo, Cr, Ta, Metals such as Ti, Au, or Ag, alloys such as Al—Nd, APC, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO), polyaniline Preferable examples include organic conductive compounds such as polythiophene and polypyrrole, and mixtures and alloys thereof.
Among these, a metal oxide such as IZO or ITO is preferably used as a main component (because the electrode layer 24 can be made transparent (transmittance to visible light is 50% or more). For example, the field effect transistor 10 Is applied to an electromagnetic wave detector, which will be described later, it is preferable that the electrode layer 24 is made transparent to enable irradiation with backlight for afterimage erasure (details will be described later) and to improve detection performance.
In addition, having a metal oxide as a main component means that the content is the largest among the constituent components of the electrode layer 24. As a result, the electrode layer 24 is transparent by having the metal oxide as a main component. It is a content of the grade which is made into a state, Preferably, it has shown that it is 50 mass% or more.

As described above, according to the method of manufacturing the field effect transistor 10 of the present embodiment, the conductive layer 20 including the source electrode 20A, the drain electrode 20B, and the pixel electrode 20C formed by the conductive layer formation step. Then, an inorganic insulating layer 23 containing an inorganic material as a main component is formed so as to cover the conductive layer 20 and the oxide semiconductor layer 18. Then, after a photoresist film 30 is formed on the inorganic insulating layer 23 and exposed in a pattern, a resist pattern 30B ′ is formed by developing using a developer in a development process. In the development step, a part of the conductive layer 20 is exposed by removing a region exposed from the resist pattern 30B ′ in the inorganic insulating layer 23 using the developer as an etching solution. As a result, a contact hole 27 is formed in the inorganic insulating layer 22.
Thus, according to the manufacturing method of the field effect transistor 10 of the present embodiment, the inorganic insulating layer 23 is an insulating layer mainly composed of an inorganic material, and the inorganic insulating layer is formed by wet etching using an etching solution. 23, the contact hole 27 is formed by exposing a part of the conductive layer 20 provided on the lower layer side of the inorganic insulating layer 23, so that the conductive layer 20 is eroded when the contact hole 27 is formed. And damage is suppressed.

Specifically, the processing accuracy is higher than that in the case where the contact hole 27 is formed in the inorganic insulating layer 23 by lift-off, and the yield is high because dust is hardly generated. Further, since the edge of the region where the contact hole 27 is formed in the inorganic insulating layer 22 (periphery of the bottom of the contact hole) can be easily tapered, it is suitable for forming the contact hole 27.
Furthermore, since the inorganic insulating layer 23 is processed by wet etching to form the contact hole 27, the equipment is less expensive than the dry etching method, so that the cost can be reduced.

  In addition, since the inorganic insulating layer 22 is a layer containing an inorganic material as a main component, it can be formed using a sputtering method, and a uniform and thin inorganic insulating layer 22 can be formed.

  Further, as described above, since an alkaline etching solution is preferably used as the etching solution, when the alkaline etching solution is used as the etching solution, the conductive layer 20 is made of amorphous IZO or the like. Even when the contact hole 27 is formed, the erosion of the conductive layer 20 is suppressed even when the contact hole 27 is formed.

In the method of manufacturing the field effect transistor 10 according to the present embodiment, the case where the developing solution used for developing the resist pattern 30B ′ is applied as the etching solution used when processing the inorganic insulating layer 23 in the developing process has been described. However, the processing of the inorganic insulating layer 23 is performed by wet etching, and the conductive layer 20 does not have to be eroded and damaged when the inorganic insulating layer 23 is processed, and development and etching may be performed using different liquids. .
In this case, an alkaline etchant is used as an etchant used for wet etching of the inorganic insulating layer 23 from the viewpoint of suppressing erosion of the conductive layer 20.

Specifically, instead of the development step, the following resist pattern forming step and processing step may be performed.
(6-1) Resist Pattern Formation Step In the resist pattern formation step, as shown in FIG. 12A, the photoresist film 30 that has undergone the exposure step is developed with a developer, as in the development step. In the photoresist film 30 that has undergone the above exposure process, the region that is soluble in the developer (if the positive photoresist is used, the region 30A irradiated with light (see FIG. 8C)) is removed, The region 30B (see FIG. 8C) that has not been irradiated with light in the exposure process is left as a resist pattern 30B ′, whereby the region in the inorganic insulating layer 23 that is in continuous contact with the resist pattern 30B ′. Region 22A other than (inorganic insulating layer 22) is exposed on the surface.
The formation of the resist pattern 30B ′ in this resist pattern forming step may be performed using the same method as the resist pattern 30B ′ in the developing step, but the choice of developer is wider than that in the developing step. That is, the developer used in this resist pattern forming step may be a liquid that can dissolve the region 30B of the photoresist film 30, and the inorganic insulating layer 23 may be an insoluble liquid.

  Further, the method for forming the resist pattern 30B 'in this resist pattern forming step is not limited to wet etching.

(6-2) Processing Step In the processing step, as shown in FIG. 12B, the region 22A exposed from the resist pattern 30B ′ formed in the resist pattern forming step in the inorganic insulating layer 23 is made alkaline. The contact hole 27 is formed by removing by wet etching using the etching solution. The alkaline etching solution used in this processing step has a wider selection than the etching solution obtained when the alkaline etching solution is used in the development step. That is, the alkaline etching solution used in this processing step may be any alkaline liquid that can dissolve the inorganic insulating layer 23 and is insoluble in the conductive layer 20, and is not suitable as a developer for the photoresist film 30. It may be.

Thus, by processing the inorganic insulating layer 23 in two steps, the developer used for developing the resist pattern 30B ′ and the alkaline etching used for processing the inorganic insulating layer 23 are processed. It is possible to make the liquid different from the liquid. For this reason, the conductive layer 20 is prevented from being eroded or damaged when the contact hole 27 is formed, and the choice of the developer and the etching solution is expanded.
Further, the developer used for forming the resist pattern 30B ′ is more suitable for forming the resist pattern 30B ′ as compared with the case where the developer is used as an etching solution used for processing the inorganic insulating layer 23. A liquid more suitable for processing the inorganic insulating layer 23 can be selected as the alkaline etching solution. For this reason, the shape and taper angle of the contact hole 27 formed in the inorganic insulating layer 23 can be adjusted to a desired shape and angle, and the contact hole 27 can be formed with higher accuracy.

  The field effect transistor 10 manufactured in the present embodiment is suitably applied to various devices such as a display device and an electromagnetic wave detector. Hereinafter, an example will be described.

(Display device)
The field effect transistor 10 manufactured in the present embodiment is preferably applied to an image display device using a liquid crystal or an EL element, in particular, a display device such as a flat panel display (FPD). More preferably, it is used for a flexible display device using a flexible substrate such as an organic plastic film as the substrate. In particular, the field effect transistor 10 of the present embodiment is suitably used for a display device using an organic EL element.

  When the field effect transistor 10 is applied to an organic EL display device, for example, as shown in FIG. 13, the contact hole 27 is provided in the field effect transistor 10 manufactured in the present embodiment. An organic EL display device 50 in which an organic EL element 41 having a configuration in which an electrode layer 24, an organic EL layer 40, and an upper electrode layer 42 are sequentially stacked on the inorganic insulating layer 22 is exemplified.

  Although not shown in the drawings, as the organic EL layer 40, for example, each pixel region is configured by using an organic EL layer 40 having a configuration in which pixel regions composed of three color regions of RGB are arranged one-dimensionally or two-dimensionally. If the organic EL display device has a configuration in which the field effect transistors 10 are arranged corresponding to the organic EL display device, the organic EL display device in which the field effect transistors 10 are arranged corresponding to the pixel regions of the pixels of the displayed image. Is configured.

  When the field effect transistor 10 is applied to a display device using a liquid crystal element, a configuration in which a liquid crystal layer is provided instead of the organic EL layer 40 may be used.

  Here, as described above, the contact hole 27 is formed in the inorganic insulating layer 22 of the field-effect transistor 10 in a state where the erosion and damage of the conductive layer 20 are suppressed. It is considered that the conductive layer 20 of the type transistor 10 and the electrode layer 24 of the organic EL element 41 are electrically connected in a good contact state. For this reason, it is thought that the drive performance can be improved.

(Electromagnetic wave detector)
The field effect transistor 10 manufactured in the present embodiment is suitably used for an electromagnetic wave detector that detects an image by an electromagnetic wave such as X-ray radiation, visible light, ultraviolet light, or the like.

  When the field effect transistor 10 is applied to an electromagnetic wave detector, for example, as shown in FIG. 14, the inorganic insulation provided with the contact hole 27 in the field effect transistor 10 manufactured in the present embodiment is used. Examples of the electromagnetic wave detector 60 include a detection element 66 having a configuration in which an electrode layer 24, a charge generation layer 62 that generates a charge according to an electromagnetic wave to be detected, and a transparent bias electrode 64 are stacked on the layer 22. The electrode layer 24 functions as a charge collection electrode that collects the electric field generated by the charge generation layer 62.

  In such an electromagnetic wave detector 60, when electromagnetic waves such as X-rays enter the charge generation layer 62, charges are generated in the charge generation layer 62. The generated electrons are accumulated in the capacitor 26 through the electrode layer 24, and are extracted to the outside when the transistor element 15 in the field effect transistor 10 is turned on. The electromagnetic wave detector 60 is arranged one-dimensionally or two-dimensionally, and the field effect transistor 10 in each electromagnetic wave detector 60 is sequentially scanned (charge reading), thereby obtaining one-dimensional or two-dimensional charge information, that is, an image. Can be used as an electromagnetic wave detector for detecting an image used for an image sensor or the like.

  Here, as described above, the contact hole 27 is formed in the inorganic insulating layer 22 of the field-effect transistor 10 in a state where the erosion and damage of the conductive layer 20 are suppressed. The conductive layer 20 of the type transistor 10 and the electrode layer 24 of the detection element 66 are considered to be electrically connected in a good contact state. For this reason, it is thought that the drive performance can be improved.

As described above, the electrode layer 24 is made transparent (by transmitting 50% or more of light in the visible light region) by selecting a constituent material, and the field effect transistor 10 is also selected by selecting a transparent material. Since the charge generation layer 62 can be irradiated with backlight for erasing afterimages, it is considered that the detection performance is improved.
The phrase “irradiate afterimage erasing backlight light” indicates that the charge generation layer 62 is irradiated with electromagnetic waves via the electrode layer 24 from the substrate 12 side. That is, if the electrode layer 24 is transparent, when recording an image, the charge generation layer 62 is irradiated with electromagnetic waves from the bias electrode 64 side of the electromagnetic wave detector 60 and the charge remaining in the charge generation layer 62 is erased. The electromagnetic wave is applied to the charge generation layer 62 from the substrate 12 side of the electromagnetic wave detector 60 through the field effect transistor 10 and the electrode layer 24. For this reason, it is thought that detection performance improves.

  Hereinafter, a field effect transistor manufactured by using the method for manufacturing a field effect transistor of the present invention and a mode in which the field effect transistor is applied to an electromagnetic wave detector will be described by way of examples. However, the present invention is not limited to these examples.

Example 1
In Example 1, a field effect transistor 1 and an electromagnetic wave detector using the field effect transistor 1 were produced.

-Fabrication of field effect transistor 1-
Conductive layer forming step In the conductive layer forming step, a stacked body in which a gate electrode and a lower electrode, a gate insulating film, and a conductive layer are stacked in order is formed on a substrate (see the stacked body 10A in FIG. 3C). did.
As the substrate, alkali-free glass (Eagle 2000, Corning) was used.

Next, Mo was vapor-deposited to a thickness of 40 nm on the substrate as an electrode layer to be a gate electrode and a lower electrode, and the gate electrode and the lower electrode were patterned. The sputtering conditions were as follows.
Mo sputtering conditions: DC power 380 W and sputtering gas flow rate Ar = 12 sccm by a DC magnetron sputtering apparatus.
For this patterning, a photolithography method and a wet etching method were used.

Further, the following gate insulating film was formed on the gate electrode and the lower electrode.
Gate insulating film: SiO ₂ by RF magnetron sputtering vacuum deposition method (conditions: target SiO ₂ , film forming temperature 54 ° C., sputtering gas Ar / O ₂ = 12/2 sccm, RF power 400 W, film forming pressure 0.4 Pa) A gate insulating film was formed to a thickness of 200 nm. Patterning of the gate insulating film SiO ₂ was performed by using a shadow mask during sputtering.

On this gate insulating film, IZO was deposited as a conductive layer 20 to a thickness of 200 nm. The sputtering conditions were as follows.
IZO sputtering conditions: DC power 40 W, sputtering gas flow rate Ar = 12 sccm using a DC magnetron sputtering apparatus. No oxygen was introduced.

  Next, a resist pattern was formed on the conductive layer. The resist pattern was formed by applying a resist with a spin coater, and the film thickness was 1 μm. After this resist film was formed, it was baked at 90 ° C. Next, a region exposed from the resist pattern in the conductive layer is etched using a phosphoric acid / nitric acid mixed solution having a liquid temperature of 25 ° C. as an etching solution, and the conductive layer is processed to obtain a source electrode and a drain. Electrodes and pixel electrodes were formed. The pixel electrode functions as an electrode (also referred to as an upper electrode) constituting a capacitor together with the formed lower electrode.

  When the taper angle of the formed source electrode and drain electrode was read from the photograph using a cross-sectional TEM photograph, it was 25 °. The taper angle of the source electrode was determined from the angle formed by the bottom surface and the side surface at the cross-sectional end of the source electrode. Further, the taper angle of the drain electrode was obtained from the angle formed by the bottom surface and the side surface at the end of the cross section of the drain electrode. In addition, this bottom surface has shown the surface at the side of the board | substrate of each source electrode and drain electrode.

Step of forming oxide semiconductor layer Next, an oxide semiconductor layer made of an amorphous oxide semiconductor was formed over the source electrode and the drain electrode. As a method for forming this oxide semiconductor layer, an RF magnetron sputtering vacuum deposition method is used to target a polycrystalline sintered body having a composition of InGaZnO ₄ on the source electrode and the drain electrode in the conductive layer 20 formed as described above. A magnetron sputtering vacuum deposition method was used under the conditions of an Ar flow rate of 97 sccm, an O ₂ flow rate of 1.6 sccm, an RF power of 200 W, and a pressure of 0.38 Pa. The thickness was 20 nm.

Next, on the oxide semiconductor layer and conductive layer (source electrode, drain electrode, and pixel electrode) formed above, Ga ₂ O ₃ is formed as an inorganic insulating layer with a thickness. Vapor deposited to 50 nm. The sputtering conditions were as follows.
Sputtering conditions: Ga ₂ O ₃ was used as a target, and the RF power was 100 W, the sputtering gas flow rate was Ar = 12 sccm, and O ₂ = 5.0 sccm using an RF magnetron sputtering apparatus.

Next, a photoresist film is formed on the inorganic insulating layer, and exposure is performed in a pattern so that a region corresponding to the pixel electrode in the conductive layer is exposed as a contact hole as a part of the conductive layer. It was.
Specifically, as a photoresist, a product name AZ5214-E manufactured by AZ Electronic Materials Co., Ltd. is used, and this is applied by a spin coater to form a photoresist film, prebaked at 90 ° C. for 15 minutes, and pattern exposure did.

Development process In the development process, the film was immersed in an AZ300MIF developer (AZ Electronic Materials Co., Ltd.) for 90 seconds as an alkaline developer.
As a result, the photoresist film formed on the inorganic insulating layer is developed to form a resist pattern, and the inorganic insulating layer provided on the lower layer side of the photoresist film is exposed from the resist pattern. Has been removed. For this reason, it was confirmed that the photoresist film was developed with the alkaline developer, and the inorganic insulating layer was processed to form a contact hole by wet etching using the alkaline developer. .

For the photoresist film developed in the development process of Example 1, the dissolution rate of the photoresist film in the alkaline developer (etching solution) used in Example 1 at a liquid temperature of 25 ° C. was 30 nm / It was confirmed that the photoresist film was soluble in the alkaline developer.
Similarly, with respect to the inorganic insulating layer etched in the developing process of Example 1, the dissolution rate of the inorganic insulating layer in the alkaline developer (etching solution) used in Example 1 having a liquid temperature of 25 ° C. is 2 It was confirmed that the inorganic insulating layer was soluble in the alkaline developer (etching solution).

  Next, the field effect transistor 1 was produced by peeling off the resist pattern using a neutral peeling solution (Tokyo Ohka Kogyo Co., Ltd., peeling solution 104).

The taper angle of the bottom edge of the contact hole in the inorganic insulating layer of the manufactured field effect transistor 1 was measured using a cross-sectional TEM photograph and found to be 70 °.
Note that the taper angle of the bottom peripheral edge of the contact hole in this inorganic insulating layer is the side surface (corresponding to the inner peripheral surface of the contact hole) formed by the contact hole of the inorganic insulating layer and the bottom surface (surface on the substrate side) of the inorganic insulating layer. ) And the angle formed by measuring.

-Production of electromagnetic wave detector-
In this field-effect transistor 1, IZO was deposited to a thickness of 40 nm as an electrode layer 24 (see FIG. 14) functioning as a charge collection electrode on the inorganic insulating layer in which the contact hole was formed. The sputtering conditions were as follows.
IZO sputtering conditions: DC power 40 W, sputtering gas flow rate Ar = 12 sccm using a DC magnetron sputtering apparatus. No oxygen was introduced.

Further, the charge collection layer was laminated on the charge collection electrode by resistance heating vapor deposition of amorphous selenium to a thickness of 500 μm. Further, on this electric field collecting layer, Au was deposited by resistance heating so as to have a thickness of 0.1 μm to form a bias electrode.
Thus, an electromagnetic wave detector having the configuration shown in FIG. 14 was produced.

For the produced electromagnetic wave detector, a positive bias voltage (+5 kV) was applied to the bias electrode, a voltage of −5 V was applied to the gate electrode of the field effect transistor 1, and the source electrode was set to 0 V (common). Using an X-ray irradiation apparatus, 1 mR of 80 kVp, 20 mm Al filter, and tungsten filament X-rays were irradiated. Next, by applying a voltage of +10 V to the gate electrode for 10 microseconds, the transistor element in the field effect transistor 1 (see transistor element 15 in FIG. 14) is turned on, so that the charge extracted from the source electrode Was detected. This charge detection was performed by detecting the amount of charge taken from the source electrode using a charge amplifier detection circuit. The amount of charge detected was 2500 pCcm ⁻² , and good electromagnetic wave detection was confirmed.

(Example 2)
In Example 2, a display device including a liquid crystal element was manufactured using the field effect transistor 1 manufactured in Example 1 above.

―Production of display device―
In the field effect transistor 1 fabricated in Example 1, IZO was deposited to a thickness of 40 nm as the electrode layer 24 (see FIG. 13) on the inorganic insulating layer in which the contact hole was formed. The sputtering conditions were as follows.
IZO sputtering conditions: DC power 40 W, sputtering gas flow rate Ar = 12 sccm using a DC magnetron sputtering apparatus. No oxygen was introduced.

  Further, on the electrode layer, a spacer member having a thickness of 10 μm is formed of an acrylic resin as a gap member for maintaining a gap between the substrate provided in a post process and the electrode layer, and then a substrate provided with an ITO electrode is formed. Laminated and fixed to the gap member by an adhesive layer. As a liquid crystal material constituting the liquid crystal layer in a region (sometimes referred to as a cell) between the substrate, the electrode layer, and the gap member (trade name, manufactured by Chisso Petrochemical Co., Ltd.) The display device was manufactured by sealing the injection hole after injecting LIXON 4032).

  With respect to the manufactured display device, when the signal line voltage was set to 5 V at the maximum, an image was displayed on the liquid crystal layer, and good image display was confirmed.

(Comparative Example 1)
In Comparative Example 1, instead of the oxide semiconductor layer and the inorganic insulating layer formed on the conductive layer in the manufacturing process of the field effect transistor 1 manufactured in Example 1 above, A comparative transistor 1 was produced using the same conditions and the same method as the method for producing the field effect transistor 1 except that a resin layer made of an acrylic resin was provided. Note that the formation of the contact hole in the acrylic resin was also performed using the same wet etching method as the formation of the contact hole in the inorganic insulating layer in the manufacturing process of the field effect transistor 1.

  In addition, formation of the layer (henceforth the comparison layer 1) by an acrylic resin was performed by the following method. First, as the acrylic resin, an alkali-soluble acrylic resin (manufactured by JSR, trade name: JEM-531) is used to apply the resin using acetone, thereby comparing the comparative layer 1 with an acrylic resin having a thickness of 50 nm. did.

(Comparative Example 2)
In Comparative Example 2, an insulating layer made of SiO ₂ was formed in place of the formed inorganic insulating layer in the manufacturing process of the field effect transistor 1 manufactured in Example 1 above.

Specifically, in the manufacturing process of the field-effect transistor 1 prepared in Example 1, instead of the inorganic insulating layer formed on the oxide semiconductor layer and the conductive layer, SiO ₂ is formed on the oxide semiconductor layer and the conductive layer. The comparative transistor 2 was fabricated using the same conditions and the same method as the method for manufacturing the field effect transistor 1 except that the layer (hereinafter referred to as the comparative layer 2) was provided.

Note that the formation of the comparative layer ₂ by SiO ₂ was performed by the following method.
Specifically, a layer (50 nm) made of SiO ₂ was formed on the oxide semiconductor layer and the conductive layer formed in the manufacturing process of the field effect transistor 1 in Example 1 by the sputtering method. As sputtering conditions, SiO ₂ was used as a target, and an oxidizing atmosphere of oxygen gas 5 sccm and argon gas 5 sccm in a mixing ratio of 50 vol% was used as a sputtering gas.
Next, the comparative layer 2 made of SiO ₂ was dry-etched using CF ₄ gas to form a contact hole in the comparative layer. Since this comparative layer 2 has acid resistance and alkali resistance, wet etching could not be performed, and thus processing was performed by dry etching.

―Evaluation―
―Evaluation of erosion and damage state of conductive layer―
In the manufacturing process of the field effect transistor 1 manufactured in Example 1, when a contact hole was formed in the inorganic insulating layer, the region exposed by the contact hole formation in the conductive layer was confirmed using a cross-sectional TEM photograph. It was confirmed that the underlying conductive layer remained, and it was confirmed that damage and erosion of the conductive layer due to the formation of the contact hole were suppressed.

  Further, in the manufacturing process of the comparative transistor 1 manufactured in Comparative Example 1, when the contact hole is formed in the comparative layer 1 made of acrylic resin, the region exposed by the formation of the contact hole in the conductive layer is similarly formed as described above. As a result of confirmation, a portion having no acrylic resin was seen in a region outside the contact hole portion. That is, it was difficult to form a thin insulating layer.

On the other hand, when a contact hole is formed in the comparative layer 2 made of SiO ₂ in the manufacturing process of the comparative transistor 2 manufactured in Comparative Example 2, similarly, the region exposed by the formation of the contact hole in the conductive layer is the same as described above. As a result, a result of a taper angle of 60 ° was confirmed, and it was found that the contact hole was well formed.

―Protective evaluation―
For the field effect transistor 1, the comparative transistor 1, and the comparative transistor 2 obtained in the example and the comparative example, the source electrode and the drain electrode are short-circuited, and the stress current is diode-connected so that the stress current IDS = 3 μA. Applied for 14 hours.

  Then, the amount of change of the threshold before and after the stress is defined as the threshold shift amount (ΔVth) and evaluated. As a result, the threshold shift amount of the field effect transistor 1 is 0.2 V, and the threshold shift of the comparison transistor 1 is The amount was 2 V, and the off-current of the comparative transistor 2 was very large, and the off operation was not obtained from the initial measurement stage.

  As described above, the field-effect transistor 1 manufactured in Example 1 has a smaller threshold shift amount than the comparative transistor 1 manufactured in Comparative Example 1 and the comparative transistor 2 manufactured in Comparative Example 2, and operates stably. Indicated.

  As described above, the field-effect transistor 1 manufactured in Example 1 is different from the comparative transistor 1 manufactured in Comparative Example 1 and the comparative transistor 2 manufactured in Comparative Example 2 in the contact hole formation of the conductive layer. It was confirmed that erosion and breakage of the conductive layer were suppressed, and that good operational stability was exhibited and the oxide semiconductor layer and the conductive layer were well protected.

10 Field Effect Transistor 12 Substrate 14A Gate Electrode 16 Gate Insulating Film 18 Oxide Semiconductor Layer 20 Conductive Layer 20A Source Electrode 20B Drain Electrode 20C Pixel Electrode 22 Inorganic Insulating Layer 24 Electrode Layer 50 Organic EL Display Device 60 Electromagnetic Wave Detector 30B ′ Resist pattern

Claims (8)

A substrate, a gate electrode, a gate insulating film, a source electrode, a drain electrode, a pixel electrode, an oxide semiconductor layer mainly containing an oxide semiconductor, an inorganic insulating layer mainly containing an inorganic material, A method of manufacturing a field effect transistor having
A conductive layer forming step of forming a conductive layer including at least one of the source electrode, the drain electrode, and the pixel electrode;
An inorganic insulating layer forming step of forming the inorganic insulating layer so as to cover the conductive layer and the oxide semiconductor layer;
A resist forming step of forming a photoresist film on the inorganic insulating layer formed by the inorganic insulating layer forming step;
An exposure step of exposing the photoresist film formed by the resist formation step in a pattern;
The photoresist film exposed in the exposure step is developed using a developer to form a resist pattern, and the developer is used as an etchant in the inorganic insulating layer exposed from the resist pattern. A developing step of exposing a portion of the conductive layer by removing
The manufacturing method of the field effect transistor which has this. An electrode layer forming step of forming an electrode layer so as to be electrically connected to the conductive layer partially exposed by the developing step through the exposed region;
2. The method of manufacturing a field effect transistor according to claim 1, wherein the electrode layer formed in the electrode layer forming step contains a metal oxide as a main component. Wherein the inorganic material, manufacturing method of a field effect transistor according to claim 1 or claim 2 which is an oxide containing at Ga. The method for manufacturing a field effect transistor according to any one of claims 1 to 3 , wherein the inorganic material is amorphous. Method for producing a field effect transistor according to any one of claims 1 to 4 wherein the etchant is an alkaline solution. Field effect transistor manufactured by the manufacturing method of the field effect transistor according to any one of claims 1 to 5. Display device having a field-effect transistor manufactured by the manufacturing method of the field effect transistor according to any one of claims 1 to 5. The electromagnetic wave detector provided with the field effect transistor manufactured by the manufacturing method of the field effect transistor of any one of Claims 1-5 .

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