JP5418120B2 - Communication circuit, communication method, and serial-parallel conversion circuit - Google Patents

Description

  The present invention relates to a communication circuit, a communication method, and a serial / parallel conversion circuit that convert a serial signal into a parallel signal.

In recent years, in order to improve the communication speed of signals connecting LSIs, attempts to connect LSIs using serial signals instead of parallel signals are increasing.
In that case, the transmission-side circuit that transmits the serial signal needs a parallel-serial conversion circuit that converts the parallel signal into a serial signal, and the reception-side circuit that receives the serial signal transmitted from the transmission-side circuit A serial-parallel conversion circuit that converts a signal into a parallel signal is required (see, for example, Patent Document 1).

JP 2006-238302 A

  However, between LSIs, there is a possibility that the reference signal of the transmission side circuit and the reference signal of the reception side circuit are fixedly shifted or temporally fluctuated due to manufacturing variations of LSI, power supply noise, signal noise, etc. Therefore, there are cases where it is difficult to perform data communication as expected.

  The present invention is considered in view of the above circumstances, and the reference signal of the transmission side circuit and the reference signal of the reception side circuit may be fixedly shifted due to manufacturing variations of LSI, power supply noise, signal noise, and the like. An object of the present invention is to provide a communication circuit, a communication method, and a serial-parallel conversion circuit capable of reliably converting a serial signal into a parallel signal and performing data communication as expected even if it varies over time. .

  In order to achieve the above object, a communication circuit of the present invention includes a reception side circuit that receives a serial signal transmitted from a transmission side circuit, and the reception side circuit determines the bit rate of the serial signal and the operation of the reception side circuit. First multi-phase clock generating means for generating at least N multi-phase clocks that change every N cycles of the serial signal, and at least N clocks that change every N cycles of the serial signal, where N is a clock ratio. A second multi-phase clock generating means for generating a multi-phase clock; and sequentially holding the bit data of the serial signal with the output of the first multi-phase clock generating means as a clock input; Serial parallel that samples the output of the phase clock generator as a clock input and outputs it as N parallel signals It is constituted comprising a switching means, a.

  In the communication method of the present invention, the receiving side circuit that receives the serial signal transmitted from the transmitting side circuit has a ratio of the bit rate of the serial signal and the operation clock of the receiving side circuit as N, and A first multiphase clock generating procedure for generating at least N multiphase clocks that change every N cycles, and a second multiphase clock for generating at least N multiphase clocks that change every N cycles of the serial signal The bit data of the serial signal is sequentially held using the generation procedure and the output of the first multiphase clock generation procedure as a clock input, and the held bit data is sampled using the output of the second multiphase clock generation procedure as a clock input And a serial-parallel conversion procedure for outputting as N parallel signals.

  The serial-parallel conversion circuit according to the present invention generates a first multi-phase clock that generates at least N multi-phase clocks that change every N cycles of the serial signal, where N is a ratio between the bit rate of the serial signal and the operation clock of the circuit. Phase clock generation means, second multiphase clock generation means for generating at least N multiphase clocks that change every N cycles of the serial signal, and output of the first multiphase clock generation means as clock inputs A serial parallel conversion unit that sequentially holds bit data of a serial signal, samples the held bit data using the output of the second multiphase clock generation unit as a clock input, and outputs the sampled data as N parallel signals; It is as.

  As described above, according to the present invention, the reference signal of the transmission side circuit and the reference signal of the reception side circuit are fixedly shifted or temporally caused by manufacturing variations of LSI, power supply noise, signal noise, and the like. Even if it fluctuates, it is possible to reliably convert the serial signal into a parallel signal in the receiving side circuit and perform data communication as expected.

It is a block diagram which shows schematic structure of the communication circuit which concerns on embodiment of this invention. FIG. 2 is a block diagram in which peripheral circuits are added to FIG. It is a circuit diagram which shows the specific example of the 1st multiphase clock generation means of the communication circuit which concerns on embodiment of this invention. It is a circuit diagram which shows the specific example of the 2nd multiphase clock generation means of the communication circuit which concerns on embodiment of this invention. It is a circuit diagram which shows the specific example of the serial parallel conversion means of the communication circuit which concerns on embodiment of this invention. FIG. 6 is a timing chart showing the operation timing when the ratio N between the pit rate of the serial signal and the operation clock of the receiving circuit is 10 in the communication circuit according to the embodiment of the present invention. FIG. 7 is a timing chart in which operations of auxiliary lines and data alignment means are added to FIG. 6. FIG. 9 is a timing chart showing the operation timing when the ratio N between the pit rate of the serial signal and the operation clock of the receiving circuit is 9 in the communication circuit according to the embodiment of the present invention. In the communication circuit according to the embodiment of the present invention, the operation timing in the case where the ratio N between the pit rate of the serial signal and the operation clock of the receiving circuit is 9 and the data alignment means performs rearrangement with 10 bits of serial data as one word. It is a timing chart figure shown.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a communication circuit according to an embodiment of the present invention.
As shown in this figure, the communication circuit according to the embodiment of the present invention has a reception side circuit (serial parallel conversion circuit) that receives a serial signal transmitted from the transmission side circuit, and the reception side circuit One multiphase clock generating means 1, second multiphase clock generating means 2, and serial / parallel conversion means 3 are provided.

The first multiphase clock generation means 1 is configured to receive a clock signal 701 having the same frequency as the bit rate of the serial signal 700 and a control signal 703 and output a signal 704 indicating the state and the multiphase clock 30. Yes.
The second multiphase clock generation means 2 is configured to receive a clock signal 702 having the same frequency as the bit rate of the serial signal 700 and a control signal 705, and output a signal 706 indicating the state and the multiphase clock 40. Yes.
The serial / parallel conversion means 3 is configured to receive the serial signal 700 and the multiphase clocks 30 and 40 and to output a parallel signal 60.

FIG. 2 is a block diagram in which peripheral circuits are added to FIG.
As shown in this figure, the receiving side circuit of the present embodiment is provided with a first multiphase clock generation means 1, a second multiphase clock generation means 2, a serial / parallel conversion means 3, and a clock when peripheral circuits are added. Extraction means 4, buffer circuit 5, and data alignment means 6 are provided.

The first multiphase clock generation means 1 is configured to receive the output 701 of the clock extraction means 4 and the control signal 703 and output a signal 704 indicating the state and the multiphase clock 30.
The second multiphase clock generation means 2 is configured to receive the output 702 of the buffer circuit 5 and the control signal 705 as inputs, and output a signal 706 indicating the state and the multiphase clock 40.
The serial / parallel conversion means 3 is configured to receive the serial signal 700 and the multiphase clocks 30 and 40 and to output a parallel signal 60.

The clock extracting means 4 is configured to receive the serial signal 700 and output a clock signal 701 having the same frequency as the bit rate of the serial signal 700.
The buffer circuit 5 is configured to receive the clock signal 701 and output the clock signal 702.
The data aligning means 6 is configured to receive a signal 710 synchronized with the clock signal of the receiving side circuit and the parallel signal 60 and output a signal 65.

  The clock extraction means 4 of the present embodiment outputs a clock signal having the same frequency as the bit rate of the serial signal 700, but outputs a frequency that is half the bit rate of the serial signal 700, and receives the clock signal. These flip-flops may be operated using both rising and falling edges of the clock signal.

FIG. 3 is a circuit diagram showing a specific example of the first multiphase clock generation means of the communication circuit according to the embodiment of the present invention.
As shown in this figure, the first multiphase clock generating means 1 of the present embodiment includes first to twelfth flip-flops 810 to 821, first and second inverters 896 and 898, first and first flip-flops. 2 OR circuits 897 and 899, first to tenth AND circuits 832 to 841, and first and second selectors 850 and 851.

  In FIG. 3, a signal 801 is a clock signal, a signal 802 is a reset signal, a signal 803 is a signal for controlling the period and phase of the multiphase clock 30 generated by the first multiphase clock generating means 1, Reference numerals 301 to 312 denote multiphase clocks output from the first multiphase clock generator 1.

In the first multiphase clock generation means 1, when the signal 802 is set to “0” and the clock signal 801 is changed from “0” to “1”, the values held by the first to twelfth flip-flops 810 to 821 are “11000... 00” is initialized.
Next, when the signal 802 is set to “1” and the clock signal 801 is changed from “0” to “1”, the values of the flip-flops 810 to 821 are sequentially shifted to generate multiphase clocks 301 to 310 (FIG. 6).

At this time, the signal 803 causes the selectors 850 and 851 to select appropriate output signals of the flip-flops 813 to 815 and 819 to 821, so that the number of loop stages of the flip-flops 810 to 821 connected in a loop is changed to the serial signal 700. It can be adjusted to be equal to the ratio N of the bit rate of the receiver and the frequency of the receiving circuit.
In other words, when changing the ratio N between the bit rate and the frequency of the receiving circuit, the signal 803 is set so that the selectors 850 and 851 select the output signals of the appropriate flip-flops 813 to 815 and 819 to 821. .
Further, the phase difference between the word boundary of the serial signal 700 and the clock signal of the receiving side circuit can be adjusted by setting the number of loop stages to a value larger or smaller than the ratio N for a certain time using the selectors 850 and 851. it can.

FIG. 4 is a circuit diagram showing a specific example of the second multiphase clock generation means of the communication circuit according to the embodiment of the present invention.
As shown in this figure, the second multiphase clock generation means 2 includes first to twelfth flip-flops 910 to 921, first and second inverters 996 and 998, and first and second OR circuits. 997, 999, first to tenth AND circuits 932 to 941, first and second selectors 950 and 951, a switch circuit 953, and first to tenth buffers 960 to 969. Has been.

  In FIG. 4, a signal 901 is a clock signal, a signal 902 is a reset signal, a signal 903 is a signal for controlling the cycle and phase of the multiphase clock 40 generated by the second multiphase clock generation means 2, Reference numerals 401 to 412 denote multiphase clocks output from the second multiphase clock generator 2.

In the second multiphase clock generation means 2, when the signal 902 is set to “0” and the clock signal 901 is changed from “0” to “1”, the values held by the first to twelfth flip-flops 910 to 921 are “11000... 00” is initialized.
Next, when the signal 902 is set to “1” and the clock signal 901 is changed from “0” to “1”, the values of the flip-flops 910 to 921 are sequentially shifted. Then, outputs of some of the flip-flops 910 to 921 are output as multiphase clocks 401 to 410 via the switch circuit 953 and the buffers 960 to 969 (see FIG. 6).

At this time, the signal 903 causes the selectors 950 and 951 to select appropriate output signals from the flip-flops 913 to 915 and 919 to 921, so that the number of loop stages 910 to 921 connected in a loop shape becomes the bit of the serial signal 700. It can be adjusted to be equal to the ratio N of the rate and the frequency of the receiving circuit. The signal 903 is also input to the switch circuit 953, and an appropriate switch operation is performed.
In other words, when the ratio N of the bit rate and the frequency of the receiving circuit is changed, the signal 903 is set so that the selectors 950 and 951 select the appropriate output signals of the flip-flops 913 to 915 and 919 to 921. .
Further, the phase difference between the word boundary of the serial signal 700 and the clock signal of the receiving circuit can be adjusted by setting the number of loop stages to a value larger or smaller than the ratio N for a certain time using the selectors 950 and 951. it can.

The multi-phase clock generating means 1 and 2 form a loop of N stages or more with respect to the ratio N of the bit rate of the serial signal 700 and the operating frequency of the receiving side circuit. Can be arbitrarily set, and can include redundant flip-flops and redundant selectors in case N becomes large.
Further, the number of selectors included in the multiphase clock generation means 1 and 2 is not limited to two, and may be one or three or more.
Further, the signal for outputting the state of the multiphase clock generating means 1 and 2 may be omitted.

FIG. 5 is a circuit diagram showing a specific example of serial-parallel conversion means of the communication circuit according to the embodiment of the present invention.
As shown in this figure, the serial / parallel conversion means 3 includes first to tenth flip-flops 101 to 110, first to 20th flip-flops 201 to 210, and a twenty-first flip-flop 299.
The first to tenth flip-flops 101 to 110 have the twenty-first flip-flop output signal 500 as a data input and the multiphase clocks 301 to 310 as clock inputs and output signals 501 to 510.
That is, the first to tenth flip-flops 101 to 110 sequentially hold the bit data of the serial signal 700 using the output of the first multiphase clock generation means 1 as a clock input.

In addition, the 11th to 20th flip-flops 201 to 210 use the 1st to 10th flip-flops 101 to 110 output signals 501 to 510 as data inputs, the multiphase clocks 401 to 410 as clock inputs, and the signals 601 to 601. 610 is output.
That is, the 11th to 20th flip-flops 201 to 210 sample the bit data held by the 1st to 10th flip-flops 101 to 110 using the output of the second multiphase clock generation means 2 as a clock input.

  The number of first to tenth flip-flops 101 to 110 and the number of first to 20th flip-flops 201 to 210 is N with respect to the ratio N of the bit rate of the serial signal 700 and the operating frequency of the receiving circuit. If it is above, it can set arbitrarily and can include a redundant flip-flop in preparation for the case where N becomes large.

  Next, the operation of the communication circuit according to the embodiment of the present invention will be described with reference to FIGS.

FIG. 6 is a timing chart showing the operation timing when the ratio N between the bit rate of the serial signal and the operation clock of the receiving circuit is 10 in the communication circuit according to the embodiment of the present invention.
In this figure, a signal 700 is a serial signal, signals 300 to 310 are multiphase clocks generated by the first multiphase clock generating means 1, and signals 501 to 510 are first to tenth flip-flops 101 to 110. The signals 401 to 410 are multiphase clocks generated by the second multiphase clock generation means 2, the signals 600 to 605 are the upper digits of the parallel signal, and the signals 606 to 610 are the lower order of the parallel signal. It is a digit.

  The communication circuit according to the embodiment of the present invention can design a flip-flop and a multi-phase clock redundantly in case the ratio N between the bit rate of the serial signal 700 and the operating frequency of the receiving circuit increases from 10. In that case, signals 511-514 appear. When the redundantly designed flip-flop is not used, a part of the first multiphase clock connected to the clock terminal of the redundantly designed flip-flop may be fixed to “0” or “1”. . In this case, the signals 511 to 514 do not change, and the redundantly designed circuit does not consume dynamic power.

FIG. 7 is a timing chart in which the operations of the auxiliary line and the data alignment means are added to FIG.
As shown in this figure, the serial signal 700 is sequentially held by the first multiphase clocks 301 to 310 and converted into signals 501 to 510 having a long N valid period. Further, these signals 501 to 510 are sampled by the second multiphase clocks 401 to 410 to become two parallel signals 601 to 605 and 606 to 610.

  The first multiphase clock so that the clock signal 699 of the receiving circuit rises during a period 698 in which both the high-order parallel signals 601 to 605 and the low-order parallel signals 606 to 610 hold the same word data. By adjusting the phases of the generating means 1 and the second multiphase clock generating means 2, the data aligning means 6 in the receiving circuit can receive a correct parallel signal.

Also, periods 991 to 994 in the figure indicate the timing deviation allowed between the signals 501 to 510 and the second multiphase clocks 401 to 410.
Also, periods 696 and 697 in the figure are timing margins for the phase difference between the parallel signal word boundary and the parallel signal clock.

These four timing margins 991 to 994 need to be larger than the timing deviation caused by manufacturing variation, design error, power supply noise, etc. (Condition 1).
Further, the timing margins 696 and 697 need to be larger than the phase difference between the serial signal word boundary and the clock of the receiving side circuit caused by PLL phase error, power supply noise, signal noise, etc. (Condition 2).
Even if the phases of the multi-phase clocks 301 to 310 and 401 to 410 are adjusted, if the conditions 1 and 2 cannot be satisfied, the expected serial-parallel conversion is not performed. ˜110 are designed redundantly, and the effective period is extended by increasing the number of bits, whereby a circuit with high noise resistance can be obtained.

FIG. 8 is a timing chart showing the operation timing when the ratio N between the bit rate of the serial signal and the operation clock of the receiving circuit is 9 in the communication circuit according to the embodiment of the present invention.
In this figure, signal 700 is a serial signal, signals 300 to 310 are first multiphase clocks, signals 501 to 510 are output signals of first to tenth flip-flops 101 to 110, and signal 401 ˜410 is a second multiphase clock, the signals 600 to 604 are the upper digits of the parallel signal, and the signals 605 to 609 are the lower digits of the parallel signal.

  Here, some of the multiphase clocks 310 do not affect the operation, and therefore may be fixed to “0” or “1” or may be changed. Further, since the boundary between the upper digits and the lower digits is changed, the timing of some of the multiphase clocks 405 is changed as compared with the case where N = 10 (see FIG. 6). The second multiphase clock generation means 2 can cope with such a change of N and a change in the timing of the multiphase clock.

FIG. 9 shows a case where the ratio N of the serial signal bit rate and the operation clock of the receiving circuit is 20 in the communication circuit according to the embodiment of the present invention, and the data alignment means rearranges 10 bits of serial data as one word. It is a timing chart figure which shows the operation timing.
In this case, the number of phases of the first multiphase clocks 301 to 320 and the second multiphase clocks 401 to 420 is 20 (twice the number of bits per word), and the flip-flops of the multiphase clock generation means 1 and 2 are used. The number needs 20 or more. Further, the number of flip-flops of the serial / parallel conversion means 3 is required to be 20 or more.

In FIG. 9, a signal 700 is a serial signal, signals 301 to 320 are first multiphase clocks, signals 501 to 520 are output signals of the first to twentieth flip-flops 101 to 120, and a signal 401 ˜420 is a second multiphase clock, and signal 65 is a parallel output signal.
The parallel output signal 65 uses both the rising edge and the falling edge of the clock 710 of the receiving side circuit, and can determine which edge is used so that the timing margin is maximized.

  According to the communication circuit of the present embodiment configured as described above, a receiving circuit for receiving a serial signal transmitted from a transmitting circuit is provided, and the receiving circuit includes a bit rate of the serial signal and a receiving circuit. The first multiphase clock generation means 1 for generating at least N multiphase clocks that change every N cycles of the serial signal, and at least N cycles that change every N cycles of the serial signal The second multi-phase clock generating means 2 for generating the multi-phase clock and the output of the first multi-phase clock generating means 1 are used as clock inputs to sequentially hold the bit data of the serial signal and the held bit data to the second multi-phase clock generating means 1 Serial-parallel conversion means 3 for sampling the output of the phase clock generation means 2 as a clock input and outputting it as N parallel signals Even if the reference signal of the transmission side circuit and the reference signal of the reception side circuit are fixedly shifted or temporally fluctuated due to manufacturing variation of LSI, power supply noise, signal noise, etc., the reception side The serial signal can be reliably converted into a parallel signal in the circuit, and data communication as expected can be performed. The reason is that serial signals are assigned to N signals 501 to 510 having a long effective period, and the effective period is longer than the time lag between the reference signal of the transmitting circuit and the reference signal of the receiving circuit, and as short as possible. This is because the waste of conversion time can be minimized.

  The first multiphase clock generation means 1 and the second multiphase clock generation means 2 can change the number of multiphase clocks to be generated, and the serial / parallel conversion means 3 can change the number of parallel signals to be output. Therefore, the ratio N between the bit rate of the serial signal and the operating frequency of the receiving side circuit can be easily changed. The reason is that the first multiphase clock generating means 1 and the second multiphase clock generating means 2 can change the number of multiphase clocks in accordance with the ratio N and perform N serial / parallel conversion operations. It is.

  The first multi-phase clock generation means 1 includes N or more flip-flops 810 to 821 that are connected in a loop and sequentially shift, and selectors 850 and 851 that change the number of loop stages of the flip-flops 810 to 821. Since the output of each of the flip-flops 810 to 821 connected in a loop is output as a multi-phase clock, the number of loop stages is changed according to an external signal, or the number of loop stages is temporarily set to N The phase can be changed by changing to a value other than N and then returning the number of loop stages to N.

  The second multi-phase clock generation means 2 includes N or more flip-flops 910 to 921 that are connected in a loop and sequentially shift, and selectors 950 and 951 that change the number of loop stages of the flip-flops 910 to 921. A switch circuit 953 that outputs N or more multiphase clocks by using outputs of some of the flip-flops 910 to 921 connected in a loop, and N or more buffer circuits 960 to 960 that buffer the output of the switch circuit 953 969, the phase can be changed by changing the number of loop stages according to an external signal, or temporarily changing the number of loop stages to a value other than N, and then returning the number of loop stages to N.

  Thus, by using the first multiphase clock generation means 1 and the second multiphase clock generation means 2 having a high degree of freedom in changing the cycle and phase, the bit rate of the serial signal and the frequency of the clock signal of the receiving side circuit are changed. In addition, the serial signal can be converted into a parallel signal in the shortest conversion time regardless of the phase difference between the serial signal word boundary and the clock signal of the receiving circuit.

  The serial-parallel converter 3 also includes N or more flip-flops 101 to 110 that sequentially hold bit data of a serial signal by using the output of the first multiphase clock generator 1 as a clock input, and these flip-flops 101 to 110. Are provided with N or more flip-flops 201 to 210 that sample the bit data held by the second multi-phase clock generation means 2 as the clock input, so that the ratio N is increased by including redundant flip-flops. Even if it becomes, reliable serial parallel conversion can be performed.

  Although the present invention has been described with reference to the embodiment, it is needless to say that the present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the claims.

  INDUSTRIAL APPLICABILITY The present invention can be applied to a communication circuit, a communication method, and a serial / parallel conversion circuit that convert a serial signal into a parallel signal, and is particularly useful in a communication circuit between LSIs that requires higher design freedom and higher communication speed.

DESCRIPTION OF SYMBOLS 1 1st multiphase clock generation means 2 2nd multiphase clock generation means 3 Serial / parallel conversion means 4 Clock extraction means 5 Buffer circuit 6 Data alignment means

Claims (5)

A receiving circuit for receiving a serial signal transmitted from the transmitting circuit is provided,
The receiving circuit is
The ratio of the bit rate of the serial signal and the operation clock of the receiving circuit is N,
First multiphase clock generating means for generating at least N multiphase clocks that change every N cycles of the serial signal;
Second multi-phase clock generating means for generating at least N multi-phase clocks that change every N cycles of the serial signal;
The serial signal bit data is sequentially held using the output of the first multiphase clock generation means as a clock input, and the held bit data is sampled using the output of the second multiphase clock generation means as a clock input. It includes a serial-parallel conversion means for output as parallel signals, and,
The first multiphase clock generation means and the second multiphase clock generation means can change the number of multiphase clocks to be generated,
The serial-parallel converter can change the number of parallel signals to be output,
The first multi-phase clock generating means
N or more flip-flops connected in a loop and sequentially shifting,
A selector that changes the number of loop stages of the flip-flop,
A communication circuit that outputs the output of each flip-flop connected in a loop as a multiphase clock . The second multi-phase clock generating means is
N or more flip-flops connected in a loop and sequentially shifting,
A selector for changing the number of loop stages of the flip-flop;
A switch circuit that outputs N or more multi-phase clocks by using the outputs of some flip-flops connected in a loop;
The communication circuit according to claim 1, further comprising a, and N or more of a buffer circuit for buffering the output of the switching circuit. The serial / parallel conversion means comprises:
N or more flip-flops that sequentially hold the bit data of the serial signal using the output of the first multiphase clock generation means as a clock input;
The communication circuit according to these bit data flip-flop is held in claim 1 or 2 and a N or more flip-flops for sampling the clock input an output of said second multiphase clock generating means. The receiving side circuit that receives the serial signal transmitted from the transmitting side circuit
The ratio of the bit rate of the serial signal and the operation clock of the receiving circuit is N,
A first multiphase clock generation procedure for generating at least N multiphase clocks that change every N cycles of the serial signal;
A second multiphase clock generation procedure for generating at least N multiphase clocks that change every N cycles of the serial signal;
The output of the first multiphase clock generation procedure is used as a clock input to sequentially hold the bit data of the serial signal, and the held bit data is sampled using the output of the second multiphase clock generation procedure as a clock input. and a serial-parallel conversion procedure is output as parallel signals, execution,
The first multiphase clock generation procedure and the second multiphase clock generation procedure can change the number of multiphase clocks to be generated,
The serial-to-parallel conversion procedure can change the number of parallel signals to be output,
The first multiphase clock generation procedure includes:
N or more flip-flops connected in a loop and sequentially shifting,
And a selector that changes the number of loop stages of the flip-flop,
A communication method characterized by outputting the output of each flip-flop connected in a loop as a multiphase clock . The ratio of the bit rate of the serial signal and the operation clock of the circuit is N,
First multiphase clock generating means for generating at least N multiphase clocks that change every N cycles of the serial signal;
Second multi-phase clock generating means for generating at least N multi-phase clocks that change every N cycles of the serial signal;
The serial signal bit data is sequentially held using the output of the first multiphase clock generation means as a clock input, and the held bit data is sampled using the output of the second multiphase clock generation means as a clock input. It includes a serial-parallel conversion means for output as parallel signals, and,
The first multiphase clock generation means and the second multiphase clock generation means can change the number of multiphase clocks to be generated,
The serial-parallel converter can change the number of parallel signals to be output,
The first multi-phase clock generating means
N or more flip-flops connected in a loop and sequentially shifting,
A selector that changes the number of loop stages of the flip-flop,
Outputs the output of each flip-flop connected in a loop as a multi-phase clock
A serial-parallel conversion circuit characterized by that .

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