KR101206146B1 - Serializer and method of serializing - Google Patents

Abstract

Serial converter according to an embodiment of the present invention includes a data register (Data Register) for receiving parallel data; A clock generator for capturing a time point at which the parallel data having different clock frequencies are input through an external clock to generate an internal clock for the parallel data; A multiplexer (MUX) unit converting the parallel data into serial data; And a control signal generator configured to generate control signals according to a plurality of modes so that the multiplexer can process the parallel data.

Description

Serializers and Serializers {SERIALIZER AND METHOD OF SERIALIZING}

The following embodiments relate to a serial converter and a serial conversion method for converting parallel data into serial data with an independent external clock.

The serial converter receives N bits of parallel data and a parallel clock (f) to generate a serial clock having a value of N * f based on the parallel clock frequency (f) in an internal phase locked loop (PLL). The received parallel data is synchronized to the serial clock and converted into serial form.

For this purpose, the serial converter includes a phase locked loop inside, which includes the entire area of the serial converter. In addition, without a phase-locked loop, the serial converter does not generate a serial clock directly from the input parallel clock, requiring an external clock.

Because the external clock is independent of the history clock, it is difficult to capture when parallel data comes in, and because the external clock is a fixed value, a serial converter is required for each clock frequency to process parallel data with various clock frequencies. do.

As a result, the area occupied by the serial converter and the amount of power increase in proportion to the frequency types to be processed.

One embodiment of the present invention provides a serial converter and a serial conversion method capable of converting parallel data having various clock frequencies into serial data using only an external independent clock, not an internal phase locked loop.

In addition, an embodiment of the present invention is possible to serialize the parallel data having various clock frequency values by adjusting the multiplexing ratio inside the serial converter according to the clock frequency of the parallel data received, and can greatly reduce the area and power consumption. Provides a serial converter and a serial conversion method.

Serial converter according to an embodiment of the present invention includes a data register (Data Register) for receiving parallel data; A clock generator for capturing a time point at which the parallel data having different clock frequencies are input through an external clock to generate an internal clock for the parallel data; A multiplexer (MUX) unit converting the parallel data into serial data; And a control signal generator configured to generate control signals according to a plurality of modes so that the multiplexer can process the parallel data.

The external clock may have four clock frequencies of 1.5 GHz, each phase difference being a quarter period.

The clock generation unit may generate an internal clock for the parallel data by capturing a time point at which the parallel data is input based on the clock of the parallel data and the external clock independent of the clock of the parallel data.

The clock generator may delay a selection signal generated to capture a time point at which the parallel data is input according to the plurality of modes.

The multiplexer may adjust the final multiplexing ratio by using the internal clock and control signals according to the plurality of modes.

The multiplexer may include a first multiplexer having a multiplexing ratio of 20: 4; And a second multiplexer having a multiplexing ratio of 4: 1, wherein when the first multiplexer sequentially transmits the parallel data to the second multiplexer, the second multiplexer determines a final multiplexing ratio according to a clock frequency of the parallel data. By adjusting, the parallel data having the plurality of clock frequencies may be converted into serial data.

The control signal generator may include a plurality of flip-flop units, each of which includes a plurality of flip-flops, and whether to use the plurality of flip-flop units may be determined according to control signals according to the plurality of modes.

The plurality of flip-flop units may include a first flip-flop unit generating a 12-bit selection signal; A second flip-flop unit generating a 5-bit select signal; A third flip-flop unit generating a 10-bit select signal; And a fourth flip-flop unit generating a 5-bit selection signal, and outputting the selection signal according to the control signals according to the plurality of modes.

Serial conversion method according to an embodiment of the present invention comprises the steps of receiving parallel data; Generating an internal clock for the parallel data by capturing a time point at which the parallel data having different clock frequencies are input through an external clock; Generating a control signal according to a plurality of modes to process the parallel data; And converting parallel data into serial data according to the control signal.

The external clock may have four clock frequencies of 1.5 GHz, each phase difference being a quarter period.

The generating of the internal clock may include: acquiring a time point at which the parallel data is input based on a clock of the parallel data and an external clock independent of a clock of the parallel data; And generating an internal clock for the parallel data based on a time point at which the parallel data is input.

Generating the internal clock may include generating a selection signal to capture a time point at which the parallel data is input; And delaying the selection signal according to the plurality of modes.

The converting the parallel data into the serial data may include adjusting a final multiplexing ratio by using the internal clock and a control signal according to the plurality of modes.

The converting the parallel data into the serial data may include sequentially transmitting the parallel data to the second multiplexer having a 4: 1 multiplexing ratio by the first multiplexer having a multiplexing ratio of 20: 4; Adjusting, by the second multiplexer, a final multiplexing ratio according to the clock frequency of the parallel data; And converting parallel data having the plurality of clock frequencies into serial data according to the final multiplexing ratio.

The generating of the control signal may include determining whether to use a plurality of flip-flops included in each of the plurality of flip-flop units according to the control signal according to the plurality of modes.

The plurality of flip-flop units may include a first flip-flop unit generating a 12-bit selection signal; A second flip-flop unit generating a 5-bit select signal; A third flip-flop unit generating a 10-bit select signal; And a fourth flip-flop unit configured to generate a 5-bit selection signal, and outputting the selection signal according to a control signal according to the plurality of modes.

According to an embodiment of the present invention, by including a circuit for capturing a data input time point, parallel data having various clock frequencies may be converted into serial data using only an independent external clock having a fixed clock frequency.

Further, according to an embodiment of the present invention, by serializing the parallel data having various clock frequencies by adjusting the final multiplexing ratio in the serial converter according to the clock frequency of the parallel data input, the area and power of the serial converter are greatly reduced. Can be.

1 is a block diagram showing an overall input / output signal of a serial converter according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating the interior of the serial converter of FIG. 1 classified by function.
FIG. 3 is a diagram illustrating a circuit for capturing an input time point of parallel data included in a clock generator of FIG. 2.
4 is a diagram illustrating a multiplexer circuit for generating an internal clock CK [0: 3] using an external clock CK_PLL [0: 3] according to an embodiment of the present invention.
5 is a timing diagram illustrating an operation timing of a circuit for capturing an input time point of the parallel data of FIG. 3.
FIG. 6 is a diagram illustrating an internal structure of a 20: 1 MUX included in the multiplexer unit of FIG. 2.
FIG. 7 is a diagram illustrating a control signal generator of FIG. 2.
FIG. 8 is a timing diagram illustrating timing of outputting 6Gbps serial data in 20: 1MUX of FIG. 2.
FIG. 9 is a timing diagram illustrating timing of outputting 3Gbps serial data in 20: 1MUX of FIG. 2.
FIG. 10 is a timing diagram illustrating timing of outputting serial data of 1.5 Gbps in 20: 1MUX of FIG. 2.
FIG. 11 is a diagram illustrating a circuit for delaying a selection signal generated in a circuit for capturing an input time of parallel data of FIG. 3 for each mode.
FIG. 12 is a diagram illustrating a circuit for receiving an delayed selection signal SEL_D [0: 3] of FIG. 11 to generate an iTBC signal.
FIG. 13 is a diagram illustrating a data register of FIG. 2.
14 is a diagram illustrating an overall timing diagram of a serial converter in 6G mode according to an embodiment of the present invention.
15 is a diagram illustrating an overall timing diagram of a serial converter in 3G mode according to an embodiment of the present invention.
16 is a diagram illustrating an overall timing diagram of a serial converter in 1.5G mode according to an embodiment of the present invention.
17 is a flowchart illustrating a serial conversion method according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the embodiments. Also, like reference numerals in the drawings denote like elements.

1 is a block diagram showing an overall input / output signal of a serial converter according to an embodiment of the present invention.

FIG. 1 illustrates a serial converter 100 according to an embodiment of the present invention. The serial converter 100 includes 10 bits of parallel data DIN [0: 9], a clock for parallel data (TBC), and four phase shifts each having a quarter period. 1bit serial data (DOUT) is received by receiving control signals according to multiple modes that control the operation of the circuit to process 1.5Ghz external clock (CK_PLL [0: 3]) and data of different clock frequencies. Will print.

Here, the plurality of modes may be at least one of 6Gmode, 3Gmode, and 1.5Gmode.

The external clock CK_PLL [0: 3] is independent of the clock TBC for parallel data, making it difficult to capture when parallel data comes in. In addition, since the external clock has a fixed value, in order to process parallel data having various clock frequencies, serial conversion for converting parallel data into serial data is required for each clock frequency.

Therefore, in one embodiment of the present invention, by using only an independent external clock, parallel data having various clock frequencies can be converted into serial data by one serial converter.

The serial converter according to an embodiment of the present invention converts and transmits parallel data to serial data in order to simplify the transmission line and to increase the reliability of the data signal in order to provide high-speed communication between data transmission / reception interface circuits, in particular, different systems. Can be used for data transmission and reception interface circuits.

FIG. 2 is a block diagram illustrating the interior of the serial converter of FIG. 1 classified by function.

2, a serial converter 200 according to an embodiment of the present invention includes a data register unit 220, a clock generator unit 240, and a multiplexer unit 260. And a control signal generator 280.

The data register unit 220 receives parallel data having different clock frequencies.

The clock generator 240 captures a time point at which parallel data having different clock frequencies are input through the external clock CK_PLL [0: 3] to generate an internal clock for the parallel data.

The external clock may have four clock frequencies of 1.5 GHz, each phase difference being a quarter period.

A configuration of a circuit for capturing a time point at which parallel data included in the clock generator 240 is input will be described with reference to FIG. 3.

The clock generator 240 captures a time point at which parallel data is input based on an external clock CK_PLL [0: 3], which is independent of a clock for parallel data (TBC) and a clock for parallel data. An internal clock CK [0: 3] can be generated.

The clock generator 240 may delay the selection signal SEL generated according to a plurality of modes to capture a time point at which parallel data is input. Hereinafter, the selection signal may be used as the same meaning as the control signal according to the plurality of modes.

A circuit for delaying the selection signal generated by the circuit which captures the time point at which the parallel data is input for each mode will be described with reference to FIG. 11.

The multiplexer (MUX) unit 260 converts parallel data into serial data.

The multiplexer 260 may adjust the final multiplexing ratio by using an internal clock and control signals according to a plurality of modes.

The multiplexer unit 260 may include a first multiplexer having a multiplexing ratio of 20: 4 and a second multiplexer having a multiplexing ratio of 4: 1.

When the first multiplexer sequentially transmits parallel data to the second multiplexer, the multiplexer 260 adjusts the final multiplexing ratio according to the clock frequency of the parallel data to convert the parallel data having a plurality of clock frequencies into serial data. I can convert it.

The control signal generator 280 generates a control signal according to a plurality of modes so that the multiplexer 260 can process parallel data (convert to serial data).

FIG. 3 is a diagram illustrating a circuit 300 for capturing an input time point of parallel data included in a clock generator of FIG. 2.

The circuit 300 for capturing the input time of the parallel data uses the external clock CK_PLL [0: 3] for operating the serial converter to capture the time point at which the data comes in. As an initial value, all of the outputs of the latch 310 have a low value, and the clock TBC for parallel data is input in synchronization with the data DIN [0: 9]. A timing diagram showing the operation timing of the circuit 300 for capturing the input time of parallel data is shown in FIG. 5.

After the first falling edge of the parallel data clock TBC, the output of the flip-flop 330 goes low due to the rising edge of the immediately following external clock CK_PLL [0: 3].

Accordingly, node A becomes high, node B becomes low, node C becomes high, and the selection signal SEL for selecting the corresponding flip flop becomes high and the remaining selection signals remain low. This select signal SEL [0: 3] is internal to the serial converter by a multiplexer circuit which generates an internal clock CK [0: 3] using the external clock CK_PLL [0: 3] shown in FIG. It can be used to generate the clock CK [0: 3].

FIG. 5 is a timing diagram illustrating an operation timing of a circuit 300 for capturing an input time point of parallel data of FIG. 3.

Referring to FIG. 5, 600 MHz parallel between CK_PLL [1] and CK_PLL [2] among the external clocks CK_PLL [0: 3] having four 1.5 GHz clock frequencies, each phase difference being 1/4 period. It can be seen that the clock (TBC @ 600MHz) of the data has a falling edge, and thus the selection signal SEL [1] for selecting the corresponding flip flop becomes HIGH.

FIG. 6 is a diagram illustrating an internal structure of a 20: 1 MUX included in the multiplexer unit of FIG. 2.

FIG. 6 is an internal structure of a 20: 1 MUX 600 that converts input parallel data into serial data. When the parallel data are sequentially transmitted at 1.5 Gbps in a 20: 4 MUX 610, the last final 4: 1 MUX (630) is illustrated. ), The final multiplexing (MUX) ratio is adjusted according to the clock frequency of the parallel data, and the parallel data is exported as serial data by 1 bit.

Here, the final multiplexing (MUX) ratio adjustment method, as shown in Figure 6 the internal clock (CK [0: 3]) and the control signal according to the plurality of modes (6Gmode, 3Gmode, 1.5Gmode), respectively, by inputting these AND gates Use only the internal clock required. A timing diagram of the 20: 1 MUX 600 for each mode will be described with reference to FIGS. 8 to 10.

FIG. 7 is a diagram illustrating a control signal generator of FIG. 2.

FIG. 7 is a circuit of a control signal generator 700 for generating a signal for controlling a 20: 4 MUX 610.

The control signal generator 700 includes a plurality of flip-flop parts 710, 730, 750, and 770, each of which includes a plurality of flip-flops, and the plurality of flip-flop parts include a plurality of modes 6. Whether to use may be determined according to control signals according to Gbps mode, 3 Gbps mode, and 1.5 Gbbps mode).

That is, the control signal generator 700 uses all four flip-flop units 710, 730, 750, and 770 when operating in the 6 Gbps mode, and two flip-flop units in the 3 Gbps mode. Only 730 and 770 are used, and only one flip-flop unit 770 is used in the 1.5 Gbps mode.

Here, the first flip-flop unit 770 of the plurality of flip-flop units may generate a 12-bit select signal SEL0_DO, and the second flip-flop unit 750 may generate a 5-bit select signal SEL1_DO. have.

In addition, the third flip-flop unit 730 may generate a 10-bit selection signal SEL2_DO, and the fourth flip-flop unit 710 may generate a 5-bit selection signal SEL3_DO.

The control signal generator 700 may output a selection signal according to control signals according to a plurality of modes.

8 to 10 are timing diagrams illustrating timings of serial data output for each mode in the 20: 1 MUX of FIG. 2.

FIG. 8 illustrates timing of outputting 6Gbps serial data in 20: 1 MUX of FIG. 2 according to an embodiment of the present invention, and FIG. 9 illustrates timing of outputting 3Gbps serial data in 20: 1 MUX. Is a timing diagram showing the timing at which 1.5Gbps serial data is output at 20: 1 MUX.

FIG. 11 is a diagram illustrating a circuit for delaying a selection signal generated in a circuit 300 for capturing an input time of parallel data of FIG. 3 for each mode.

Referring to FIG. 11, the selection signals SEL [0: 3] generated by the circuit 300 for capturing the input time point of the parallel data are input to each D-flip flop, and input to each D-flip flop. The selection signal is output as the selection signal SEL_D [0: 3] delayed according to each mode (6Gbps, 3Gbps and 1.5Gbps modes).

FIG. 12 is a diagram illustrating a circuit for receiving an delayed selection signal SEL_D [0: 3] of FIG. 11 to generate an iTBC signal. The iTBC signal generated here may be applied as a clock signal of a D-flip flop included in the data register unit described with reference to FIG. 13.

Here, the circuit for generating the iTBC signal is an iTBC having a frequency of any one of 150MhZ and 300MHz by properly combining 5-divider and 2-divider according to any one of 1.5Gbps mode, 3Gbps mode, and 6Gbps mode. You can generate a signal.

That is, in the case of the 1.5Gbps mode, for example, a 5-divider and a 2-divider may be combined to form a 10 divider, thereby generating a signal having a frequency of 150 MHz.

FIG. 13 is a diagram illustrating a data register of FIG. 2.

Referring to FIG. 13, the data register unit 220 converts the input 10-bit parallel data DIN [0: 9] into D0 [0: 9] or D1 according to a plurality of modes (1.5 GMode, 3Mode, 6GMode). Can be output as [0: 9].

14 through 16 illustrate an overall timing diagram of a serial converter in each of a plurality of modes according to an embodiment of the present invention.

FIG. 14 shows the overall timing diagram of the serial converter in 6G mode, FIG. 15 in 3G mode, and FIG. 16 in 1.5G mode.

17 is a flowchart illustrating a serial conversion method according to an embodiment of the present invention. Referring to FIG. 17, after receiving a parallel data (1710), the serial converter captures a time point at which parallel data having different clock frequencies are input through an external clock to generate an internal clock for the parallel data (1720). .

At this time, the external clock may have four clock frequencies of 1.5 GHz, with each phase difference being a quarter period.

In order to generate the internal clock at 1720, the serial converter may capture a time point at which parallel data is input based on the clock of the parallel data and an external clock independent of the clock of the parallel data. The serial converter may then generate an internal clock for the parallel data based on the point in time at which the parallel data is input.

In addition, the serial converter may generate a selection signal to capture a time point at which parallel data is input at 1720, and then delay the selection signal according to a plurality of modes.

The serial converter generates 1730 control signals according to a plurality of modes so that the multiplexer can process parallel data, and then converts the parallel data into serial data according to the control signal (1740).

In 1730, the serial converter may determine whether to use a plurality of flip-flops included in each of the plurality of flip-flop units according to a control signal according to a plurality of modes.

Here, the plurality of flip-flop units may include a first flip-flop unit for generating a 12-bit selection signal, a second flip-flop unit for generating a 5-bit selection signal, a third flip-flop unit for generating a 10-bit selection signal, and It may include a fourth flip-flop unit for generating a bit selection signal.

In addition, at 1730, the serial converter may output a selection signal according to control signals according to a plurality of modes.

In 1740, the serial converter may adjust the final multiplexing ratio using an internal clock and control signals according to a plurality of modes.

Further, at 1740, the serial converter may sequentially transmit parallel data to a second multiplexer having a multiplexing ratio of 4: 1 by a first multiplexer having a multiplexing ratio of 20: 4. Thereafter, if the second multiplexer adjusts the final multiplexing ratio according to the clock frequency of the parallel data, the serial converter may convert parallel data having a plurality of clock frequencies into serial data according to the final multiplexing ratio.

The above-described methods may be embodied in the form of program instructions that can be executed by various computer means and recorded on a computer-readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the medium may be those specially designed and constructed for the present invention or may be available to those skilled in the art of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks. Magneto-optical media, and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

As described above, the present invention has been described by way of limited embodiments and drawings, but the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains various modifications and variations from such descriptions. This is possible.

Therefore, the scope of the present invention should not be construed as being limited to the embodiments described, but should be determined by equivalents to the appended claims, as well as the appended claims.

200: serial converter
220: data register
240: clock generator
260: multiplexer section
280: control signal generator

Claims (16)

A data register unit for receiving parallel data;
A clock generator for capturing a time point at which the parallel data having different clock frequencies are input through an external clock to generate an internal clock for the parallel data;
A multiplexer (MUX) unit converting the parallel data into serial data; And
A control signal generator for generating a control signal according to a plurality of modes so that the multiplexer can process the parallel data.
Including,
The clock generator
And delaying the selected signal generated according to the plurality of modes to capture a time point at which the parallel data is input. The method of claim 1,
The external clock
Serial converters with four 1.5 GHz clock frequencies each with a quarter-phase shift. The method of claim 1,
The clock generator
And generating an internal clock for the parallel data by capturing a time point at which the parallel data is input based on the clock of the parallel data and the external clock independent of the clock of the parallel data. delete A data register unit for receiving parallel data;
A clock generator for capturing a time point at which the parallel data having different clock frequencies are input through an external clock to generate an internal clock for the parallel data;
A multiplexer (MUX) unit converting the parallel data into serial data; And
A control signal generator for generating a control signal according to a plurality of modes so that the multiplexer can process the parallel data.
Including,
The multiplexer unit
And controlling a final multiplexing ratio using the internal clock and the control signal according to the plurality of modes. The method of claim 1,
The multiplexer unit
A first multiplexer having a multiplexing ratio of 20: 4; And
Second multiplexer with 4: 1 multiplexing ratio
Including,
When the first multiplexer sequentially transmits the parallel data to the second multiplexer, the second multiplexer converts parallel data having the plurality of clock frequencies into serial data by adjusting a final multiplexing ratio according to a clock frequency of the parallel data. To serial converter. The method of claim 1,
The control signal generator
A plurality of flip-flop portions each including a plurality of flip-flops,
The plurality of flip-flop portions
The serial converter determines whether to use according to the control signal according to the plurality of modes. The method of claim 7, wherein
The plurality of flip-flop parts
A first flip-flop unit configured to generate a 12-bit selection signal according to the control signal according to the plurality of modes;
A second flip-flop unit configured to generate a 5-bit selection signal according to the control signals according to the plurality of modes;
A third flip-flop unit configured to generate a 10-bit selection signal according to the control signal according to the plurality of modes; And
A fourth flip-flop unit configured to generate a 5-bit selection signal according to the control signals according to the plurality of modes
Serial converter comprising a. delete delete delete delete delete delete delete delete

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