JP5415229B2 - Frequency synthesizer - Google Patents

Description

  The present invention relates to a frequency synthesizer using a mixer.

  As this type of frequency synthesizer, a frequency synthesizer disclosed in Patent Document 1 below is known. The frequency synthesizer divides the output of the first VCO with a frequency divider, and the first PLL that outputs a frequency signal from the first VCO by matching the phase of the divided signal and the reference frequency signal, and the first PLL The frequency signal output from the PLL and the output of the second VCO are mixed by a mixer, one of the two frequency signals obtained by the mixer is selected, and the phases of the frequency signal and the addition / subtraction frequency signal are matched. The second PLL that outputs the frequency signal from the second VCO and the level of the signal applied to the first VCO and the level of the signal applied to the second VCO are compared, and the level difference between the two signals is greater than the set voltage. And a control circuit that applies a level signal corresponding to a signal applied to the first VCO to the input terminal of the second VCO during the period.

  This frequency synthesizer includes the first and second PLL circuits as described above, but the first PLL circuit having the frequency divider has a quick response and does not have the frequency divider. The second PLL has a slow response. Therefore, in this frequency synthesizer, when the output frequency is greatly changed (that is, when the response time is long), the control voltage applied to the first VCO provided in the first PLL having a fast response is changed to the second with a slow response. By adding to the second VCO provided in the PLL, the operating point of the second VCO is forcibly shifted to the vicinity of a desired frequency, thereby speeding up the overall response.

Japanese Examined Patent Publication No. 7-24380 (page 3, Fig. 1)

  However, the frequency synthesizer has the following problems to be solved. That is, in this frequency synthesizer, the level of each signal applied to the first VCO and the second VCO is compared, and a level signal corresponding to the signal applied to the first VCO is output during the period when the level difference between the signals is equal to or higher than the set voltage. A control circuit to be applied to the input terminal is configured using a plurality of electronic components (a plurality of constant current sources, a plurality of resistors, a plurality of diodes, and an FET). Therefore, this frequency synthesizer has a problem that such a complicated control circuit must be designed in consideration of the operations inside the two VCOs and the characteristics of each electronic component. In addition, since the control circuit generates a level signal itself applied to the VCO, the VCO is directly affected by noise generated in the control circuit and noise superimposed on the control circuit. There is also a problem that it is easy to get worse.

  The present invention has been made in view of such problems, and has as its main object to provide a frequency synthesizer that is easy to design and has good noise characteristics.

  In order to achieve the above object, a frequency synthesizer according to claim 1 includes a voltage-controlled oscillator that generates an output signal having a frequency corresponding to an input control voltage, and a low-frequency signal having an arbitrary frequency within a preset frequency range. A low-frequency signal generation unit that generates a high-frequency signal generation unit that generates a high-frequency signal having a set frequency, a mixer unit that mixes the output signal and the high-frequency signal and outputs the mixed signal, and the mixing signal A low-pass filter that selectively passes a difference frequency signal between the output signal and the high-frequency signal included; and inputs the output signal, the high-frequency signal, and the difference frequency signal, and the frequency of the output signal and the A signal processing unit that outputs a comparison signal based on a level relationship of the frequency of the high-frequency signal; the low-frequency signal; and A frequency synthesizer comprising: a phase comparison unit that outputs an error signal for each phase of a comparison signal; and a control voltage generation unit that generates the control voltage based on the error signal, wherein the signal processing unit includes: When the frequency of the high-frequency signal is newly set and the frequency of the output signal is lower than the frequency of the newly set high-frequency signal, the comparison signal to the phase comparison unit When the output signal frequency is equal to or higher than the frequency of the newly set high-frequency signal and the absolute frequency of the difference frequency signal is equal to or higher than the cutoff frequency of the low-pass filter section. A reference signal having a frequency higher than the frequency of the low frequency signal is output as the comparison signal to the phase comparison unit, and the frequency of the output signal is newly set. When the absolute frequency of the difference frequency signal is higher or lower than the cut-off frequency of the low-pass filter unit, the difference frequency signal is used as the comparison signal to the phase comparison unit. Output.

  The frequency synthesizer according to claim 2 is the frequency synthesizer according to claim 1, wherein the signal processing unit divides the high-frequency signal by M (M is an integer of 2 or more) and outputs a first divided signal. A first frequency divider, a second frequency divider that divides the output signal by (M + L) (L is an integer equal to or greater than 1) and outputs a second frequency-divided signal, and a frequency of the second frequency-divided signal A first frequency comparator that outputs a first detection signal when the frequency of the output signal is equal to or higher than the frequency of the first frequency-divided signal; When the two-frequency comparator, the difference frequency signal and the reference signal are input, and the first detection signal and the second detection signal are input, the reference signal is used as the comparison signal in the phase comparator. And input the first detection signal. When the second detection signal is not input, the difference frequency signal is output as the comparison signal to the phase comparison unit, and when the second detection signal is not input, the phase comparison unit A selection unit that stops the output of the comparison signal to the frequency, and when the frequency of the high-frequency signal is f and the cut-off frequency is fco, the numerical value M is the largest value (L × f / fco). It is specified to be a close integer.

  In the frequency synthesizer according to claim 1, when the frequency of the high frequency signal is newly set, the signal processing unit has a phase when the frequency of the output signal is lower than the newly set frequency of the high frequency signal. By stopping the output of the comparison signal to the comparison unit and thereby forcibly increasing the frequency of the output signal, the frequency synthesizer is shifted to the locked state. Also, when the frequency of the output signal is higher than the newly set frequency of the high frequency signal and the absolute frequency of the difference frequency signal is higher or lower than the cutoff frequency of the low-pass filter section, it is higher than the frequency of the low frequency signal. The frequency reference signal is output as a comparison signal to the phase comparison unit, thereby forcibly reducing the frequency of the output signal, thereby shifting the frequency synthesizer to the locked state. In addition, the signal processing unit determines that the difference frequency is higher when the frequency of the output signal is higher than the newly set frequency of the high frequency signal and the absolute frequency of the difference frequency signal is lower than the cutoff frequency of the low pass filter unit. The locked state is continued by outputting the signal as a comparison signal to the phase comparison unit.

  Therefore, according to this frequency synthesizer, unlike the conventional frequency synthesizer, as a circuit for shifting the frequency synthesizer to the lock state when the frequency of the high frequency signal is newly set, the operation inside the two VCOs and each Since it is not necessary to design and use a complicated control circuit in consideration of the characteristics of the electronic component, the design can be facilitated. In addition, the control voltage applied to the voltage control oscillator is not directly controlled, but the comparison signal input to the phase comparator is switched. As a result of avoiding the problem that the part directly receives, good noise characteristics can be realized.

  According to the frequency synthesizer of claim 2, the signal processing unit includes the first frequency divider, the second frequency divider, the first frequency comparator, the second frequency comparator, and the selection unit as described above. The number of divisions of the second divider is set to (M + L) with respect to the number of divisions M of the first divider, and both numerical values are taken into account in consideration of the cutoff frequency of the low-pass filter unit. By adopting a configuration that defines M and L, even when the cut-off frequency is changed in response to the change in the frequency of the low-frequency signal, the signal processing unit can be changed by changing at least one of the numerical values M and L. An appropriate comparison signal can be output to the phase comparison unit.

1 is a configuration diagram showing a configuration of a frequency synthesizer 1. FIG. It is a block diagram which shows the structure of the signal processing part 10 of FIG. It is a functional diagram which shows the function of the selection part 27 in FIG. The cutoff frequency fco of the low-pass filter section 7 in the locked state, the difference frequency component (fdi = | fout−f2 |) of the difference frequency signal Sdi, the frequency f3 of the second reference signal S3, the frequency f2 of the high frequency signal S2, and the output signal It is explanatory drawing for demonstrating the height relationship of the frequency fout of Sout. When the frequency f2 of the high-frequency signal S2 is lowered, the cut-off frequency fco of the low-pass filter unit 7, the difference frequency component (fdi = | fout−f2 |) of the difference frequency signal Sdi, and the frequency f3 of the second reference signal S3 FIG. 8 is an explanatory diagram for explaining a transition state of the frequency f2 of the high-frequency signal S2 and the frequency fout of the output signal Sout. When the frequency f2 of the high-frequency signal S2 is increased, the cut-off frequency fco of the low-pass filter unit 7, the difference frequency component (fdi = | fout−f2 |) of the difference frequency signal Sdi, the frequency f2 and the output of the high-frequency signal S2 It is explanatory drawing for demonstrating the transition state of the frequency fout of the signal Sout.

  Hereinafter, embodiments of the frequency synthesizer will be described with reference to the accompanying drawings.

  First, the configuration of the frequency synthesizer 1 will be described with reference to the drawings.

  A frequency synthesizer 1 shown in FIG. 1 includes a reference signal generation unit 2, a low frequency signal generation unit 3, a high frequency signal generation unit 4, a voltage controlled oscillation unit (hereinafter also referred to as “VCO”) 5, a mixer unit 6, and a low-pass filter. Unit 7, phase comparison unit 8, control voltage generation unit (hereinafter also referred to as “loop filter”) 9, and signal processing unit 10, which is configured as a PLL (Phase Locked Loop) circuit and has a predetermined frequency range The output signal Sout having an arbitrary frequency fout can be output with a predetermined frequency resolution (frequency interval).

  As an example, the reference signal generation unit 2 includes a crystal oscillator that outputs a clock signal having a constant frequency, and a frequency divider (none of which is shown) that divides the clock signal in synchronization with the clock signal. A first reference signal Sr having a predetermined frequency fr that is a divided signal of the clock signal and a second reference signal (reference signal) S3 having a predetermined frequency f3 that is a divided signal of the clock signal are generated. Output. In this case, the frequency f3 of the second reference signal S3 exceeds the upper limit frequency f1max of the setting range (upper limit frequency f1max, lower limit frequency f1min) for the frequency f1 of the low frequency signal S1 output from the low frequency signal generator 3. It is stipulated in.

  As an example, the low-frequency signal generation unit 3 includes a DDS (Direct Digital Synthesizer), and generates a low-frequency signal S1 having an arbitrary frequency f1 set within a setting range (upper limit frequency f1max, lower limit frequency f1min). Output. As an example, the high-frequency signal generation unit 4 is configured by a PLL (Phase Locked Loop) circuit in which a frequency divider is interposed in a loop. The high-frequency signal generator 4 is configured to change the frequency f2 of the high-frequency signal S2 to be output (an example of the frequency f of the high-frequency signal) by performing frequency division setting on the frequency divider.

  The VCO 5 generates an output signal Sout having a frequency fout in accordance with the input control voltage Vc (increases as the control voltage Vc increases and decreases (eg, proportional) as the control voltage Vc decreases). The mixer unit 6 receives and mixes the output signal Sout and the high frequency signal S2, and outputs a mixing signal Smix. In this case, the mixing signal Smix includes the difference frequency signal Sdi composed of the difference frequency components (fdi = | fout−f2 |) of the frequencies fout and f2 of the output signal Sout and the high frequency signal S2, and the frequencies fout and f2. And a sum frequency signal composed of sum frequency components (fsu = fout + f2).

  The low-pass filter unit 7 is composed of a low-pass filter having a cutoff frequency fco. This cut-off frequency fco exceeds the difference frequency component (fdi = | fout−f2 |) included in the mixing signal Smix that is output when the frequency synthesizer 1 configured by the PLL circuit is in the frequency locked state. It is defined to be less than the sum frequency component (fsu = fout + f2). With this configuration, the low-pass filter unit 7 selectively allows the difference frequency signal Sdi composed of the difference frequency component of the difference frequency component and the sum frequency component included in the mixing signal Smix to pass through. As will be described later, when the frequency synthesizer 1 is in the locked state, the frequency (fout−f2) is equal to the frequency f1. Therefore, when the frequency f1 is changed, the cut-off frequency fco needs to be changed corresponding to the changed frequency f1 so that the relationship of fco> f1 (= fout−f2) is established. For this reason, the low-pass filter unit 7 of this example is configured to be able to change the cutoff frequency fco.

  The signal processing unit 10 receives the output signal Sout, the high frequency signal S2, the second reference signal S3, and the difference frequency signal Sdi, and compares them based on the level relationship between the frequency fout of the output signal Sout and the frequency f2 of the high frequency signal S2. The signal S4 is output. In this example, when the frequency f2 of the high-frequency signal S2 is newly set, the signal processing unit 10 has the frequency fout of the output signal Sout that is equal to or higher than the newly set frequency f2 of the high-frequency signal S2 and the difference frequency signal. When the absolute frequency of Sdi (fdi = | fout−f2 |) is higher or lower than the cut-off frequency fco of the low-pass filter unit 7 (hereinafter also referred to as “first height relationship”), the frequency of the low-frequency signal S1 The second reference signal S3 having a frequency f3 higher than f1 (in this example, the frequency f3 is a constant frequency as an example) is output to the phase comparator 8 as a comparison signal S4. In addition, the signal processing unit 10 has a frequency fout of the output signal Sout that is not less than the newly set frequency f2 of the high-frequency signal S2, and the absolute frequency (| fout−f2 |) of the difference frequency signal Sdi is the low-pass filter unit 7. Has a function of outputting the difference frequency signal Sdi as the comparison signal S4 to the phase comparator 8 when the relationship is lower than the cut-off frequency fco (hereinafter also referred to as “second height relationship”). Further, the signal processing unit 10 performs phase comparison when the frequency fout of the output signal Sout is lower than the newly set frequency f2 of the high-frequency signal S2 (hereinafter also referred to as “third height relationship”). It has a function of stopping the output of the comparison signal S4 to the unit 8.

  In order to realize these functions with a simple configuration, the signal processing unit 10 specifically includes four frequency dividers 21, 22, 23, 24, and two frequency phase comparators 25 as shown in FIG. , 26 and a selection unit 27. In this case, the frequency divider (first frequency divider) 21 divides the input high-frequency signal S2 by M (M is an integer equal to or larger than 2, and the same applies hereinafter) to obtain a frequency-divided signal (first frequency-divided signal). ) Output as S21 (frequency f21 = f2 / M). The frequency divider (second frequency divider) 22 divides the input output signal Sout by (M + L) and outputs it as a frequency-divided signal (second frequency-divided signal) S22 (frequency f22 = fout / (M + L)). To do. L is an integer of 1 or more.

  The frequency divider 23 divides the input high-frequency signal S2 by N (N is an integer equal to or greater than 1. The same applies hereinafter), and outputs the result as a frequency-divided signal S23 (frequency f23 = f2 / N). The frequency divider 24 divides the input output signal Sout by N and outputs it as a divided signal S24 (frequency f24 = fout / N). Here, when N = 1, each of the frequency dividers 23 and 24 outputs the input signal as it is without frequency division.

  The frequency phase comparator (first frequency comparator) 25 receives the frequency-divided signals S21 and S22 output from the frequency dividers 21 and 22, and compares both the frequencies f21 and f22. A detection signal (first detection signal) Sa is output when f21 or more. The frequency phase comparator (second frequency comparator) 26 receives the frequency-divided signals S23 and S24 output from the frequency dividers 23 and 24 and compares both the frequencies f23 and f24. A detection signal (second detection signal) Sb is output when f23 or more.

  The selection unit 27 includes a switch matrix circuit (not shown) using an analog switch as an example. Further, as shown in FIG. 2, the selection unit 27 inputs the difference frequency signal Sdi, the second reference signal S3, and the detection signals Sa and Sb, and a switch matrix according to the input state of the detection signals Sa and Sb. By performing switching control of the circuit, a comparison signal S4 is output. Specifically, as shown in FIG. 3, when the detection signal Sa and the detection signal Sb are input, the selection unit 27 outputs the second reference signal S3 to the phase comparison unit 8 as a comparison signal S4. Further, when the detection signal Sa is not input (the detection signal Sa is not input) and the detection signal Sb is input, the selection unit 27 outputs the difference frequency signal Sdi as the comparison signal S4 to the phase comparison unit. 8 is output. Further, when the detection signal Sb is not input (when the detection signal Sb is not input), the selection unit 27 performs comparison with the phase comparison unit 8 regardless of whether the detection signal Sa is input or not. The output of the service signal S4 is stopped. Here, stopping the output of the comparison signal S4 means outputting a low level voltage in the second reference signal S3 and the difference frequency signal Sdi.

  Thus, in this specific circuit configuration, the output states of the detection signals Sa and Sb generated by the four frequency dividers 21 to 24 and the two frequency phase comparators 25 and 26 of the signal processing unit 10 are as follows. The first elevation relationship, the second elevation relationship, and the third elevation relationship described above are defined. In this case, among the conditions defining the first height relationship, the second height relationship, and the third height relationship, the relationship between the frequency fout of the output signal Sout and the frequency f2 of the high frequency signal S2 is as follows. Directly shown in output state.

  On the other hand, regarding the relationship between the absolute frequency (| fout−f2 |) of the difference frequency signal Sdi and the cutoff frequency fco of the low-pass filter unit 7, which is another condition that defines the first height relationship and the second height relationship. Is shown by the output state of the detection signal Sa. Specifically, when this frequency synthesizer 1 configured by a PLL circuit is in a locked state, it is configured by a difference frequency component (fdi = | fout−f2 |) included in the mixing signal Smix output from the mixer unit 6. The difference frequency signal Sdi passing through the low-pass filter unit 7 is output to the signal processing unit 10, and the signal processing unit 10 outputs the difference frequency signal Sdi to the phase comparison unit 8. This state needs to be a state in which the detection signal Sa is not output to the selection unit 27 in the signal processing unit 10 (that is, a state where the frequency f22 is less than the frequency f21). In the locked state, the frequency fout is higher than the frequency f2 by the frequency f1 of the low frequency signal S1, but the frequency divider 22 is L times (M + L) times higher than the frequency divider 21. The output signal Sout (frequency fout) is divided to output a divided signal S22. For this reason, by appropriately setting the numerical values M and L, the frequency divider 22 divides the frequency f22 (= fout / (M + L)) of the frequency-divided signal S22 M times by the frequency divider S21 (frequency f2). The frequency division signal S21 to be output can be set lower than the frequency f21 (= f2 / M). As a result, the detection signal Sa is not output from the frequency phase comparator 25.

  On the other hand, the frequency division setting for the high-frequency signal generator 4 is changed in the locked state, and the frequency f2 of the output high-frequency signal S2 is set to a lower frequency. As a result, the difference frequency signal Sdi included in the mixing signal Smix is set. When the absolute frequency (| fout−f2 |) of the signal becomes equal to or higher than the cutoff frequency fco of the low-pass filter unit 7, the second reference signal S3 is used for comparison from the signal processing unit 10 to the phase comparison unit 8. The signal S4 needs to be output to the phase comparison unit 8. To this end, the signal processing unit 10 is in a state where the detection signal Sa is output to the selection unit 27 (that is, the state where the frequency f22 is equal to or higher than the frequency f21). There is a need. Also in this state, the numerical values M and L are appropriately set, so that the frequency divider 21 has M times less than the frequency divider 22 (M + L). By setting the frequency f2 of the high-frequency signal S2 divided by 21 to a lower frequency, the frequency f21 (= f2 / M) of the divided signal S21 is changed to the frequency f22 (= fout / () of the divided signal S22. M + L)) or less, and as a result, a state in which the detection signal Sa is output from the frequency phase comparator 25 can be obtained.

Specifically, the procedure for setting the numerical values M and L will be described. First, as described above, when the frequency synthesizer 1 is in the locked state, the difference frequency signal Sdi composed of the difference frequency component (fdi = | fout−f2 |) included in the mixing signal Smix is the low-pass filter unit 7. And is output to the signal processing unit 10 and further output from the signal processing unit 10 to the phase comparison unit 8. That is, it is necessary that the frequency (fout−f2) is less than the cutoff frequency fco and the frequency phase comparator 25 does not output the detection signal Sa. In the locked state, the frequency fout is higher than the frequency f2 by the frequency f1 of the low frequency signal S1. That is, the frequency (fout−f2) is equal to the frequency f1. Therefore, the following formula (1) is established between the cut-off frequency fco and the frequency f1 of the low-frequency signal S1.
fco> f1 (1)

Secondly, as described above, the condition that the frequency phase comparator 25 should start outputting the detection signal Sa to the selection unit 27 is that the absolute frequency (| fout−f2 |) of the difference frequency signal Sdi is low. The condition is when the cutoff frequency fco of the filter unit 7 is reached, that is, when the following equation (2) is satisfied. Further, the frequency phase comparator 25 is configured when the frequency f22 (= fout / (M + L)) of the frequency-divided signal S22 matches the frequency f21 (= f2 / M) of the frequency-divided signal S21 (the following equation (3) holds). Output of the detection signal Sa is started.
fout−f2 = fco (2)
fout / (M + L) = f2 / M (3)
Moreover, the following formula (4) is calculated by modifying the above formula (3),
fout−f2 = L / M × f2 (4)
Based on this equation (4) and the above equation (2), the following equation (5) is calculated.
fco = L × f2 / M (5)

  Thirdly, when the frequency f1 of the low frequency signal S1 is set, the cutoff frequency fco is defined to be a frequency higher than the frequency f1 from the above equation (1). Further, since the frequency fout of the output signal Sout is an addition value of the frequency f1 of the low frequency signal S1 and the frequency f2 of the high frequency signal S2, the frequency f2 of the high frequency signal S2 is defined based on the frequency fout and the frequency f1. Is done. Further, since the frequency f2 of the high-frequency signal S2 and the frequency fout of the output signal Sout are extremely high compared to the cutoff frequency fco and the frequency f1 of the low-frequency signal S1, the numerical value L is significantly higher than the numerical value M. Small number. For this reason, the cut-off frequency fco, the frequency f2 of the high-frequency signal S2 and the numerical value L (generally, a numerical value of one-tenths of the numerical value M. As an example, 1 such as 1, 2, 3,. The number M and L are set by defining the number of digits) and substituting it into the above equation (5) and calculating the numerical value M that is the closest integer to the value (L × f2 / fco). .

  The phase comparison unit 8 is configured by a logic circuit as an example, and inputs the low frequency signal S1 of the frequency f1 output from the low frequency signal generation unit 3 and the comparison signal S4 output from the signal processing unit 10, A phase difference between the two signals S1 and S4 is detected, and a pulse signal having a duty ratio (a ratio obtained by dividing the pulse width by the pulse period) according to the detected phase difference is output as the error signal Ser. Specifically, the phase comparison unit 8 increases the duty ratio of the error signal Ser when the phase of the comparison signal S4 is delayed with respect to the low frequency signal S1, while comparing with the low frequency signal S1. When the phase of the signal S4 is advanced, the duty ratio of the error signal Ser is reduced. Further, in the phase comparison unit 8, when the comparison signal S4 is not input in the input state of the low frequency signal S1, the phase of the comparison signal S4 is greatly delayed with respect to the phase of the low frequency signal S1. By increasing the duty ratio of the error signal Ser, an error signal Ser having a high duty ratio is output.

  The loop filter 9 is configured by a low-pass filter as an example, and generates and outputs a control voltage Vc as a DC voltage by smoothing the input error signal Ser. With this configuration, the control voltage Vc output from the loop filter 9 increases when the phase of the comparison signal S4 is delayed with respect to the low frequency signal S1, and is compared with the low frequency signal S1. When the phase of the service signal S4 is advanced, the voltage is lowered.

  Next, the operation of the frequency synthesizer 1 will be described. As an example, the high-frequency signal generation unit 4 has a resolution of 12.5 MHz within the frequency range of 800 MHz to 2.1 GHz based on the first reference signal Sr having the frequency fr output from the reference signal generation unit 2. It is assumed that a high frequency signal S2 having a frequency f2 can be output. In addition, the low frequency signal generation unit 3 is based on the first reference signal Sr having the frequency fr output from the reference signal generation unit 2 and has a low frequency f1 with a resolution of 0.1 Hz within a frequency range of 25 MHz to 100 MHz. It is assumed that the frequency signal S1 can be output, so that the frequency synthesizer 1 can output the output signal Sout having the frequency fout with a resolution of 0.1 Hz within the frequency range of 825 MHz to 2.1 GHz. .

  In this configuration, as an example, the frequency f1 of the low frequency signal S1 output from the low frequency signal generation unit 3 is set to 25 MHz, and the frequency f2 of the high frequency signal S2 output from the high frequency signal generation unit 4 is 975 MHz. An example in which the frequency synthesizer 1 is operated in a state of outputting an output signal Sout having a frequency fout (= 1 GHz) in the initial state will be described. Since the frequency range of the low frequency signal generation unit 3 is 25 MHz to 100 MHz and the frequency range of the high frequency signal generation unit 4 is 800 MHz to 2.1 GHz, the cutoff frequency fco of the low pass filter unit 7 is Although the frequency can be set to any frequency that is equal to or higher than the actually set frequency f1 (25 MHz as described above) and less than 800 MHz, the difference frequency signal Sdi output from the low-pass filter unit 7 is used. Since it is preferable not to include unnecessary frequency components as much as possible, the cutoff frequency fco is set to a frequency close to the frequency f1, for example, 50 MHz.

Therefore, when the frequency f2 is 975 MHz, the cutoff frequency fco is 50 MHz, the numerical value L is “2”, and the numerical value M is obtained based on the above (L × f2 / fco), the numerical value M is expressed as follows: A numerical value “39” is calculated.
M≈2 × 975/50 = 39

  In the operating state of the frequency synthesizer 1, the reference signal generator 2 generates and outputs a first reference signal Sr having a frequency fr, and generates and outputs a second reference signal S3 having a frequency f3. The frequency f3 of the second reference signal S3 is a setting range (the upper limit frequency f1max (= 100 MHz), the lower limit frequency f1min (= 25 MHz)) for the frequency f1 of the low frequency signal S1 output from the low frequency signal generation unit 3. Is defined as a value exceeding the upper limit frequency f1max (= 100 MHz) (200 MHz as an example).

  In this case, when the frequency synthesizer 1 configured in the PLL circuit is operating in the locked state, as shown in FIG. 1, the VCO 5 outputs the output signal Sout of the frequency fout (= 1 GHz), and the mixer unit 6 The mixing signal Smix is output by mixing the output signal Sout and the high-frequency signal S2 (frequency f2 is 975 MHz) output from the high-frequency signal generation unit 4. In this case, the mixing signal Smix includes a difference frequency signal Sdi composed of difference frequency components (fdi = | fout−f2 | = 25 MHz) of the frequencies fout and f2 of the output signal Sout and the high-frequency signal S2, and the frequencies fout, and a sum frequency signal composed of a sum frequency component of f2 (fsu = fout + f2 = 1975 MHz).

  Since the cut-off frequency fco is regulated to 50 MHz, the low-pass filter unit 7 inputs the mixing signal Smix, and the difference frequency signal Sdi of the difference frequency signal Sdi and the sum frequency signal constituting the mixing signal Smix. Only output.

  In the signal processing unit 10, as shown in FIG. 2, the frequency divider 21 frequency-divides the high-frequency signal S2 by M and outputs a frequency-divided signal S21 having a frequency f21, and the frequency divider 22 outputs the output signal Sout to (M + L). The frequency is divided to output a frequency divided signal S22, and the frequency divider 23 divides the high frequency signal S2 by N and outputs the frequency f23 frequency divided signal S23, and the frequency divider 24 outputs the output signal Sout to N. Frequency division is performed to output a frequency division signal S24 having a frequency f24.

  The frequency phase comparator 25 compares the frequencies f21 and f22 of the frequency-divided signals S21 and S22, and outputs the detection signal Sa when the frequency f22 is equal to or higher than the frequency f21, and when the frequency f22 is lower than the frequency f21. An operation for stopping the output of the detection signal Sa is executed. In this example, as described above, since M = 39 and L = 2, the frequency f21 of the frequency-divided signal S21 output from the frequency divider 21 is 975 MHz / 39 = 25 MHz, and the frequency divider The frequency f22 of the frequency-divided signal S22 output from 22 is 1 GHz / (39 + 2) ≈24.4 MHz. Accordingly, since the frequency f22 is less than the frequency f21, the frequency phase comparator 25 stops outputting the detection signal Sa.

  On the other hand, the frequency phase comparator 26 compares the frequencies f23 and f24 of the frequency-divided signals S23 and S24, and outputs the detection signal Sb when the frequency f24 is equal to or higher than the frequency f23, and when the frequency f24 is lower than the frequency f23. An operation for stopping the output of the detection signal Sb is executed. When the frequency synthesizer 1 is in the locked state, the frequency fout of the output signal Sout is always higher than the frequency f2 of the high-frequency signal S2 by the frequency S1 of the low-frequency signal S1. In other words, the frequency-divided signal S24 obtained by dividing the output signal Sout between the frequency-divided signals S23 and S24 output from the frequency dividers 23 and 24, which are defined to have the same frequency division number N, The frequency is always higher than the frequency-divided signal S23 obtained by dividing the high-frequency signal S2. Therefore, the frequency phase comparator 26 outputs the detection signal Sb.

  Therefore, since the detection signal Sa is not input (not input) and the detection signal Sb is input to the selection unit 27, the selection unit 27 uses the difference frequency signal Sdi for comparison as shown in FIG. The signal S4 is output to the phase comparison unit 8. As a result, the VCO 5, the mixer unit 6, the low-pass filter unit 7, the signal processing unit 10, the phase comparison unit 8 and the loop filter 9 are configured in a closed loop state, and the frequency synthesizer 1 configured in the PLL circuit maintains the locked state. However, the operation is continued. In this locked state, the frequency fout of the output signal Sout, the frequency f2 of the high-frequency signal S2, the cut-off frequency fco, the absolute frequency (| fout−f2 |) of the difference frequency signal Sdi, and the level f3 of the second reference signal S3. Is in the state shown in FIG.

  Next, in the locked state, as shown in FIG. 5, the frequency division setting for the high-frequency signal generation unit 4 is changed, and the frequency f2 of the output high-frequency signal S2 is changed from the frequency A (975 MHz) to the frequency B (937. 5 MHz (= 975-12.5 × 3)), thereby the absolute frequency (| fout−f2 | = 62.5 MHz (= 1 GHz−937.5 MHz) of the difference frequency signal Sdi is reduced to the low-pass filter unit. 7, when the difference frequency signal Sdi is not output from the low-pass filter unit 7 to the signal processing unit 10, that is, the VCO 5, the mixer unit 6, the low-pass filter unit 7, Since the processing unit 10, the phase comparison unit 8, and the loop filter 9 are not configured in the closed loop state, the PLL circuit is not configured.

  In this state, in the signal processing unit 10, the frequency divider 21 divides the high-frequency signal S2 (frequency f2 (= 937.5 MHz)) by M (= 39) and the frequency-divided signal of frequency f21 (≈24.0 MHz). S21 is output, and the frequency divider 22 divides the output signal Sout (frequency fout (= 1 GHz)) by (39 + 2) and outputs a frequency-divided signal S22 having a frequency f22 (≈24.4 MHz). Thereby, since the frequency f22 of the frequency-divided signal S22 becomes equal to or higher than the frequency f21 of the frequency-divided signal S21, the frequency phase comparator 25 compares the frequencies f21 and f22 of both the frequency-divided signals S21 and S22 and detects the detection signal Sa. Starts output.

  Further, since the frequency fout of the output signal Sout is higher than the frequency f2 of the high-frequency signal S2, the frequency f24 of the frequency-divided signal S24 output from the frequency divider 24 is the frequency of the frequency-divided signal S23 output from the frequency divider 23. The state is higher than f23. For this reason, the frequency phase comparator 26 compares the frequencies f23 and f24 of the divided signals S23 and S24 and outputs the detection signal Sb.

  Accordingly, since the detection signal Sa and the detection signal Sb are input to the selection unit 27, the selection unit 27 performs phase comparison using the second reference signal S3 having the frequency f3 as a comparison signal S4 as illustrated in FIG. Begin output to part 8. Since the frequency f3 of the second reference signal S3 is defined to be a value that exceeds the upper limit frequency f1max of the low frequency signal S1 output from the low frequency signal generation unit 3, the phase comparison unit 8 is provided between the signals S1 and S4. And a pulse signal having a duty ratio corresponding to the detected phase difference is output as an error signal Ser. Specifically, since the phase of the comparison signal S4 is advanced with respect to the low-frequency signal S1, the phase comparison unit 8 outputs the error signal Ser with a reduced duty ratio compared to the locked state. To do.

  The loop filter 9 generates a control voltage Vc based on the error signal Ser and outputs the control voltage Vc to the VCO 5. In this case, the phase of the comparison signal S4 is advanced with respect to the low frequency signal S1, so that the loop filter 9 is in the locked state. A control voltage Vc having a reduced voltage as compared with the above is output. The VCO 5 receives this control voltage Vc and reduces the frequency fout of the output signal Sout. As described above, in a state where the second reference signal S3 is output from the signal processing unit 10 as the comparison signal S4, the phase comparison unit 8 and the loop filter 9 execute open loop control on the VCO 5, and the VCO 5 The frequency fout of the output signal Sout to be output is forcibly reduced.

  As a result, as shown in FIG. 5, the absolute frequency (| fout− of the difference frequency signal Sdi that once exceeds the cutoff frequency fco (50 MHz) of the low-pass filter unit 7 and reaches the frequency C (62.5 MHz). f2 |) also decreases as the frequency fout of the output signal Sout decreases, reaches the cutoff frequency fco in a short time, and further decreases.

  In this state, the low-pass filter unit 7 resumes the output of the difference frequency signal Sdi. In the signal processing unit 10, the frequency fout of the output signal Sout decreases to about 984.5 MHz (the absolute frequency | fout−f2 | of the difference frequency signal Sdi becomes 47 MHz (= 984.5 MHz−937.5 MHz). The frequency f21 (24.04 MHz (= 937.5 / 39)) of the frequency-divided signal S21 output from the frequency divider 21 at the time). f22 (24.01 MHz (= 984.5 / 41)) is lower. Thereby, the frequency phase comparator 25 stops the output of the detection signal Sa. On the other hand, in the frequency phase comparator 26, the frequency fout of the output signal Sout is higher than the frequency f2 of the high-frequency signal S2, so that the frequency f24 of the divided signal S24 is higher than the frequency f23 of the divided signal S23. Therefore, the detection signal Sb is output.

  Accordingly, since the detection signal Sa is not input and the detection signal Sb is input to the selection unit 27, the selection unit 27 is replaced with the second reference signal S3 as shown in FIG. The output of the difference frequency signal Sdi output from the low-pass filter unit 7 is started. Accordingly, since the VCO 5 is shifted from the open loop control state to the closed loop control state (lock state), the frequency synthesizer 1 operates as a PLL circuit, and the absolute frequency | fout−f2 | of the difference frequency signal Sdi is low. The frequency fout of the output signal Sout is lowered until the frequency f1 (25 MHz) of the low-frequency signal S1 output from the frequency signal generator 3 is reached. As a result, the frequency synthesizer 1 outputs an output signal Sout having a frequency fout of 962.5 MHz (= 937.5 + 25).

  Further, when the frequency synthesizer 1 operates in the locked state and the VCO 5 outputs the output signal Sout having the frequency fout (= 1 GHz), the frequency division setting for the high-frequency signal generator 4 is changed and output. The frequency f2 of the high-frequency signal S2 exceeds the frequency fout of the output signal Sout, for example, as shown in FIG. 6, the frequency f2 of the output high-frequency signal S2 is changed from the frequency A (975 MHz) to the frequency D (for example, 1025 MHz (= When raised to 975 + 12.5 × 4)), the frequency fout of the output signal Sout becomes less than the frequency f2 of the high-frequency signal S2. In this case, since the frequency f2 of the high-frequency signal S2 is higher than the frequency fout of the output signal Sout in the signal processing unit 10, the frequency divider 23 is higher than the frequency f24 of the frequency-divided signal S24 output from the frequency divider 24. The frequency f23 of the frequency-divided signal S23 output from is higher. For this reason, the frequency phase comparator 26 compares the frequencies f23 and f24 of the divided signals S23 and S24 and stops outputting the detection signal Sb.

  As a result, the selection unit 27 is in a state in which the detection signal Sb is not input. Therefore, as shown in FIG. 3, the selection unit 27 is independent of the input state of the detection signal Sa (that is, the absolute value of the difference frequency signal Sdi). The output of the comparison signal S4 to the phase comparator 8 is stopped regardless of whether the frequency | fout−f2 | exceeds the cutoff frequency fco). In this case, the phase comparison unit 8 increases the duty ratio of the error signal Ser compared to the locked state because the phase of the comparison signal S4 is significantly delayed from the phase of the low frequency signal S1. As a result, an error signal Ser having a high duty ratio is output.

  The loop filter 9 generates a control voltage Vc based on the error signal Ser and outputs it to the VCO 5. In this case, since the duty ratio of the error signal Ser is high, the loop filter 9 is compared with the lock state. The control voltage Vc with the increased voltage is output. The VCO 5 receives this control voltage Vc and increases the frequency fout of the output signal Sout. As described above, in a state where the signal processing unit 10 stops outputting the comparison signal S4, the phase comparison unit 8 and the loop filter 9 execute open-loop control on the VCO 5, and the output output from the VCO 5 The frequency fout of the signal Sout is forcibly increased.

  Thereafter, the frequency fout of the output signal Sout reaches the frequency f2 (1025 MHz) of the high-frequency signal S2. In this case, in the signal processing unit 10, the frequency phase comparator 26 resumes outputting the detection signal Sb. On the other hand, since the frequency f22 of the frequency division signal S22 output from the frequency divider 22 is lower than the frequency f21 of the frequency division signal S21 output from the frequency divider 21, the frequency phase comparator 25 detects the frequency f. The output of the signal Sa is stopped.

  Accordingly, since the detection signal Sa is not input and the detection signal Sb is input to the selection unit 27, the selection unit 27 is replaced with the second reference signal S3 as shown in FIG. The output of the difference frequency signal Sdi output from the low-pass filter unit 7 is started. As a result, the VCO 5 shifts from the open-loop control state to the closed-loop control state (locked state). Thereafter, the frequency synthesizer 1 operates as a PLL circuit, and as shown in FIG. Until the frequency | fout−f2 | becomes the frequency f1 (25 MHz) of the low-frequency signal S1, that is, the frequency fout of the output signal Sout is higher by 25 MHz (frequency f1) than the frequency f2 (1025 MHz) of the high-frequency signal S2. Raise to. Thus, the frequency synthesizer 1 outputs an output signal Sout having a frequency fout of 1050 MHz (= 1025 + 25).

  As described above, in the frequency synthesizer 1, when the frequency f2 of the high-frequency signal S2 is newly set, the signal processing unit 10 uses the frequency f2 of the high-frequency signal S2 in which the frequency fout of the output signal Sout is newly set. In the case of a low and high relationship, the output of the comparison signal S4 to the phase comparison unit 8 is stopped, thereby forcibly increasing the frequency fout of the output signal Sout, thereby shifting the frequency synthesizer 1 to the locked state. Further, the frequency fout of the output signal Sout is not less than the newly set frequency f2 of the high frequency signal S2, and the absolute frequency (| fout−f2 |) of the difference frequency signal Sdi is not less than the cut-off frequency fco of the low-pass filter unit 7. , The second reference signal S3 having a frequency f3 that is higher (constant as an example) than the frequency f1 of the low-frequency signal S1 is output to the phase comparison unit 8 as a comparison signal S4, whereby the output signal Sout By forcibly reducing the frequency fout, the frequency synthesizer 1 is shifted to the locked state. Further, the frequency fout of the output signal Sout is equal to or higher than the newly set frequency f2 of the high-frequency signal S2, and the absolute frequency (| fout−f2 |) of the difference frequency signal Sdi is from the cutoff frequency fco of the low-pass filter unit 7. In the case of a low and high relationship, the locked state is continued by outputting the difference frequency signal Sdi as the comparison signal S4 to the phase comparator 8.

  Therefore, according to this frequency synthesizer 1, unlike the conventional frequency synthesizer, when the frequency f2 of the high-frequency signal S2 is newly set, a circuit for shifting the frequency synthesizer 1 to the locked state is provided in the two VCOs. Therefore, it is not necessary to design and use a complicated control circuit that takes into account the operation of and the characteristics of each electronic component, so that the design can be facilitated. In addition, since the control voltage Vc applied to the VCO 5 is not directly controlled but the configuration in which the comparison signal S4 input to the phase comparator 8 is switched is adopted, the VCO 5 directly affects the influence of noise generated in the internal circuit. As a result of avoiding the problem of receiving, good noise characteristics can be realized.

  Further, according to the frequency synthesizer 1, the four frequency dividers 21, 22, 23, 24, the two frequency phase comparators 25, 26 and the selection unit 27 send the comparison signal S 4 to the phase comparison unit 8. Since the output signal processing unit 10 can be configured, unlike the conventional frequency synthesizer, it is possible to realize a circuit that outputs the comparison signal S4 with fewer types of electronic components.

  The frequency synthesizer 1 is locked by setting the frequency f1 of the low-frequency signal S1 to 25 MHz, thereby setting the cutoff frequency fco to 50 MHz, and setting the frequency f2 of the high-frequency signal S2 output from the high-frequency signal generator 4 to 975 MHz. In the state where the output signal Sout of the frequency fout (= 1 GHz) is output in the state, the numerical values M and L are set to “39” and “2”, respectively. However, the frequency f1 of the low frequency signal S1 is changed. Even when the cut-off frequency fco is also changed correspondingly, by changing the numerical values M and L, the detection signal is sent from the frequency phase comparator 25 to the selection unit 27 in the same manner as in the above example. Sa can be output in an optimum state.

For example, the frequency synthesizer 1 is locked by setting the frequency f1 of the low-frequency signal S1 to 50 MHz, thereby setting the cutoff frequency fco to 100 MHz, and setting the frequency f2 of the high-frequency signal S2 output from the high-frequency signal generator 4 to 950 MHz. In the state in which the output signal Sout having the frequency fout (= 1 GHz) is output in the state, as an example, when the numerical value L is “4”, the numerical value M is defined as follows.
M = 4 × 950/100 = 38

  Also in this configuration, the frequency division setting for the high-frequency signal generator 4 is changed from the locked state to reduce the frequency f2 of the high-frequency signal S2 to be output, and thereby the absolute frequency (| fout− When f2 |) becomes equal to or higher than the cutoff frequency fco (100 MHz) of the low-pass filter unit 7 (for example, when the frequency f2 is reduced to 887.5 MHz), in this state, the signal processing unit 10 The frequency divider 21 divides the high-frequency signal S2 (frequency f2 (= 887.5 MHz)) by M (= 38) and outputs a frequency-divided signal S21 having a frequency f21 (≈23.4 MHz), and the frequency divider 22 The output signal Sout (frequency fout (= 1 GHz)) is divided by (38 + 4), and a frequency-divided signal S22 having a frequency f22 (≈23.8 MHz) is output. Thereby, since the frequency f22 of the frequency-divided signal S22 becomes equal to or higher than the frequency f21 of the frequency-divided signal S21, the frequency phase comparator 25 starts outputting the detection signal Sa, so that the signal processing unit 10 transfers the phase comparison unit 8 to the phase comparison unit 8. On the other hand, the second reference signal S3 can be output as the comparison signal S4, and the frequency fout of the output signal Sout can be forcibly reduced.

  Further, the frequency division setting for the high-frequency signal generator 4 is changed from the locked state, and the frequency f2 of the output high-frequency signal S2 is increased to a frequency (for example, 1012.5 MHz) exceeding the frequency fout of the output signal Sout. Sometimes, in the signal processing unit 10, the frequency f2 of the high-frequency signal S2 is higher than the frequency fout of the output signal Sout, so that the frequency divider 24 outputs the frequency signal 24 that is output from the frequency divider 24. The frequency f23 of the divided signal S23 to be output is in a higher state. Therefore, the frequency phase comparator 26 compares the frequencies f23 and f24 and stops outputting the detection signal Sb, so that the signal processing unit 10 stops outputting the comparison signal S4 to the phase comparison unit 8. The frequency fout of the output signal Sout can be forcibly increased.

In addition, the frequency synthesizer 1 is locked by setting the frequency f1 of the low frequency signal S1 to 100 MHz, thereby setting the cutoff frequency fco to 150 MHz, and setting the frequency f2 of the high frequency signal S2 output from the high frequency signal generator 4 to 900 MHz. In the state where the output signal Sout having the frequency fout (= 1 GHz) is output in the state, as an example, when the numerical value L is “3”, the numerical value M is defined as follows.
M = 3 × 900/100 = 27

  Also in this configuration, the frequency division setting for the high-frequency signal generator 4 is changed from the locked state to reduce the frequency f2 of the high-frequency signal S2 to be output, and thereby the absolute frequency (| fout− When f2 |) becomes equal to or higher than the cutoff frequency fco (150 MHz) of the low-pass filter unit 7 (for example, when the frequency f2 is reduced to 837.5 MHz), in this state, the signal processing unit 10 The frequency divider 21 divides the high-frequency signal S2 (frequency f2 (= 837.5 MHz)) by M (= 27) and outputs a frequency-divided signal S21 of frequency f21 (≈31.0 MHz), and the frequency divider 22 The output signal Sout (frequency fout (= 1 GHz)) is divided by (27 + 3), and a frequency-divided signal S22 having a frequency f22 (≈33.3 MHz) is output. Thereby, since the frequency f22 of the frequency-divided signal S22 becomes equal to or higher than the frequency f21 of the frequency-divided signal S21, the frequency phase comparator 25 starts outputting the detection signal Sa, so that the signal processing unit 10 transfers the phase comparison unit 8 to the phase comparison unit 8. On the other hand, the second reference signal S3 can be output as the comparison signal S4, and the frequency fout of the output signal Sout can be forcibly reduced.

  Further, the frequency division setting for the high-frequency signal generator 4 is changed from the locked state, and the frequency f2 of the output high-frequency signal S2 is increased to a frequency (for example, 1012.5 MHz) exceeding the frequency fout of the output signal Sout. Sometimes, in the signal processing unit 10, the frequency f2 of the high-frequency signal S2 is higher than the frequency fout of the output signal Sout, so that the frequency divider 24 outputs the frequency signal 24 that is output from the frequency divider 24. The frequency f23 of the divided signal S23 to be output is in a higher state. Therefore, the frequency phase comparator 26 compares the frequencies f23 and f24 and stops outputting the detection signal Sb, so that the signal processing unit 10 stops outputting the comparison signal S4 to the phase comparison unit 8. The frequency fout of the output signal Sout can be forcibly increased.

  As described above, according to the frequency synthesizer 1, the frequency division number M of the frequency divider 21 in the signal processing unit 10 is set to (M + L) as the frequency division number of the other frequency divider 22 and the low-pass filter. Even if the cutoff frequency fco is changed in accordance with the change of the frequency f1 of the low-frequency signal S1 by considering the cutoff frequency fco of the unit 7 and defining the both values M and L, By changing at least one of the numerical values M and L, an appropriate comparison signal S4 can be output from the signal processing unit 10 to the phase comparison unit 8.

  The most preferable configuration in which the numerical value M is set so as to be an integer closest to the value (L × f2 / fco) has been described above. However, as a general characteristic of the filter, even if it is a cutoff frequency, Since the signal component at that frequency does not become zero, the integer near the nearest integer can be set as the numerical value M instead of the integer itself closest to the value (L × f2 / fco). Further, in the setting of the numerical values M and L that define the frequency division number (M + L) of the frequency divider 22, the numerical value L is first set, and then the numerical value M is set as described above. Of course, a configuration in which the numerical value L is set may be adopted. In addition, a configuration has been adopted in which two frequency dividers 23 and 24 are disposed in front of the frequency phase comparator 26 to reduce the frequency of the signal input to the frequency phase comparator 26. In the configuration in which the output signal Sout and the frequencies fout and f2 of the high-frequency signal S2 can be directly compared, the arrangement of the frequency dividers 23 and 24 can be omitted.

1 frequency synthesizer 3 low frequency signal generator 4 high frequency signal generator 5 VCO
6 Mixer unit 7 Low pass filter unit 8 Phase comparison unit 9 Loop filter 10 Signal processing unit Vc Control voltage S1 Low frequency signal S2 High frequency signal S3 Reference signal S4 Comparison signal Sdi Difference frequency signal Ser Error signal Sout Output signal Smix Mixing signal

Claims (2)

A voltage controlled oscillator that generates an output signal having a frequency according to the input control voltage;
A low frequency signal generation unit that generates a low frequency signal of an arbitrary frequency within a preset frequency range;
A high-frequency signal generation unit that generates a high-frequency signal of a set frequency;
A mixer unit that mixes the output signal and the high-frequency signal and outputs the mixed signal;
A low-pass filter that selectively passes a difference frequency signal between the output signal and the high-frequency signal included in the mixing signal;
A signal processing unit that inputs the output signal, the high-frequency signal, and the difference frequency signal, and that outputs a comparison signal based on a level relationship between the frequency of the output signal and the frequency of the high-frequency signal;
A phase comparator that outputs an error signal for each phase of the low-frequency signal and the comparison signal;
A frequency synthesizer comprising a control voltage generator for generating the control voltage based on the error signal,
When the frequency of the high-frequency signal is newly set and the frequency of the output signal is lower than the frequency of the newly set high-frequency signal, the signal processing unit is The output of the comparison signal to the output is stopped, the frequency of the output signal is equal to or higher than the frequency of the newly set high-frequency signal, and the absolute frequency of the difference frequency signal is equal to or higher than the cutoff frequency of the low-pass filter unit In the case of the height relationship, a reference signal having a frequency higher than the frequency of the low frequency signal is output as the comparison signal to the phase comparison unit, and the frequency of the output signal is the frequency of the newly set high frequency signal. When the above relationship is high and the absolute relationship of the difference frequency signal is lower than the cutoff frequency of the low-pass filter unit, the difference frequency signal is Frequency synthesizer output to the phase comparator as 較用 signal. The signal processing unit
A first frequency divider that divides the high-frequency signal by M (M is an integer of 2 or more) and outputs a first frequency-divided signal;
A second divider for dividing the output signal by (M + L) (L is an integer of 1 or more) and outputting a second divided signal;
A first frequency comparator that outputs a first detection signal when the frequency of the second divided signal is equal to or higher than the frequency of the first divided signal;
A second frequency comparator that outputs a second detection signal when the frequency of the output signal is equal to or higher than the frequency of the high-frequency signal;
When the difference frequency signal and the reference signal are input, and when the first detection signal and the second detection signal are input, the reference signal is output as the comparison signal to the phase comparison unit, and the first When the first detection signal is not input and the second detection signal is input, the difference frequency signal is output as the comparison signal to the phase comparison unit, and when the second detection signal is not input. A selection unit for stopping the output of the comparison signal to the phase comparison unit,
2. The frequency according to claim 1, wherein a numerical value M is defined to be an integer closest to a value (L × f / fco), where f is the frequency of the high-frequency signal and fco is the cutoff frequency. Synthesizer.

Images