JP5412496B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine, a sparrow ball gaming machine, a ball ball gaming machine such as an arrangement ball, and a revolving gaming machine such as a slot machine. Furthermore, the present invention relates to an authentication method for data transmission between each control unit in an electronic apparatus including a plurality of control units.

Main control that controls basic actions associated with the progress of a game, among illegal acts that are performed on a gaming machine and forcibly pays out medals, game balls, etc. (hereinafter referred to as “game media”) regardless of the game content. As for the peripheral control board on which the peripheral control unit that executes the rendering process and the like based on the control command information (hereinafter referred to as “control command”) from the main control board on which the unit is mounted, is there.
(1) Replacing an authorized main control board with an unauthorized main control board (2) A ROM storing a legitimate program executed by the CPU mounted on the main control board and an unauthorized program obtained by falsifying the above program are stored. (3) An illegal board (impersonated board) is provided between the main control board and the peripheral control board, and the ROM of (2) above is replaced.

  In order to prevent such illegal acts, the conventional gaming machines include the following. For example, in the gaming machine described in Patent Document 1, the main control board generates a control command and transmits it to the sub-control board, and checks the control command transmitted by the first transmission means within a predetermined period. Second transmission means for transmitting the thumb as a state monitoring command at a predetermined timing. In addition, the sub-control board verifies the validity of the control command transmitted within the predetermined period by comparing the checksum of the control command received within the predetermined period with the state monitoring command received at the predetermined timing. doing. That is, the gaming machine described in Patent Document 1 attempts to prevent the illegal act by transmitting a state monitoring command for verifying the validity of the control command at a predetermined timing.

JP 2002-18095 A

  However, in the gaming machine described in Patent Document 1, a state monitoring command having a data format or data amount different from that of a normal control command is transmitted alone at a predetermined timing. Therefore, there is a fear that a person who intends to perform an illegal act (hereinafter referred to as “illegal person”) can easily know the timing of sending the state monitoring command and steal it. Further, in the gaming machine described in Patent Document 1, a checksum of a control command transmitted within a predetermined period is used as a state monitoring command. Therefore, there is a possibility that an unauthorized person who knows the transmission timing of the state monitoring command can easily analyze the contents of the state monitoring command by acquiring and comparing the control command and its checksum within a predetermined period. there were.

  In addition, in the gaming machine described in Patent Document 1, in order to realize the addition of the security function, a process different from the normal process of transmitting a state monitoring command is added. It is getting complicated. Therefore, in the gaming machine described in Patent Document 1, the code size of the program executed by the CPU of the main control board increases, and the processing load on the CPU increases. Also, in gaming machines, the ROM and RAM capacities of the main control board are limited due to regulations unique to public games, and more limited resources are allocated to game machine manufacturers for programs related to performance processing. There is a desire to want. Therefore, the problem that the processing load of the CPU of the main control board and the code size of the program increase by adding a security function to the gaming machine cannot be overlooked.

  In addition, when adding security functions by hardware, it is possible to suppress an increase in processing load and code size. However, when a new function is added to the existing main control board by hardware, the configuration of the CPU and peripheral circuits related to the hardware must be changed, which increases the development cost and development time of the gaming machine. Invited, it will be a big burden for game machine manufacturers. For this reason, the conventional technology cannot meet the demands of gaming machine manufacturers who want to add effective security functions to existing gaming machines relatively easily.

  The present invention has been made in view of the above circumstances, and is relatively simple while preventing the above-mentioned fraud by improving the security strength by suppressing the increase in processing load and code size. It is an object to provide a gaming machine having a security function that can be added to the game machine.

In order to solve the above problems, the present invention is provided between a main control unit that outputs a control command, a peripheral control unit that performs processing based on the control command, and the main control unit and the peripheral control unit a game machine comprising an intermediate control unit, wherein the main controller performs the processing according to predetermined game information stored in the storage unit to generate the control command, previously negotiated the generated control command an arithmetic processing unit that outputs an output control method which are provided so as to follow to the arithmetic processing unit, is added to the control command outputted by the processing unit for checking the validity of the control command A first check value generation unit for generating the error check value and adding the generated error check value to the control command for output, and the error check value provided after the first check value generation unit. Value added His command and a transmission unit for transmitting to the intermediate control unit, the intermediate control portion includes a first generating an error check value for verifying that corresponds to the error check value generated by the first check value generator 2 check value generation unit , comparing the error check value transmitted by the transmission unit with the error check value generated by the second check value generation unit and verifying the validity of the control command transmitted by the transmission unit An inspection unit that performs inspection and outputs the result information of the inspection , and a relay transmission unit that relays and transmits the control command transmitted by the transmission unit to the peripheral control unit and transmits the result information to the peripheral control unit When, wherein the peripheral control unit, performs processing based on the control command relayed by the relay transmitting unit, a process corresponding to the result information transmitted by the relay transmitting unit Comprising starts selling processing unit, the first check value generating unit inputs a control command outputted by the processing unit, and a buffer means to output in advance specify control command input timing, said buffer means Is input to the control command, and a conversion method for converting the bit string of the error check value to be added to the input control command, or is added to the control command output by the arithmetic processing unit after the input control command. A conversion method for converting the bit string of the error check value is determined as one of a plurality of different conversion methods determined in advance based on the input control command, and conversion method information indicating the determined conversion method and a determination means to output in response to said timing, enter a control command outputted by said buffer means input The error-checking value generated by a predetermined generation method by using the output control command by the processing unit from the past control command, and generating means to output according to the timing, output by the generating means The error check value and the conversion method information output by the determining means are input, the bit string of the input error check value is converted by the conversion method indicated by the input conversion method information, and the error check value obtained by converting the bit string and a conversion means to output in response to said timing inputs the error check value output by the output control command and said converting means by said buffer means, the control command entered, entered該誤Ri A check value is added, and the control command to which the error check value is added is the output control method determined in advance in the arithmetic processing unit. Flip output control method, anda additional means to output in response to the timing, and the transmission unit, the control command in which the error check value is added output by said adding means, said intermediate control It transmits to a part.

  In the present invention, in order to add an authentication function for the main control unit as a security function, an error check value adding function provided in the main control unit is configured by hardware, and a control command to be transmitted is generated in the past from the control command. The control command error check value is added and transmitted. At this time, according to the present invention, it is possible to achieve the effectiveness by utilizing the control means provided in the existing gaming machine without newly providing a control command for generating an error check value or newly providing encryption processing. An authentication function has been added. By applying such an unprecedented simple method, it becomes difficult for an unauthorized person to analyze the relationship between the control command and the error check value added thereto, and the security strength of the gaming machine is improved by a simple method. be able to. Furthermore, the processing load and code size of the CPU of the main control unit, which increase with the addition of the security function, can be suppressed to the maximum. Moreover, such a security function can be added relatively easily to an existing gaming machine.

  According to the present invention, the authentication function for the main control unit is provided in an intermediate control unit that is independent from the peripheral control unit that performs processing related to normal game progression. Therefore, it is possible to suppress the processing load and code size of the CPU of the peripheral control unit that increases due to the addition of the authentication function. And a security function can be added comparatively easily with respect to the existing game machine.

It is a front view which shows the external appearance structure of the game machine which concerns on embodiment of this invention. It is a perspective view which shows the external appearance structure of the state which open | released the glass frame of the game machine which concerns on embodiment of this invention. It is a perspective view which shows the external appearance structure of the back surface side of the game machine which concerns on embodiment of this invention. It is a block diagram which shows the internal structure of the game machine which concerns on embodiment of this invention. It is a block diagram which shows the structure regarding the authentication process of the main control part which comprises the game machine which concerns on embodiment of this invention. It is the schematic for demonstrating the memory map of main ROM and boot ROM of the main control part which comprises the game machine which concerns on embodiment of this invention. It is the schematic for demonstrating the addition procedure of the error check value to the control command which the main control part which comprises the game machine which concerns on embodiment of this invention outputs. It is a block diagram which shows the structure regarding the authentication process of the intermediate | middle control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the classification of the control command transmitted to the production | presentation control part from the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the main process by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the interruption process by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the special figure special electricity control process by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the special symbol memory | storage determination process by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the boot process at the time of starting by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the command transmission process by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the main process by the intermediate | middle control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the main process by the production | presentation control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the interruption process by the production | presentation control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the command analysis process 1 by the presentation control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the command analysis process 2 by the production | presentation control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the authentication result data analysis process by the presentation control part which comprises the game machine which concerns on embodiment of this invention.

  Embodiments for carrying out the present invention will be described with reference to the drawings. Specifically, a pachinko gaming machine 1 (hereinafter referred to as “gaming machine 1”), which is one of the gaming machines according to the embodiment of the present invention, will be described.

[Composition of gaming machine]
Hereafter, the configuration of the gaming machine 1 according to one embodiment of the present invention will be described.
FIG. 1 is a front view showing an external configuration of the gaming machine 1 according to the present embodiment. FIG. 2 is a perspective view showing an external configuration of the gaming machine 1 according to the present embodiment in a state where the glass frame is opened. FIG. 3 is a perspective view showing an external configuration of the back side of the gaming machine 1 according to the present embodiment.

  The gaming machine 1 includes an outer frame 60 attached to an island facility of a game store, and a glass frame 50 that is rotatably supported by the outer frame 60 (see FIGS. 1 and 2). In addition, the outer frame 60 is provided with a game board 2 in which a game area 6 in which the game ball 200 flows down is formed. In the glass frame 50, an operation handle 3 for launching a game ball toward the game area 6 by being rotated, an audio output device 32 including a speaker, an effect lighting device 34 having a plurality of lamps, An effect button 35 for changing the effect mode by a pressing operation is provided.

  Further, the glass frame 50 is provided with a tray 40 for storing a plurality of game balls 200, and the tray 40 has a downward slope so that the game balls 200 flow down toward the operation handle 3. (See FIG. 2). A receiving opening (not shown) for receiving a game ball is provided at the end of the downward slope of the tray 40, and the game ball received in the receiving opening is driven by the ball feed solenoid 4b, so that the glass frame One by one is sent to a ball feed opening 41 provided on the back surface of 50. Then, the game ball sent out to the ball feed opening 41 is guided to the end of the downward slope of the launch rail 42 by the launch rail 42 having a downward slope toward the launching member 4c. A stopper 43 for stopping the game ball is provided above the downwardly inclined end portion of the launch rail 42, and the game ball 200 sent out from the ball feed opening 41 is the downwardly inclined end portion of the launch rail 42. Thus, one game ball is stopped (see FIG. 2).

  When the player rotates the operation handle 3, the launch volume 3b (see FIG. 4) directly connected to the operation handle 3 also rotates, and the launch volume of the game ball is adjusted and adjusted by the launch volume 3b. The launching member 4c directly connected to the firing solenoid 4a (see FIG. 4) rotates with the firing strength. By rotating the launch member 4 c, the game ball 200 stored at the end of the downward slope of the launch rail 42 is launched by the launch member 4 c, and the game ball is launched into the game area 6.

  When the game ball fired as described above rises between the rails 5a and 5b from the launch rail 42 and exceeds the ball return prevention piece 5c, the game ball reaches the game area 6 and then falls in the game area 6. At this time, the game ball falls unpredictably by a plurality of nails and windmills provided in the game area 6.

  The game area 6 is provided with a plurality of general winning awards 12. Each of these general winning awards 12 is provided with a general winning opening detecting switch 12a (see FIG. 4). When this general winning opening detecting switch 12a detects the winning of a game ball, a predetermined winning ball (for example, 10) Game balls).

  Further, in the area below the center of the game area 6, there are a first start port 14 and a second start port 15 that constitute a start area into which game balls can enter, and a second large area in which game balls can enter. A winning opening 17 is provided.

  The second starting port 15 has a pair of movable pieces 15b, a mode in which the pair of movable pieces 15b is maintained in a closed state (hereinafter referred to as “first mode”), and a pair of movable pieces. The movement control is performed so that 15b is in an open state (hereinafter referred to as “second aspect”). When the second starting port 15 is controlled in the first mode, the winning member of the second large winning port 17 located immediately above the second starting port 15 becomes an obstacle, and the game ball Is impossible to accept. On the other hand, when the second start port 15 is controlled to the second mode, the pair of movable pieces 15b function as a tray, and it is easy to win a game ball to the second start port 15. That is, when the second start port 15 is in the first mode, there is no game ball winning opportunity, and when it is in the second mode, the game ball winning opportunity is increased.

  Here, the first start port 14 is provided with a first start port detection switch 14a (see FIG. 4) for detecting the entrance of a game ball, and the second start port 15 is a first for detecting the entrance of a game ball. 2 A start port detection switch 15a (see FIG. 4) is provided. When the first start port detection switch 14a or the second start port detection switch 15a detects the entry of a game ball, a special symbol determination random number value is acquired, and a right acquisition lottery (to be described later) Hereinafter, “Lottery for jackpot” is performed. Also, when the first start port detection switch 14a or the second start port detection switch 15a detects the entry of a game ball, a predetermined prize ball (for example, three game balls) is paid out.

  Further, the second grand prize winning port 17 is constituted by an opening formed in the game board 2. Below the second grand prize opening 17, there is a second big prize opening / closing door 17b that can protrude from the game board surface side to the glass plate 52 side. It is controlled to move between an open state protruding to the side and a closed state buried in the game board surface. When the second grand prize opening opening / closing door 17b protrudes from the game board surface, it functions as a tray for guiding the game ball into the second big prize opening 17, and the game ball can enter the second big prize opening 17. Become. The second big prize opening 17 is provided with a second big prize opening detection switch 17a (see FIG. 4). When the second big prize opening detection switch 17a detects the entry of a game ball, it is set in advance. Award balls (for example, 15 game balls) are paid out.

Furthermore, in the area on the right side of the game area 6, there are provided a normal symbol gate 13 constituting a normal area through which game balls can pass and a first grand prize winning opening 16 through which game balls can enter.
For this reason, if the operation ball 3 is not a game ball which has been greatly rotated and launched with a strong force, the normal design gate 13 and the first big winning opening 16 are configured so that the game ball does not pass or win. Yes. In particular, even if the short game state, which will be described later, is entered, if the game ball flows down to the left side of the game area 6, the game ball does not pass through the normal symbol gate 13, so that it is at the second start port 15. The pair of movable pieces 15b are not opened, and it is difficult for a game ball to win the second starting port 15.

  The normal symbol gate 13 is provided with a gate detection switch 13a (see FIG. 4) for detecting the passage of the game ball. When the gate detection switch 13a detects the passage of the game ball, the normal symbol determination random number value. Is acquired, and a “normal symbol lottery” to be described later is performed.

  The first grand prize opening 16 is normally kept closed by the first big prize opening opening / closing door 16b, and it is impossible to enter a game ball. In contrast, when a special game, which will be described later, is started, the first grand prize opening opening / closing door 16b is opened, and the first big prize opening opening / closing door 16b puts the game ball in the first big winning opening 16; It functions as a receiving tray that guides the game ball and can enter the first grand prize opening 16. The first big prize opening 16 is provided with a first big prize opening detection switch 16a (see FIG. 4). When the first big prize opening detection switch 16a detects the entry of a game ball, it is set in advance. Prize balls (for example, 15 game balls) are paid out.

  Furthermore, in the lowermost area of the game area 6 and the lowermost area of the game area 6, the general winning opening 12, the first starting opening 14, the second starting opening 15, the first major winning opening 16, and the second large winning opening. An out port 11 is provided for discharging game balls that have not entered any of the winning ports 17.

In addition, a decoration member 7 that affects the flow of the game ball is provided in the center of the game area 6. A liquid crystal display device 31 is provided at a substantially central portion of the decorative member 7, and an effect driving device 33 in the form of a belt is provided above the liquid crystal display device 31.
In this embodiment, the liquid crystal display device 31 is used as a liquid crystal display. However, an organic EL display may be used, a projector, a reel made of an annular structure, a so-called 7-segment LED, a dot matrix. A display device or the like may be used.

The liquid crystal display device 31 displays an image during standby when no game is being performed, or displays an image according to the progress of the game. Among them, three effect symbols 36 for informing the jackpot lottery result, which will be described later, are displayed, and a combination of specific effect symbols 36 (for example, 777) is stopped and displayed as a jackpot lottery result. A jackpot is announced.
More specifically, when a game ball enters the first start port 14 or the second start port 15, the three effect symbols 36 are scroll-displayed, and the scroll is stopped after a predetermined time, The effect design 36 is stopped and displayed. Further, by displaying various images, characters, and the like during the variation display of the effect symbol 36, a high expectation that the player may win a big hit is given to the player.

  The effect driving device 33 gives a player a sense of expectation according to the operation mode. The effect driving device 33 performs, for example, an operation in which the belt moves downward or a rotating member at the center of the belt rotates. Various operational feelings are given to the player depending on the operation mode of the effect driving device 33.

  Furthermore, in addition to the above-described various production devices, the audio output device 32 outputs background music, sound effects, and the like, and produces productions using sound. The production lighting device 34 includes the illumination direction of each lamp, The luminescent color is changed to produce lighting.

  The effect button 35 is effective only when, for example, a message for operating the effect button 35 is displayed on the liquid crystal display device 31. The effect button 35 is provided with an effect button detection switch 35a (see FIG. 4). When the effect button detection switch 35a detects the player's operation, a further effect is executed in accordance with this operation.

  In the lower right of the game area 6, a first special symbol display device 20, a second special symbol display device 21, a normal symbol display device 22, a first special symbol hold indicator 23, a second special symbol hold indicator 24, a normal A symbol hold indicator 25 is provided.

  The first special symbol display device 20 is for notifying a lottery result obtained when a game ball enters the first start port 14, and is composed of 7-segment LEDs. That is, a plurality of special symbols corresponding to the jackpot lottery result are provided, and the lottery result is notified to the player by displaying the special symbol corresponding to the jackpot lottery result on the first special symbol display device 20. I am doing so. For example, “7” is displayed when the jackpot is won, and “−” is displayed when the player wins. “7” and “−” displayed in this way are special symbols, but these special symbols are not displayed immediately, but are displayed in a stopped state after being displayed for a predetermined time. .

  Here, the “successful lottery” means that when a game ball enters the first start port 14 or the second start port 15, a special symbol determination random number value is acquired, and the acquired special symbol determination random value is acquired. Is a random number value corresponding to “big hit” or a random number value corresponding to “small hit”. The jackpot lottery result is not immediately notified to the player, and the first special symbol display device 20 displays a variation such as blinking of the special symbol, and when the predetermined variation time has passed, the jackpot lottery result The special symbol corresponding to is stopped and displayed so that the player is notified of the lottery result. The second special symbol display device 21 is for notifying a lottery result of a jackpot that is performed when a game ball enters the second start port 15, and the display mode is the above-described first display mode. This is the same as the special symbol display mode in the special symbol display device 20.

  Further, in this embodiment, “big hit” means that a right to win a big hit game is obtained in a big win lottery performed on condition that a game ball has entered the first start port 14 or the second start port 15 Say what you did. In the “hit game”, a round game in which the first big prize opening 16 or the second big prize opening 17 is opened is performed 15 times in total. A predetermined time is set for the maximum opening time of the first grand prize port 16 or the second grand prize port 17 in each round game, and during this time, the first grand prize port 16 or the second grand prize port 17 is set. When a predetermined number of game balls (for example, nine) enter, one round game is completed. In other words, the “big hit game” is a game in which a game ball can enter the first grand prize winning opening 16 or the second big winning prize opening 17 and the player can acquire a winning ball according to the winning prize.

In this embodiment, in the “hit lottery”, two gaming states are set according to the winning probability. That is, the “low probability gaming state” in which the winning probability is set to 1 / 299.5 and the “high probability gaming state” in which the winning probability is set to 1 / 29.95. Also, in the “jackpot game”, a plurality of types of jackpot games are set. For example, in the case of “game per long”, the first big prize opening 16 is released once (× 15 rounds) for 29.000 seconds for each round game. If it is “short win game”, the second big prize opening 17 is opened for 0.052 seconds × 1 time (× 15 rounds) for each round of game. In the case of “game per development”, the second grand prize opening 17 is opened for 0.052 seconds × 3 times in the first round game, and 29.000 seconds × 1 for each round game after the second round. Times (× 14 rounds).
In the case of “small hit”, one gaming state with a winning probability of 1 / 149.75 is set. In addition, if it is a “small hit game”, although it is not a round game, the second big prize opening 17 is opened for 0.052 seconds × 15 times. In the present embodiment, “big hit game” and “small hit game” are collectively referred to as “special game”.

  The normal symbol display device 22 is for notifying the lottery result of the normal symbol that is performed when the game ball passes through the normal symbol gate 13. As will be described in detail later, when the winning symbol is won by the normal symbol lottery, the normal symbol display device 22 is turned on, and then the second start port 15 is controlled to the second mode for a predetermined time.

  Here, “normal symbol lottery” means that when a game ball passes through the normal symbol gate 13, the normal symbol determination random number value is acquired, and the acquired normal symbol determination random value corresponds to “winning”. A process for determining whether or not the value is a random value. The lottery result of the normal symbol is not always notified immediately after the game ball passes through the normal symbol gate 13, but the normal symbol display device 22 displays a variation such as blinking of the normal symbol. When the fluctuation time elapses, the normal symbol corresponding to the lottery result of the normal symbol is stopped and displayed so that the player is notified of the lottery result.

Furthermore, if a game ball enters the first start port 14 or the second start port 15 during special symbol fluctuation display or a special game to be described later, and if the big hit lottery cannot be performed immediately, a certain condition The right to win a jackpot will be withheld. More specifically, the random number value for special symbol determination acquired when the game ball enters the first start port 14 is stored as the first hold, and when the game ball enters the second start port 15 The acquired special symbol determination random number value is stored as the second hold.
For both of these holds, the upper limit hold number is set to 4, and the hold number is displayed on the first special symbol hold indicator 23 and the second special symbol hold indicator 24, respectively. When there is one first hold, the LED on the left side of the first special symbol hold indicator 23 lights up, and when there are two first holds, two LEDs on the first special symbol hold indicator 23 Lights up. In addition, when there are three first holds, the LED on the left side of the first special symbol hold indicator 23 blinks and the right LED is lit, and when there are four first holds, the first special symbol hold. Two LEDs on the display 23 blink. The second special symbol hold indicator 24 also displays the number of second hold on hold in the same manner as described above.
The upper limit reserved number of normal symbols is also set to four, and the reserved number of normal symbols is displayed in the same manner as the first special symbol hold indicator 23 and the second special symbol hold indicator 24. Displayed on the instrument 25.

  The glass frame 50 supports a glass plate 52 that covers the game area 6 so as to be visible in front of the game board 2 (player side). The glass plate 52 is detachably fixed to the glass frame 50.

  The glass frame 50 is connected to the outer frame 60 via a hinge mechanism 51 on one end side in the left-right direction (for example, the left side facing the gaming machine 1), and the left-right direction with the hinge mechanism 51 as a fulcrum. The other end side (for example, the right side facing the gaming machine 1) can be rotated in a direction to release from the outer frame 60. The glass frame 50 covers the game board 2 together with the glass plate 52, and can be opened like a door with the hinge mechanism 51 as a fulcrum to open the inner part of the outer frame 60 including the game board 2. On the other end side of the glass frame 50, a lock mechanism for fixing the other end side of the glass frame 50 to the outer frame 60 is provided. The fixing by the lock mechanism can be released by a dedicated key. The glass frame 50 is also provided with a door opening switch 133 (see FIG. 4) for detecting whether or not the glass frame 50 is opened from the outer frame 60.

  On the back side of the gaming machine 1, a main control board on which the main control unit 110 is mounted, an intermediate control board on which the intermediate control unit 180 is mounted, an effect control board on which the effect control unit 120 is mounted, and a payout control unit 130 are mounted. The payout control board, the power supply board on which the power supply unit 170 is mounted, the game information output terminal board 30 and the like are provided. Further, the power supply unit 170 is provided with a power plug 171 for supplying power to the gaming machine 1 and a power switch (not shown).

[Internal configuration of gaming machine]
Hereafter, the control means which controls the process which concerns on the game progress of the game machine 1 which concerns on embodiment of this invention is demonstrated.
FIG. 4 is a block diagram showing an internal configuration of the gaming machine 1 according to the present embodiment.

  The main control unit 110 is a main control means for controlling the basic operation of the game, and receives various detection signals from the first start port detection switch 14a, etc., and opens and closes the first special symbol display device 20 and the first grand prize opening. The game is controlled by driving the solenoid 16c and the like.

  The main control unit 110 includes a one-chip microcomputer 110m including at least a main CPU 110a, a main ROM 110b, a main RAM 110c, and a boot ROM 110d, a test value generation unit 500, a transmission unit 550, an input port and an output port for main control. (Not shown).

  The main control input port includes a payout control unit 130, a general winning port detecting switch 12a for detecting that a gaming ball has entered the general winning port 12, and a game ball having been inserted into the normal symbol gate 13. Gate detection switch 13a to detect, first start port detection switch 14a to detect that a game ball has entered the first start port 14, and second start to detect that a game ball has entered the second start port 15 The mouth detection switch 15a, the first grand prize opening detection switch 16a that detects that a game ball has entered the first grand prize opening 16, and the second that detects that a game ball has entered the second grand prize opening 17 A big prize opening detection switch 17a is connected. Various signals are input to the main control unit 110 through the input port for main control.

  The main control output port includes a payout control unit 130, a start opening / closing solenoid 15c for opening / closing the pair of movable pieces 15b of the second start opening 15, and a first large winning opening opening / closing door 16b. A special winning opening / closing solenoid 16c, a second large winning opening / closing solenoid 17c for operating the second winning opening / closing door 17b, a first special symbol display device 20 and a second special symbol display device 21 for displaying special symbols, and a normal symbol. A normal symbol display device 22 for displaying a symbol, a first special symbol hold indicator 23 and a second special symbol hold indicator 24 for displaying the number of reserved balls for a special symbol, and a normal symbol hold indicator for displaying the number of reserved balls for a normal symbol 25. A game information output terminal board 30 for outputting an external information signal is connected. Various signals are output from the main control output port.

  The main CPU 110a of the main control unit 110 reads out a program stored in the main ROM 110b based on an input signal from each detection switch or a timer (not shown) incorporated as an internal function, and performs arithmetic processing. Depending on the result, a control instruction (hereinafter referred to as “control signal”) for each component constituting the main control unit 110 and a control command for another control unit other than the main control unit 110 are output.

The main ROM 110b of the main control unit 110 stores in advance a game processing program that describes the content and procedure of processing related to game progress, and fixed data and tables necessary for determining various games.
As an example of a table stored in the main ROM 110b, a jackpot determination table referred to in the jackpot lottery, a hit determination table referred to in the normal symbol lottery, a symbol determination table for determining the stop symbol of the special symbol, after the jackpot ends End of jackpot game setting data table for determining the gaming state of the game, special electric accessory operating mode determination table for determining the opening / closing conditions of the special winning opening opening door, determining the opening pattern table of the special winning opening, and the variation pattern of the special symbol There is a variation pattern determination table.

  Further, the main ROM 110b is used when executing an authentication processing program describing the content and procedure of processing for transmitting a control command from the transmission unit 550 via the inspection value generation unit 500, and an authentication processing program. Fixed data and the like are stored in advance. The main ROM 110b also stores initial values set for the built-in circuit and peripheral circuits of the one-chip microcomputer 110m during the boot process of the main control unit 110 performed when the gaming machine 1 is reset such as when the power is turned on. So-called hardware parameters) are stored in advance. In addition, unique information that is unique to the gaming machine 1 is stored in the main ROM 110b in advance.

  The boot ROM 110d of the main control unit 110 includes a boot executed by the main CPU 110a, including initialization of internal circuits and peripheral circuits of the one-chip microcomputer 110m and initial value setting processing (hereinafter referred to as “initial value setting processing”). A boot processing program describing the contents and procedure of processing, and fixed data used when executing the boot processing program are stored. This boot processing program is set to start immediately after the main CPU 110a is activated.

The main RAM 110c of the main control unit 110 functions as a data work area when the main CPU 110a performs arithmetic processing, and has a plurality of storage areas.
As an example of the storage area that the main RAM 110c has, a normal symbol holding number (G) storage area, a normal symbol holding storage area, a normal symbol data storage area, a first special symbol holding number (U1) storage area, a second special symbol Reservation count (U2) storage area, first special symbol random value storage area, second special symbol random value storage area, round game number (R) storage area, number of open times (K) storage area, number of big winning entrances ( C) Storage area, game state storage area (high probability game flag storage area, etc. and short time game flag storage area), high probability game number (X) counter, short time number (J) counter, game state buffer, stop symbol data storage area There are various timer counters such as a storage area for transmission data, a special symbol time counter, and a special game timer counter.

  The inspection value generation unit 500 of the main control unit 110 is provided between the main CPU 110a and the transmission unit 550. When the main control unit 110 transmits a control command, the check value generation unit 500 checks the validity of the control command and generates an error check value for authenticating the validity of the main control unit 110. Has a function (hereinafter referred to as “error check value addition function”). Specifically, the inspection value generation unit 500 receives a control command from the main CPU 110a when the main CPU 110a performs a process of transmitting a control command by the transmission unit 550 (hereinafter referred to as “command transmission process”). Then, the check value generation unit 500 performs a process of generating an error check value of the received control command (hereinafter referred to as “check value generation process”). Then, check value generation unit 500 performs processing for adding the generated error check value to the control command (hereinafter referred to as “check value addition processing”), and then outputs the control command with the error check value to transmission unit 550. To do.

  The transmission unit 550 of the main control unit 110 is a control command to a control unit (intermediate control unit 180 to be described later) that is determined in advance to perform an authentication function for the main control unit 110 among the output ports for main control. Used for output. Specifically, the transmission unit 550 is provided subsequent to the check value generation unit 500 and transmits a control command with an error check value output from the check value generation unit 500 to the intermediate control unit 180.

  The game information output terminal board 30 is a board for outputting an external information signal generated by the main control unit 110 to a hall computer or the like of a game store. The game information output terminal board 30 is connected to the main controller 110 by wiring, and is provided with a connector for connecting external information to a hall computer or the like of a game store.

  The power supply unit 170 includes a backup power source composed of a capacitor, supplies a power supply voltage to the gaming machine 1, and monitors a power supply voltage supplied to the gaming machine 1, and when the power supply voltage becomes a predetermined value or less, An electric interruption detection signal is output to the main control unit 110. More specifically, when the power interruption detection signal is at a low level and a certain time has elapsed since the power supply voltage is equal to or lower than a set value, the reset signal is at a low level and the main CPU 110a performs a process of stopping the operation. Thereafter, when the power interruption detection signal becomes a high level because the power supply voltage is equal to or higher than the set value and a predetermined time elapses, the reset signal becomes a high level, and the main CPU 110a performs a process of starting an operation. The backup power source is not limited to a capacitor, and may be a battery, for example, or a capacitor and a battery may be used in combination.

  The intermediate control unit 180 is a control means for mainly realizing an authentication function for the main control unit 110, and includes a CPU 180a, a ROM 180b, and a RAM 180c. The intermediate control unit 180 is provided between the main control unit 110 and a control unit (the effect control unit 120, the payout control unit 130, etc.) to which the main control unit 110 transmits a control command related to the original game process. It has been.

  For example, as shown in FIG. 4, when the intermediate control unit 180 is provided between the main control unit 110 and the effect control unit 120, the intermediate control unit 180 is transferred from the main control unit 110 to the intermediate control unit 180. They are connected so as to be communicable in one direction, and are connected so as to be communicable in one direction from the intermediate control unit 180 to the effect control unit 120. Although not shown, when the intermediate control unit 180 is provided between the main control unit 110 and the payout control unit 130, the intermediate control unit 180 can communicate with the main control unit 110 in both directions. And are connected so as to be able to communicate bidirectionally with the payout control unit 130. Therefore, when the intermediate control unit 180 is interposed, the effect control unit 120, the payout control unit 130, and the like are not transmitted directly from the main control unit 110, but are transmitted via the intermediate control unit 180.

  The CPU 180a reads out a program stored in the ROM 180b based on a control command transmitted from the main control unit 110 or an input signal from a timer (not shown) incorporated as an internal function, and performs arithmetic processing. Then, CPU 180a transmits the corresponding data to subsequent effect control unit 120 and payout control unit 130 based on the processing. The RAM 180c functions as a data work area during the arithmetic processing of the CPU 180a.

  For example, when the CPU 180a of the intermediate control unit 180 receives a control command transmitted from the main control unit 110, the CPU 180a performs error check processing for checking the validity of the control command and authenticating the validity of the main control unit 110. Then, the CPU 180a transmits the authentication result information (hereinafter referred to as “authentication result data”) obtained by the processing to the subsequent effect control unit 120, the payout control unit 130, and the like, and performs processing based on the authentication result data. Let it run. In addition, the CPU 180a performs a relay transmission process of transmitting the control command to the subsequent effect control unit 120, the payout control unit 130, or the like while maintaining the specific processing content and the reception order of the received control command.

Further, the ROM 180b has an authentication processing program describing the contents and procedure of the authentication processing including error checking processing for the received control command performed by the CPU 180a, and a fixed used for executing the authentication processing program. Data and information corresponding to the unique information stored in the main ROM 110b of the main control unit 110 are stored in advance.
As described above, the intermediate control unit 180 is obtained by the error checking process, the authentication function for the main control unit 110, the function of relaying the received control command to the subsequent effect control unit 120, the payout control unit 130, and the like. At least a function of transmitting the authentication result data to the subsequent effect control unit 120, payout control unit 130, and the like. In addition, the structure regarding these authentication processes is mentioned later.

  The effect control unit 120 mainly controls each effect such as during a game or standby. The effect control unit 120 includes a sub CPU 120a, a sub ROM 120b, and a sub RAM 120c, and is provided so as to be able to communicate in one direction from the main control unit 110 to the effect control unit 120. As shown in FIG. 4, when the intermediate control unit 180 is provided between the main control unit 110 and the effect control unit 120, the effect control unit 120 is connected to the main control unit 110 via the intermediate control unit 180. To the direction control unit 120 in one direction.

  The sub CPU 120a reads out the program stored in the sub ROM 120b based on the control command transmitted from the main control unit 110 or the input signal from the effect button detection switch 35a and the timer, performs arithmetic processing, and Based on the processing, the corresponding data is transmitted to the lamp control unit 140 or the image control unit 150. The sub RAM 120c functions as a data work area during the arithmetic processing of the sub CPU 120a.

  For example, when the sub CPU 120a in the effect control unit 120 receives a variation pattern designation command indicating a variation pattern of a special symbol, which is one of the control commands transmitted from the main control unit 110, the contents of the received variation pattern designation command are displayed. Analysis is performed to generate data for causing the liquid crystal display device 31, the audio output device 32, the effect driving device 33, and the effect illumination device 34 to execute a predetermined effect, and the data is used for the image control unit 150 and the lamp control unit. 140.

The sub ROM 120b of the effect control unit 120 stores a program for effect control, data necessary for determining various games, and a table.
As an example of the table stored in the sub-ROM 120b, to determine the combination of the effect pattern determination table for determining the effect pattern based on the variation pattern designation command received from the main control unit and the effect symbol 36 to be stopped and displayed. There is a production design determination table.

The sub RAM 120c of the effect control unit 120 functions as a data work area during the arithmetic processing of the sub CPU 120a, and has a plurality of storage areas.
As an example of the storage area that the sub-RAM 120c has, there are a game state storage area, an effect mode storage area, an effect pattern storage area, an effect symbol storage area, and the like.

  The payout control unit 130 controls payout of game balls. The payout control unit 130 includes a one-chip microcomputer including a payout CPU, a payout ROM, and a payout RAM (not shown), and is provided so as to be capable of bidirectional communication with the main control unit 110. . Although not shown, when the intermediate control unit 180 is provided between the main control unit 110 and the payout control unit 130, the payout control unit 130 communicates with the main control unit 110 via the intermediate control unit 180. It becomes possible to communicate in both directions.

  The payout CPU reads out a program stored in the payout ROM based on input signals from the payout ball count switch 132, the door opening switch 133, and the timer that detect whether or not the game ball has been paid out, and performs arithmetic processing. At the same time, the corresponding data is transmitted to the main control unit 110 based on the processing.

  Further, a payout motor 131 of a payout device for paying out a predetermined number of game balls from the game ball storage unit is connected to the output side of the payout control unit 130. The payout CPU reads out a predetermined program from the payout ROM based on a payout number designation command that is one of the control commands transmitted from the main control unit 110, performs arithmetic processing, and controls the payout motor 131 of the payout device. Then, a predetermined game ball is paid out. At this time, the payout RAM functions as a data work area at the time of calculation processing of the payout CPU.

  The lamp control unit 140 controls lighting of the effect lighting device 34 provided on the game board 2 and controls driving of the motor for changing the light irradiation direction. In addition, energization control is performed on a drive source such as a solenoid or a motor that operates the effect driving device 33. The lamp control unit 140 is connected to the effect control unit 120, and performs the above-described controls based on various commands transmitted from the effect control unit 120.

  The image control unit 150 stores a host CPU for performing image display control of the liquid crystal display device 31, a host RAM having a temporary storage area functioning as a work area of the host CPU, a control processing program for the host CPU, and the like. A host ROM, a CGROM storing image data, a VRAM having a frame buffer for drawing image data, a VDP (Video Display Processor) serving as an image processor, and a sound control circuit for controlling sound.

Based on the effect pattern designation command received from the effect control unit 120, the host CPU instructs the liquid crystal display device 31 to display the image data stored in the CGROM in the VDP.
The VDP draws image data stored in the CGROM in the frame buffer of the VRAM based on an instruction from the host CPU. Next, a video signal (RGB signal or the like) is generated based on the image data stored in the display frame buffer in the VRAM, and the generated video signal is output to the liquid crystal display device.

  The sound control circuit includes an audio ROM that stores a large number of audio data. The sound control circuit reads a predetermined program based on a command transmitted from the effect control unit 120 and also outputs the audio output device 32. Audio output control at.

  The launch control unit 160 performs launch control of the game ball. In the firing control unit 160, the touch sensor 3a and the firing volume 3b are connected to the input side, and the firing solenoid 4a and the ball feeding solenoid 4b are connected to the output side. The firing control unit 160 inputs a touch signal from the touch sensor 3a and performs control to energize the firing solenoid 4a and the ball feed solenoid 4b based on the voltage supplied from the firing volume 3b.

  The touch sensor 3a is provided in the inside of the operation handle 3, and is comprised from the electrostatic capacitance type proximity switch using the change of the electrostatic capacitance by the player touching the operation handle 3. When the touch sensor 3a detects that the player has touched the operation handle 3, the touch sensor 3a outputs a touch signal that permits energization of the firing solenoid 4a to the firing control unit 160 (see FIG. 4). The firing control unit 160 is configured so that the game ball 200 is not fired into the game area 6 unless a touch signal is input from the touch sensor 3a.

  The firing volume 3b is provided directly connected to a rotating portion around which the operation handle 3 rotates, and is composed of a variable resistor. The firing volume 3b divides a constant voltage (for example, 5V) applied to the firing volume 3b by a variable resistor, and supplies the divided voltage to the firing control unit 160 (the voltage to be supplied to the firing control unit 160). Variable). The launch controller 160 energizes the launch solenoid 4a based on the voltage divided by the launch volume 3b, and rotates the launch member 4c directly connected to the launch solenoid 4a, thereby playing the game ball 200 in the game. Fire into area 6.

  The firing solenoid 4a is composed of a rotary solenoid, and a launching member 4c is directly connected to the firing solenoid 4a, and the launching member 4c is rotated by rotating the launching solenoid 4a.

  Here, the rotational speed of the firing solenoid 4a is set to about 99.9 (times / minute) based on the frequency based on the output period of the crystal oscillator provided in the firing control unit 160. As a result, the number of games played per minute is about 99.9 (pieces / minute) because one shot is fired every time the firing solenoid rotates. That is, one game ball is fired about every 0.6 seconds.

  The ball feed solenoid 4b is composed of a linear solenoid, and sends out the game balls in the tray 40 one by one toward the launch member 4c directly connected to the launch solenoid 4a.

  Here, based on the control command from the main control unit 110 such as the effect control unit 120, the payout control unit 130, the lamp control unit 140, the image control unit 150, and the launch control unit 160 having the above-described configuration, or based on the control command. A control unit that performs control processing of the gaming machine 1 in accordance with a command generated based on the command, and the control units other than the intermediate control unit 180 are collectively referred to as a “peripheral control unit 300”. In addition, each control board on which each control unit of the peripheral control unit 300 is mounted, such as an effect control board on which the effect control unit 120 is mounted and a payout control board on which the payout control unit 130 is mounted, is collectively referred to as “peripheral control board” " The intermediate control unit 180, the lamp control unit 140, and the image control unit 150 can be mounted on the same substrate as the effect control unit 120. Further, the payout control unit 130 and the firing control unit 160 can be mounted on the same substrate as the main control unit 110.

[Internal configuration related to authentication processing of gaming machines]
The control means for realizing the security function that the gaming machine 1 having the above configuration has for preventing fraud will be described.
The security function of the gaming machine 1 according to the present embodiment is realized by the intermediate control unit 180 checking the validity of the control command transmitted from the main control unit 110 and authenticating the main control unit 110. The authentication result obtained by the intermediate control unit 180 is transmitted to the peripheral control unit 300, and processing according to the authentication result received by the peripheral control unit 300 is performed. For this purpose, the processing executed by the main control unit 110, the intermediate control unit 180, and the peripheral control unit 300 is referred to as “authentication processing” in the sense of distinguishing from processing related to normal game progress. In the present embodiment, the intermediate control unit 180 is provided between the effect control unit 120 of the peripheral control unit 300 and the main control unit 110, and the authentication result obtained by the intermediate control unit 180 is It is transmitted to the production control unit 120 of the peripheral control unit 300, and the production control unit 120 will be described as performing processing according to the authentication result.

  Specifically, when the main control unit 110 generates a control command and transmits it to the intermediate control unit 180 in this command transmission process, the main control unit 110 uses the control command generated before (past) the control command. An error check value is generated, and the generated error check value is added to the control command to be transmitted this time and transmitted. On the other hand, intermediate control unit 180 collates the error check value added to the control command received this time with the error check value generated using the control command received before (in the past) the control command. If the two match, the validity of the control command received this time is authenticated, and it is determined that the main control unit 110 has been successfully authenticated. Intermediate control unit 180 transmits the obtained authentication result for main control unit 110 to effect control unit 120. The effect control unit 120 confirms the authentication result transmitted from the intermediate control unit 180 and performs processing according to the authentication result.

  The control command generated before (in the past) by the main control unit 110 in the current command transmission process is stored in a predetermined storage area of the main control unit 110 (a storage circuit 522 of the generation unit 520 described later). Stored. Similarly, a control command received before (in the past) the control command received by the intermediate control unit 180 in the current command transmission process is stored in a predetermined storage area (a storage unit 622 described later) of the intermediate control unit 180. Yes.

  In the present embodiment, the control command generated in the current command transmission process is the control command (P), and the control command generated N (N: positive integer) before the control command (P) is the control command. (PN). The value of P (P; a positive integer) is stored in the predetermined storage area when the main control unit 110 and the intermediate control unit 180 are initialized at the time of resetting the gaming machine 1 such as immediately after the power is turned on. This is a value indicating how many control commands have been generated from immediately after the previous control command was cleared (hereinafter, P is referred to as “number of generations”).

  That is, in the present embodiment, the control command (1) means a control command that is first generated immediately after the control command stored in the predetermined storage area is cleared, and the control command (P) It means the P-th generated control command after the control command stored in the predetermined storage area is cleared. In addition, what is necessary is just to count the value of P of a production | generation number using a well-known counter etc. In the present embodiment, a generated number storage area (P) is provided in the main RAM 110c, and the main CPU 110a updates the value of the generated number storage area (P) by adding 1 during command transmission processing.

  In the present embodiment, an error check value generated using a control command (PN) generated N times before the control command (P) generated in the current command transmission process. The control command (P) to which (PN) is added and the error check value (PN) is added is transmitted to the intermediate control unit 180. The value of N is a value indicating how many error check values of the previously generated control command are added to the control command output in the current command transmission process (hereinafter, N is "Retrospective number").

  The possible range of the retroactive number N is limited by the storage capacity of a storage circuit 522 (and a storage unit 622, which will be described later) of the intermediate control unit 180, which is the predetermined storage area. Is optional. If the value of N is large, it becomes more difficult for an unauthorized person to analyze the relationship between a control command and an error check value added to the control command, and illegal acts can be further prevented.

  If the main control unit 110 generates a control command (P) and transmits it to the intermediate control unit 180, the retroactive number N is set to what number before the control command transmitted this time. It can be considered that the number is determined as to whether an error check value of the transmitted control command is added, and such a concept is also included in the present invention.

  Further, in the present embodiment, after generating an error check value (PN) to be added to the control command (P), a bit operation is performed on the bit string of the generated error check value (PN) to obtain an error. A process (hereinafter referred to as “bit string conversion process”) for appropriately converting the bit string of the inspection value (PN) is performed. In the present embodiment, when performing bit string conversion processing on the error check value (PN), a bit operation method (hereinafter referred to as “conversion method”) performed on the bit string of the error check value (PN). As a method, a bit rotation operation is performed on the bit string of the error check value (PN) to convert the bit string.

  In addition, a plurality of conversion methods are prepared in advance as conversion methods for performing bit string conversion processing on the error check value (PN). The number of conversion methods prepared in advance is not particularly limited in the present invention, but in this embodiment, two conversion methods are prepared in advance. Specifically, in this embodiment, in a bit rotation operation performed in one bit string conversion process, a method of determining a “shift amount” that indicates how many bits each bit constituting the bit string is shifted. Accordingly, two conversion methods are prepared in advance.

  More specifically, a conversion method (hereinafter referred to as “conversion method A”) in which the shift amount regularly varies according to a rule previously determined between the main control unit 110 and the intermediate control unit 180, and the shift amount These are two conversion methods that are not determined in advance between the main control unit 110 and the intermediate control unit 180 and that change randomly (hereinafter referred to as “conversion method B”). In the present embodiment, the shift amount used in the bit rotation operation when performing the bit string conversion processing by the conversion method A is referred to as “shift amount A”, and is used in the bit rotation operation when performing the bit sequence conversion processing by the conversion method B. The shift amount is referred to as “shift amount B”.

  In this embodiment, the bit string conversion process is performed on the error check value (PN) while properly using the two conversion methods prepared in advance. Specifically, it is determined in advance that one of conversion method A and conversion method B is used as the default conversion method. When the bit string conversion process is performed on the error check value (PN), based on the control command (P) generated in the command transmission process this time, a predetermined conversion method change rule (hereinafter, referred to as the conversion command) According to “change protocol”), the conversion method set up to now is changed to a new conversion method.

  In the present embodiment, a conversion unit used in the bit string conversion process is determined by a determination unit 540 described later. The determination unit 540 determines the conversion method, and will be described later so that the bit string conversion process is performed using the determined conversion method. The process for setting the generation unit 520 is referred to as “conversion method setting process”. In addition, a condition for the control command (P) generated in the current command transmission process to be a control command for changing the conversion method is referred to as a “change condition”. In the present embodiment, a plurality of change conditions are also used for the change condition. Are prepared in advance. Details of the change protocol and the change condition will be described later.

  In the present embodiment, the generation unit 520 described later updates the shift amount used in the bit rotation calculation when performing the bit string conversion processing. However, the generation unit 520 updates the shift amount, and the updated shift amount is used as a bit. A process for setting a rotate arithmetic unit that bears a bit string conversion circuit 525, which will be described later, so that the rotate calculation is performed is referred to as a “shift amount setting process”. In the shift amount setting process, the shift amount A is appropriately updated in order to change the shift amount A regularly, and the shift amount B is appropriately updated in order to randomly change the shift amount B. In the present embodiment, as conditions for defining at what timing the shift amounts A and B are updated (hereinafter referred to as “update timing conditions”), there are a plurality of update timing conditions related to the shift amount A. Is prepared in advance, and one condition is prepared in advance for the update timing condition related to the shift amount B.

  As described above, in this embodiment, the error check value added to the control command (P) generated in the current command transmission process is the control command (P) generated N times before the control command (P). -N) is an error check value (PN) generated by using the conversion method A or the conversion method B, and is an error check value (PN) that has been subjected to bit string conversion processing. At this time, if the control command (P) is a control command that satisfies the change condition, the bit string conversion is performed on the error check value (PN) after changing the conversion method set up to the present to a new conversion method. Applied. Then, an error check value (PN) that has been subjected to bit string conversion processing by a new conversion method is added to the control command (P). Further, in the present embodiment, even if the shift amount A and the shift amount B are updated as appropriate and the bit string conversion process is performed by any one of the conversion methods, the result of the bit rotation operation varies depending on the timing of performing the bit string conversion process. Will vary. Details of the update of the shift amount A and the shift amount B will be described later.

  FIG. 5 is a functional block diagram showing an internal configuration related to authentication processing of the main control unit 110 according to the present embodiment. FIG. 6 is a schematic diagram for explaining a memory map of (a) main ROM 110b and (b) boot ROM 110d according to the present embodiment. FIG. 7 is a schematic diagram for explaining a procedure for adding an error check value to a control command according to the present embodiment. In FIG. 6, areas other than the characteristic area of the present invention are omitted. The address notation such as “xxxFH” is provided for convenience in order to indicate the division of each region, and the positional relationship between the regions is not limited to the positional relationship shown in FIG. .

  In addition to the main CPU 110a, the main ROM 110b, and the boot ROM 110d as described above, the main control unit 110 includes a test value generation unit 500 that performs error check value generation processing and addition processing based on control instructions from the main CPU 110a, And a transmission unit 550 that performs processing for transmitting a control command to the control unit 180. Each component of the main control unit 110 is connected by a bus (not shown) so that various data and signals output from the main control unit 110 can be transmitted and received.

  The bus has at least the functions of an address bus, a data bus, and a control bus, assigns data passing on the bus based on control signals output from each component of the main control unit 110, and does not cause data collision So that it is controlled. In FIG. 5, for convenience, it is not shown in the form of a bus, but is represented as a signal line that connects each component of the main control unit 110, and only the characteristic ones are shown. In addition, a predetermined clock signal output from a clock pulse generation circuit (not shown) is input to each component of the main control unit 110.

  The main CPU 110a executes processing related to game progress as described above, and also executes authentication processing in the gaming machine 1. The main CPU 110a executes various arithmetic processes using an authentication processing program and various fixed data stored in the main ROM 110b. Further, the main CPU 110a executes various arithmetic processes using a boot processing program stored in the boot ROM 110d and various initial values stored in the main ROM 110b. Then, the main CPU 110a outputs a control signal and a control command according to the result of these arithmetic processes.

  For example, when the main CPU 110a performs a command transmission process of a control command to be transmitted to the intermediate control unit 180, a control signal for writing the control command to the inspection value generation unit 500 (hereinafter referred to as “write signal”). And the control command is transmitted by the transmission unit 550 via the inspection value generation unit 500.

  Further, the main CPU 110a, when performing initial value setting processing during boot processing based on the boot processing program, reads control signals (hereinafter referred to as “read signals”) for reading various initial values stored in the main ROM 110b. To obtain various initial values, and outputs the obtained initial values to the configuration circuit corresponding to each of the obtained initial values to perform various initial value settings.

  When the main CPU 110a needs to set unique information (described later) in the test value generation unit 500 during the initialization process of the main control unit 110, the main CPU 110a outputs a read signal for reading the unique information stored in the main ROM 110b. A process of outputting and acquiring the unique information and setting the acquired unique information in the inspection value generation unit 500 is performed.

  In addition to the game processing program and data as described above, the main ROM 110b stores in advance an authentication processing program for the main CPU 110a to execute the authentication processing in the gaming machine 1 (FIG. 6A). (Region of “xxx0H” to “xxxzFH”). The main ROM 110b stores unique information of the gaming machine 1 used as an error check value added to a control command that is output for the first time after the main control unit 110 is initialized (in FIG. 6A). “Xyz0H” to “xzzFH”). Further, the main ROM 110b outputs an authentication processing program code, unique information, and the like in response to a read signal from the main CPU 110a.

  The unique information is not particularly limited as long as it is unique to the gaming machine 1 held by the main control unit 110. In FIG. 6A, the unique information is data (for example, control) in a specific address (area “xyz0H” to “xzzFH” in FIG. 6A) in the area where the fixed data of the main ROM 110b is stored. Command data), for example, a checksum value at a specific address in an area (the area from “0000H” to “xxxFH” in FIG. 6A) in which the program code of the main ROM 110b is stored, An identification number (ID) uniquely assigned to the main CPU 110a, product information such as a manufacturer code and a model code, and the like can be used. In addition, the unique information can be dummy data of an error check value that is negotiated with the intermediate control unit 180 in advance. These data may be values obtained by performing four arithmetic operations or logical operations. The unique information may be stored in storage means (memory cell, ROM, etc.) separate from the main ROM 110b.

  The error check value generated by the main control unit 110 is generated using a past control command stored in a storage circuit 522 described later, which is the predetermined storage area. However, when the main control unit 110 is initialized, such as when the gaming machine 1 is reset, the past control command stored in the storage circuit 522 is cleared, and this is used to generate an error check value. Can not do it. Therefore, in the present embodiment, when the past control command stored in the storage circuit 522 is cleared, unique information stored in advance in the main ROM 110b is used as an initial setting value for the storage circuit 522.

  In the present embodiment, N pieces of unique information are prepared as unique information for the storage circuit 522. When the control command of the storage circuit 522 is cleared by the initialization of the main control unit 110, the main CPU 110a refers to the value of the generated number storage area (P) of the main RAM 110c and is unique to the storage circuit 522. Determine whether information needs to be set. When the value of the generated number storage area (P) is P = 1, the main CPU 110a sets unique information in the storage circuit 522 as an initial setting value. In the present embodiment, an error check value generated using unique information without using a control command is also referred to as an “initial check value”.

  The main ROM 110b has one of the initial values (so-called hardware parameters) of the built-in circuit and peripheral circuits of the one-chip microcomputer 110m as described above, and is a hardware parameter (hereinafter referred to as a “test value generation unit 500”). , “HW parameter”) is stored in advance (regions “yyy0H” to “yyzFH” in FIG. 6A). The HW parameter is selection information for selecting which error check value addition function is to be adopted from among the functions (error check value addition function) for generating and adding a plurality of error check values that the check value generation unit 500 has. is there. The error check value addition function and its selection information are determined in advance between the main control unit 110 and the intermediate control unit 180.

  In the present embodiment, as a specific embodiment of a plurality of error check value addition functions, the check value generation unit 500 has a plurality of update timing conditions related to a plurality of change conditions and shift amounts A as described above. It is prepared. That is, depending on which change condition is adopted, the type of control command that satisfies the change condition also changes. When the type of the control command that satisfies the change condition changes, the conversion method used when the bit string conversion process is performed for the error check value added to the control command transmitted at a certain time also changes. As a result, the bit string of the error check value added to the control command also changes according to the adopted change condition. Furthermore, depending on which update timing condition is adopted, the timing at which the shift amount A when the bit string conversion process is performed in the conversion method A also changes, and an error check added to a control command transmitted at a certain time point For the value, the shift amount used in the bit rotation operation of the conversion method A also changes. As a result, the bit string of the error check value added to the control command changes according to the adopted update timing condition. In the present embodiment, during the initial value setting process during the boot process, a specific condition among a plurality of change conditions prepared in advance for the inspection value generation unit 500 is set and the shift amount A is related. A specific condition among the plurality of update timing conditions is set. The HW parameter is selection information for selecting which condition is adopted as the specific change condition and update timing condition.

  In this embodiment, a plurality of HW parameters associated with each of a plurality of change conditions are prepared in advance and stored in advance in a determination unit 540 described later of the inspection value generation unit 500. In the present embodiment, a plurality of HW parameters associated with each of a plurality of update timing conditions related to the shift amount A are prepared in advance and stored in advance in a generation unit 520 described later of the inspection value generation unit 500. ing. When the main CPU 110a sets a specific HW parameter in the test value generation unit 500 during the initial value setting process during the boot process, the test value generation unit 500 confirms the set HW parameter and sets the HW parameter. The corresponding change condition and update timing condition are used as default conditions.

  In the present embodiment, in the setting process performed by the main CPU 110a and the initial value setting process during the boot process, the process of setting a specific HW parameter in the test value generation unit 500 is particularly referred to as “HW parameter setting process”. Further, in the present embodiment, a setting process performed by the inspection value generation unit 500, a default change condition is determined along with the HW parameter setting process, and the determined change condition is described later which configures the inspection value generation unit 500. The process set for the determining means 540 is referred to as “change condition setting process”. Further, in the present embodiment, a setting process performed by the test value generation unit 500, a default update timing condition related to the shift amount A is determined in accordance with the HW parameter setting process, and the determined update timing condition is set as the test value. A process that is set for a generation unit 520 (to be described later) constituting the generation unit 500 is referred to as an “update timing condition setting process”.

  The area for storing the initial value and the HW parameter is the area in the main ROM 110b in FIG. 6, but the present invention is not limited to this, and the area is stored in a memory cell separate from the main ROM 110b or the boot ROM 110d. It can also be configured to be stored in. That is, in the present invention, the storage area for the initial value and the HW parameter and the storage area for the game processing program, fixed data, etc. may be mounted on the same storage means (memory cell, ROM, etc.). It may be mounted on different storage means.

  The boot ROM 110d stores a boot processing program and fixed data used when executing the boot processing program in advance (regions “zxx0H” to “zyzFH” in FIG. 6B). The boot processing program is set in advance to be read from the boot ROM 110d into a boot processing dedicated RAM (not shown) immediately after the main CPU 110a is started, and to be executed by the main CPU 110a. It controls diagnosis processing, initialization of a built-in circuit of the one-chip microcomputer 110m on which the main CPU 110a is mounted, peripheral circuits including the test value generation unit 500, and initial value setting processing (that is, initial value setting processing). In the present embodiment, a program other than the boot processing program such as a game processing program executed after the boot processing is referred to as a “user program”.

  The boot processing program is a program developed and implemented by a CPU manufacturer, and access to the boot ROM 110d in which these programs are stored is limited to access from the main CPU 110a during boot processing after the gaming machine 1 is shipped. . On the other hand, the user program is a program developed and implemented by a gaming machine manufacturer, and access to the main ROM 110b in which these are stored is accessed from the main CPU 110a every time a game process is executed.

  However, even in the storage area of the main ROM 110b, user programs, fixed data, etc. (such as areas in which initial values (including HW parameters) such as built-in circuits of the one-chip microcomputer 110m and peripheral circuits including the test value generation unit 500 are stored) A storage area other than the area in which the unique information is stored (for example, an area from “xxx0H” to “yyzFH” in FIG. 6A) is an area defined only in the boot processing program, It is an area that does not appear at all on the user program related to game processing. That is, after the boot process is completed, the above-mentioned area ("xxx0H" to "yyzFH" in FIG. 6A) is an area that is substantially restricted so that it cannot be accessed from the user program. ing.

  However, in consideration of the case where unauthorized access is attempted, the following additional restrictions can be applied to further improve the confidentiality of the HW parameters obtained only during the boot process.

  To restrict access to the boot ROM 110d and the main ROM 110b, for example, an execution address monitoring unit (not shown) is provided in the main control unit 110, and the execution address monitoring unit is activated after the boot process is completed. If an attempt is made to access an area exceeding (for example, the area from “0000H” to “xzyFH” in FIG. 6A), a reset signal is output to the main CPU 110a to stop the operation of the main CPU 110a. Good. Further, a notification signal indicating that an abnormality has been detected may be output before the reset signal is output.

  A plurality of methods are conceivable for mounting the HW parameters in the main ROM 110b. For example, a plurality of HW parameters corresponding to each of a plurality of change conditions prepared in advance in the inspection value generation unit 500 and a plurality of update timing conditions related to the shift amount A are prepared in advance and mounted in the main ROM 110b. In the HW parameter setting process, a program for selecting which HW parameter to use is installed in the boot ROM 110d, and any change condition and update timing condition are arbitrarily used for each boot process. It can be configured to be selectable. When implemented in this way, the change condition and the update timing condition are changed every time the boot process is performed, the confidentiality of the error check value addition function can be improved, and the security strength of the gaming machine 1 can be improved.

  On the other hand, although a plurality of change conditions, update timing conditions related to the shift amount A, and HW parameters provided in the inspection value generation unit 500 are prepared in advance, only specific HW parameters are mounted on the main ROM 110b and the corresponding specification It is also possible to configure so that only the change condition and the update timing condition are adopted. When implemented in this way, it is not necessary to newly provide a program associated with the HW parameter selection process in the boot process, and the code size of the program is not increased. Also, when implemented in this way, even if a gaming machine manufacturer wants to adopt only specific modification conditions and update timing conditions, it can handle the desired modification conditions and update timing conditions in the program implementation process performed by the gaming machine manufacturer. It is sufficient that only the HW parameters are mounted on the main ROM 110b, and it is possible to flexibly cope with the usage and preference of the gaming machine manufacturer.

  Even in this case, since the HW parameter is stored in a storage area that is not accessed except when the initial value is set during the boot process of the main control unit 110, the contents of the change condition and update timing condition are externally set. I can't know. Therefore, it is difficult for an unauthorized person to analyze the change condition and the update timing condition adopted in the gaming machine 1, and the confidentiality of the error check value adding function of the gaming machine 1 is ensured. In addition, by changing the HW parameters used for design / verification work during the development stage of the gaming machine 1 and the HW parameters that are actually mounted thereafter, it is possible to know which HW parameters are finally mounted. The person who obtains it is limited, and the confidentiality of the error check value adding function is further improved. In the present embodiment, it will be described that only specific HW parameters corresponding to specific change conditions and update timing conditions are mounted in the main ROM 110b.

  The inspection value generation unit 500 is provided between the main CPU 110a and the transmission unit 550. The connection between the main CPU 110a and the inspection value generation unit 500 and the connection between the inspection value generation unit 500 and the transmission unit 550 are bus-connected as described above, and the buses used for each connection are the same standard. It has become a bus. That is, a method (hereinafter referred to as “input / output control format”) for controlling data transmission / reception between each of the input interface on the main CPU 110a side of the inspection value generation unit 500 and the input interface on the inspection value generation unit 500 side of the transmission unit 550. “)” Is a method corresponding to the input / output control method set in the output interface on the inspection value generation unit 500 side of the main CPU 110a. As the bus standard, a known standard may be used.

  In the present embodiment, the input / output control method of the output interface on the inspection value generation unit 500 side of the main CPU 110a is referred to as “CPU interface method”. The CPU interface method may use a known input / output control method determined based on the above bus standard, and the bus standard between the main CPU 110a and the transmission unit 550 before the test value generation unit 500 is added. The input / output control method determined based on The output interface on the transmission unit 550 side of the inspection value generation unit 500 is also configured by the CPU interface method.

  The CPU interface system of this embodiment will be specifically described. For example, when the main CPU 110a outputs a control command to the test value generation unit 500, the main CPU 110a uses the control command as the data bus, the address data specifying the predetermined storage area of the test value generation unit 500 as the address bus, and the control bus. Outputs a write signal. This address data is converted into a chip select signal via a decoder and input to the inspection value generation unit 500. When the chip select signal and the write signal become active (in this embodiment, the fact that the control signal becomes active is also referred to as “the control signal is input”), the inspection value generation unit 500 takes in the control command on the data bus. . With such an input / output control method, a control command is output from the main CPU 110 a to the inspection value generation unit 500. The same applies when the main CPU 110a outputs the HW parameter to the inspection value generation unit 500.

  Also, when the test value generation unit 500 outputs a control command to the transmission unit 550, the test value generation unit 500 also includes address data that specifies a control command for the data bus and a predetermined storage area of the transmission unit 550 for the address bus, A write signal is output to the control bus. Then, when the chip select signal and the write signal of the address data are input, the transmission unit 550 takes in the control command on the data bus, and the control command is transferred from the test value generation unit 500 to the transmission unit 550. The same applies when the inspection value generation unit 500 outputs the error inspection value to the transmission unit 550.

  In the present embodiment, the output address data is converted to a chip select signal and then input to a designated component in the main control unit 110. Conversion from address data to a chip select signal Description of is omitted.

  In this embodiment, a bus having a bit width equal to or greater than the data length of the smaller one of the control command and the error check value may be provided. For example, if the control command is 2-byte data and the error check value is 1-byte data, the bit width of the data bus may be at least 1 byte. In this case, the main CPU 110a and the test value generation unit 500 first output the upper 1 byte of the 2-byte control command to the data bus, and then output the lower 1 byte to the data bus. Subsequently, the check value generation unit 500 outputs a 1-byte error check value to the data bus.

  The check value generation unit 500 performs a function of adding an error check value to the control command output from the main CPU 110a and outputting the control command to the transmission unit 550, and includes a change condition setting process, an update timing condition setting process, and a conversion method setting process. This is a circuit that executes all the processes of the main control unit 110 related to realizing the security function of the gaming machine 1, such as a shift amount setting process, a test value generation process, a bit string conversion process, and a test value addition process. Specifically, the inspection value generation unit 500 includes at least a buffer unit 510, a determination unit 540, a generation unit 520, and an addition unit 530. Each means of the inspection value generation unit 500 is configured by a wired logic control system.

  In the present embodiment, data transmission / reception between each means in the test value generation unit 500 and between each circuit in each means is performed in synchronization with the clock signal output from the clock pulse generation circuit of the main control unit 110. . For this reason, in this embodiment, the input / output control method of each means and each circuit in the test value generation unit 500 is referred to as a “synchronous interface method”. In the synchronous interface method, when an enable signal or the like is output to a connection destination of data to be output, the connection destination takes in the output data based on inputs of the enable signal and a clock signal. Therefore, the synchronous interface method is different from the CPU interface method that requires address data (chip select signal) and a write signal transmitted via the bus.

  The buffer unit 510 is a circuit that inputs and temporarily holds a control command or unique information output from the main CPU 110a in command transmission processing after boot processing. The buffer unit 510 is a circuit that outputs the held control command to the subsequent determination unit 540, generation unit 520, and addition unit 530. When the unique information is input, it is output only to the generation means 520. That is, the buffer unit 510 temporarily holds a control command that the main CPU 110a transmits to the intermediate control unit 180, and executes the command transmission process execution timing of the main CPU 110a, and the conversion method setting process and generation unit of the subsequent determination unit 540. It plays a role of adjusting the execution timing of the inspection value generation process 520, the bit string conversion process, the shift amount setting process, and the inspection value addition process of the adding means 530.

  Data transmission / reception is controlled between the input side of the buffer means 510 and the main CPU 110a by the input / output control method corresponding to the CPU interface method as described above. On the other hand, on the output side of the buffer unit 510, data transmission / reception is controlled by the synchronous interface method with the subsequent determination unit 540, generation unit 520, and addition unit 530. That is, the buffer unit 510 has different input / output control methods on its input side and output side, and plays a role of matching the CPU interface method of the main CPU 110a with the synchronous interface method in the test value generation unit 500. Yes.

  The buffer unit 510 includes at least a data buffer 511 and a control circuit 512. The data buffer 511 is a circuit that captures and holds control commands and unique information output from the main CPU 110a via a data bus. The control circuit 512 is a circuit that controls the operation of the data buffer 511 based on the input of a control signal output from the main CPU 110a.

  Specifically, the control circuit 512 receives a write signal for writing a control command or unique information output from the main CPU 110 a into the data buffer 511 of the buffer unit 510 and address data designating the buffer unit 510. Then, an enable signal (hereinafter referred to as “operation permission signal”) for operating the data buffer 511 to take in a control command and specific information on the data bus is output. The data buffer 511 takes in a control command and unique information on the data bus based on the input of the operation permission signal.

  In addition, the control circuit 512 outputs an operation permission signal for causing the control command and the unique information taken in by the data buffer 511 to be output to the determination unit 540, the generation unit 520, and the addition unit 530. Based on the input of the operation permission signal, the data buffer 511 outputs the captured control command to the determination unit 540, the generation unit 520, and the addition unit 530, and outputs the captured unique information to the generation unit 520.

  The control circuit 512 controls the determination circuit 541 of the determination unit 540 and the generation unit 520 so that the control command output from the data buffer 511 can be input by the determination unit 540, the generation unit 520, and the addition unit 530. An operation permission signal is output to the circuit 523 and the control circuit 532 of the adding means 530. Note that the timing at which the control circuit 512 outputs each operation permission signal is determined by each unit to input the control signal and the clock signal from the main CPU 110a while taking into account the operation time of each unit in the test value generation unit 500. The timing is set in advance so that it can operate normally in synchronization with the timing.

  Further, the control circuit 512 outputs an operation permission signal to the control circuit 523 of the generation unit 520 so that the unique information output from the data buffer 511 can be input by the generation unit 520. In FIG. 5, only the control command is described in the data line extending from the data buffer 511 to the generation unit 520. However, also in the unique information, the data buffer 511 to the generation unit 520 via the data line. Is output.

  The determination unit 540 is a circuit that determines a default change condition and sets the conversion method to be changed based on the determined change condition. Further, the determination unit 540 determines a conversion method for performing the bit string conversion process on the error check value added to the control command output from the buffer unit 510, and checks the error of the bit string converted using the determined conversion method. This is a circuit for setting the generation means 520 so that a value is output. That is, the determination unit 540 plays a role of executing the change condition setting process and the conversion method setting process of the inspection value generation unit 500.

  Specifically, the determination unit 540 determines a default change condition based on the HW parameter set from the main CPU 110a as a change condition setting process during the boot process, and sets according to the determined change condition. I do. In addition, during the boot process, the determination unit 540 performs setting in the generation unit 520 according to a predetermined default conversion method as a conversion method setting process. Further, in the command transmission process after the boot process, the determination unit 540 inputs the control command output from the buffer unit 510 as the conversion method setting process, and determines the conversion method based on the input control command. Then, the generation unit 520 is set according to the determined conversion method.

  The determination unit 540 includes at least a determination circuit 541 and a determination circuit 542. The determination circuit 541 receives the control command output from the buffer unit 510, executes a determination process as to whether or not the input control command is a control command that satisfies the change condition, and notifies the determination circuit 542 of the determination result. Circuit. Specifically, the determination circuit 541 includes a change condition storage unit 541a that stores a change condition in advance, and a comparator 541b that compares the input control command with the change condition.

  The change condition storage unit 541a includes a register or the like, and the input side of the change condition storage unit 541a is connected to the determination circuit 542 through a data line. The output side of the change condition storage unit 541a is connected to the comparator 541b by a data line. Then, when the default change condition corresponding to the HW parameter set in the HW parameter setting process is output from the determination circuit 542, the change condition storage unit 541a captures and stores the change condition, and changes the change condition. The bit pattern is output to the comparator 541b.

  The comparator 541b is composed of an equal comparator, a magnitude comparator or the like that can compare the number of bits equal to or greater than that of the change condition storage 541a, and the input side of the comparator 541b is the data buffer of the change condition storage 541a and the buffer means 510. 511 and the data line, respectively. The output side of the comparator 541b is connected to the determination circuit 542 through a control line.

  The comparator 541b inputs the control command output from the data buffer 511 during the command transmission process based on the input of the operation permission signal output from the control circuit 512. Subsequently, the comparator 541b compares the bit pattern of the control command with the bit pattern of the change condition output from the change condition storage unit 541a. Subsequently, the comparator 541b outputs a control signal (hereinafter referred to as “determination result signal”) for notifying the determination result of whether or not the input control command is a control command satisfying the change condition.

  The comparator 541b compares the input control command with the change condition, and if the two match, the comparator 541b determines a determination result signal indicating that the control command output from the buffer means 510 is a control command satisfying the change condition. Output to 542. On the other hand, if they do not match, the comparator 541b outputs a determination result signal indicating that the control command output from the buffer means 510 is not a control command satisfying the change condition to the determination circuit 542.

  The change condition is basically arbitrary if it is agreed with the intermediate control unit 180 in advance. For example, in this embodiment, it is possible to set various conditions such as whether or not the number of input control commands output from the buffer unit 510 (that is, the number P of generated control commands) is a predetermined number. In the present embodiment, whether or not the type of the control command output from the buffer unit 510 corresponds to a predetermined control command is set as a change condition. The changing conditions in this embodiment will be described below.

  Various gaming states that appear as the game progresses are set in the gaming machine 1, and the main control unit 110 performs control processing in various operation modes according to the gaming state. Then, during a predetermined operation mode period, a predetermined control command group corresponding to the operation mode is generated and transmitted to the effect control unit 120. At this time, the predetermined control command group includes control commands that can confirm the transition of the operation mode by the main control unit 110 and the intermediate control unit 180, such as a control command indicating the start and end of the operation mode period. Yes.

  For example, as will be described later with reference to FIG. 9, in the operation mode of the jackpot state, an opening designation command indicating the start of various jackpot states (in FIG. 9, a control command whose information of “MODE” is “EBH”) ) And an ending designation command (control command in which “MODE” information is “ECH” in FIG. 9) indicating the end of various jackpot states are generated and transmitted to the intermediate control unit 180, respectively. Further, for example, in the operation mode of the short-time gaming state, the short-time operation gaming state designation command (in FIG. 9, the information of “MODE” is “EEH”) in accordance with the transition from the non-short-time gaming state to the short-time gaming state. And a control command whose information of “DATA” is “01H” is generated and transmitted to the intermediate control unit 180. Then, along with the transition from the short-time gaming state to the non-short-time gaming state, the short-time non-operating gaming state designation command (in FIG. 9, “MODE” information is “EEH” and “DATA” information is “00H”. A certain control command) is generated and transmitted to the intermediate control unit 180.

  In this embodiment, during the period of the predetermined operation mode, that is, during the period during which the predetermined control command group is transmitted, the conversion method of the error check value used in the bit string conversion processing is the conversion method B, and the others The conversion method is referred to as conversion method A. Therefore, in this embodiment, the default conversion method is determined as the conversion method A, and the conversion method is changed to the conversion method B at the time of command transmission processing related to the control command generated first in the predetermined control command group. Decide to change. Then, it is determined that the conversion method is returned to the conversion method A in the command transmission process related to the control command generated first after the generation of the predetermined control command group is completed. That is, in the present embodiment, the type of the control command (P) output from the buffer unit 510 is the first control command generated in the predetermined control command group, and the generation of the predetermined control command group has been completed. The change condition is whether or not one of the first control commands generated later is applicable. In this manner, in the bit string conversion processing of the present embodiment, the conversion method A is used as the default conversion method, the conversion method B is used when the predetermined operation mode period starts, and the predetermined operation mode is changed. When the period ends, conversion method A is used.

  In the present embodiment, as a type of the predetermined control command group, a control command group that can predict how each control command constituting the control command group will appear during a predetermined operation mode period. Use. By using a control command group in which the appearance of each control command can be predicted, the intermediate control unit 180 side suppresses the number of trials when performing a bit string conversion process on the received error check value (PN). Can do.

  Further, as the type of the predetermined control command group, for example, a control command group having a high appearance frequency can be adopted. In this case, since the period in which the conversion method B is adopted frequently arrives, an error check value that has been subjected to bit string conversion processing with a random shift amount is frequently transmitted. For this reason, it is difficult to analyze the correspondence between the control command and the error check value, and the security strength can be improved. Further, as the type of the predetermined control command group, for example, a control command group with a low appearance frequency can be employed. In this case, since the period of adopting the conversion method B arrives only at a low frequency, the opportunity for stealing the control command and the error check value using the conversion method B is reduced. For this reason, it is difficult for an unauthorized person to steal control commands and error check values with a sufficient number of samples to analyze the correspondence between control commands and error check values. It becomes difficult to analyze, and the security strength can be improved.

  The predetermined control command group type may be a single control command group type or a plurality of control command group types. Adopting multiple types of control command groups means that the period for adopting conversion method B increases, so that the correspondence between control commands and error check values becomes more difficult to analyze, and security strength can be improved. it can.

  On the other hand, the determination circuit 542 determines a default change condition according to the HW parameter set from the main CPU 110a, and sets the determination circuit 541 so that the determination circuit 541 executes the determination process according to the determined change condition. It is a circuit which performs. In addition, the determination circuit 542 determines a conversion method according to the determination result signal of the determination circuit 541, and performs a setting to the generation unit 520 so that the generation unit 520 performs the bit string conversion process according to the determined conversion method. It is.

  The input side of the decision circuit 542 is connected to the main CPU 110a via a bus, and data transmission / reception is controlled with the main CPU 110a by an input / output control method corresponding to the CPU interface method. Then, the decision circuit 542 takes in the HW parameter output from the main CPU 110a from the data bus during the HW parameter setting process. Further, the input side of the decision circuit 542 is connected to the determination circuit 541 through a control line, and data transmission / reception is controlled between the determination circuit 541 and the input / output control method corresponding to the synchronous interface method. Then, the determination circuit 542 receives the determination result signal output from the determination circuit 541.

  Further, the output side of the determination circuit 542 is connected to the change condition storage unit 541a of the determination circuit 541 through a data line, and is also connected to the control circuit 523 of the generation unit 520 through a control line. Data transmission / reception is controlled by the synchronous interface method. Then, the determination circuit 542 outputs one of a plurality of change conditions prepared in advance to the determination circuit 541 according to the HW parameter set from the main CPU 110a. In addition, the determination circuit 542 determines a conversion method according to the determination result signal output from the determination circuit 541 and outputs a control signal for setting the determined conversion method to the generation unit 520.

  Specifically, the determination circuit 542 is provided with a data table that shows the correspondence between a plurality of change conditions prepared in advance and a plurality of HW parameters. Then, the determination circuit 542 can uniquely determine a specific change condition based on the captured HW parameter. Then, in the HW parameter setting process, the determination circuit 542 stores a change condition corresponding to the HW parameter set from the main CPU 110a in the change condition storage area (D) as a default change condition. Then, the determination circuit 542 outputs the change condition stored in the change condition storage area (D) to the change condition storage unit 541a of the determination circuit 541.

  The determination circuit 542 generates conversion method information that is information indicating the conversion method determined according to the determination result signal output from the determination circuit 541. The conversion method information may be a value such as an identification number that can identify the conversion methods A and B, which are the two conversion methods prepared in advance. The determination circuit 542 is provided with a conversion method information storage area (S) for storing conversion method information. The conversion method information indicating the conversion method determined according to the determination result signal is converted into the conversion method information storage area. Store in (S).

  In the present embodiment, a specific aspect of the conversion method is represented by a plurality of rotate calculators (rotate calculators A and B in FIG. 5) provided in a bit string converter circuit 525 described later of the generation unit 520. ing. Specifically, the conversion method A corresponds to the rotate calculator A, and the conversion method B corresponds to the rotate operator B. The determination circuit 542 is provided with a data table that shows the correspondence between the conversion method information and the plurality of rotation calculators.

  The determination circuit 542 stores the conversion method information indicating the default conversion method A in the conversion method information storage area (S) during the conversion method setting process during the boot process. Then, the decision circuit 542 uses the value stored in the conversion method information storage area (S) to obtain the error check value that has been subjected to the bit string conversion processing by the rotate computing unit A corresponding to the default conversion method A. A control signal (hereinafter referred to as “conversion method control signal”) to be output from the bit string conversion circuit 525 to the adding unit 530 is output to the control circuit 523 of the generation unit 520.

  In the conversion method information storage area (S), when the conversion method is changed, the S value of the conversion method information indicating the changed conversion method (hereinafter, the value of the converted conversion method information is set to “ S '") is stored. When the conversion method is changed in the current command transmission process, the determination circuit 542 confirms the value of the conversion method information storage area (S) that stores the conversion method information indicating the conversion method after the change. It is possible to grasp the conversion method when the bit string conversion process is performed on the error check value to be output from the generation unit 520 to the addition unit 530 in the command transmission process.

  Further, the determination circuit 542 is provided with a generation number storage area (P) for storing the value of the number of generations of control commands up to the present, similarly to the main RAM 110c. When the determination circuit 542 detects that the determination result signal is output from the determination circuit 541, the determination circuit 542 adds 1 to the value of the generated number storage area (P) and updates it. As a result, the determination circuit 542 clears the control command output from the buffer unit 510 corresponding to the output of the determination result signal, and the control command stored in the storage circuit 522 after the main control unit 110 is initialized. It can be grasped that the control command (P) is generated in the P-th time since the generation.

  The value of the generated number storage area (P) provided in the main RAM 110c and the value of the generated number storage area (P) provided in the determination circuit 542 are the same value, and the control command output from the buffer means 510 is obtained. (P) is the same as the control command (P) actually output from the main CPU 110a.

  In the present embodiment, as described above, the main CPU 110a determines whether or not the unique information needs to be set in the storage circuit 522 of the generation unit 520, but the determination circuit 542 may determine it. For example, when the HW parameter is set, the determination circuit 542 notifies the buffer unit 510 to that effect. Then, the buffer unit 510 may output a control signal for requesting the main CPU 110a to output the unique information and output the unique information stored in the main ROM 110b.

  Further, the determination circuit 542 changes the conversion method according to the conversion method change protocol negotiated with the intermediate control unit 180 in advance in the conversion method setting process after the boot process. Specifically, the determination circuit 542 confirms the determination result signal output from the determination circuit 541 and grasps whether or not the control command output from the buffer unit 510 is a control command that satisfies the change condition. Then, if the control command output from the buffer means 510 is a control command that satisfies the change condition, the decision circuit 542 sets the value of the conversion method information storage area (S) according to a predetermined change method at a predetermined change timing. change. That is, the change protocol includes at least the change condition for determining whether or not the conversion method should be changed, a conversion method change timing setting method, and a conversion method change method.

  As described above, in the present embodiment, the change condition is that the control command output from the buffer unit 510 is generated first in the predetermined control command group, and the predetermined control command group is generated. Whether it corresponds to one of the first control commands generated after completion.

  The conversion method change method is basically arbitrary as long as it is agreed with the intermediate control unit 180 in advance. In this embodiment, two conversion methods A and B are prepared, and the default conversion method is the conversion method A. At this time, for example, every time a control command that satisfies the change condition is output, a method of determining the conversion method from conversion method A → conversion method B and conversion method B → conversion method A can be considered. Further, for example, every time a control command that satisfies the change condition is output, a method of operating a random number generation circuit prepared in advance and determining a conversion method corresponding to the obtained random number value can be considered. However, when using a random number generation circuit, it is necessary to notify the intermediate control unit 180 of the obtained random number value or to prepare a random number generation circuit that operates in synchronization with the random number generation circuit in the intermediate control unit 180 as well. . As the change method negotiated in the present embodiment, a method is adopted in which the conversion method is determined as conversion method A → conversion method B each time a control command that satisfies the change condition is output.

  In addition, the conversion method change timing setting method is basically arbitrary as long as it is agreed with the intermediate control unit 180 in advance, but in this embodiment, the change timing is set as follows. . In other words, when the control command (P) output from the buffer means 510 is a control command that satisfies the change condition, the decision circuit 542 determines when the generation number Mo (Mo; non-negative integer) has elapsed (that is, generation). When the number is P + Mo), the value of the conversion method information storage area (S) is updated to S ′ according to the change method. As a result, the conversion method used when the bit string conversion process is performed on the error check value added to the control command (P + Mo) output at that time is the changed method stored in the conversion method information storage area (S). The value of S ′ indicating the conversion method is reflected. Then, the error check value (P + Mo−N) obtained by converting the bit string using the conversion method corresponding to the value of S ′ is added to the control command (P + Mo). In the present embodiment, Mo is a fixed value determined in advance with the intermediate control unit 180.

  The determination circuit 542 is provided with a change timing information storage area (Mi) that stores change timing information Mi indicating the value of the number of generations at the change timing of the conversion method information. When the control command (P) output from the buffer means 510 is a control command that satisfies the change condition, the determination circuit 542 adds a predetermined value of Mo to the number of generated control commands (P). The value (P + Mo) is stored in the change timing information storage area (Mi) as change timing information Mi (= P + Mo). That is, the value stored in the change timing information storage area (Mi) is equal to the value P of the number of generated control commands output Mo after the output of the control command satisfying the change condition.

  Therefore, the decision circuit 542 compares the current number of generated control commands, that is, the value of the generated number storage area (P) with the value of the change timing information storage area (Mi), so that the present time is not changed. Whether or not there is can be grasped. The determination circuit 542 is provided with a comparison circuit (not shown) for comparing the value of the generated number storage area (P) and the value of the change timing information storage area (Mi). Note that the decision circuit 542 changes the conversion method after the value of the generated number storage area (P) and the value of the change timing information storage area (Mi) coincide with each other and changes the conversion method (conversion method information storage area). After changing the value of (S), the change timing information storage area (Mi) is cleared.

  In the present embodiment, there is a control command that satisfies the change condition between the time when it is determined that the control command output from the buffer means 510 is a control command that satisfies the change condition and the time when the conversion method is actually changed. It may be output. Therefore, in this embodiment, a plurality of change timing information storage areas (Mi) are provided. i is an identification number for each of the plurality of change timing information storage areas (Mi).

  The decision circuit 542 stores each change timing information Mi in the change timing information storage area (Mi) every time a control command satisfying the change condition is output. The change timing information storage area (Mi) is cleared after changing the conversion method (after changing the value of the conversion method information storage area (S)). Therefore, the change timing information Mi is stored as many as the number of error check values that satisfy the change condition from the time when the conversion method change timing arrives, and the decision circuit 542 has a maximum of Mo + 1. It is sufficient to secure the change timing information storage area (Mi). If determined in this way, the possible range of the value of i is 1 ≦ i ≦ Mo + 1. In the present embodiment, the smallest value of the change timing information Mi among the plurality of change timing information Mi values is referred to as “Mmin”.

  In this manner, the determination circuit 542 determines the conversion method used in the bit string conversion process according to the determination result of the determination circuit 541. Then, the determination circuit 542 can set the generation unit 520 according to the determined conversion method by outputting the conversion method control signal to the control circuit 523 of the generation unit 520, and uses the determined conversion method. Thus, the error check value obtained by converting the bit string is output to the adding means 530.

  The generation unit 520 is a circuit that generates an error check value using the control command output from the buffer unit 510, converts a bit string of the generated error check value, and outputs the converted bit string to the subsequent adding unit 530. The generation unit 520 is a circuit that controls a shift amount used in a bit rotation operation when performing a bit string conversion process. That is, the generation unit 520 plays a role of executing a test value generation process, a bit string conversion process, an update timing condition setting process, and a shift amount setting process. In order to execute these processes, the generation unit 520 includes at least a generation circuit 521, a storage circuit 522, a control circuit 523, an input selection circuit 524, and a bit string conversion circuit 525.

  The generation circuit 521 is a circuit that generates an error check value by performing arithmetic processing on a control command output in the past from the buffer unit 510. The storage circuit 522 is a circuit that stores the control command output from the buffer unit 510. The control circuit 523 is a circuit that controls operations of the generation circuit 521 and the storage circuit 522 based on the input of the operation permission signal output from the buffer unit 510. The control circuit 523 is a circuit that controls an error check value output from the generation circuit 521 to the adding unit 530 via the bit string conversion circuit 525 based on the input of the conversion method control signal output from the determination unit 540. . The input selection circuit 524 is a circuit that selectively switches the connection between the bit string conversion circuit 525 and the adding unit 530. The bit string conversion circuit 525 is a circuit that converts the bit string of the error check value output from the generation circuit 521. Hereinafter, the details of each circuit provided in the generation unit 520 will be described.

  The storage circuit 522 is a circuit for storing the control command output from the buffer unit 510. The storage circuit 522 is composed of N stages of storage circuits corresponding to at least the retroactive N value. Each storage circuit that bears the storage circuit 522 is connected so as to have a pipeline configuration, and has at least a function of an N-stage shift register (FIFO memory) corresponding to the value of N in the retroactive number. ing.

  The storage circuit 522 receives control commands generated by the main CPU 110a in the past from the control command (P) received by the buffer unit 510 from the main CPU 110a and output to the determining unit 540, the generating unit 520, and the adding unit 530. Can be stored. Specifically, the storage circuit 522 receives N control commands from the control command (P-1) to the control command (PN) generated in the past from the control command (P) output from the buffer means 510. Can be stored. In the present embodiment, among the storage circuits that bear the storage circuit 522, the storage circuit (P-1) is the first storage circuit, and the storage circuit (PN) is the final storage circuit. Each storage circuit that bears the storage circuit 522 is referred to as a storage circuit (P-1) to a storage circuit (PN).

  The input side of the first stage storage circuit (P-1) of the storage circuit 522 is connected to the data buffer 511 of the buffer means 510 by a data line. The storage circuits (P-1) to (PN) are connected to the control circuit 523 through control lines. The control circuit 523 sequentially shifts the data stored in the storage circuits (P-1) to (PN) based on the input of the operation permission signal output from the control circuit 512 of the buffer means 510. Control signal (hereinafter referred to as “shift processing signal”) for output. The output side of the storage circuit (PN) at the final stage of the storage circuit 522 is connected to the generation circuit 521 through a data line.

  When the shift processing signal is input from the control circuit 523, each of the storage circuits (P-1) to (P-N) sequentially shifts the control commands stored therein to the storage circuit of the next stage and stores the previous stage. Stores control commands shifted from the circuit. At this time, the first stage storage circuit (P-1) newly takes in and stores the control command (P) output from the data buffer 511 of the buffer means 510 in response to the input of the shift processing signal. Further, the storage circuit (PN) in the final stage shifts the control command (PN) stored therein in accordance with the input of the shift processing signal, and outputs it to the subsequent generation circuit 521.

  In addition, the generation circuit 521 generates an error check value by calculating the control command output from the storage circuit 522 using a preset calculation method for error check value generation (hereinafter referred to as “generation method”). Then, the generated error check value is output to the subsequent bit string conversion circuit 525.

  The input side of the generation circuit 521 is connected to the final storage circuit (PN) of the storage circuit 522 through a data line, and is connected to the control circuit 523 through a control line. The output side of the generation circuit 521 is connected to the bit string conversion circuit 525 through a data line. Then, the control circuit 523 outputs, to the generation circuit 521, an operation permission signal for operating to input a control command and perform arithmetic processing based on the operation permission signal output from the control circuit 512 of the buffer means 510. To do.

  When the operation permission signal is input from the control circuit 523, the generation circuit 521 inputs a control command (PN) that is output along with the shift processing signal to the storage circuit 522 of the control circuit 523. Then, the generation circuit 521 performs arithmetic processing on the input control command (PN) using a preset generation method, and generates an error check value (PN). Then, the generation circuit 521 outputs the generated error check value (PN) to the subsequent bit string conversion circuit 525.

  The generation method is not particularly limited as long as it is agreed with the intermediate control unit 180 in advance. As the generation method, for example, a known method such as a checksum method, a CRC method, an odd parity method, an even parity method, a group count check method, a vertical parity method, a horizontal parity method, or a Hamming code method can be used. Note that the generation circuit 521 can be configured to input and calculate the control command output from the storage circuit 522 as it is, or to input and calculate only a part of the control command output from the storage circuit 522. It can also be configured. For example, the control command is composed of 1-byte “MODE” information and 1-byte “DATA” information as will be described later, but only the “MODE” information of the output control command is input. It can be configured to operate.

  The bit string conversion circuit 525 is a circuit that receives the error check value output from the generation circuit 521 and performs bit string conversion processing on the input error check value. Specifically, the bit string conversion circuit 525 includes a plurality of rotation calculators that perform a bit rotation operation on the bit string of the input error check value, and a shift amount control unit C that controls the shift amount used in the bit rotation operation. Is provided.

  The plurality of rotation arithmetic units that carry the bit string conversion circuit 525 performs a rotation operation unit A that performs a bit rotation operation using a regularly varying shift amount A and a bit rotation operation that uses a randomly varying shift amount B. And a rotate computing unit B. The rotate arithmetic units A and B are each composed of a shift register having a bit width equivalent to the error check value. The input sides of the rotation calculators A and B are connected to the generation circuit 521 through a data line, and connected to the shift amount control unit C through a control line. The output sides of the rotation computing units A and B are connected to the input selection circuit 524 via data lines. Further, the output side of the rotation calculator B is connected to the shift amount control unit C through a data line.

  Then, the rotation calculators A and B receive the error check value output along with the operation permission signal to the generation circuit 521 of the control circuit 523, and perform bit rotation operation on the bit string of the input error check value. After that, each calculation result is output to the subsequent input selection circuit 524. At this time, the rotation computing unit A performs a bit rotation operation with the shift amount A set by the shift amount control unit C, and the rotation operation unit B performs the bit rotation operation with the shift amount B set by the shift amount control unit C. I do.

  In the shift register that constitutes the rotation arithmetic units A and B, the output of the last flip-flop of each flip-flop constituting the shift register is fed back and directly connected to the input of the first flip-flop. When the bits constituting the bit string of the error check value are input to the rotation calculators A and B, the shift amounts A and B set by the shift amount control unit C are set in synchronization with the clock signal. Shifting is performed in a predetermined direction (hereinafter referred to as “shift direction”) by the number of bits shown. Then, the rotation calculators A and B feed back the output bits output from the final stage flip-flop as input bits to the first stage flip-flop.

  Note that the shift direction is either the direction from the most significant bit of the bit string to the least significant bit or the direction from the least significant bit to the most significant bit. In the present embodiment, the shift direction is basically arbitrary as long as it is determined in advance with the intermediate control unit 180 even when the rotation calculators A and B are different directions.

  On the other hand, during the boot process, the shift amount control unit C determines and determines the default update timing condition related to the shift amount A based on the HW parameter set from the main CPU 110a as the update timing condition setting process. Set according to the update timing conditions. Further, during the boot process, the shift amount control unit C performs a process of setting predetermined default shift amounts A and B in the rotation calculators A and B as a shift amount setting process. In addition, the shift amount control unit C performs the shift amount based on the error check value obtained by converting the bit string output from the rotate computing unit B during the bit conversion process performed in the command transmission process after the boot process. As the setting process, the shift amounts A and B are updated to new shift amounts A and B, and the updated shift amounts A and B are set in the rotation calculators A and B.

  The shift amount control unit C includes a shift amount storage area (CS) for storing the shift amounts A and B set in the rotation computing units A and B, and an update timing condition storage area for storing update timing conditions. (CR) is provided. The input side of the shift amount control unit C is connected to the rotation computing unit B through a data line, and is connected to the control circuit 523 through a control line. Further, the output side of the shift amount control unit C is connected to the rotation computing units A and B through control lines. Further, the shift amount control unit C is connected to the main CPU 110a via a bus, and data transmission / reception is controlled with the main CPU 110a by an input / output control method corresponding to the CPU interface method.

  The default shift amounts A and B are basically arbitrary as long as they are values determined in advance with the intermediate control unit 180, and may be the same or different values between the shift amount A and the shift amount B. It is often stored in a predetermined storage area of the main ROM 110b. The main CPU 110a reads the default shift amounts A and B from the main ROM 110b during the initial value setting process during the boot process, and stores them in the shift amount storage area (CS) of the shift amount control unit C, respectively.

  Then, the shift amount control unit C takes in the HW parameter output from the main CPU 110a from the data bus during the HW parameter setting process during the boot process. The shift amount control unit C is provided with a data table in which correspondence relationships between a plurality of update timing conditions and a plurality of HW parameters related to the shift amount A prepared in advance are known. Then, the shift amount control unit C can uniquely determine a specific update timing condition based on the captured HW parameter. Then, as the update timing condition setting process during the boot process, the shift amount control unit C uses the update timing condition corresponding to the HW parameter set from the main CPU 110a as the default update timing condition related to the shift amount A. Store in the storage area (CR). In FIG. 5, only the data transmission / reception of the HW parameter and the random number value is described between the main CPU 110a and the shift amount control unit C, but actually, the address data, the write signal, the read signal, etc. With input and output.

  In addition, the control circuit 523 determines the shift amount to be set in the rotation calculator based on the input of the conversion method control signal output from the determination circuit 542 of the determination unit 540 during the conversion method setting process during the boot process. A control signal (hereinafter referred to as “shift amount control signal”) to be controlled by the shift amount control unit C is output to the shift amount control unit C. The shift amount control unit C performs a shift amount setting process related to the shift amounts A and B based on the input of the shift amount control signal output from the control circuit 523. Specifically, the shift amount control unit C sets the shift amount A stored in the shift amount storage area (CS) in the rotation calculator A as the shift amount setting process related to the shift amount A during the boot process. The control signal (hereinafter referred to as “shift amount A setting signal”) is output to the rotation calculator A, and the default shift amount A stored in the shift amount storage area (CS) is set in the rotate calculator A. In addition, the shift amount control unit C outputs a shift amount B setting signal to the rotate calculator B as a shift amount setting process related to the shift amount B during the boot process, and stores the default stored in the shift amount storage area (CS). Is set in the rotation calculator B.

  As described above, the conversion method of the present embodiment is changed from the conversion method A to the conversion method B by the conversion method setting process of the determination unit 540 when the period of the predetermined operation mode starts. When the processing is completed, the conversion method B is changed to the conversion method A by the conversion method setting process of the determination unit 540. At this time, the shift amount control unit C updates the shift amount A used in the bit rotation calculation when performing the bit string conversion processing by the conversion method A (hereinafter referred to as the update method previously determined with the intermediate control unit 180). Update according to the "update method".

  The update method related to the shift amount A is basically arbitrary as long as it is negotiated with the intermediate control unit 180 in advance and the shift amount A varies regularly. For example, a method in which the shift amount control unit C accumulates a predetermined value with respect to the default shift amount A every time the update timing comes can be adopted. Further, the shift amount control unit C diverts the error check value output from the rotation computing unit B to the default shift amount A by using the arithmetic functions such as parity check and checksum provided in the existing gaming machine. A method of calculating and accumulating the obtained results every time the update timing arrives can be adopted. In this case, in the method of accumulating the error check value output from the rotation calculator B and the result obtained using the calculation function of the existing gaming machine, the main control unit 110 stores a predetermined value that is fixed data in advance. This is preferable because it is not necessary to hold the data in a static manner and there is no possibility of illegal analysis by a static analysis method.

  Although omitted in FIG. 5, a parity check circuit or the like that realizes an arithmetic function such as a parity check provided in these existing gaming machines is provided in the generation unit 520 according to the arrival of the update timing related to the shift amount A. The value obtained from the parity check circuit or the like can be used. In this case, the update of the shift amount A can be realized only by the internal processing of the generation unit 520 configured by a wired logic control type hardware. For this reason, it is possible to suppress the processing load and code size of the main control unit 110 that increase as security functions are added, which is preferable. In any case, the update method related to the shift amount A is consistent with the intermediate control unit 180, and the shift amount A regularly varies based on the error check value output from the rotation calculator B. Any method can be used.

  An update timing condition that defines the update timing is basically arbitrary as long as it is negotiated with the intermediate control unit 180 in advance and the shift amount A is updated so as to change regularly. . For example, the shift amount control unit C is connected to the data buffer 511 of the buffer unit 510 via a data line, or connected to the determination circuit 542 of the determination unit 540 via a control line, and the control command output from the buffer unit 510 is output. It is counted whether or not the number of generated P is a predetermined number. Then, when the number of generated control commands P output from the buffer means 510 is equal to or greater than a predetermined number, a shift amount setting process is performed to update the shift amount A.

  The update timing condition relating to the shift amount A of the present embodiment is that the shift amount A is regular each time the conversion method set by the conversion method setting process of the determination unit 540 is changed from the conversion method B to the conversion method A. It is assumed that the shift amount A is defined to be updated so as to vary. Specifically, in the present embodiment, a period of a predetermined operation mode starts, and an error check value that has been subjected to bit string conversion processing by the conversion method B is added to the control command and transmitted to the intermediate control unit 180. The shift amount A is updated while the predetermined operation mode period ends, and the error check value obtained by converting the bit string by the bit rotation operation using the updated shift amount A is used as the control command. Specifies the update timing condition to be added to

  In this case, the update timing condition related to the shift amount A is basically arbitrary as long as it is defined based on the error check value added to the control command during the predetermined operation mode. In the present embodiment, during the period of the predetermined operation mode, a plurality of shift amounts A related to the shift amount A depending on the error check value added to the control command is the error check value added during the period. It is assumed that the update timing conditions are prepared in advance. For example, during a predetermined operation mode, an update timing condition defined based on an error check value added to a control command first, or an error check value added to a control command last. It is assumed that a plurality of update timing conditions, update timing conditions defined based on an error check value added to the control command first, and the like are prepared.

  Among these, in this embodiment, during the update timing condition setting process during the boot process, an error check that is first added to the control command as the update timing condition corresponding to the HW parameter during the predetermined operation mode It is assumed that an update timing condition defined based on the value is set. That is, in the present embodiment, the period of the predetermined operation mode starts after the boot process, and the error check value output from the rotation computing unit B (that is, the error check value obtained by converting the bit string by the conversion method B) is It is assumed that the shift amount A is updated when it is first output to the adding means 530 during the period.

  More specifically, when the command transmission process is performed for the first time during the predetermined operation mode period after the boot process, the control circuit 523 of the generation unit 520 includes the determination unit 540. A conversion system control signal is output from the determination circuit 542. The control circuit 523 outputs a shift amount control signal to the shift amount control unit C based on the input of the conversion method control signal. Based on the input of the shift amount control signal output from the control circuit 523, the shift amount control unit C can detect that the period of the predetermined operation mode has started.

  For example, the shift amount control unit C is provided with a counter circuit that counts the number of times the shift amount control signal output from the control circuit 523 is input, and 1 is added each time the shift amount control signal is input. Then, the shift amount control unit C detects that the value of the counter circuit or the like has transitioned to an even number or an odd number, so that the shift amount control unit C detects that the period of the predetermined operation mode has started or ended. can do. For example, including that the initial value of the counter circuit or the like is 0 and 1 is added by the shift amount control signal output by the conversion method setting process during the boot process, the value of the counter circuit or the like changes to an even number. For example, it indicates that the period of the predetermined operation mode has started, and thereafter, if the value of the counter circuit or the like transitions to an odd number, it indicates that the period of the predetermined operation mode has ended. Therefore, the shift amount control unit C detects that the period of the predetermined operation mode has started or ended based on the input of the shift amount control signal, and determines whether or not the current period is in the period of the predetermined operation mode. Judgment can be made. That is, the shift amount control unit C can determine the update timing of the shift amounts A and B based on the input of the shift amount control signal.

  When the shift amount control unit C detects that the period of the predetermined operation mode has started, it performs a shift amount setting process to update the shift amount A. That is, the shift amount control unit C performs the shift amount setting process related to the shift amount A based on the error check value output from the rotate computing unit B and the shift amount A stored in the shift amount storage area (CS). The value is updated according to a predetermined update method related to the shift amount A. Then, the shift amount control unit C outputs a shift amount A setting signal to the rotation calculator A, and sets the updated shift amount A stored in the shift amount storage area (CS) in the rotation calculator A.

  During the subsequent predetermined operation mode, an error check value is output from the rotation calculator B to the shift amount control unit C. The error check value is the first during the predetermined operation mode. Therefore, the update timing condition for the shift amount A is not satisfied, and the shift amount A is not updated. Thereafter, the period of the predetermined operation mode ends, and after the period in which the error check value in which the bit string is converted by the bit rotation operation using the shift amount A is output to the adding unit 530, the period of the predetermined operation mode is again obtained. When the conversion method control signal is output from the determination unit 540, the shift amount control unit C updates the shift amount A again as described above.

  On the other hand, the shift amount B is not negotiated with the intermediate control unit 180 in advance, and is set to a value that varies randomly. The update method related to the shift amount B is not a method in which the shift amount varies regularly like the shift amount A, but a method in which a random value is used for the shift amount B. As this random number value, as shown in FIG. 5, a special symbol determination random number value or a jackpot symbol random number value provided in an existing gaming machine stored in a predetermined random number value storage area of the main RAM 110c can be used. .

  Although the random number value is omitted in FIG. 5, a random number generation circuit provided in an existing gaming machine is provided in the generation unit 520 and is acquired from the random number generation circuit when the update timing related to the shift amount B arrives. This value can be used as the value of the shift amount B. In this case, the update of the shift amount B can be realized only by the internal processing of the generation unit 520 configured with a wired logic control type hardware. For this reason, it is possible to suppress the processing load and code size of the main control unit 110 that increase as security functions are added, which is preferable. In any case, the random number value used as the update method of the shift amount B is not a value negotiated with the intermediate control unit 180. It is sufficient that it does not operate in synchronization with the random number generation circuit provided in the unit 180.

  Further, the update timing condition related to the shift amount B in the present embodiment is that the period of a predetermined operation mode starts, and an error check value that has been subjected to bit string conversion processing by the conversion method B is added to the control command and intermediate It is assumed that the shift amount B is updated every time it is transmitted to the control unit 180.

  More specifically, when a command transmission process is performed for the first time during the period of the predetermined operation mode, the control circuit 523 inputs the conversion method control signal output from the determination unit 540. Based on the above, a shift amount control signal is output to the shift amount control unit C. Based on the input of the shift amount control signal output from the control circuit 523, the shift amount control unit C can detect that the period of the predetermined operation mode has started.

  When the shift amount control unit C detects that the period of the predetermined operation mode has started, it performs a shift amount setting process to update the shift amount B. That is, the shift amount control unit C performs the shift amount stored in the shift amount storage area (CS) every time the error check value output from the rotation computing unit B is input as the shift amount setting process related to the shift amount B. The value of the amount B is updated according to a predetermined update method related to the shift amount B. Then, the shift amount control unit C outputs a shift amount B setting signal to the rotation calculator B, and sets the updated shift amount B stored in the shift amount storage area (CS) in the rotation calculator B. The updated shift amount B is reflected when the rotation calculator B performs a bit rotation operation in the next command transmission process performed during the period of the predetermined operation mode.

  During the period of the predetermined operation mode thereafter, the control circuit 523 does not output the shift amount control signal to the shift amount control unit C because the conversion method control signal is not output, but the error output from the rotation computing unit B Each time the inspection value is added to the control command and transmitted to the intermediate control unit 180, it is input to the shift amount control unit C. Therefore, the shift amount control unit C only needs to acquire a new random value and update the shift amount B each time based on the input of the error check value output from the rotation computing unit B.

  Further, when the period of the predetermined operation mode ends, the control circuit 523 outputs a shift amount control signal to the shift amount control unit C based on the input of the conversion method control signal. Based on the input of the shift amount control signal output from the control circuit 523, the shift amount control unit C can detect that the predetermined operation mode period has ended.

  The shift amount control unit C does not need to perform the shift amount setting process when detecting that the period of the predetermined operation mode has ended. That is, the shift amount control unit C only needs to discard the error check value output from the rotation computing unit B, and does not need to update the shift amount B. Thereafter, after an error check value obtained by converting the bit string by the bit rotation operation using the shift amount A is added to the control command, if the period of the predetermined operation mode starts again, the shift amount control unit C Thus, the shift amount B is updated again.

  Note that the shift amount control unit C may update the shift amount B even after the period of the predetermined operation mode ends, but as an update method related to the shift amount B, the shift amount control unit C stores the random amount value storage area of the main RAM 110c. When the stored random number value is used, unnecessary processing related to data transmission / reception of the random value occurs with the main CPU 110a. In this case, since an extra processing load is applied to the main CPU 110a, it is preferable not to update the shift amount B when it is detected that the period of the predetermined operation mode has ended. Further, as a method for updating the shift amount B, if a random number value is acquired by a random number generation circuit provided in the generation unit 520, processing related to data transmission / reception of the random value does not occur. Regardless of whether or not to update, the load on the main CPU 110a is minimized. In addition, when designing the update timing condition related to the shift amount B, the degree of freedom in design is not restricted by considering the load on the main CPU 110a, which is preferable.

  In this way, the shift amount A is updated based on a predetermined update method and update timing conditions that have been negotiated with the intermediate control unit 180 in advance, and fluctuates regularly. On the other hand, the shift amount B is updated with a random value that has not been negotiated with the intermediate control unit 180 in advance, and varies randomly. For this reason, in the rotation computing unit B that performs the bit rotation operation using the shift amount B, “rotate” indicating how many positions of the respective bits constituting the bit string have moved as a result before and after one bit string conversion process. The “number” also varies randomly.

  However, in the rotate computing unit B, although the shift amount B is randomly changed for each bit string conversion process, each bit is only shifted regularly in one bit string conversion process. The combination of the values of each bit does not change every time. Therefore, if the bit rotation operation is performed a plurality of times on the intermediate control unit 180 side, the bit string can be restored to the bit string of the error check value (hereinafter referred to as “original error check value”) that has not been converted. The number of rotations indicates how many bits have moved as a result of the position of each bit constituting the bit string before and after one bit string conversion process. For this reason, the possible range of the rotation number is defined by the bit width of the bit string of the error check value.

  For example, when the bit width of the error check value is 1 byte (8 bits), the possible range of the rotation number is an integer from 0 to 8, and if the bit rotation operation is performed at least 8 times, the original error check value It can be converted back to a bit string. Therefore, for example, even if the range of random values used as the shift amount B is 0 to 255, if the bit width of the error check value is 1 byte (8 bits), the bit rotation operation is performed at least 8 times. It is possible to return to the bit string of the original error check value only by performing.

  In particular, in the rotation computing unit B in which the shift amount B varies randomly, the error check value of the same bit string may be output after the bit string conversion process even if the bit string of the original error check value is different. In general, the fact that an error detection code added to transmission data takes a duplicated value for each transmission data is an event that should be avoided as lowering the reliability of error detection, which is a problem. However, in the present embodiment, even if a duplicate value occurs every bit string conversion, it is possible to return to the original error check value, and the original error check value itself has the reliability of error detection. Must not. Rather, if a duplicate value occurs in each bit string conversion, when an unauthorized person steals multiple control commands and error check values, analyze whether there is regularity regarding shift amount fluctuations or whether the conversion method has changed. This makes it difficult to analyze the correspondence between the control command and the error check value, which is preferable.

  In this way, in the bit string conversion circuit 525, the rotation calculation using the shift amounts A and B of the above configuration for the bit string of the error check value output from the generation circuit 521 during the command transmission process after the boot process. Bit rotation operations are performed by the devices A and B, and the error check value obtained by converting the bit string is output to the subsequent input selection circuit 524, respectively.

  In this embodiment, since the bit string conversion circuit 525 is composed of the rotation arithmetic units A and B that can be realized by a shift register having a relatively simple circuit configuration, after the circuit of the rotation arithmetic unit A is designed, the circuit data is stored. It can also be used for the rotate computing unit B. For this reason, in this embodiment, it is possible to suppress the development man-hours and development difficulty related to circuit design and verification work. That is, in this embodiment, the effect that the correspondence relationship between the control command and the error check value becomes difficult to analyze and the security strength is improved by providing a plurality of conversion methods is smaller than the number of conversion methods provided. It can be obtained simply by designing the computing unit, and a large fraud prevention effect can be obtained with a small development cost.

  In the present embodiment, the rotation calculator B randomly shifts the shift amount B. Therefore, each bit of the error check value obtained by converting the bit string by the rotation calculator B is irregularly shifted every bit string conversion process. To do. For this reason, it is difficult for an unauthorized person to analyze how much the bit string is converted by the error check value added to the control command. Therefore, it is difficult to analyze the correspondence between the control command and the error check value, and the security strength can be further improved.

  Further, in this embodiment, the arithmetic unit in which the shift amount varies randomly is only the rotate arithmetic unit B. In addition, when the error check value obtained by converting the bit string by the rotate computing unit B is added to the control command and transmitted to the intermediate control unit 180, it is also during a predetermined operation mode period, that is, a predetermined control command group. Is limited to a period during which is transmitted to the intermediate control unit 180. Therefore, when returning to the original error check value bit string in the error check process on the intermediate control unit 180 side, the tendency that the number of trials of the bit string conversion process increases by changing the shift amount at random is maximized. Can be suppressed.

  In the present embodiment, the shift amount A used in the rotation computing unit A is regularly changed. Therefore, in the present embodiment, the rotation arithmetic unit A is also used in a period other than the period in which the error check value obtained by converting the bit string in the rotation arithmetic unit B is added to the control command, that is, in a period other than the predetermined operation mode period. Each bit of the error check value obtained by converting the bit string in step fluctuates for each bit string conversion process. For this reason, in this embodiment, an unauthorized person transmits a bit string converted by the error check value added to the control command in a period other than the predetermined operation mode period. This also makes it difficult to perform the error check value, and can further improve the security strength.

  In the rotation computing unit A, the regularity regarding the update of the shift amount A depends on the update method and the update timing condition related to the shift amount A, and the update timing condition is set to an initial value at the time of boot processing of the main control unit 110. It is determined based on the value of the HW parameter stored in a specific storage area of the main ROM 110b that is not accessed except at times. Therefore, it becomes difficult for an unauthorized person to analyze the regularity regarding the update of the shift amount A, and the security strength can be further improved.

  In the present embodiment, as described above, when the period of the predetermined operation mode starts or ends and the change condition that is a condition for whether or not to change the conversion method is satisfied, the conversion method is actually set. The timing at which the conversion method control signal is output from the determining means 540 can be distributed for changing. At this time, even if both timings are dispersed, in this embodiment, the timing for updating the shift amount in the shift amount control unit C depends on the timing at which the conversion method control signal is output, as described above. It is defined based on the output timing of the shift amount control signal. In the description of the present embodiment, the expression “when the predetermined operation mode period starts”, “when the predetermined operation mode period ends”, or “when the predetermined operation mode period is in progress” is used. Includes the case where the timings of both are distributed.

  The input selection circuit 524 is configured by a multiplexer or the like, and has a function of selectively switching the connection between the bit string conversion circuit 525 and the adding unit 530. Specifically, the input side of the input selection circuit 524 is connected to a plurality of rotate arithmetic units (rotate arithmetic units A and B in FIG. 5) that bear the bit string conversion circuit 525 through data lines, and controls the control circuit 523. Connected with wires. The output side of the input selection circuit 524 is connected to the input selection circuit 531 of the adding means 530 through a data line. The input selection circuit 524 is preset so that the connection with the rotation arithmetic unit A that outputs the error check value that has been subjected to the bit string conversion processing by the conversion method A becomes valid, and is output from the rotation arithmetic unit A. The error check value thus obtained is taken in and output to the input selection circuit 531 of the adding means 530.

  Based on the input of the conversion method control signal output from the determination circuit 542 of the determination unit 540 in the conversion method setting process, the control circuit 523 validates the connection with one of the rotation calculators A and B of the input selection circuit 524. A control signal (hereinafter referred to as “input selection signal”) is output to the input selection circuit 524. This input selection signal is valid only for connection with a rotation operator corresponding to the conversion method so that only error check values that have been subjected to bit string conversion processing in the specific conversion method indicated by the conversion method control signal are input. Is a signal for For example, when an input selection signal for enabling connection with the rotation calculator B is input from the control circuit 523, the input selection circuit 524 switches to enable only the connection with the rotation calculator B. Then, the input selection circuit 524 takes in the error check value that has been subjected to the bit string conversion processing by the conversion method B output from the rotation computing unit B, and outputs it to the input selection circuit 531 of the adding means 530.

  In this way, the generation unit 520 can perform bit string conversion processing by a plurality of conversion methods on the error check value (PN) added to the control command (P) output from the buffer unit 510. it can. Then, the generation unit 520 inputs an input selection signal corresponding to the conversion method control signal to the input selection circuit 524, so that the error check value obtained by converting the bit string using the conversion method determined by the determination unit 540 is used. Only (PN) can be output to the adding means 530. Therefore, the error check value (PN) output from the generating unit 520 to the adding unit 530 is obtained by using the control command (PN) N times before the control command (P) output from the buffer unit 510. This is an error check value (PN) that is generated, and becomes an error check value (PN) in which the bit string is converted by the conversion method determined according to the change protocol.

  The adding unit 530 is a circuit that adds the error check value output from the generating unit 520 to the control command output from the buffer unit 510 and outputs the error check value to the transmitting unit 550. That is, the adding unit 530 plays a role of executing the inspection value adding process. On the input side of the adding means 530, data transmission / reception is controlled between the buffer means 510 and the generating means 520 by a synchronous interface method. On the other hand, data transmission / reception is controlled between the output side of the adding unit 530 and the subsequent transmission unit 550 by the input / output control method corresponding to the CPU interface method as described above. That is, the adding unit 530 has different input / output control methods on its input side and output side, and an input / output control method corresponding to the synchronous interface method in the test value generation unit 500 and the CPU interface method of the transmission unit 550. It plays a role to align.

  The adding unit 530 includes at least an input selection circuit 531 constituted by a multiplexer or the like, and a control circuit 532. The input selection circuit 531 is a connection switching function that selectively takes in the control command output from the buffer unit 510 and the error check value output from the generation unit 520 so as to match a predetermined retroactive number. It is a circuit which has. The control circuit 532 is a circuit that controls the operation of the input selection circuit 531 based on the input of the operation permission signal output from the buffer means 510.

  Specifically, the input side of the input selection circuit 531 is connected to the data buffer 511 of the buffer means 510 by a data line, and is connected to the input selection circuit 524 of the generation means 520 by a data line. The input side of the input selection circuit 531 is connected to the control circuit 532 through a control line. The input selection circuit 531 is set in advance so that the connection with the data buffer 511 is valid, and takes in the control command output from the data buffer 511. Then, the control circuit 532 delays a predetermined time based on the operation permission signal output from the control circuit 512 of the buffer means 510, and makes a control signal (valid for connection with the generation means 520 of the input selection circuit 531). (Hereinafter referred to as “input selection signal”) is output to the input selection circuit 531. When the input selection signal is input from the control circuit 532, the input selection circuit 531 takes in the error check value output from the input selection circuit 524 of the generation unit 520.

  Then, the input selection circuit 531 outputs the control command and the error check value taken into the data bus connected to the transmission unit 550. In addition, the control circuit 532 outputs address data for designating a predetermined storage area of the transmission unit 550 to an address bus connected to the transmission unit 550 and a write signal to the control bus. At this time, the timing at which the control circuit 532 outputs the write signal is based on the operation time of the generation unit 520 and the transmission unit 550 based on the input of the operation permission signal output from the control circuit 512 of the buffer unit 510. However, the timing is set in advance so that an error check value corresponding to a predetermined retroactive number is added.

  The transmission unit 550 functions to transmit the control command and error check value output from the check value generation unit 500 to the intermediate control unit 180, and includes at least a transmission buffer 551 and a transmission circuit 552.

  The transmission buffer 551 is a buffer circuit for temporarily holding data to be transmitted to the intermediate control unit 180. Specifically, when a write signal for writing the control command output from the test value generation unit 500 to the transmission buffer 551 and address data specifying the transmission buffer 551 are input to the transmission buffer 551, the control is performed. Capture commands via the bus. The transmission buffer 551 receives a write signal for writing the error check value to be added to the control command output from the check value generation unit 500 to the transmission buffer 551 and address data designating the transmission buffer 551. Then, the error check value is taken in via the bus. Then, the transmission buffer 551 immediately transfers the fetched control command and error check value to the transmission circuit 552.

  The transmission circuit 552 has a function of converting data to be transmitted to the intermediate control unit 180 into a data format corresponding to a data transmission format (serial transmission format or parallel transmission format) between the main control unit 110 and the intermediate control unit 180. It has. Then, the transmission circuit 552 performs the above-described data format conversion processing on the data transferred from the transmission buffer 551 to obtain transmission data, and immediately transmits it to the intermediate control unit 180.

  Due to the configuration related to the authentication process of the main control unit 110 as described above, an error check value is added to the control command transmitted from the main control unit 110 to the intermediate control unit 180 in the procedure illustrated below. Hereinafter, the procedure for adding an error check value will be described with reference to FIG. FIG. 7 shows an example of control commands (control command (1) to control command (11)) output eleventh after the stored control command is cleared.

In FIG. 7, conversion method A is referred to as “method A”, and conversion method B is referred to as “method B”. In FIG. 7, the error check value (P) subjected to bit string conversion processing by the conversion method A is denoted as “error check value (PA)”, and the bit string conversion processing is performed by the conversion method B. Is expressed as “error check value (PB)”. In addition, the shift amount A used in performing the bit string conversion process is updated as appropriate, but the bit string conversion process using the default shift amount A before the update is “error check value (PA ₀ )”. And “error check value (PA ₁ )”, “error check value (PA ₂ )”,... The same applies to the error check value (PB). Then, the retroactive number is N = 2, and the value of Mo that is an index of change timing is Mo = 4.

  In FIG. 7, the default conversion method is conversion method A. That is, in the conversion method information storage area (S), the value of the conversion method information corresponding to the conversion method A is stored, but in FIG. 7, for convenience, S = A is written. In FIG. 7, the control command that satisfies the change condition is a control command that is generated first in a predetermined control command group, and a control command that is generated first after generation of the predetermined control command group is completed. Either one. In addition, as a change method, a method of determining the conversion method from conversion method A to conversion method B every time a control command that satisfies the change condition is generated is adopted.

  First, when it is time to execute the command transmission process, the main CPU 110a updates the value of the generated number storage area (P) of the main RAM 110c to “P = 1” and reads the unique information stored in the main ROM 110b. Then, the main CPU 110a sets the read unique information as initial setting values in the storage circuits (P-1) to (PN) of the storage circuit 522.

  In FIG. 7, N = 2, and the storage circuit 522 includes two storage circuits (P-1) and a storage circuit (P-2). The main CPU 110a reads two pieces of unique information and sets them as initial setting values. When P ≦ N, that is, when a control command generated before the Nth time is cleared after the control command stored in the storage circuit 522 is cleared, it is added to the control command (P). The error check value (PN) is an initial check value generated using unique information. In FIG. 7, P ≦ 2, and initial check values are added to the control command (1) and the control command (2), respectively. The initial inspection values are expressed as initial inspection value (1) to initial inspection value (N) in the order of addition to the control command.

  Subsequently, the main CPU 110 a outputs the control command (1) to the buffer means 510. The buffer unit 510 outputs the control command (1) output from the main CPU 110a to the determination unit 540, the generation unit 520, and the addition unit 530. The determination unit 540 performs conversion method setting processing. Specifically, the determination circuit 541 inputs the control command (1) output from the buffer unit 510, that is, the control command (1) output from the main CPU 110a, and the control command (1) satisfies the change condition. It is determined whether or not it is a control command, and a determination result signal is output to the decision circuit 542. The same applies to the description of FIG.

  When the determination circuit 542 receives the determination result signal, the determination circuit 542 updates the value of the generated number storage area (P) to “P = 1”, and the control command (1) is a control command having a value of the generated number. (Hereinafter the same in the description of FIG. 7). Then, the determination circuit 542 confirms the determination result signal, and confirms whether the control command (1) is a control command that satisfies the change condition (hereinafter, the same applies in the description of FIG. 7). In FIG. 7, it is assumed that the control command (1) is not a control command that satisfies the change condition. At this time, the change timing information storage area (Mi) remains cleared, and there is no need to set the change timing information Mi. Further, the value of the conversion method information storage area (S) is also the default “A”, and an error check value that has been subjected to the bit string conversion processing by the method A is added. Further, P ≦ 2, and the error check value added to the control command (1) is the initial check value (1) obtained by performing bit string conversion processing on the unique information by the method A. The same applies when the control command (2) is output, and the error check value added to the control command (2) is the initial check value (2) obtained by subjecting the unique information to the bit string conversion processing by the method A.

Next, a case where the control command (3) is output from the main CPU 110a will be described. In FIG. 7, since the control command (3) is not a control command that satisfies the change condition, the determination unit 540 does not set the change timing information Mi. Further, the value of the conversion method information storage area (S) is also the default “A”, and an error check value that has been subjected to the bit string conversion processing by the method A is added. Further, the value (P = 3) of the generated number storage area (P) is larger than the value of the retroactive number (N = 2) (P> N). Therefore, the error check value to be added to the control command (3) is the error check value (PN) that has been subjected to the bit string conversion process by the method A, that is, the error check value (1A) (hereinafter, FIG. 7). The same shall apply in the description). At this time, since it is not the change timing, the conversion method control signal is not output from the determining unit 540 to the control circuit 523 of the generating unit 520. For this reason, the shift amount control signal is not output from the control circuit 523 even to the shift amount control unit C responsible for the bit string conversion circuit 525 of the generation unit 520. Therefore, the shift amount A used in the conversion method A remains the default shift amount A, and the error check value added to the control command (3) is the error check value (1A ₀ ) (hereinafter, description of FIG. 7). The same shall apply).

Next, a case where the control command (4) is output from the main CPU 110a will be described. In FIG. 7, since the control command (4) is a control command that satisfies the change condition, the determination unit 540 sets the change timing information Mi as M1. As described above, the change timing information M1 is M1 = P + Mo = 4 + 4 = 8, and the determination unit 540 stores the value of M1 = 8 in the change timing information storage area (M1). Accordingly, it is understood that the determination unit 540 must change the value of the conversion method information storage area (S) at the timing when the value of the generated number storage area (P) becomes P = 8. Further, the determination means 540 compares the value (M1 = 8) of the change timing information storage area (Mi) with the value (P = 4) of the generated number storage area (P) (hereinafter the same in the description of FIG. 7). And). In FIG. 7, since the value of the change timing information storage area (M1) does not match the value of the generated number storage area (P), the value of the conversion method information storage area (S) (S = A) is not the change timing at present. ) Is maintained, and an error check value that has been subjected to the bit string conversion processing by the method A is added. Therefore, the error check value added to the control command (4) is the error check value (PN) that has been subjected to the bit string conversion processing by the method A, that is, the error check value (2A). At this time, since it is not the change timing, the generation unit 520 does not output a shift amount control signal from the control circuit 523 to the shift amount control unit C. Therefore, the shift amount A used in the conversion method A remains the default shift amount A, and the error check value added to the control command (4) is the error check value (2A ₀ ). The same applies when the control command (5) and the control command (6) are output. The error check values added to the control command (5) and the control command (6) are the error check value (3A ₀ ) and the error, respectively. It becomes an inspection value (4A ₀ ) (hereinafter the same in the description of FIG. 7).

Next, a case where the control command (7) is output from the main CPU 110a will be described. In FIG. 7, since the control command (7) is a control command that satisfies the change condition, the determination unit 540 sets the change timing information Mi as M2. As described above, the change timing information M2 is M2 = P + Mo = 7 + 4 = 11, and the determination unit 540 stores the value of M2 = 11 in the change timing information storage area (M2). Accordingly, two change timing information of M1 = 8 and M2 = 11 are set in the change timing information storage area (Mi). Then, the determination unit 540 determines the value (M1 = 8) of the change timing information storage area (M1) having the minimum value Mmin in the change timing information storage area (Mi) and the value of the generated number storage area (P). Compare (P = 7). Since the value of the change timing information storage area (M1) does not match the value of the generated number storage area (P), the value (S = A) of the conversion method information storage area (S) is maintained instead of the change timing at present. Then, an error check value that has been subjected to the bit string conversion processing by method A is added. Therefore, the error check value added to the control command (7) is the error check value (PN) that has been subjected to the bit string conversion processing by the method A, that is, the error check value (5A ₀ ).

  Next, the case where the control command (8) is output from the main CPU 110a will be described. In FIG. 7, since the control command (8) is not a control command that satisfies the change condition, the determination unit 540 does not newly set the change timing information Mi. Further, the value (M1 = 8) of the change timing information storage area (M1) having the minimum value Mmin in the change timing information storage area (Mi) is the value (P = 8) of the generated number storage area (P). Since it matches, the current timing is the change timing. The determination unit 540 changes the value (S = A) of the conversion method information storage area (S) according to a predetermined change method. In FIG. 7, assuming that the method is changed from method A to method B, the determination unit 540 generates conversion method information corresponding to method B. Then, the determination unit 540 stores S ′ = B of the converted conversion method information value in the conversion method information storage area (S).

Then, the determination unit 540 adds the error check value that has been subjected to the bit string conversion processing in the method B based on the value (S ′ = B after the change) in the conversion method information storage area (S). The conversion method control signal is output to the control circuit 523 of the generation unit 520. The control circuit 523 of the generation unit 520 outputs an input selection signal for effectively operating the connection between the input selection circuit 524 and the rotation calculator B of the bit string conversion circuit 525 based on the conversion method control signal. It is set so that the error check value that has been subjected to the bit string conversion processing in B is output to the adding means 530 (hereinafter the same as in the description of FIG. 7). As a result, the error check value added to the control command (8) becomes the error check value (PN) that has been subjected to the bit string conversion processing by the method B, that is, the error check value (6B ₀ ). Further, the determination unit 540 clears the value (M1 = 8) of the change timing information storage area (M1) having the minimum value Mmin. Further, the control circuit 523 of the generating unit 520 outputs a shift amount control signal to the shift amount control unit C of the bit string conversion circuit 525 based on the conversion method control signal. Based on the input of the shift amount control signal and the error check value (6B ₀ ), the shift amount control unit C updates the shift amount A by a predetermined update method, acquires a random value, and updates the shift amount B. And stored in the shift amount storage area (CS). Then, the shift amount control unit C outputs the shift amount A setting signal and the shift amount B setting signal to the rotation computing units A and B, and the updated shift amount A and the shift amount storage area (CS) stored in the shift amount storage area (CS). B is set to rotate arithmetic units A and B (hereinafter the same in the description of FIG. 7).

Next, a case where the control command (9) is output from the main CPU 110a will be described. In FIG. 7, since the control command (9) is not a control command that satisfies the change condition, the determination unit 540 does not set the change timing information Mi. The value (M2 = 11) of the change timing information storage area (M2) having the minimum value Mmin in the change timing information storage area (Mi) and the value (P = 9) of the generated number storage area (P). Compare. Since the value of the change timing information storage area (M2) does not match the value of the generated number storage area (P), the value (S = B) of the conversion method information storage area (S) is maintained instead of the change timing at present. Then, an error check value that has been subjected to the bit string conversion process by the method B is added. Therefore, the error check value added to the control command (9) is the error check value (PN) that has been subjected to the bit string conversion processing by the method A, that is, the error check value (7B ₁ ). Further, the shift amount control unit C acquires a random value to update only the shift amount B based on the non-input of the shift amount control signal and the input of the error check value (7B ₁ ), and acquires the shift amount storage area (CS ) Is updated and set in the rotate computing unit B (hereinafter the same in the description of FIG. 7). Then, the shift amount control unit C updates only the shift amount B until the change timing comes again and the shift amount control signal is output from the control circuit 523, and changes the shift amount B at random.

  Thereafter, processing similar to the above is performed, and the bit string conversion process is performed on the error check value to be added to the control command output from the buffer unit 510 while changing the value of the conversion method information storage area (S) by the determination unit 540. The conversion method is determined, and the error check value subjected to the bit string conversion processing by the determined conversion method is added to the control command by the adding unit 530. Then, a control command with an error check value is transmitted to the intermediate control unit 180 by the transmission unit 550.

Thereafter, the control command (P) transmitted from the transmission unit 550 constituting the main control unit 110 is received by the reception unit 600 constituting the intermediate control unit 180.
FIG. 8 shows functional blocks related to authentication processing of the intermediate control unit 180 according to the present embodiment.
The intermediate control unit 180 includes at least a reception unit 600, an inspection unit 610, an inspection value generation unit 620, an addition unit 630, and a relay transmission unit 640 as functions related to authentication processing. Further, the check value generation unit 620 includes a storage unit 622 that stores the received control command, a generation unit 621 that generates an error check value, a bit string conversion unit 624 that performs bit string conversion processing on the generated error check value, and a bit string It has at least a function with a conversion unit used in the conversion unit 624 and a determination unit 623 that controls the shift amount.

  The receiving unit 600 has a function of performing a process corresponding to the data format conversion process on the transmission data from the main control unit 110 to generate a control command (P) and storing the control command (P) in its own reception buffer. In addition, the receiving unit 600 outputs a signal indicating that a control command (P) reception interrupt request has been made, or sets a flag indicating that the reception of the control command (P) is completed, so that the CPU 180a. However, it has a function that makes it possible to detect that the reception of the control command (P) transmitted from the main control unit 110 has been completed.

  The receiving unit 600 extracts the error check value (PN) added from the received control command (P) with the error check value and outputs the error check value (PN) to the check unit 610. N) has a function of outputting the control command (P) after extraction to the inspection value generation unit 620. Note that specific means for realizing the function of the receiving unit 600 includes a part of the CPU 180a, a part of the ROM 180b, a part of the RAM 180c, and a command receiving input port (not shown) shown in FIG. be able to.

  The inspection value generation unit 620 has a function of storing the control command (P) output from the reception unit 600 in the storage unit 622. Also, the check value generation unit 620 uses the control command (PN) stored in the storage unit 622 in the past to generate an error check value (P− N). The error check value generated by this function is used to verify the validity of the received control command (P). Also, the check value generation unit 620 performs bit string conversion processing by the bit string conversion unit 624 on the error check value (PN) generated by the generation unit 621 by the conversion method determined by the determination unit 623, and checks This has a function of outputting to the unit 610. Also, the test value generation unit 620 has a function for the determination unit 623 to determine a specific conversion method to be set in the bit string conversion unit 624 from among a plurality of conversion methods previously determined with the main control unit 110. It is what you have. In addition, the test value generation unit 620 determines the shift amount A when the bit string conversion unit 624 performs the bit string conversion process by the conversion method A in accordance with the update method and the update timing condition previously determined with the main control unit 110. It has a function controlled by the determination unit 623.

  That is, the check value generation unit 620 has a function of generating an error check value using a control command stored in the past and outputting the error check value to the check unit 610 and determining a conversion method using the control command received this time (hereinafter, referred to as a check method). , “Error check value output function”) is the same as the error check value addition function of the main control unit 110. The check value generation unit 620 has a plurality of error check value output functions in advance, like the main control unit 110, and as a specific embodiment thereof, the change condition and the shift amount are the same as those of the main control unit 110. A plurality of update timing conditions for A are prepared in advance. The selection information for the error check value output function is also the same as the HW parameter of the main control unit 110, and a specific change condition and update timing condition are set as a default according to the HW parameter set during the boot process. It has a function to set as a change condition and an update timing condition. The error check value output function and the selection information thereof of the intermediate control unit 180 are determined in advance between the main control unit 110 and the intermediate control unit 180.

  And in the function in which the determination part 623 changes a conversion system based on the control command (P) output from the receiving part 600, it is the same as the function which changes the conversion system which the determination means 540 of the main control part 110 has. Is. In other words, the determination unit 623 determines whether or not the control command is a control command satisfying the change condition (corresponding to the determination circuit 541 of the main control unit 110), and determines the conversion method according to the determination result. A function (corresponding to the determination circuit 542 of the main control unit 110) is set in the bit string conversion unit 624. In addition, every time the conversion method set in the bit string conversion unit 624 is changed from the conversion method B to the conversion method A, the determination unit 623 sets the update method and the update timing condition negotiated with the main control unit 110 in advance. Based on this, the shift amount A is updated and the shift amount A is regularly varied (the shift amount control unit C of the main control unit 110).

  The update method related to the shift amount A included in the determination unit 623 is defined based on the error check value that has been subjected to the bit string conversion processing by the conversion method B, similarly to the shift amount control unit C of the main control unit 110. The error check value that has been subjected to the bit string conversion processing by the conversion method B is the error output from the receiving unit 600 among the plurality of error check values (PN) output from the bit string converting unit 624 to the checking unit 610. The error check value (PN) coincides with the check value. Of the plurality of update timing conditions related to the shift amount A included in the determination unit 623, the update timing condition corresponding to the HW parameter set during the boot process is the same as the shift amount control unit C of the main control unit 110. Assume that it is defined based on an error check value that is first added to the control command during a predetermined operation mode.

  In order to realize the function of the determining unit 623, the RAM 180c corresponds to a storage area corresponding to the change condition storage area (D) of the main control unit 110 and a generated number storage area (P) of the main control unit 110. A reception number storage area (P) is provided. The same applies to the conversion method information storage area (S), the change timing information storage area (Mi), the update timing condition storage area (CR), and the shift amount storage area (CS).

  The storage unit 622 stores the control command (P) output from the receiving unit 600 and also outputs the control command (PN) stored in the past to the generation unit 621. This is the same function as the storage circuit 522 of the unit 110. In addition, when the main control unit 110 or the intermediate control unit 180 is initialized and the past control command stored in the storage unit 622 is cleared, the CPU 180a reads the unique information from the ROM 180b and sets it as an initial setting value. The function to be set in the storage unit 622 is the same as that of the main control unit 110.

  Further, the generation unit 621 generates an error check value (PN) by a preset generation method using the control command (PN) output from the storage unit 622 and outputs the error check value (PN) to the bit string conversion unit 624. The function to perform is the same as the function of the generation circuit 521 of the main control unit 110.

  In addition, the bit string conversion unit 624 has a plurality of conversion methods (conversion method A and conversion method B), sets a specific conversion method by the conversion method control of the determination unit 623, and checks the error output output from the generation unit 621. The function of performing bit string conversion processing on the value (PN) by the set conversion method and outputting the value to the checking unit 610 is the same as the function of the bit string conversion circuit 525 of the main control unit 110.

  Note that the shift amount A when the conversion method is the conversion method A is a value that regularly varies according to the update method that is negotiated with the main control unit 110 in advance. In this case, the bit string conversion unit 624 performs a bit rotation operation on the bit string of the error check value (PN) using the shift amount A determined by the determination unit 623 according to the update method, and the original error check value The bit string is returned and output to the inspection unit 610. Further, the shift amount B when the conversion method is the conversion method B is a value that randomly varies and is not negotiated with the main control unit 110 in advance. In this case, the bit string conversion unit 624 performs bit rotation operation on the bit string of the error check value (PN) by the number of rotations that can be taken by the rotation number defined by the bit width of the bit string. Then, the bit string conversion unit 624 outputs error check values (PN) corresponding to the number of ranges that can be taken by the rotation number, to which the bit string is converted, to the checking unit 610, respectively.

  Specific means for realizing the functions of the determination unit 623, the storage unit 622, the generation unit 621, and the bit string conversion unit 624 include a part of the CPU 180a, a part of the ROM 180b, a part of the RAM 180c, and the like shown in FIG. be able to.

  The checking unit 610 has a function of performing an error checking process for collating the error check value output from the receiving unit 600 with the error check value output from the bit string conversion unit 624 of the check value generating unit 620. In the error check process, the error check value output from the receiving unit 600 is compared with the error check value output from the bit string conversion unit 624. If the two match, it is determined that the check result is normal, If they do not match, it is determined that the test result is not normal.

  When the conversion method B is set in the bit string conversion unit 624, error checking values are output from the bit string conversion unit 624 to the number of rotations that can be taken from the bit string conversion unit 624. In this case, checking section 610 compares all error check values output from bit string conversion section 624 with error check values output from receiving section 600. Then, when any error check value output from the bit string conversion unit 624 matches the error check value output from the reception unit 600, the check unit 610 determines that the check result is normal, and any error is detected. If the inspection value does not match the error inspection value output from the receiving unit 600, it is determined that the inspection result is not normal.

  When the inspection result is determined to be normal, the inspection unit 610 generates the control command (P) to which the currently received error check value (PN) is added and the current error check value (PN) generation source. It is determined that the validity of the control command (PN) is authenticated and the validity of the main control unit 110 can be authenticated. Then, the inspection unit 610 generates authentication result data indicating successful authentication and outputs the generated authentication result data to the adding unit 630.

  In addition, when the inspection unit 610 determines that the inspection result is normal, the conversion method B is set, and a plurality of errors (the number of ranges that the rotation number can take) output from the bit string conversion unit 624 to the inspection unit 610 are detected. Among the check values (PN), the error check value (PN) that matches the error check value output from the receiving unit 600 is output to the determining unit 623. Then, when it is time to update the shift amount A, the determination unit 623 updates the shift amount A based on the matched error check value (PN).

  On the other hand, when the inspection result is not determined to be normal, the inspection unit 610 determines that the legitimacy of the main control unit 110 could not be authenticated due to an illegal act or a communication error. Then, the inspection unit 610 generates authentication result data indicating unsuccessful authentication and outputs it to the adding unit 630. The data format of the authentication result data is not particularly limited, but may be a data format having the same data length as the error check value added to the received control command. Further, specific means for realizing the function of the inspection unit 610 can be configured from a part of the CPU 180a, a part of the ROM 180b, a part of the RAM 180c, and the like shown in FIG.

  The adding unit 630 adds the authentication result data output from the checking unit 610 to the control command (P) extracted from the error check value (PN) output from the receiving unit 600, and includes the authentication result data. It has a function of generating a control command (P). The adding unit 630 has a function of outputting the generated control command (P) with authentication result data to the relay transmitting unit 640. Note that specific means for realizing the function of the adding unit 630 can be configured from a part of the CPU 180a, a part of the ROM 180b, a part of the RAM 180c, and the like shown in FIG.

  The relay transmission unit 640 has a function of transmitting the control command (P) with authentication result data output from the adding unit 630 to the effect control unit 120. The control command (P) with authentication result data transmitted from the relay transmission unit 640 to the effect control unit 120 indicates an effect process having the same content as the control command (P) received by the receiving unit 600. That is, the control command (P) received by the receiving unit 600 is output to the relay transmission unit 640 in a state where the specific processing content and the reception order are maintained, and the relay transmission unit 640 sends the control command (P) to the effect control unit 120. Will be sent. Specific means for realizing the function of the relay transmission unit 640 includes a part of the CPU 180a, a part of the ROM 180b, a part of the RAM 180c, a command transmission output port (not shown), and the like shown in FIG. can do.

  When transmitting the generated authentication result data to the effect control unit 120, the intermediate control unit 180 adds the received authentication result data to the effect control unit 120 and adds it to the received control command. That is, the authentication result data is not transmitted by the authentication result data alone, but is transmitted to the effect control unit 120 integrally with the control command which is other transmission data. If the authentication result data and the error check value are in a data format having the same data length, transmission data transmitted from the main control unit 110 to the intermediate control unit 180 and transmission from the intermediate control unit 180 to the effect control unit 120 are transmitted. The transmission data may have a data format having the same data length. By doing so, it is difficult for an unauthorized person to steal transmission data between the intermediate control unit 180 and the effect control unit 120 and to illegally analyze the transmission timing of the authentication result data to the effect control unit 120. Thus, the security strength of the gaming machine 1 can be improved.

[Explanation of control commands]
Hereinafter, the types of control commands transmitted from the main control unit 110 of the gaming machine 1 according to the embodiment of the present invention to the effect control unit 120 will be described.
FIG. 9 is a diagram showing the types of control commands transmitted from the main control unit 110 to the effect control unit 120 constituting the gaming machine 1 according to the present embodiment. The control command shown in FIG. 9 is an example, and the control command according to the present invention is not limited to this.

  The control command transmitted from the main control unit 110 to the effect control unit 120 via the intermediate control unit 180 is composed of 1-byte data, and a 1-byte “ID” for identifying the control command classification. “MODE” information and 1-byte “DATA” information indicating the detailed control contents of each control command. The “MODE” information and the “DATA” information are stored in advance in the main ROM 110b as described above.

  In the main control unit 110, when it is the transmission timing of the control command, the control command is generated based on the “MODE” information and the “DATA” information read from the main ROM 110b, and then the transmission data storage area of the main RAM 110c. Set to An error check value is added to the control command set in the transmission data storage area by the command transmission processing of the main control unit 110, and is transmitted to the intermediate control unit 180 as a control command with an error check value. Is transmitted to the effect control unit 120 by the relay transmission process. In the following description, it is assumed that each control command is transmitted from the main control unit 110 to the effect control unit 120 via the intermediate control unit 180 in this way, and each control command is stored in the main RAM 110c for transmission data. The description of the processing after being set in the area is omitted. Further, in the following description, the expression “transmit a control command” includes transmitting the control command with an error check value, and the expression “transmitting to the effect control unit 120”. Includes transmission to the effect control unit 120 via the intermediate control unit 180.

The “designation designating command” indicates the type of the special symbol that is stopped and displayed. The “MODE” information is set as “E0H”, and the “DATA” information is set according to the special symbol type. ing. Since the special symbol type eventually determines the jackpot type and gaming state, the effect symbol designation command can also be said to indicate the jackpot type and gaming state.
In the effect symbol designation command, when various special symbols are determined and the variation display of the special symbol is started, an effect symbol designation command corresponding to the determined special symbol is transmitted to the effect control unit 120. Specifically, when the lottery result of the jackpot is determined, various special symbols are determined, and the variation display of the special symbols is started, an effect designating command corresponding to the determined special symbol is transmitted to the main RAM 110c. Set in the data storage area.
The process related to the jackpot lottery related to the production symbol designation command will be described later.

  Here, among the effect designating commands, the “losing effect designating command” set with “DATA” information being “00H” is a control for stopping and displaying the result of the losing when the lottery result is losing. It is a command. That is, it is a control command that is surely transmitted from the main control unit 110 to the effect control unit 120 when the lose design symbol designation command is a loss. Hereinafter, the lose effect designating command is also referred to as a “lose command” as a command for executing a process in case of loss.

The “first special symbol memory designation command” indicates the number of reserved memories stored in the first special symbol reservation number (U1) storage area, and the information of “MODE” is set to “E1H”, “DATA” information is set according to the number of memories.
This first special symbol memory designation command is effect-controlled by the first special symbol memory designation command corresponding to the number of reserved memories when the number of reserved memories stored in the first special symbol reservation number (U1) storage area is switched. Is transmitted to the unit 120. Specifically, when the value stored in the first special symbol hold number (U1) storage area is increased or decreased when determining the result of entering the first start port 14 or the big win lottery result, the reserved memory after the increase or decrease is stored. The first special symbol storage designation command corresponding to the number is set in the transmission data storage area of the main RAM 110c.

The “second special symbol memory designation command” indicates the number of reserved memories stored in the second special symbol reservation number (U2) storage area, and the information of “MODE” is set to “E2H”, “DATA” information is set according to the number of memories.
This second special symbol memory designation command is directed by the second special symbol memory designation command corresponding to the number of reserved memories when the number of reserved memories stored in the second special symbol reservation number (U2) storage area is switched. Is transmitted to the unit 120. Specifically, when the value stored in the second special symbol holding number (U2) storage area is increased or decreased in determining the result of entering the second starting port 15 or the jackpot lottery result, the holding storage after the increase / decrease is performed. The second special symbol storage designation command corresponding to the number is set in the transmission data storage area of the main RAM 110c.
In the present embodiment, the “first special symbol memory designation command” and the “second special symbol memory designation command” are collectively referred to as “special symbol memory designation command”.

The “symbol confirmation command” indicates that the special symbol is stopped and displayed, and “MODE” information is set to “E3H” and “DATA” information is set to “00H”.
This symbol confirmation command is transmitted to the effect control unit 120 when the special symbol is stopped and displayed. Specifically, after determining the jackpot lottery result and the special symbol change time has elapsed, when the special symbol is stopped and displayed on the first special symbol display device 20 or the second special symbol display device 21, the symbol confirmation command Is set in the transmission data storage area of the main RAM 110c.

The “power-on designation command” indicates that the gaming machine 1 is powered on, the “MODE” information is set to “E4H”, and the “DATA” information is set to “00H”. ing.
The power-on designation command is transmitted to the effect control unit 120 when the gaming machine 1 is powered on. When the gaming machine 1 is powered on and the initialization process of the main control unit 110 is performed, if the backup information of the main RAM 110c generated when the power is turned off (hereinafter referred to as “power interruption”) is not valid, The work area in the RAM 110c is cleared and a new work area is set. Thereafter, a power-on designation command is set in the transmission data storage area of the main RAM 110c.
The initialization process related to the power-on designation command and the like will be described later.

The “RAM clear designation command” indicates that the information stored in the main RAM 110c has been cleared. The “MODE” information is set to “E4H” and the “DATA” information is set to “01H”. Has been.
A RAM clear button (not shown) is provided on the back side of the gaming machine 1. When the gaming machine 1 is turned on while pressing the RAM clear button, a system reset occurs in the main control unit 110 and initialization processing is performed. . After the work area of the main RAM 110c is cleared and a new work area is set and a power-on designation command is transmitted, the RAM clear designation command is set in the transmission data storage area of the main RAM 110c.

The “power recovery designation command” indicates that the gaming machine 1 has been powered on and has been restored normally. The “MODE” information is set to “E4H” and is matched according to the gaming state at the time of power interruption. "DATA" information is set.
This power supply restoration designation command is transmitted to the effect control unit 120 when the gaming machine 1 is turned on and normally restored. Specifically, when the gaming machine 1 is turned on and the initialization process is performed, if the backup information of the main RAM 110c generated at the time of power interruption is valid, the power is restored according to the gaming state indicated by the backup information. A designated command is generated, and the generated power supply restoration designation command is set in the transmission data storage area of the main RAM 110c.

  When the power is turned on, at least one of a power-on designation command, a RAM clear designation command, and a power restoration designation command is transmitted from the main control unit 110 to the effect control unit 120. That is, the above-described control command group in which “MODE” information is set to “E4H” is a command for executing a process at power-on. Hereinafter, the control command group in which the “MODE” information is set to “E4H” is also referred to as “power-on command”.

The “demonstration designation command” indicates that the first special symbol display device 20 or the second special symbol display device 21 is not operating, the information of “MODE” is set to “E5H”, and “DATA” Is set to “00H”.
This demonstration designation command is used for effect control when there is no special symbol hold storage in the first special symbol display device 20 or the second special symbol display device 21 and a non-game state in which there is no operation by the player has elapsed for a predetermined time. Is transmitted to the unit 120. Specifically, when the jackpot lottery, the special electric accessory, and the gaming state are controlled, either the first special symbol hold number (U1) storage area or the second special symbol hold number (U2) storage area In addition, when a state in which one or more data is not set continues for a predetermined time, the demo designation command is set in the transmission data storage area of the main RAM 110c.

  The demonstration designation command may be sent immediately when there is no special symbol holding storage of the first special symbol display device 20 or the second special symbol display device 21. In this case, after receiving the demonstration designation command, the effect control unit 120 executes the demonstration effect when no other control command is received for a predetermined time, that is, when the non-game state has elapsed for a predetermined time.

The “variable pattern designation command for the first special symbol” indicates the variation time (variation mode) of the special symbol in the first special symbol display device 20, the information of “MODE” is set as “E6H”, and various “DATA” information is set in accordance with the fluctuation pattern.
The first special symbol variation pattern designation command is a first special symbol variation pattern corresponding to the variation pattern of the special symbol determined when the special symbol variation display of the first special symbol display device 20 is started. A designation command is transmitted to the effect control unit 120. Specifically, the variation pattern for the first special symbol corresponding to the determined variation pattern of the special symbol when the variation pattern of the special symbol is determined and the variation display of the special symbol is started by judging the lottery result of the jackpot The designated command is set in the transmission data storage area of the main RAM 110c.

The “variable pattern designation command for the second special symbol” indicates the variation time (variation mode) of the special symbol in the second special symbol display device 21, and the information of “MODE” is set to “E7H”. “DATA” information is set in accordance with the fluctuation pattern.
The second special symbol variation pattern designation command is a second special symbol variation pattern corresponding to the variation pattern of the special symbol determined when the special symbol variation display of the second special symbol display device 21 is started. A designation command is transmitted to the effect control unit 120. Specifically, the variation pattern for the second special symbol corresponding to the determined variation pattern of the special symbol when the variation pattern of the special symbol is determined and the variation display of the special symbol is started by judging the lottery lottery result The designated command is set in the transmission data storage area of the main RAM 110c.
In the present embodiment, the “first special symbol variation pattern designation command” and the “second special symbol variation pattern designation command” are collectively referred to as a “variation pattern designation command”.

  Here, among the variation pattern designation commands, the control command group in which the information of “DATA” is set to “01H”, “02H”, “03H”, “04H”, “05H” is a control for executing the reach effect. It is a command. Hereinafter, the control command group in which the “MODE” information is set to “E6H” and the “DATA” information is set to “01H” to “05H” is also referred to as “reach command”.

The “big prize opening opening designation command” indicates the number of rounds of jackpots according to various types of jackpots, and “MODE” information is set as “EAH”, and “DATA” is set according to the number of rounds of jackpots. Information is set.
With regard to the special winning opening opening designation command, when the big hit round is started, the big winning opening opening designation command corresponding to the started round number is transmitted to the effect control unit 120. Specifically, when the first big prize opening opening / closing door 16b (or the second big prize opening opening / closing door 17b) is opened in the big hit game process, the big winning opening opening designation command corresponding to the number of rounds to be opened is It is set in the transmission data storage area of the main RAM 110c.
Note that the command group in which the information of “MODE” is set to “EAH” is a command for executing processing corresponding to each round of jackpot. Hereinafter, a command group in which “MODE” information is set to “EAH” is also referred to as a “hit command”.

The “opening designation command” indicates that various jackpots start, “MODE” information is set as “EBH”, and “DATA” information is set according to the jackpot type.
As for this opening designation command, when various jackpots start, an opening designation command corresponding to the type of jackpot is transmitted to the effect control unit 120. Specifically, at the start of the jackpot game process, an opening designation command corresponding to the jackpot type is set in the transmission data storage area of the main RAM 110c.
Note that the command group in which the information of “MODE” is set to “EBH” is a command for starting the big hit state processing. Hereinafter, a command group in which “MODE” information is set to “EBH” is also referred to as a “big hit start command”.

The “ending designation command” indicates that various types of jackpots have ended, “MODE” information is set as “ECH”, and “DATA” information is set according to the jackpot type.
As for this ending designation command, when various jackpots are finished, an ending designation command corresponding to the jackpot type is transmitted to the effect control unit 120. Specifically, at the start of the jackpot game end process, an ending designation command corresponding to the jackpot type is set in the transmission data storage area of the main RAM 110c.
Note that the command group in which the “MODE” information is set to “ECH” is a command for ending the jackpot state process. Hereinafter, a command group in which “MODE” information is set to “ECH” is also referred to as a “hit end command”.

The “gaming state designation command” indicates the contents of the gaming state, the information of “MODE” is set as “EDH”, and the information of “DATA” is set according to the contents of the gaming state.
As for the gaming state designation command, a gaming state designation command corresponding to the gaming state is transmitted to the effect control unit 120 at the start and end of variation of the special symbol or at the beginning and end of the big hit game. Specifically, when the special symbol variation display is started, when the special symbol is stopped and displayed, when the high probability game flag, the high probability game number, the short time game flag, and the short time game number (J) are cleared, the high probability When the game flag, the high probability game count, the short-time game flag, and the short-time game count (J) are set, a game status designation command corresponding to the current game status is set in the transmission data storage area of the main RAM 110c.

[Control processing of main control unit]
Hereafter, the control process of the main control part 110 of the gaming machine 1 according to the embodiment of the present invention will be described. First, main processing of the main control unit 110 will be described.
FIG. 10 is a flowchart showing main processing by the main control unit 110 according to the present embodiment.

  When the gaming machine 1 is powered on and powered by the power supply unit 170, a system reset occurs in the main control unit 110, and the main CPU 110a performs initialization processing (processing from step S1 to step S17 in FIG. 10). ) And random number value update processing (step S20 and step S30 in FIG. 10).

In step S1, the main CPU 110a performs a boot process as a premise of the initialization process of the main control unit 110. In this boot process, the main CPU 110a performs its own self-diagnosis process, initializes built-in circuits and peripheral circuits, and sets initial values. Details of the boot process will be described later.
In step S2, the main CPU 110a sets permission to access the main RAM 110c.
In step S3, the main CPU 110a determines whether or not the RAM clear switch is on. If it is determined that the RAM clear switch is on, the main CPU 110a shifts the processing to step S10 to perform RAM clear. On the other hand, if the RAM clear switch is not determined to be on, the process proceeds to step S4.

In step S4, the main CPU 110a generates a checksum in a predetermined storage area of the main RAM 110c when the power is turned on.
In step S5, the main CPU 110a compares the generated checksum with the checksum in the predetermined storage area of the main RAM 110c generated at the time of power interruption. If they match, it is determined to be normal, and the process proceeds to step S6. If they do not match, it is determined to be an error, and the process proceeds to step S10.

In step S <b> 6, the main CPU 110 a adjusts the start timing of the operation after activation with the peripheral control unit 300 including the effect control unit 120 and the intermediate control unit 180. Specifically, after all the peripheral control unit 300 and the intermediate control unit 180 are activated and become in a stable state, the system waits for a certain period of time so that the rendering process and the like can be started at substantially the same timing.
In step S7, the main CPU 110a sets an initial value in a work area of the main RAM 110c that requires an initial value upon recovery from power interruption, and performs a RAM setting process when backup is valid.

In step S8, the main CPU 110a reads the backup information of the main RAM 110c generated at the time of power interruption in order to restore the gaming state at the time of power interruption. Specifically, the game state information is read from the game state storage area of the main RAM 110c that is backed up.
In step S9, the main CPU 110a determines a power restoration designation command based on the read gaming state information, and sets the decided power restoration designation command in the transmission data storage area of the main RAM 110c.

In step S10, the main CPU 110a performs timing adjustment with the peripheral control unit 300 and the intermediate control unit 180 in the same manner as in step S6.
In step S11, the main CPU 110a clears the work area of the main RAM 110c.
In step S12, the main CPU 110a sets initial values in the work area of the main RAM 110c that requires initial values when initializing the gaming machine 1, including setting initial values of various random numbers, and backup is not valid. In this case, the main RAM 110c is set.

In step S13, the main CPU 110a generates a power-on designation command, and sets the generated power-on designation command in the transmission data storage area of the main RAM 110c.
In step S <b> 14, the main CPU 110 a performs a command transmission process for transmitting the control command set in the transmission data storage area to the intermediate control unit 180. That is, a power-on designation command is transmitted to the intermediate control unit 180. Note that the command transmission processing in step S14 and step S16 includes conversion method setting processing, inspection value generation processing, bit string conversion processing, shift amount setting processing, and inspection value addition processing. Further, the command transmission process of step S14 and step S16 involves a process of setting the unique information as an initial setting value in the storage circuit 522. Details of the command transmission process will be described later.

In step S15, the main CPU 110a generates a RAM clear designation command, and sets the generated RAM clear designation command in the transmission data storage area of the main RAM 110c.
In step S16, the main CPU 110a performs a command transmission process for transmitting a control command set in the transmission data storage area of the main RAM 110c to the intermediate control unit 180. That is, the control command of either the power supply restoration designation command or the RAM clear designation command is transmitted to the intermediate control unit 180.
In step S <b> 17, the main CPU 110 a sets the interrupt permission and sets the execution period (α, for example, 4 milliseconds) of the timer interrupt program.

  Note that the command transmission processing in step S14 and step S16 may be performed in the timer interrupt processing performed after interrupt permission in step S17. At this time, it is determined in advance that the transmission order of each control command is not changed.

In step S20, the main CPU 110a performs an effect random number update process for updating the reach determination random number value and the special figure variation random value for determining the variation mode (variation time) of the special symbol.
In step S30, the main CPU 110a performs an initial random number value updating process for updating the special symbol determining initial random number value, the big hit symbol initial random number value, the small hit symbol initial random number value, and the normal symbol determining initial random number value. Thereafter, the processes in steps S20 and S30 are repeated until a predetermined interrupt process is performed.

Next, interrupt processing of the main control unit 110 will be described.
FIG. 11 is a flowchart showing interrupt processing by the main control unit 110 according to the present embodiment.
The main CPU 110a executes a timer interrupt process of the main control unit 110 at every predetermined cycle (α) based on a clock signal output from a clock pulse generation circuit provided in the main control unit 110.

  First, in step S100, the main CPU 110a saves the information stored in the register of the main CPU 110a to the stack area.

  In step S110, the main CPU 110a updates the special symbol time counter, updates the special game timer counter such as the opening time of the special electric accessory, updates the normal symbol time counter, and updates the normal power release time counter. A time control process for updating various timer counters is performed. Specifically, a process of subtracting 1 from a special symbol time counter, a special game timer counter, a normal symbol time counter, and a general electricity open time counter is performed.

In step S120, the main CPU 110a performs a random number update process for the special symbol determination random number value, the big hit symbol random number value, the small hit symbol random number value, and the normal symbol determination random number value.
Specifically, 1 is added to each random number value and random number counter to be updated. When the added random number counter exceeds the maximum value in the random number range (when the random number counter makes one revolution), the random number counter is returned to 0, and each random number value is newly updated from the initial random number value at that time. .

  In step S130, as in step S30, the main CPU 110a updates the initial random number value for special symbol determination, the initial random number value for jackpot symbol, the initial random number value for small bonus symbol, and the initial random number value for normal symbol determination. Perform numerical value update processing.

  In step S200, the main CPU 110a performs input control processing. In this process, the main CPU 110a includes a general winning opening detection switch 12a, a first large winning opening detection switch 16a, a second large winning opening detection switch 17a, a first starting opening detection switch 14a, a second starting opening detection switch 15a, a gate. An input process for determining whether or not there is an input to each switch of the detection switch 13a is performed.

  Specifically, various detection signals from the general winning opening detecting switch 12a, the first big winning opening detecting switch 16a, the second large winning opening detecting switch 17a, the first starting opening detecting switch 14a, and the second starting opening detecting switch 15a. Is inputted, predetermined data is added to a prize ball counter used for a prize ball provided for each winning opening and updated.

  Further, when a detection signal is input from the first start port detection switch 14a, if the data set in the first special symbol hold number (U1) storage area is less than 4, the first special symbol hold number ( U1) Add 1 to the storage area to obtain special symbol determination random number value, jackpot symbol random number value, small hit symbol random number value, reach determination random value, and special symbol variation random value The random number value is stored in a predetermined storage unit (0th storage unit to 4th storage unit) in the first special symbol random value storage area.

  Similarly, when a detection signal is input from the second start port detection switch 15a, if the data set in the second special symbol hold number (U2) storage area is less than 4, the second special symbol hold number (U2) 1 is added to the storage area, and a special symbol determination random number value, a big hit symbol random number value, a small hit symbol random number value, a reach determination random number value, and a special symbol variation random value are acquired. Various random numbers are stored in a predetermined storage unit (0th storage unit to 4th storage unit) in the second special symbol random number value storage area.

  When a detection signal is input from the gate detection switch 13a, if the data set in the normal symbol hold number (G) storage area is less than 4, the normal symbol hold number (G) storage area is set to 1. It adds, acquires the random number value for normal symbol determination, and memorize | stores the acquired random number value for normal symbol determination in the predetermined memory | storage part (0th memory | storage part-4th memory | storage part) in a normal symbol holding | maintenance storage area.

  Further, when a detection signal from the first grand prize opening detection switch 16a or the second big prize opening detection switch 17a is inputted, the number of game balls won in the first big prize opening 16 or the second big prize opening 17 is counted. 1 is added to the number of entries (C) storage area for the big winning opening to update.

  In step S300, the main CPU 110a, based on the input control process in step S200, performs a special symbol / special electric accessory control process (hereinafter referred to as “a special jackpot lottery, a special electric accessory, and a gaming state control”). Special figure special electricity control process ”). Details of the special figure special electric control process will be described later with reference to FIG.

In step S400, the main CPU 110a performs a normal symbol / ordinary electric accessory control process (hereinafter referred to as a “general-purpose electric power control process”) for performing the normal symbol lottery and the control of the ordinary electric accessory.
Specifically, it is first determined whether or not 1 or more data is set in the normal symbol hold count (G) storage area, and 1 or more data must be set in the normal symbol hold count (G) storage area. If this is the case, the current ordinary power transmission control process is terminated.

If 1 or more data is set in the normal symbol holding number (G) storage area, after subtracting 1 from the value stored in the normal symbol holding number (G) storage area, the data is in the normal symbol holding storage area. The normal symbol determination random numbers stored in the first storage unit to the fourth storage unit are shifted to the previous storage unit. At this time, the normal symbol determination random value already written in the 0th storage unit is overwritten and erased.
Then, referring to the hit determination table, a process is performed to determine whether or not the normal symbol determination random number value stored in the 0th storage unit of the normal symbol hold storage area is a random value corresponding to “win”. Thereafter, the normal symbol display device 22 displays the normal symbol variation display, and when the normal symbol variation time has elapsed, the normal symbol corresponding to the result of the normal symbol lottery display is stopped. If the random number for normal symbol determination referred to is “winning”, the start opening / closing solenoid 15c is driven to control the second start opening 15 to the second mode for a predetermined opening time.
Here, in the non-short-time gaming state, the variation time of the normal symbol is set to 29 seconds, and if it is “winning”, the second start port 15 is controlled to the second mode for 0.2 seconds. On the other hand, in the short-time gaming state, the variation time of the normal symbol is set to 3 seconds, and if it is “winning”, the second start port 15 is controlled to the second mode for 3.5 seconds.

  In step S500, the main CPU 110a performs a payout control process. In this payout control process, the main CPU 110 a refers to each prize ball counter, generates payout number designation commands corresponding to various winning ports, and transmits the generated payout number designation commands to the payout control unit 130. To do.

  In step S600, the main CPU 110a, external information data, start opening / closing solenoid data, first big prize opening opening / closing solenoid data, second big prize opening opening / closing solenoid data, special symbol display device data, normal symbol display device data, number of stored Performs data creation for the specified command.

In step S700, the main CPU 110a performs output control processing. In this process, port output processing is performed for outputting signals of the external information data, the start opening / closing solenoid data, the first big prize opening / closing solenoid data, and the second big prize opening / closing solenoid data created in step S600.
Further, the special symbol display device data and the normal symbol display device data created in S600 are used to turn on the LEDs of the first special symbol display device 20, the second special symbol display device 21 and the normal symbol display device 22. Display device output processing is performed.

  In step S710, the main CPU 110a performs a command transmission process of transmitting a control command set in the transmission data storage area of the main RAM 110c to the intermediate control unit 180. Note that the command transmission processing in step S710 also involves conversion method setting processing, inspection value generation processing, bit string conversion processing, shift amount setting processing, and inspection value addition processing, as described above, and details will be described later.

  In step S800, the main CPU 110a restores the information saved in step S100 to the register of the main CPU 110a.

Next, the special figure special electric control process of the main control unit 110 will be described.
FIG. 12 is a flowchart showing a special figure special power control process by the main control unit 110 according to the present embodiment.

  In step S301, the main CPU 110a reads the value of the special figure special electricity processing data. This “Special Figure Special Electric Processing Data” is a value assigned to the address of the storage area in which each subroutine of the special figure special electric control process is stored, and which subroutine is processed by referring to the special figure special electric processing data. You can identify what to do. The special figure special electricity processing data is set as necessary in each subroutine of the special figure special electricity control processing as will be described later, and the subroutine necessary for the game is appropriately processed.

  In step S302, the main CPU 110a refers to the branch address from the read special figure special processing data, and if special figure special electric treatment data = 0, the main CPU 110a moves the processing to the special symbol storage determination process (step S310). If data = 1, the process moves to the special symbol variation process (step S320), and if the special figure special electricity process data = 2, the process moves to the special symbol stop process (step S330), and the special figure special electricity process data = 3. If there is, the process is transferred to the jackpot game process (step S340). If the special figure special electric processing data = 4, the process is transferred to the jackpot game end process (step S350). The processing is moved to processing (step S360).

  In the special symbol memory determination process in step S310, the main CPU 110a performs a jackpot determination process, a special symbol determination process for determining a special symbol to be stopped and displayed, a variation time determination process for determining a variation time of the special symbol, and the like. Here, the specific content of the special symbol memory determination process will be described with reference to FIG.

  FIG. 13 is a flowchart in the special symbol memory determination process by the main control unit 110 according to the present embodiment.

In step S311, the main CPU 110a determines whether or not one or more data is set in the first special symbol hold count (U1) storage area or the second special symbol hold count (U2) storage area.
If one or more data is not set in any storage area of the first special symbol hold count (U1) storage area or the second special symbol hold count (U2) storage area, the special figure special electricity processing data = 0. The special symbol variation process of this time is terminated while holding.
On the other hand, if one or more data is set in the first special symbol hold count (U1) storage area or the second special symbol hold count (U2) storage area, the process proceeds to step S312.

In step S312, the main CPU 110a performs a jackpot determination process.
Specifically, when one or more data is set in the second special symbol hold count (U2) storage area, 1 is calculated from the value stored in the second special symbol hold count (U2) storage area. After the subtraction, the various random numbers stored in the first to fourth storage units in the second special symbol random number storage area are shifted to the previous storage unit. At this time, various random values already written in the 0th storage unit are overwritten and deleted. Then, referring to the jackpot determination table, whether the special symbol determination random number value stored in the 0th storage unit of the second special symbol random value storage area is a random value corresponding to “big hit” or “small hit” It is determined whether it is a random value corresponding to.

  In addition, when one or more data is not set in the second special symbol hold number (U2) storage area and one or more data is set in the first special symbol hold number (U1) storage area, Various random numbers stored in the first to fourth storage units in the first special symbol random number storage area after subtracting 1 from the value stored in the first special symbol hold number (U1) storage area Is shifted to the previous storage unit. Also at this time, various random numbers already written in the 0th storage unit are overwritten and deleted. Then, referring to the jackpot determination table, whether the special symbol determination random number value stored in the 0th storage unit of the first special symbol random number storage area is a random value corresponding to “big hit” or “small hit” It is determined whether it is a random value corresponding to.

  In the present embodiment, the random number value stored in the second special symbol random value storage area is shifted (digested) with priority over the first special symbol random value storage area. However, the first special symbol storage area or the second special symbol storage area may be shifted in the order of winning in the starting opening, and the first special symbol storage area is given priority over the second special symbol storage area. You may let them.

In step S313, the main CPU 110a performs a special symbol determination process for determining the type of special symbol to be stopped and displayed.
In this special symbol determination process, when it is determined as “big hit” in the jackpot determination process (step S312), the symbol determination table is referred to and stored in the 0th storage unit of the first special symbol random value storage area. The jackpot symbol (special symbol 1 to special symbol 6) is determined based on the random number value for the jackpot symbol. In addition, when it is determined as “small hit” in the jackpot determination process (step S312), the small hit stored in the 0th storage unit of the first special symbol random value storage area with reference to the symbol determination table Based on the symbol random number value, the small hit symbol (special symbol A, special symbol B) is determined. Further, when it is determined as “losing” in the jackpot determination process (step S312), the symbol determining table (special symbol 0) is determined with reference to the symbol determining table.
Then, stop symbol data corresponding to the determined special symbol is stored in the stop symbol data storage area.

In step S314, the main CPU 110a performs special symbol variation time determination processing.
Specifically, referring to the variation pattern determination table, based on the reach determination random value and the special diagram variation random value stored in the 0th storage unit of the first special symbol random value storage area, the special symbol Determine the variation pattern. Thereafter, the variation time of the special symbol corresponding to the determined variation pattern of the special symbol is determined. Then, a process of setting a counter corresponding to the determined variation time of the special symbol in the special symbol time counter is performed.

In step S315, the main CPU 110a sets, in a predetermined processing area, variation display data for causing the first special symbol display device 20 or the second special symbol display device 21 to perform special symbol variation display (LED blinking). . As a result, when the variable display data is set in the predetermined processing area, the LED lighting / extinguishing data is appropriately created in step S600, and the created data is output in step S700. Variation display of the special symbol display device 20 or the second special symbol display device 21 is performed.
Further, the main CPU 110a, when the special symbol variation display is started, the special symbol variation pattern designation command (the first special symbol variation pattern designation command) corresponding to the special symbol variation pattern determined in step S314. Alternatively, the second special symbol variation pattern designation command) is set in the transmission data storage area of the main RAM 110c.

  In step S316, the main CPU 110a sets the special symbol special electricity processing data = 0 to the special symbol special electric treatment data = 1, prepares to move to the special symbol variation processing subroutine, and ends the special symbol memory determination processing.

Again, the description of the special figure special electric control process shown in FIG. 12 will be returned.
In the special symbol variation process of step S320, the main CPU 110a performs a process of determining whether or not the special symbol variation time has elapsed.
Specifically, it is determined whether or not the variation time of the special symbol determined in step S314 has elapsed (special symbol time counter = 0), and if it is determined that the variation time of the special symbol has not elapsed The special symbol variation process is terminated while the special symbol special electricity processing data = 1 is held. Note that the special symbol variation time counter set in step S314 is subtracted in step S110.

If it is determined that the variation time of the special symbol has elapsed, the special symbol determined in step S313 is stopped and displayed on the first special symbol display device 20 or the second special symbol display device 21. Thereby, the special symbol is stopped and displayed on the first special symbol display device 20 or the second special symbol display device 21, and the player is notified of the jackpot determination result.
Also, when the number of time reduction (J)> 0, 1 is subtracted from the time reduction (J) counter and updated. When the number of time reduction (J) = 0, the time reduction game flag is cleared and the number of high probability games (X )> 0 is updated by subtracting 1 from the high probability game number (X) counter, and if the high probability game number (X) = 0, the high probability game flag is cleared.
Finally, the special symbol special power processing data = 1 is set to the special symbol special power processing data = 2, preparation is made to move to a special symbol stop processing subroutine, and the special symbol variation processing is terminated.

In the special symbol stop process in step S330, the main CPU 110a performs a process of determining whether the special symbol that is stopped and displayed is a “big hit symbol”, a “small bonus symbol”, or a “losing symbol”. Do.
If it is determined that the game is a jackpot symbol, the data stored in the gaming state storage area is referred to and data (00H to 03H) indicating the current gaming state is set in the gaming state buffer. Thereafter, data (high probability game flag and short time game flag) stored in the game state storage area (high probability game flag storage area and the like and short time game flag storage area), high probability game number (X) counter, short time number (J) Clear the counter. Further, the special figure special power processing data = 2 is set to the special figure special electric processing data = 3, preparation is made to move to the jackpot game processing subroutine, and the special symbol stop processing is terminated.

In addition, when it is determined that the small winning symbol, the data stored in the game state storage area is not cleared, and the special figure special electric processing data = 2 to the special figure special electric treatment data = 5 is set. The special symbol stop process is completed by making preparations for transferring to a winning game process subroutine.
On the other hand, if it is determined that the symbol is a lost symbol, the special symbol special electric processing data = 2 is set to special special electric symbol processing data = 0, and the special symbol memory determination processing subroutine is prepared for the special symbol stop processing. finish.

In the jackpot game process of step S340, the main CPU 110a determines which jackpot of the long hit or short hit is executed, and performs a process of controlling the determined jackpot.
Specifically, first, with reference to the special electric accessory operating mode determination table, the jackpot release mode is determined based on the type of jackpot symbol (stop symbol data) determined in step S313.

Next, in order to execute the determined jackpot opening mode, the bonus game opening mode table is referred to, the opening time corresponding to the type of jackpot is set in the special game timer counter, and the first jackpot opening / closing solenoid The drive data of 16c (or the second big prize opening / closing solenoid 17c) is output to open the first big prize opening / closing door 16b (or the second big prize opening / closing door 17b). At this time, 1 is added to the round game count (R) storage area.
When a predetermined number of game balls enter during the opening or when the opening time of the big prize opening has elapsed (the number of the big prize opening (C) = 9 or the special game timer counter = 0), The output of the drive data of the big prize opening / closing solenoid 16c (or the second big prize opening / closing solenoid 17c) is stopped, and the first big prize opening / closing door 16b (or the second big prize opening / closing door 17b) is closed. Thereby, one round game is completed. This round game control is repeated 15 times.

  When the 15 round games are completed (round game count (R) = 15), the data stored in the round game count (R) storage area and the number of winning prize entrance (C) storage areas are cleared, The special figure special electric processing data = 3 is set to the special figure special electric treatment data = 4, preparation is made to move to the big hit game end processing subroutine, and the big hit game processing is ended.

In the jackpot game ending process in step S350, the main CPU 110a determines the probability game state of either the high probability game state or the low probability game state, and changes the game state of either the short-time game state or the non-time-short game state. Perform the decision process.
Specifically, with reference to the jackpot game end setting data table, based on the data stored in the game state buffer and the type of jackpot symbol (stop symbol data) determined in step S313, the high probability game A flag is set, a high probability game count (X) is set, a short-time game flag is set, and a short-time count (J) is set. For example, in the case of the special symbol 1, the high probability game flag is set in the high probability game flag storage area, and the high probability game number (X) counter is set to 10,000 times. Further, the time-shortage game flag is set in the time-shortage game flag storage area, and the time-shortage number (J) counter is set to 10,000 times.
After that, the special symbol special power processing data = 4 is set to the special symbol special power processing data = 0, preparation is made to move to a special symbol memory determination processing subroutine, and the jackpot game end processing is terminated.

In the small hit game process of step S360, the main CPU 110a first refers to the special electric accessory operation mode determination table, and based on the type of small hit symbol (stop symbol data) determined in step S313 above, Determine the opening mode.
Next, in order to execute the determined small winning opening mode, the large winning opening opening mode table is referred to, and the small winning opening time is set in the special game timer counter, and the second large winning port opening / closing solenoid 17c is set. The drive data is output to open the second big prize opening / closing door 17b. At this time, 1 is added to the number-of-releases (K) storage area.
When the small winning opening time elapses (special game timer counter = 0), the drive data output of the second big prize opening / closing solenoid 17c is stopped and the second big prize opening / closing door 17b is closed. The opening / closing control of the second big prize opening opening / closing door 17b is repeated 15 times.

  Then, the opening / closing control of the second grand prize opening / closing door 17b is performed 15 times, or a predetermined number of game balls enter the second big prize opening 17 (the number of times of opening (K) = 15 or the grand prize opening entrance) Number (C) = 9), in order to end the small hit game, the output of the drive data of the second large winning opening / closing solenoid 17c is stopped, the number of times of opening (K) storage area and the number of winning winning holes (C) Clear the data stored in the storage area, set special figure special electricity processing data = 5 to special figure special electricity treatment data = 0, and prepare to move to a special symbol memory judgment processing subroutine. The winning game process is terminated.

[Control processing related to authentication processing of the main control unit]
Hereafter, the control process regarding the authentication process of the main control part 110 of the gaming machine 1 according to the embodiment of the present invention will be described. First, the boot process of the main control unit 110 will be described.
When the gaming machine 1 is powered on, a system reset occurs in the main control unit 110, and the main CPU 110a performs a boot process of the main control unit 110 based on a boot processing program stored in advance in the boot ROM 110d. .
FIG. 14 is a flowchart showing a boot process by the main control unit 110 according to the present embodiment.

In step S51, the main CPU 110a sets the internal state to interrupt prohibition.
In step S52, the main CPU 110a performs a self-diagnosis process for checking whether or not the main CPU 110a itself can operate normally after initialization. As a result of the self-diagnosis process, if the normal operation is possible, the process proceeds to step S53.

  In step S53, the main CPU 110a performs an initial value setting process for a built-in circuit or the like. Specifically, the main CPU 110a sets the stack point designation address in the stack pointer, initializes the internal register, initializes the internal circuit and peripheral circuits of the one-chip microcomputer 110m, and initializes the input / output ports. I do. Then, the main CPU 110a sets various initial values to these built-in circuits that require initial values. At this time, the main CPU 110a performs the same process on each component of the inspection value generation unit 500 to perform an initial value setting process on the inspection value generation unit 500.

  In step S54, the main CPU 110a performs HW parameter setting processing on the inspection value generation unit 500. Specifically, the main CPU 110a outputs a read signal for reading the HW parameter for the inspection value generation unit 500 to the main ROM 110b. Then, the main CPU 110a takes in the HW parameters output from the main ROM 110b by the read signal via the bus.

  Subsequently, the main CPU 110 a outputs a write signal for writing the fetched HW parameter to the determination unit 540 of the test value generation unit 500 and a write signal for writing to the generation unit 520. Then, the main CPU 110a sets the HW parameter output from the main CPU 110a in response to the write signal to the shift amount control unit C that bears the determination circuit 542 of the determination unit 540 and the bit string conversion circuit 525 of the generation unit 520 via the bus. . Note that the HW parameter setting process in step S54 is a special feature of the process of setting the HW parameter in the test value generation unit 500 among the initial value setting processes performed by the main CPU 110a. Therefore, as part of the initial value setting process, It is also possible to configure so as to be performed in step S53.

  In step S55, the inspection value generation unit 500 performs change condition setting processing. Specifically, the determination circuit 542 of the determination unit 540 confirms to which change condition the set HW parameter corresponds to a change condition among a plurality of change conditions prepared in advance. Then, the determination circuit 542 sets the change condition corresponding to the set HW parameter in the change condition storage area (D) as a default change condition. Then, the determination circuit 542 sets the change condition set in the change condition storage area (D) in the change condition storage unit 541a that bears the determination circuit 541 of the determination unit 540. The determination circuit 541 outputs the bit pattern of the change condition set in the change condition storage unit 541a to the comparator 541b.

  Thereby, the determination unit 540 can determine whether or not the control command output from the buffer unit 510 is a control command that satisfies the change condition during the command transmission processing after the boot processing. It is possible to perform conversion method setting processing according to the above.

  In step S56, the inspection value generation unit 500 performs an update timing condition setting process. Specifically, the shift amount control unit C responsible for the bit string conversion circuit 525 of the generation unit 520 determines that the set HW parameter has a value corresponding to which update timing condition among a plurality of update timing conditions prepared in advance. Check if it exists. Then, the shift amount controller C sets the update timing condition corresponding to the set HW parameter in the update timing condition storage area (CR) as a default condition. The shift amount control unit C updates the shift amount A according to the update timing condition set in the update timing condition storage area (CR).

  In step S57, the inspection value generation unit 500 performs conversion method setting processing. Specifically, the determination circuit 542 of the determination unit 540 sets conversion method information indicating the conversion method A, which is a default conversion method decided in advance, in the conversion method information storage area (S) as a default value. Based on the value set in the conversion method information storage area (S), the determination circuit 542 performs the bit string conversion process by the rotation calculator A among the plurality of rotate calculators that bear the bit string conversion circuit 525 of the generation unit 520. The conversion method control signal is output to the control circuit 523 of the generation unit 520 so that the error check value subjected to is output. The control circuit 523 of the generation unit 520 outputs an input selection signal corresponding to the conversion method control signal to the input selection circuit 524.

  In step S58, the inspection value generation unit 500 performs a shift amount setting process. Specifically, the control circuit 523 of the generation unit 520 outputs a shift amount control signal to the shift amount control unit C that is responsible for the bit string conversion circuit 525 based on the input of the conversion method control signal. Based on the input of the shift amount control signal output from the control circuit 523, the shift amount control unit C responsible for the bit string conversion circuit 525 sends a shift amount A setting signal to the rotate computing unit A responsible for the bit string conversion circuit 525. The default shift amount A that is output and stored in the shift amount storage area (CS) is set in the rotation calculator A. In addition, the shift amount control unit C outputs a shift amount B setting signal to the rotate computing unit B that bears the bit string conversion circuit 525 based on the input of the shift amount control signal output from the control circuit 523, and shifts The default shift amount B stored in the amount storage area (CS) is set in the rotation calculator B.

  As a result, the generation unit 520 adds the error check value that has been subjected to the bit rotation operation by the rotation operation unit corresponding to the conversion method information stored in the conversion method information storage area (S) during the bit string conversion process. 530 can be output. Further, the error check value can be used as an error check value obtained by performing a bit rotation operation using the shift amount stored in the shift amount storage area (CS) and converting the bit string. The adding unit 530 can add the error check value obtained by converting the bit string with the conversion method and the shift amount to the control command output from the buffer unit 510 in the check value adding process. When this process ends, the boot process ends.

Next, command transmission processing of the main control unit 110 including conversion method setting processing, inspection value generation processing, bit string conversion processing, shift amount setting processing, and inspection value addition processing will be described.
FIG. 15 is a flowchart showing command transmission processing in the main control unit 110 according to the present embodiment. In each step of FIG. 15, the notation in curly braces {} represents the generated number storage area (P), the change timing information storage area (Mi), and the change timing information storage area (Mi) provided in the determination circuit 542 of the inspection value generation unit 500. This is to outline the processing for the conversion method information storage area (S).

  After the initialization process including the boot process of the main control unit 110, when the execution timing of the command transmission process is reached, the main CPU 110a checks the control command (P) set in the transmission data storage area of the main RAM 110c. The data is output to the transmission unit 550 via the value generation unit 500 and transmitted to the intermediate control unit 180.

In step S71, the main CPU 110a adds 1 to the value of the generated number storage area (P) of the main RAM 110c and updates it.
In step S72, the main CPU 110a determines whether or not the control command (P) set in the transmission data storage area corresponds to the control command (1). Specifically, the main CPU 110a refers to the value of the generated number storage area (P) and determines whether P = 1. If P = 1, the process proceeds to step S73, and if P = 1, the process proceeds to step S75.

In step S73, the main CPU 110a reads the unique information stored in the main ROM 110b. Then, the main CPU 110a outputs the read unique information to the inspection value generation unit 500.
In step S74, the test value generation unit 500 stores the unique information output from the main CPU 110a in each of the storage circuits (P-1) to (PN) serving as the storage circuit 522 of the generation unit 520, and performs initial setting. Set as a value. Specifically, the buffer unit 510 of the inspection value generation unit 500 takes in the unique information from the main CPU 110a via the bus to the data buffer 511 and outputs it to the generation unit 520. The generation unit 520 stores the unique information output from the data buffer 511 in each of the storage circuits (P-1) to (PN) that bears the storage circuit 522.

  In step S75, the main CPU 110a writes the control command (P) set in the transmission data storage area to the buffer means 510 of the inspection value generation unit 500. Specifically, the main CPU 110a outputs a write signal and address data for writing the control command (P) to the buffer means 510, and sends the control command (P) set in the transmission data storage area to the data bus. Output. The control circuit 512 of the buffer unit 510 outputs an operation permission signal to the data buffer 511 of the buffer unit 510 based on the input of the write signal output from the main CPU 110a. The data buffer 511 takes in the control command (P) on the data bus based on the input of the operation permission signal output from the control circuit 512.

  In step S76, the buffer unit 510 outputs the fetched control command (P) to the determination unit 540, the generation unit 520, and the addition unit 530. Specifically, the control circuit 512 of the buffer unit 510 outputs an operation permission signal to the data buffer 511 with a predetermined time delay from the input of the write signal output from the main CPU 110a. The data buffer 511 outputs the fetched control command (P) to the determination unit 540, the generation unit 520, and the addition unit 530 based on the input of the operation permission signal. Subsequently, the control circuit 512 outputs an operation permission signal to these means so that the control command output from the data buffer 511 can be input by the determining means 540, the generating means 520, and the adding means 530. .

  In step S77, the determination unit 540 takes in the control command (P) based on the input of the operation permission signal output from the buffer unit 510, and determines the type of the control command (P). Specifically, the determination circuit 541 of the determination unit 540 determines that the control command (P) is the first control command generated in the predetermined control command group and the generation of the predetermined control command group is completed. It is determined whether it corresponds to one of the control commands generated first. The determination circuit 541 determines a determination result signal indicating that the control command output from the buffer means 510 is a control command satisfying the change condition if the control command (P) is a control command corresponding to any of the control commands (P). The data is output to the circuit 542, and the process proceeds to step S78. On the other hand, if the control command (P) is not one of the control commands, the determination circuit 541 outputs a determination result signal indicating that the control command output from the buffer means 510 is not a control command that satisfies the change condition. The data is output to the decision circuit 542, and the process proceeds to step S78.

In step S78, the determination circuit 542 updates the value of the generated number storage area (P) provided in the determination circuit 542 by adding 1 in accordance with the input of the determination result signal output from the determination circuit 541. Thereby, the determination circuit 542 can grasp the number P of generated control commands (P) output from the buffer unit 510.
In step S79, the determination circuit 542 is a determination result signal indicating that the determination result signal output from the determination circuit 541 is that the control command (P) output from the buffer unit 510 satisfies the change condition. Check if it exists. If the content of the determination result signal indicates that the control command (P) is a control command that satisfies the change condition, the determination circuit 542 moves the process to step S80. On the other hand, if the content of the determination result signal indicates that the control command (P) is not a control command that satisfies the change condition, the determination circuit 542 moves the process to step S81.

In step S80, when a control command that satisfies the change condition is output from the buffer means 510, the decision circuit 542 calculates the conversion method change timing, that is, the value of S stored in the conversion method information storage area (S). Set the timing to change. Specifically, the decision circuit 542 sets Mo in advance to the value of the current generated number storage area (P) with respect to its own change timing information storage area (Mi) in order to set the change timing information Mi. A value obtained by adding the values (P + Mo) is stored.
In step S81, the determination circuit 542 determines whether it is time to change the conversion method. Specifically, the determination circuit 542 compares the minimum value Mmin of the change timing information storage area (Mi) with the value of the current generated number storage area (P). If the two match, the determination circuit 542 determines that the current timing is the change timing, moves to step S82, and if both do not match, the determination circuit 542 determines that the current timing is not the change timing. The processing is moved to S84.

  In step S82, the determination circuit 542 changes the value of S indicating the conversion method information stored in the conversion method information storage area (S) in order to change the conversion method. Specifically, the determination circuit 542 changes the value of S indicating the conversion method information according to a predetermined change method, and sets S ′, which is the value of S indicating the changed conversion method information, in the conversion method information storage area. Store in (S). Then, the determination circuit 542 generates a conversion method control signal based on the changed S ′ value stored in the conversion method information storage area (S) in order to set the changed conversion method in the generation unit 520. It outputs to the control circuit 523 of 520.

  In step S <b> 83, the control circuit 523 of the generation unit 520 determines a specific rotation calculation among a plurality of rotation calculation units that bear the bit string conversion circuit 525 of the generation unit 520 based on the conversion method control signal output from the determination circuit 542. An input selection signal that enables only the connection between the generator and the input selection circuit 524 of the generation means 520 is output to the input selection circuit 524. Based on the input selection signal, the input selection circuit 524 sets a connection with a specific rotation calculator. The generation unit 520 adds the error check value that has been subjected to the bit string conversion processing by the specific rotation arithmetic unit according to the conversion method after the change by inputting the input selection signal to the input selection circuit 524. 530 can be output.

  In addition, the control circuit 523 of the generation unit 520 outputs a shift amount control signal to the shift amount control unit C responsible for the bit string conversion circuit 525 based on the input of the conversion method control signal output from the determination circuit 542. Thus, the shift amount control unit C can detect that the period of the predetermined operation mode has started or ended.

  In step S84, the generation unit 520 captures and stores the control command (P) based on the input of the operation permission signal output from the buffer unit 510, and also stores the control command (PN) stored in the past. Is output to the generation circuit 521. Specifically, the control circuit 523 of the generation unit 520 outputs a shift processing signal to the storage circuit 522 based on the input of the operation permission signal output from the control circuit 512 of the buffer unit 510. Based on the input of the shift processing signal output from the control circuit 523, the storage circuit 522, from among the storage circuits (P-1) to (PN), from the storage circuit (PN) at the final stage, The control command (PN) stored in the storage circuit is output to the generation circuit 521. At the same time, the storage circuit 522 sequentially shifts the control commands stored in the storage circuits (P-1) to (PN) to the next stage and outputs the control commands output from the data buffer 511 of the buffer means 510. (P) is newly taken in and stored in the first stage storage circuit (P-1).

  In step S85, the generation circuit 521 takes in the control command (PN) output from the storage circuit 522 based on the input of the operation permission signal output from the control circuit 523. Then, the generation circuit 521 generates an error check value (PN) by a preset generation method using the fetched control command (PN), and outputs the error check value (PN) to the bit string conversion circuit 525.

  In step S <b> 86, the bit string conversion circuit 525 performs bit string conversion processing on the error check value (PN) output from the generation circuit 521 and outputs the result to the adding unit 530. Specifically, the rotate arithmetic unit A that takes charge of the bit string conversion circuit 525 takes in the error check value (PN) output from the generation circuit 521, and stores the error check value (PN) in advance in the bit string of the read error check value (PN). Bit rotation calculation is performed with the set shift amount A. Then, the rotation calculator A uses the error check value (PN) that has been subjected to the bit rotation calculation with the shift amount A as the error check value (PN) that has been subjected to the bit string conversion processing by the conversion method A. The data is output to the input selection circuit 524. Further, the rotation calculator B of the bit string conversion circuit 525 takes in the error check value (PN) output from the generation circuit 521 and shifts the bit string of the error check value (PN) thus set in advance. A bit rotate operation is performed with the quantity B. Then, the rotation calculator B uses the error check value (PN) that has been subjected to the bit rotation calculation by the shift amount B as the error check value (PN) that has been subjected to the bit string conversion processing by the conversion method B. The data is output to the input selection circuit 524 and the shift amount control unit C.

  Based on the input selection signal output from the control circuit 523, the input selection circuit 524 effectively activates only the connection with either the rotation calculator A or B. Therefore, the bit string conversion circuit 525 uses only the error check value output from the specific rotation operator whose connection with the input selection circuit 524 is effectively operated as the error check value (PN) obtained by converting the bit string. Output to the adding means 530.

  In step S87, the shift amount control unit C responsible for the bit string conversion circuit 525 determines whether it is time to update the shift amount. Specifically, the shift amount control unit C detects the start or end of the period of the predetermined operation mode based on the input of the shift amount control signal output from the control circuit 523, and the current is in the predetermined operation mode. It is determined whether it is during the period.

  Then, the shift amount control unit C determines that it is now time to update the shift amount A and the shift amount B at the time when the period of the predetermined operation mode starts, and moves the process to step S88. . Further, the shift amount control unit C determines that it is currently the timing to update only the shift amount B if it is during a predetermined operation mode period, and moves the process to step S88. Further, the shift amount control unit C determines that the current timing is when the update of the shift amount B is stopped at the time when the period of the predetermined operation mode ends, and moves the process to step S88. On the other hand, the shift amount control unit C is not currently at the timing to update the shift amount unless it is the time when the current period of the predetermined operation mode starts or ends or the current time is not during the period of the predetermined operation mode. Is determined, and the process proceeds to step S89.

  In step S88, the shift amount control unit C responsible for the bit string conversion circuit 525 controls the shift amount. Specifically, the shift amount control unit C updates the shift amount A and the shift amount B at the time when the current period of the predetermined operation mode starts. That is, the shift amount control unit C performs the shift amount setting process related to the shift amount A based on the error check value output from the rotate computing unit B and the shift amount A stored in the shift amount storage area (CS). The value is updated according to a predetermined update method related to the shift amount A. Then, the shift amount control unit C outputs a shift amount A setting signal to the rotation calculator A, and sets the updated shift amount A stored in the shift amount storage area (CS) in the rotation calculator A. In addition, the shift amount control unit C acquires a random value as a shift amount setting process related to the shift amount B, and updates the value of the shift amount B stored in the shift amount storage area (CS) using the random number value. Then, the shift amount control unit C outputs a shift amount B setting signal to the rotation calculator B, and sets the updated shift amount B stored in the shift amount storage area (CS) in the rotation calculator B.

  Further, the shift amount control unit C updates only the shift amount B if the current point in time is in the predetermined operation mode. That is, as the shift amount setting process related to the shift amount B, the shift amount control unit C acquires a random value, updates the value of the shift amount B stored in the shift amount storage area (CS), and sets the shift amount B. A signal is output and the updated shift amount B is set in the rotation calculator B. In addition, the shift amount control unit C discards the error check value output from the rotation computing unit B without updating the shift amount B when the present time period of the predetermined operation mode ends.

  In step S89, the adding means 530 takes in the control command (P) and the error check value (PN) based on the input of the operation permission signal output from the buffer means 510. Then, the adding unit 530 writes the fetched control command (P) and error check value (PN) to the transmission unit 550. Specifically, the input selection circuit 531 of the adding unit 530 receives the control command (P) output from the data buffer 511 of the buffer unit 510 and outputs the acquired control command (P) to the data bus. Further, the control circuit 532 of the adding unit 530 writes a control signal (P) to the transmission buffer 551 of the transmission unit 550 based on the input of the operation permission signal output from the control circuit 512 of the buffer unit 510. And output address data.

  Further, the control circuit 532 outputs an input selection signal to the input selection circuit 531 with a predetermined time delay from the output of the write signal. The input selection circuit 531 switches the connection source from the data buffer 511 to the input selection circuit 524 of the generation unit 520 based on the input of the input selection signal output from the control circuit 532. Then, the input selection circuit 531 takes in the error check value (PN) output from the generation circuit 521 of the generation means 520 via the input selection circuit 524, and takes the error check value (PN) thus taken in the data bus. Output to. In addition, when the control circuit 532 outputs the input selection signal and the error check value (PN) is output from the input selection circuit 531 onto the data bus, the error check value (PN) is sent to the transmission buffer 551. A write signal and address data for writing are immediately output.

  In step S90, the transmission unit 550 immediately transmits the control command (P) and the error check value (P-N) output from the adding unit 530 to the intermediate control unit 180. Specifically, the transmission buffer 551 of the transmission unit 550 receives the control command (P) on the data bus based on the input of the write signal of the control command (P) output from the adding unit 530, and takes in the control. The command (P) is immediately output to the transmission circuit 552. The transmission buffer 551 takes in the error check value (PN) on the data bus based on the input of the write signal of the error check value (PN) output from the adding means 530, and takes in the error check. The value (P−N) is immediately output to the transmission circuit 552. The transmission circuit 552 immediately transmits the control command (P) and error check value (PN) output from the transmission buffer 551 to the intermediate control unit 180 as a series of transmission data. Therefore, the control command (P) is transmitted to the intermediate control unit 180 as a control command to which the error check value (PN) is added.

Note that the process of step S84 only needs to be performed between step S76 and step S85, and need not be performed immediately after step S83.
In step S89, when the control circuit 532 outputs an input selection signal to the input selection circuit 531, the control command (P) output from the input selection circuit 531 is completely written to the transmission buffer 551. After the elapse of the time required until the error check value (PN), the timing is set such that the writing of the error check value (PN) to the transmission buffer 551 is started. As a result, the error check value (PN) is written into the transmission buffer 551 so that the error check value (PN) is written immediately after the control command (P) written in the transmission buffer 551. It will be the right timing.

  By setting the error check value write timing as described above, an overrun or underrun of the transmission buffer 551 occurs, and an error check value (P−) to be added to the control command (P) to be transmitted this time. N) can be prevented from being added appropriately. This is because the error check value actually added and transmitted during the error check process in the intermediate control unit 180 is not consistent with the error check value to be originally added. The possibility that the inspection result will not be determined to be normal is suppressed, and the accuracy of the error inspection process is improved.

  Also, by setting the error check value write timing as described above, the error check value (PN) to be added this time is written to the transmission buffer 551 and the control command (P) is sent to the transmission buffer 551. The positional relationship of the write timing on the time axis is clarified, and the error check value (PN) is surely added immediately after the control command (P) and transmitted as one transmission data. Thereby, the error check value (PN) is not transmitted to the intermediate control unit 180 as a single error check value (PN). Therefore, it becomes difficult for an unauthorized person to steal transmission data between the main control unit 110 and the intermediate control unit 180, illegally analyze and reuse the error check value (PN), and the gaming machine 1 Security strength can be improved.

[Control processing of intermediate control unit]
Hereafter, the control process of the intermediate control unit 180 of the gaming machine 1 according to the embodiment of the present invention will be described.
FIG. 16 is a flowchart showing main processing by the intermediate control unit 180 according to the present embodiment. In each step of FIG. 16, the notation in curly braces {} indicates the received number storage area (P), the change timing information storage area (Mi), and the conversion method information storage area (S) provided in the RAM 180c. It is intended to outline the process.

  In step S4010, the CPU 180a performs initialization processing. In this process, the CPU 180a reads a program code related to the main process from the ROM 180b in response to power-on. Along with this, the CPU 180a performs processing for initializing flags and the like stored in the RAM 180c and setting the set values.

  In step S4010, processing for setting an error check value output function corresponding to the error check value addition function of the main control unit 110 to the check value generation unit 620 is performed. That is, the CPU 180a performs the same processes as the HW parameter setting process, the change condition setting process, the change timing condition setting process, the conversion method setting process, and the shift amount setting process executed during the boot process in the main control unit 110. . At that time, the CPU 180a determines the update timing condition related to the default conversion method and the shift amount A by the determination unit 623, and sets the bit string conversion unit 624 according to the determined conversion method and the update timing condition related to the shift amount A. Do. If this process ends, the process moves to a step S4020.

In step S4020, CPU 180a determines whether or not the control command transmitted from main control unit 110 has been received.
When the reception unit 600 of the intermediate control unit 180 receives the control command transmitted from the main control unit 110 and stores it in its own reception buffer, it indicates that the main control unit 110 has received a control command reception interrupt request. A signal is output to generate a control command reception interrupt process.
In step S4020, the CPU 180a waits until the reception interrupt request signal from the reception unit 600 is input. When the signal from the reception unit 600 is input, the CPU 180a stores the control command stored in the reception buffer. Error check processing is performed on Specifically, it is the process of the next step S4030 to step S4230.

In step S4030, when a signal indicating that a control command reception interrupt request has been made is output from the reception unit 600, the CPU 180a updates the value of the reception number storage area (P) of the RAM 180c.
In step S4040, the CPU 180a determines whether or not the control command (P) stored in the reception buffer of the reception unit 600 corresponds to the control command (1). Specifically, the CPU 180a refers to the value of the received number storage area (P) and determines whether P = 1. If P = 1, the process proceeds to step S4050, and if P = 1, the process proceeds to step S4070.

In step S4050, the CPU 180a reads unique information stored in the ROM 180b. Then, the CPU 180a outputs the read unique information to the inspection value generation unit 620.
In step S4060, the CPU 180a stores the unique information output to the inspection value generation unit 620 in the storage unit 622 in the inspection value generation unit 620, and sets it as an initial setting value.

In step S4070, the CPU 180a extracts the error check value (PN) added to the control command (P) from the control command (P) stored in the reception buffer of the reception unit 600.
In step S4080, the CPU 180a outputs the extracted error check value (PN) to the check unit 610, and outputs the control command (P) after extracting the error check value (PN) to the check value generation unit 620. The data is output to the storage unit 622, the determination unit 623, and the addition unit 630.

In step S4090, the CPU 180a takes in the control command (P) output from the receiving unit 600, and the determining unit 623 determines the type of the control command (P). Specifically, the CPU 180a controls the control command (P) to be generated first after the control command generated first in the predetermined control command group and the generation of the predetermined control command group is finished. It is determined whether it corresponds to one of the commands.
In step S4100, if the control command (P) is one of the control commands, the CPU 180a determines that the extracted control command (P) is a control command that satisfies the change condition, and the process proceeds to step S4110. Move processing. On the other hand, if the control command (P) is not a control command corresponding to any of the control commands, the CPU 180a determines that the extracted control command (P) is not a control command satisfying the change condition, and moves the process to step S4120. .

If CPU 180a determines in step S4110 that a control command satisfying the change condition has been received, CPU 180a changes the conversion method, that is, determines the timing for changing the value of the conversion method information stored in the conversion method information storage area (S). Set in section 623. Specifically, the CPU 180a adds the predetermined value of Mo to the value of the current generated number storage area (P) to the change timing information storage area (Mi) in order to set the change timing information Mi. The obtained value (P + Mo) is stored.
In step S4120, the CPU 120a determines in the determination unit 623 whether or not the present time is the timing for changing the conversion method. Specifically, the CPU 180a compares the minimum value Mmin of the change timing information storage area (Mi) with the value of the current reception number storage area (P). If they match, the CPU 180a determines that the current timing is the change timing, and moves to step S4130. If they do not match, the CPU 180a determines that the current timing is not the current timing, and proceeds to step S4150. Move processing.

In step S4130, the CPU 180a changes the value of S indicating the conversion method information stored in the conversion method information storage area (S) in the determination unit 623 to change the conversion method. Specifically, the CPU 180a changes the value of S indicating the conversion method information in accordance with a predetermined change method, and converts S ′ indicating the conversion method information after the change into a conversion method information storage area (S ).
In step S4140, the CPU 180a sets the conversion method corresponding to the changed value of S ′ stored in the conversion method information storage area (S) in the bit string conversion unit 624 by the determination unit 623. The bit string conversion unit 624 can output to the checking unit 610 an error check value that has been subjected to bit string conversion processing by the conversion method after the change.

In step S4150, the CPU 180a stores the control command (P) output from the receiving unit 600 in the storage unit 622 and generates the control command (PN) stored in the past from the storage unit 622. Output to 621.
In step S4160, the CPU 180a uses the control command (PN) output from the storage unit 622 to generate an error check value (PN) using the preset generation method in the generation unit 621. The data is output to the bit string conversion unit 624.

  In step S4170, the CPU 180a performs a bit string conversion process on the error check value (PN) generated by the generation unit 621 by the bit string conversion unit 624, and outputs the result to the check unit 610. Specifically, if the conversion method set by the determination unit 623 is conversion method A, the CPU 180a uses a bit amount of a preset shift amount A with respect to the bit sequence of the error check value (PN). The conversion unit 624 performs a bit rotation operation. Then, the CPU 180a outputs the error check value (PN) returned to the original bit string, which is the obtained calculation result, to the check unit 610.

  In addition, when the conversion method set by the determination unit 623 is conversion method B, the CPU 180a, for the bit string of the error check value (PN), the bit of the bit string of the error check value (PN). The bit string conversion unit 624 performs bit rotation calculation for the number of rotations that can be taken by the number of rotations defined by the width. Then, the CPU 180a outputs error check values (PN) corresponding to the number of ranges that can be taken by the rotation number, to which the bit string is converted, to the check unit 610, respectively.

  In step S4180, the CPU 180a compares the error check value (PN) output from the receiving unit 600 with the error check value (PN) output from the bit string converter 624 in the check unit 610. Collate. If the two match, the CPU 180a determines that the inspection result of the error inspection is normal. On the other hand, if the two do not match, the CPU 180a determines that the inspection result is not normal.

  When the conversion method B is set and the error check values (PN) are output from the bit string conversion unit 624 for the number of rotations that can be taken, the CPU 180a outputs all the error checks that have been output. The value (P−N) is compared with the error check value output from the receiving unit 600 and collated. At this time, if any error check value (PN) output from the bit string conversion unit 624 matches the error check value output from the reception unit 600, the CPU 180a determines that the check result is normal. If any error check value (PN) does not match the error check value output from the receiving unit 600, it is determined that the check result is not normal.

  In step S4190, CPU 180a determines whether or not the inspection result is normal in inspection unit 610. When it is determined that the inspection result is normal, the CPU 180a generates the control command (P) to which the currently received error check value (PN) is added and the current error check value (PN). It is determined that the validity of the main control unit 110 has been authenticated because the validity of the original N previous control commands (PN) has been authenticated. Then, the CPU 180a determines that the gaming machine 1 is operating normally, and moves the process to step S4200. On the other hand, if it is determined that the test result is not normal, the CPU 180a determines that the validity of the main control unit 110 has not been authenticated. Then, the CPU 180a determines that there is a possibility that an illegal act or the like has occurred in the gaming machine 1, and moves the process to step S4210.

In step S4200, CPU 180a generates authentication result data indicating successful authentication in inspection unit 610, outputs the generated authentication result data to adding unit 630, and moves the process to step S4220.
In step S4210, the CPU 180a generates authentication result data indicating unsuccessful authentication in the inspection unit 610, outputs the generated authentication result data to the adding unit 630, and shifts the processing to step S4240.

  In step S4220, CPU 180a determines in decision unit 623 whether or not the present time is the timing for updating the shift amount. Specifically, CPU 180a determines that it is now time to update shift amount A at the time when the period of the predetermined operation mode starts, and moves to step S4230. . Further, the CPU 180a determines that the current timing is not the time for updating the shift amount A unless it is the time when the period of the predetermined operation mode has started, and moves the process to step S4240.

  In step S4230, the CPU 180a controls the shift amount. Specifically, the CPU 180a sets the conversion method B at the time when the period of the predetermined operation mode starts, and sets the conversion method B and outputs a plurality of (rotate counts) output from the bit string conversion unit 624 to the inspection unit 610. The error check value (PN) that matches the error check value output from the receiving unit 600 among the error check values (PN) of the number of obtained ranges) is output to the determining unit 623. Then, CPU 180a updates shift amount A in accordance with a predetermined update method based on the error check value, and moves the process to step S4240.

In step S4240, the CPU 180a adds the authentication result data output from the inspection unit 610 to the control command (P) output from the receiving unit 600, and adds a control command with authentication result data. (P) is output to the relay transmission unit 640, and the process proceeds to step S4250.
In step S4250, CPU 180a immediately transmits control command (P) with authentication result data as transmission data to effect control unit 120 at relay transmission unit 640. Thereafter, the processes after step S4020 are repeated until a predetermined interrupt process is performed.

  Note that the process of step S4150 only needs to be performed between step S4080 and step S4160, and need not be performed immediately after step S4140. Further, the processes of step S4220 and step S4230 may be performed after step S4180, and need not be performed immediately after step S4200. Further, after the process of step S4210, the process may be transferred to step S4220 instead of the process to step S4240.

[Control processing of production control unit]
Hereafter, the control process of the production control unit 120 of the gaming machine 1 according to the embodiment of the present invention will be described. First, the main process of the production control unit 120 will be described.
FIG. 17 is a flowchart showing main processing by the effect control unit 120 according to the present embodiment.

  In step S1000, the sub CPU 120a performs an initialization process. In this process, the sub CPU 120a reads the program code related to the main process from the sub ROM 120b in response to power-on. At the same time, the sub CPU 120a initializes a flag and the like stored in the sub RAM 120c, and performs a process of setting a setting value. If this process ends, the process moves to a step S1100.

  In step S1100, the sub CPU 120a performs an effect random number update process. In this process, the sub CPU 120a performs a process of updating the effect random number value, effect design determining random number, effect mode determining random number and the like stored in the sub RAM 120c. Thereafter, the process of step S1100 is repeated until a predetermined interrupt process is performed.

Next, the interruption process of the production control unit 120 will be described.
FIG. 18 is a flowchart showing interrupt processing by the effect control unit 120 according to the present embodiment.
Based on a clock signal output from a clock pulse generation circuit (not shown) provided in the effect control unit 120, the sub CPU 120a performs timer allocation of the effect control unit 120 every predetermined period (for example, 2 milliseconds). Execute the included process.

In step S1200, the sub CPU 120a saves the information stored in the register of the sub CPU 120a to the stack area.
In step S1300, the sub CPU 120a performs update processing of various timer counters used in the effect control unit 120.

  In step S1500, the sub CPU 120a performs command analysis processing. In this process, the sub CPU 120a performs a process of analyzing the type of control command stored in the received data storage area of the sub RAM 120c.

When the receiving unit (not shown) of the effect control unit 120 receives the control command transmitted from the intermediate control unit 180 and stores it in its own reception buffer, there is a control command reception interrupt request from the intermediate control unit 180. A signal indicating that the control command has been received is generated, and a control command reception interrupt process is generated.
Then, the sub CPU 120a performs an authentication result data analysis process for analyzing the contents of the authentication result data added to the received control command. When the sub-CPU 120a confirms that the validity of the control command has been authenticated by the intermediate control unit 180 in the authentication result data analysis process, the sub-CPU 120a takes the control command from the reception buffer into the reception data storage area of the sub RAM 120c and stores it. To do. Then, the sub CPU 120a analyzes the type of the control command stored in the received data storage area, and performs processing according to the type of the control command. Details of the command analysis process will be described later.

In step S <b> 1700, the sub CPU 120 a checks the signal of the effect button detection switch 35 a, and performs effect input control processing related to input from the effect button 35.
In step S1800, the sub CPU 120a performs an effect output control process that is a process for transmitting the control command and various data set in the transmission data storage area of the sub RAM 120c to the lamp control unit 140 and the image control unit 150. Do.
In step S1900, the sub CPU 120a restores the information saved in step S1200 to the register of the sub CPU 120a.

Next, command analysis processing of the effect control unit 120 will be described.
19 and 20 are flowcharts showing command analysis processing by the effect control unit 120 according to the present embodiment. The command analysis process 2 in FIG. 20 is performed subsequent to the command analysis process 1 in FIG.

In step S1501, the sub CPU 120a checks whether a control command is stored in the reception buffer of the receiving unit 600, and determines whether the control command has been received.
If the control command is stored in the reception buffer, the sub CPU 120a moves the process to step S1650, and if the control command is not stored in the reception buffer, the sub CPU 120a ends the command analysis process.

  In step S1650, the sub CPU 120a performs an authentication result data analysis process on the authentication result data added to the control command stored in the reception buffer. Then, when the sub controller 120a can confirm that the validity of the control command has been authenticated by the intermediate control unit 180, the sub CPU 120a takes the received control command into the received data storage area and moves the process to step S1510. The details of the authentication result data analysis process will be described later.

In step S1510, the sub CPU 120a checks whether or not the control command stored in the received data storage area is a demo designation command.
If the control command stored in the received data storage area is a demo designation command, the sub CPU 120a moves the process to step S1511, and if not, moves the process to step S1520.

In step S1511, the sub CPU 120a performs a demonstration effect pattern determination process for determining a demonstration effect pattern.
Specifically, the demonstration effect pattern is determined, the determined demonstration effect pattern is set in the effect pattern storage area, and information on the determined demonstration effect pattern is transmitted to the image control unit 150 and the lamp control unit 140. An effect pattern designation command based on the demo effect pattern is set in the transmission data storage area of the sub-RAM 120c.

In step S1520, sub CPU 120a checks whether or not the control command stored in the reception data storage area is a special symbol storage designation command.
If the control command stored in the received data storage area is the special symbol storage designation command, the sub CPU 120a moves the process to step S1521, and moves to step S1530 if it is not the special symbol storage designation command.

  In step S1521, the sub CPU 120a analyzes the special symbol storage designation command to determine the number of display images of special symbols to be displayed on the liquid crystal display device 31 (hereinafter referred to as “special diagram reserved images”). The special symbol display number designation command corresponding to the display number of the special figure reserved images is transmitted to the image control unit 150 and the lamp control unit 140, and a special symbol storage number determination process is performed.

In step S1530, the sub CPU 120a checks whether or not the control command stored in the received data storage area is an effect designating command.
If the control command stored in the storage area for received data is an effect designating command, the sub CPU 120a moves the process to step S1531, and moves to step S1540 if it is not an effect designating command.

In step S1531, the sub CPU 120a performs an effect symbol determination process for determining an effect symbol 36 to be stopped and displayed on the liquid crystal display device 31 based on the content of the received effect symbol designation command.
Specifically, the effect designating command is analyzed, the effect symbol data constituting the combination of the effect symbols 36 is determined according to the presence / absence of jackpot and the type of jackpot, and the determined effect symbol data is stored in the effect symbol storage area In addition, in order to transmit the effect symbol data to the image control unit 150 and the lamp control unit 140, a stop symbol designation command indicating the effect symbol data is set in the transmission data storage area of the sub RAM 120c.

  In step S1532, the sub CPU 120a acquires one random value from the effect mode determination random value updated in step S1100, and based on the acquired effect mode determination random value and the received effect designating command, An effect mode determination process for determining one effect mode from a plurality of effect modes (for example, a normal effect mode and a chance effect mode) is performed. Further, the determined effect mode is set in the effect mode storage area.

In step S1540, the sub CPU 120a checks whether or not the control command stored in the received data storage area is a variation pattern designation command.
If the control command stored in the storage area for received data is a variation pattern designation command, the sub CPU 120a proceeds to step S1541 and proceeds to step S1550 if it is not a variation pattern designation command.

In step S1541, the sub CPU 120a acquires one random number value from the effect random number value updated in step S1100, and is set in the acquired effect random number value, the received variation pattern designation command, and effect mode storage area. Based on the effect mode being performed, a variation effect pattern determination process is performed in which one variation effect pattern is determined from a plurality of variation effect patterns.
Specifically, in the normal effect mode, the variation effect pattern determination table is referred to, one change effect pattern is determined based on the acquired effect random number value, and the determined change effect pattern is stored in the effect pattern storage area. At the same time, in order to transmit the determined variation effect pattern information to the image control unit 150 and the lamp control unit 140, an effect pattern designation command based on the determined variation effect pattern is set in the transmission data storage area of the sub RAM 120c.
Thereafter, based on the effect pattern, the liquid crystal display device 31, the audio output device 32, the effect drive device 33, and the effect illumination device 34 are controlled. Note that the variation mode of the effect symbol 36 is determined based on the variation effect pattern determined here.

In step S1550, the sub CPU 120a checks whether or not the control command stored in the received data storage area is a symbol determination command.
If the control command stored in the received data storage area is the symbol confirmation command, the sub CPU 120a moves the process to step S1551, and moves to step S1560 if it is not the symbol confirmation command.

  In step S1551, the sub CPU 120a performs an effect symbol stop display process for setting a stop designation command for stopping the effect symbol in the transmission data storage area of the sub RAM 120c in order to stop the effect symbol 36.

In step S1560, the sub CPU 120a determines whether or not the control command stored in the received data storage area is a gaming state designation command.
If the control command stored in the received data storage area is a gaming state designation command, the sub CPU 120a moves the process to step S1561, and moves to step S1570 if it is not a gaming state designation command.

  In step S1561, the sub CPU 120a sets data indicating the gaming state based on the received gaming state designation command in the gaming state storage area in the sub RAM 120c.

In step S1570, the sub CPU 120a checks whether or not the control command stored in the received data storage area is an opening designation command.
If the control command stored in the received data storage area is an opening designation command, the sub CPU 120a moves the process to step S1571, and if not the opening command, moves the process to step S1580.

In step S1571, the sub CPU 120a performs a hit start effect pattern determination process for determining a hit start effect pattern.
Specifically, the hit start effect pattern is determined based on the opening designation command, the determined hit start effect pattern is set in the effect pattern storage area, and information on the determined hit start effect pattern is transmitted to the image controller 150 and the lamp. In order to transmit to the control unit 140, an effect pattern designation command based on the determined hit start effect pattern is set in the transmission data storage area of the sub RAM 120c.

In step S1580, the sub CPU 120a confirms whether or not the control command stored in the received data storage area is a special winning opening opening designation command.
If the control command stored in the received data storage area is a big prize opening release designation command, the sub CPU 120a moves the process to step S1581, and if it is not a big prize opening opening designation command, the sub CPU 120a moves the process to step S1590.

In step S1581, the sub CPU 120a performs a jackpot effect pattern determination process for determining a jackpot effect pattern.
Specifically, the jackpot effect pattern is determined based on the big prize opening opening designation command, the determined jackpot effect pattern is set in the effect pattern storage area, and information on the determined jackpot effect pattern is transmitted to the image controller 150 and the lamp. In order to transmit to the control unit 140, an effect pattern designation command based on the determined jackpot effect pattern is set in the transmission data storage area of the sub RAM 120c.

In step S1590, the sub CPU 120a checks whether or not the control command stored in the received data storage area is an ending designation command.
If the control command stored in the received data storage area is an ending designation command, the sub CPU 120a moves the process to step S1591, and ends the command analysis process if it is not an ending designation command.

In step S1591, the sub CPU 120a performs a hit end effect pattern determination process for determining a hit end effect pattern.
Specifically, the winning end effect pattern is determined based on the ending designation command, the determined hit end effect pattern is set in the effect pattern storage area, and information on the determined hit end effect pattern is stored in the image control unit 150 and the lamp. In order to transmit to the control unit 140, an effect pattern designation command based on the determined winning end effect pattern is set in the transmission data storage area of the sub RAM 120c. When this process ends, the command analysis process ends.

Next, the authentication result data analysis process of the production control unit 120 will be described.
FIG. 21 is a flowchart showing an authentication result data analysis process performed by the effect control unit 120 according to the present embodiment.

In step S1651, the sub CPU 120a determines whether or not authentication result data is added to the control command stored in the reception buffer of the reception unit constituting the effect control unit 120. If the authentication result data is added, the sub CPU 120a moves the process to step S1652. If the authentication result data is not added to the control command, the sub CPU 120a ends the authentication result data analysis process.
In step S1652, the sub CPU 120a extracts authentication result data from the control command stored in the reception buffer, and the process proceeds to step S1653.

In step S1653, the sub CPU 120a determines whether or not the extracted authentication result data indicates that the inspection result of the error inspection process performed by the intermediate control unit 180 is normal and the validity of the main control unit 110 can be authenticated. Determine. Then, the sub CPU 120a determines that the gaming machine 1 is operating normally when the authentication result data is a result indicating a successful authentication. Then, the sub CPU 120a outputs the received control command to the received data storage area of the sub RAM 120c, and ends the authentication result data analysis process so as to perform processing according to the control command. On the other hand, if the authentication result data is a result indicating that the authentication is unsuccessful, the sub CPU 120a determines that there is a possibility that an illegal act or the like has occurred in the gaming machine 1, and moves the process to step S1654.
In step S1654, when the sub CPU 120a determines that there is a possibility that an illegal act or the like has occurred in the gaming machine 1, the sub CPU 120a outputs a notification signal to notify that fact, and ends the authentication result data analysis processing.

  The sub CPU 120a transmits the generated notification signal to, for example, the lamp control unit 140, the image control unit 150, or a hall computer that manages the gaming machine 1. Based on the received notification signal, the lamp control unit 140, the image control unit 150, and the like perform an effect that notifies that there is a possibility that an illegal act has occurred in the gaming machine 1. This effect is, for example, causing a character that does not normally appear on the liquid crystal display device 31 to appear, or causing a character that normally appears to appear by a method different from normal. In addition, the brightness of the liquid crystal display device 31 may be changed, the color may be changed, or the lamp controller 140 may be controlled to display a predetermined lamp. In any case, when the employee of the game shop passes in front of the gaming machine 1, it is only necessary to notice the state. This effect may be an effect that the customer does not notice the state or an effect that the customer can easily notice. If the production is easily noticed by the customer, fraud can be efficiently suppressed.

  Moreover, you may include the information regarding the gaming state or jackpot type of the gaming machine 1 in the notification signal. Based on these pieces of information, it may be determined whether a fraudulent act is being performed by a hall computer or the like that manages the gaming machine 1. For example, the “high probability gaming state” may be normal even if prize balls are concentrated. Therefore, during the high-probability gaming state, it is preferable to determine whether or not there is a risk of cheating under different conditions from the other states. Moreover, you may make it output the information regarding a gaming state or jackpot type as a separate signal without including it in a notification signal. In this case, the employee determines whether or not there is a risk of fraud based on both the notification signal and the information regarding the gaming state and the jackpot type.

  The authentication process when the intermediate control unit 180 is provided between the main control unit 110 and the other control units of the peripheral control unit 300 is an intermediate control between the main control unit 110 and the effect control unit 120. Since the procedure is almost the same as the authentication process when the unit 180 is provided, the description is omitted.

  As described above, in the present embodiment, as a security function, the validity of the control command output from the main control unit 110 is inspected to authenticate the validity of the main control unit 110. The main control unit 110 generates an error check value using a control command generated before (past) the control command transmitted this time. Then, the main control unit 110 adds the error check value to the control command to be transmitted this time and transmits it to the intermediate control unit 180. On the other hand, the intermediate control unit 180 generates an error check value using the control command generated and received by the main control unit 110 before (in the past) the control command received this time. Then, the intermediate control unit 180 performs error checking by comparing the error check value added to the control command received this time with the generated error check value.

  Normally, an error check value such as a checksum is added to the control command of the generation source and used for a communication error check. In contrast, in the present embodiment, as described above, the error check value of the control command generated in the past is added to the control command to be transmitted this time. By using such a new and simple method that has not been used in the past, even if an unauthorized person steals a control command and an error check value, the correspondence between the control command and the error check value cannot be easily known. Can do. Therefore, according to this embodiment, fraud can be prevented and the security strength of the gaming machine 1 can be improved.

  Also, the error check value of the control command generated in the past by the main control unit 110 is added to the control command to be transmitted this time and transmitted, and the intermediate control unit 180 has received this time by performing the error check process of the control command. In addition to authenticating the validity of the control command, it is also possible to authenticate the validity of the control command generated in the past, that is, the control command from which the error check value added this time is generated. That is, it is possible to authenticate the continuity of the control command, and it becomes easier to detect fraud, and the security strength of the gaming machine 1 can be improved.

  In the present embodiment, the error check value is set to a value unique to the gaming machine 1 by adding unique information unique to the gaming machine 1 to the control command transmitted when P ≦ N. Can do. As a result, even if an unauthorized person who does not know the specific information steals a part of the control command, the error check value cannot be analyzed, and the security strength of the gaming machine 1 can be further improved.

  In this embodiment, an error check value that is normally used for communication error check is used as a check value for detecting fraud. In this way, by using an error check value conventionally used for communication error check, it is possible to detect fraud without separately providing test value generation means for detecting fraud. Can be improved. That is, in a situation where the resources of the main control unit of the gaming machine are limited, an increase in processing load on the main control unit 110 can be suppressed while improving the security strength.

  In the present embodiment, the test value generation unit 500 added as a specific aspect of the security function added to the main control unit 110 is configured with a wired logic control type hardware, and includes the main CPU 110a, the transmission unit 550, and the like. It is provided between. At this time, the input / output control method between the inspection value generation unit 500 and the main CPU 110a and the input / output control method between the inspection value generation unit 500 and the transmission unit 550 are each a CPU interface method. The input / output control method between each means and each circuit in the test value generation unit 500 is a synchronous interface method. Therefore, in the present embodiment, the test value generation unit 500 that does not increase the processing load and code size of the main CPU 110a is added while maintaining the input / output control method between the main CPU and the transmission unit of the existing gaming machine. be able to. Therefore, according to the present embodiment, while the gaming machine 1 has the security function, the processing load and code size of the CPU of the main control unit 110, which increase by having the security function, can be suppressed to the maximum. At the same time, according to the present embodiment, a security function having such a feature can be added to an existing gaming machine relatively easily.

  In the present embodiment, the check value generation unit 500 further performs bit string conversion processing on the error check value of the control command generated in the past. In addition, the test value generation unit 500 includes a plurality of conversion methods used for the bit string conversion processing, and changes appropriately based on the control command to be transmitted. Therefore, even if an unauthorized person steals a plurality of control commands and error check values, it becomes more difficult to analyze the correspondence between the control commands and error check values. Therefore, the confidentiality of the error check value adding function of the gaming machine 1 can be further improved, and the security strength of the gaming machine 1 can be further improved.

  Further, in the present embodiment, the timing for actually changing the conversion method is the output timing of the control command output after Mo commands from the output timing of the control command to be determined whether or not to change the conversion method. . That is, in this embodiment, the timing at which the conversion method change condition is satisfied and the actual change timing are distributed. Therefore, even if an unauthorized person steals a plurality of control commands and error check values, it becomes more difficult to analyze the correspondence between the control commands and error check values. Therefore, the confidentiality of the error check value adding function of the gaming machine 1 can be further improved, and the security strength of the gaming machine 1 can be further improved.

  Further, in the present embodiment, the check value generation unit 500 includes a plurality of change conditions that are conditions for appropriately changing the conversion method used in the bit string conversion processing, thereby preparing a plurality of error check value addition functions in advance. Yes. Based on what change condition the conversion method is changed, the HW parameter stored in a specific storage area of the main ROM 110b that is not accessed except when the initial value is set during the boot process of the main control unit 110 Is determined based on the value of. Therefore, even if an unauthorized person steals multiple control commands and error check values, it becomes difficult to analyze under what change conditions the conversion method is changed. It becomes more difficult to analyze. Therefore, the confidentiality of the error check value adding function of the gaming machine 1 can be further improved, and the security strength of the gaming machine 1 can be further improved.

  In this embodiment, a plurality of types of error check value addition functions and HW parameters as selection information thereof are prepared in advance, but only specific HW parameters are implemented. Therefore, it is not necessary to newly provide a program associated with the HW parameter selection process in the boot process, and the code size of the program is not increased. Even if a gaming machine manufacturer wants to adopt only a specific error check value addition function, only the HW parameter corresponding to the desired error check value addition function needs to be implemented. Can respond flexibly. Therefore, even diverse security functions can be added relatively easily, and a highly versatile security function can be provided. In addition, by changing the HW parameters used for design / verification work during the development stage of the gaming machine 1 and the HW parameters that are actually mounted before the gaming machine 1 is shipped, which HW parameters are finally adopted. It is possible to limit the persons who can know whether or not it has been made, and it is possible to further improve the confidentiality of the error check value addition function of the gaming machine 1.

  In the present embodiment, as a plurality of conversion methods used for the bit string conversion process, a conversion method A in which the shift amount regularly varies and a conversion method B in which the shift amount varies randomly are provided. In the conversion method B, since the shift amount varies randomly, each bit of the error check value that has been subjected to the bit string conversion processing using the conversion method B is irregularly shifted every bit string conversion processing. Therefore, even if an unauthorized person steals a plurality of control commands and error check values, it is difficult to analyze the shift amount by which the bit string is converted. It becomes more difficult to analyze. Therefore, the confidentiality of the error check value adding function of the gaming machine 1 can be further improved, and the security strength of the gaming machine 1 can be further improved.

  In particular, in the conversion method B in which the shift amount is randomly changed, even if the bit string of the original error check value is different, a duplicate value may be output for each bit string conversion process. Even if multiple values are stolen, it is difficult to analyze whether there is regularity regarding the shift amount variation and whether the conversion method has been changed, and it is even more difficult to analyze the correspondence between control commands and error check values. . Therefore, the confidentiality of the error check value adding function of the gaming machine 1 can be further improved, and the security strength of the gaming machine 1 can be further improved.

  In this embodiment, only the conversion method B is the conversion method in which the shift amount varies randomly. The error check value obtained by converting the bit string by the conversion method B is added to the control command and transmitted to the intermediate control unit 180 during a predetermined operation mode, that is, when a predetermined control command group is The period is limited to the period transmitted to the intermediate control unit 180. Therefore, when returning to the original error check value bit string in the error check process on the intermediate control unit 180 side, the tendency that the number of trials of the bit string conversion process increases by changing the shift amount at random is maximized. Can be suppressed. In other words, in this embodiment, it is difficult to analyze the correspondence between the control command and the error check value by randomly changing the shift amount, and while increasing the security strength, the processing load that is increased by adding the security function is maximized. Can be limited. Moreover, the increase in processing load is borne not by the main control unit 110 having limited resources but by the intermediate control unit 180 having a relatively large amount of resources, and a large fraud prevention effect can be obtained with a small load.

  In this embodiment, as a specific embodiment of the conversion method, the test value generation unit 500 includes the bit string conversion circuit 525, and the bit string conversion circuit 525 is configured with a shift register having a relatively simple circuit configuration. For this reason, in this embodiment, after designing the circuit of the rotation computing unit A, the circuit data can be diverted to the rotation computing unit B, and the development man-hours and development related to the circuit design and its verification work The difficulty level can be suppressed. That is, in this embodiment, the effect that the correspondence relationship between the control command and the error check value becomes difficult to analyze and the security strength is improved by providing a plurality of conversion methods is smaller than the number of conversion methods provided. It can be obtained simply by designing the computing unit, and a large fraud prevention effect can be obtained with a small development cost.

  In the present embodiment, the error check value of the control command generated in the past is not subjected to the encryption process using the encryption key, but the bit string conversion process is performed. A bit rotation operation is performed using a rotation operation unit. In the method of performing the encryption process using the encryption key, it is necessary to store the encryption key information, which is fixed data, in the main control unit 110, and there is a possibility that it is easily analyzed illegally by a static analysis method. . In addition, in order to configure the encryption key information so that it can be analyzed only by a dynamic analysis method, it is necessary to newly provide complicated processing such as encryption key exchange, sharing, and synchronization. On the other hand, in the present embodiment, the bit string conversion circuit 525 that performs the bit string conversion processing calculates the shift amount A using the error check value output from the internal rotation calculator B and the parity check provided in the existing gaming machine. Update the function. In addition, the bit string conversion circuit 525 updates the shift amount B by using a random value used in an existing game machine. In other words, in this embodiment, the shift amounts A and B, which are the key in the bit string conversion process, are changed by a simple method of using and updating the configuration provided in the existing game machine, thereby providing dynamic configuration security. The function is realized. In addition, the rotation arithmetic units A and B are composed of shift registers having a relatively simple circuit configuration, and are overwhelmingly wired resources compared to an arithmetic circuit that performs encryption processing using encryption key information. Less is. For this reason, in the present embodiment, in circuit design and verification work, it is possible to suppress adverse effects on the determination of the operating frequency, die size, and the like by circuit arrangement adjustment and delay time adjustment by wiring resources.

  In this embodiment, the shift amount is changed not only when the bit string conversion process is performed by the conversion method B but also when the bit string conversion process is performed by the conversion method A. Therefore, in this embodiment, the bit string is converted by the conversion method A even when the error check value obtained by converting the bit string by the conversion method B is not included in the period when the error check value is added to the control command. Each bit of the converted error check value varies for each bit string conversion process. For this reason, in this embodiment, an unauthorized person transmits a bit string converted by the error check value added to the control command in a period other than the predetermined operation mode period. This also makes it difficult to perform the error check value, and can further improve the security strength.

  In the present embodiment, a plurality of error check value addition functions are provided in advance by providing a plurality of update timing conditions related to the shift amount A defined in order to regularly vary the shift amount A used in the conversion method A. I have prepared it. The update timing condition based on which update amount A is updated is stored in a specific storage area of the main ROM 110b that is not accessed except when an initial value is set during the boot process of the main control unit 110. It is determined based on the value of the HW parameter. Therefore, even if an unauthorized person steals a plurality of control commands and error check values, it becomes difficult to analyze the regularity regarding the update of the shift amount A, and it is further possible to analyze the correspondence between the control commands and error check values. It becomes difficult. Therefore, the confidentiality of the error check value adding function of the gaming machine 1 can be further improved, and the security strength of the gaming machine 1 can be further improved.

  In the present embodiment, the authentication function for the main control unit 110 is provided in the intermediate control unit 180 that is independent of the peripheral control unit 300 that performs processing related to normal game progression. Therefore, for example, when the intermediate control unit 180 is provided between the main control unit 110 and the effect control unit 120, the authentication process is executed by the effect control unit 120 from the authentication result data from the intermediate control unit 180. Is only received. That is, the processing load of the CPU of the effect control unit 120 increases only when the authentication result data is received by performing the authentication process, and thus the rate of increase in the processing load of the effect control unit 120 can be suppressed. it can. Further, it is only necessary to add a program code related to the authentication result data analysis process to the program executed by the effect control unit 120. Therefore, since it is not necessary to perform new timing design over the entire program executed by the effect control unit 120, the mounting and verification work when adding the authentication function can be performed more easily and with less work man-hours.

  In the present embodiment, since the intermediate control unit 180 is provided between the main control unit 110 and the effect control unit 120, the main CPU 110 a configuring the main control unit 110 and the sub CPU 120 a configuring the effect control unit 120. In the intermediate control unit 180, the difference in processing capacity between the main ROM 110b and the main RAM 110c constituting the main control unit 110 and the storage capacity difference between the sub ROM 120b and the sub RAM 120c constituting the effect control unit 120 Can be absorbed. Thereby, even when there is a difference in processing capacity and storage capacity between the main control unit 110 and the effect control unit 120, the security strength between the main control unit 110 and the effect control unit 120 can be maintained. This also applies to the case where the intermediate control unit 180 is provided between the main control unit 110 and another control unit of the peripheral control unit 300.

  In this embodiment, the data buffer 511 of the buffer means 510 and the storage circuit 522 of the generation means 520 are connected, the data buffer 511 is disposed on the input side of the storage circuit 522, and the generation circuit is provided on the output side of the storage circuit 522. The circuit configuration is such that 521 is arranged. In other words, in the present embodiment, the object to be stored in the storage circuit 522 is the control command output from the buffer unit 510. However, the present invention is not limited to this, and the storage circuit 522 may be provided on the output side of the generation circuit 521 so that an object to be stored in the storage circuit 522 may be an error check value. In the intermediate control unit 180 as well, the object stored in the storage unit 622 may be an error check value or a control command. Further, the storage target in the main control unit 110 and the storage target in the intermediate control unit 180 may be different.

  In the present embodiment, the HW parameter is defined as selection information for determining the default change condition and the update timing condition related to the shift amount A, but the present invention is not limited to this. For example, the HW parameter can be used as selection information for determining an update timing condition related to the default conversion method and the shift amount A. At this time, in the determination circuit 542, HW parameters corresponding to a plurality of conversion methods are prepared in advance, and default change conditions are prepared. Then, during the boot process, the determination circuit 542 stores conversion method information indicating a conversion method corresponding to the HW parameter set in the HW parameter setting process in the conversion method information storage area (S), and controls the conversion method. A signal may be output and setting to the generation unit 520 may be performed.

  The HW parameter can also be defined as selection information for determining the change method used by the determination unit 540 and the change timing setting method. For example, when the change method is determined by the HW parameter, the determination circuit 542 prepares a plurality of change methods for defining a change order of predetermined conversion methods and associates them with the HW parameter. Then, in the HW parameter setting process during the boot process, the determination circuit 542 sets a specific change method corresponding to the HW parameter set from the main CPU 110a, and changes the conversion method according to the set change method. Good.

  The HW parameter can also be defined as selection information for determining an update method related to the shift amount B used by the generation unit 520. For example, when the update timing condition related to the shift amount B is determined by the HW parameter, the shift amount control unit C responsible for the bit string conversion circuit 525 is connected so as to be able to acquire a random value from a plurality of random number generation circuits provided in an existing gaming machine In addition, each random number generation circuit is associated with the HW parameter. Then, in the HW parameter setting process during the boot process, the shift amount control unit C effectively operates only the connection with the specific random number generation circuit corresponding to the HW parameter set by the main CPU 110a, and the specific random number generation circuit The shift amount B may be updated using the random value acquired from the above.

  In other words, in the present invention, the HW parameter is not limited to the selection condition for determining the update condition used in the determination unit 540 or the update timing condition related to the shift amount A used in the generation unit 520. It can be defined as selection information for determining a rule for updating the shift amount. That is, the HW parameter is selection information for the error check value addition function in which the change protocol related to the conversion method and the rule related to the shift amount update are implemented.

  As described above, in the present invention, the error check value addition function is based on the value of the HW parameter stored in the specific storage area of the main ROM 110b that is not accessed except when the initial value is set during the boot process of the main control unit 110. Determined. Therefore, even if an unauthorized person steals a plurality of control commands and error check values, it becomes difficult to analyze what error check value addition function is installed in the gaming machine 1, and the error check value addition function Can be further improved, and the security strength of the gaming machine 1 can be further improved.

  In the present embodiment, the comparator 541b responsible for the determination circuit 541 indicates that when the control command output from the buffer unit 510 satisfies the change condition, the control command is a control command that satisfies the change condition. The determination result signal may not be output every time. That is, even if the control command output from the buffer means 510 is a control command that satisfies the change condition, the comparator 541b does not change the conversion method in the decision circuit 542, and an unauthorized person sets the conversion method change condition. It becomes more difficult to analyze.

  Further, the comparator 541b may not output the determination result signal itself every time a control command is input. In this case, the control circuit 512 of the buffer means 510 and the determination circuit 542 are directly connected by a control line, and an operation permission signal is output from the control circuit 512 to the determination circuit 542. The determination circuit 542 may update the value of the generated number storage area (P) based on the input of the operation permission signal and perform the conversion method setting process. Further, the control circuit 512 of the buffer unit 510 is not connected to the determination circuit 541 and the determination circuit 542 of the determination unit 540, but is connected to the control circuit 523 of the generation unit 520 and the determination circuit is connected from the control circuit 523 to the determination circuit. The operation permission signal may be output to 541 or the determination circuit 542.

  In the present embodiment, the unique information is set in the generation unit 520 as an initial setting value when P = 1. When P ≦ N, the main control unit 110 adds an initial check value to the control command (P) and transmits it, and the intermediate control unit 180 uses the corresponding initial check value to perform error check processing. However, the present invention is not limited to this, and the intermediate control unit 180 does not perform error check processing when P ≦ N, and performs error check processing only after P> N. Also good.

  In the present embodiment, the intermediate control unit 180 is the determination unit 623 having the same function as the function of changing the conversion method of the main control unit 110, but the present invention is not limited to this. For example, the intermediate control unit 180 collates the error check value added to the received control command with the error check value obtained by converting the bit string in all the conversion methods of the bit string conversion unit 624, and performs error check processing. It may be done. In this case, the intermediate control unit 180 may authenticate the validity of the received control command and the validity of the main control unit 110, assuming that the inspection result is normal if it matches any error check value.

  In this embodiment, when P = 1, the unique information is set as the initial setting value in the storage circuit 522. However, the present invention is not limited to this. For example, the main control unit 110 is provided with time measuring means, or using the time measuring means provided in the main control unit 110 in advance, the elapsed time from the power-on to the transmission timing of the control command is acquired as time-lapse information and acquired. Time information may be used as an initial inspection value. Since the value of the acquired time-lapse information is a fluctuation value having randomness, it is difficult to reuse the initial inspection value generated by using this, and the security strength of the gaming machine 1 is further improved. Can do. At this time, the intermediate control unit 180 may not perform the error check process when P ≦ N as described above.

  At this time, if N ≧ 2 is determined in advance, the intermediate control unit 180 determines whether or not the temporal information added to the control command has continuity in time series between the temporal information transmitted continuously. In other words, the error checking process may be performed by confirming whether or not the value of the time information transmitted continuously increases in accordance with the transmission order. The time information may be an absolute time acquired by using a time measuring means as a real time clock circuit or the like, or may be a relative time counted from the reset time. In any case, the time-lapse information changes to various values as the timing of acquisition is irregular, so that it can be regarded as information inherent to the gaming machine 1 substantially. Further, when N ≧ 2, the time information may be obtained from the time measuring means for each control command transmission timing, or a plurality of time information acquired at the transmission timing of the first generated control command may be used. It may be used for control commands. Also, for example, the initial setting value that is the source of the error check value added to the first generated control command uses the identification number (ID) of the main CPU 110a, which is a fixed value, and is added to subsequent control commands. The initial setting value from which the error check value is generated can be a combination of a fixed value and a variation value, such as using time-lapse information that is a variation value.

  Further, as an initial setting value set in the storage circuit 522, for example, an HW parameter that is selection information of an error check value addition function of the main control unit 110 may be used. That is, the determination unit 540 constituting the inspection value generation unit 500 of the main control unit 110 stores the HW parameter set in its determination circuit 542 during the boot process even after the HW parameter setting process. Then, the determination circuit 542 determines whether it is necessary to set unique information in the storage circuit 522. At this time, the control circuit 512 of the buffer means 510 and the determination circuit 542 are connected by a control line, and an operation permission signal is output from the control circuit 512. The decision circuit 542 updates the value of the generated number storage area (P) based on the input of the operation permission signal. If the value of the generated number storage area (P) is P = 1, it is output from the buffer means 510. The control command is determined to be a control command first generated by the main CPU 110a after the control command stored in the storage circuit 522 is cleared. In this case, the determination circuit 542 may notify the buffer unit 510 to request that the specific information be output, set the HW parameter stored in the storage circuit 522, and use it as an initial setting value. .

  The content and mounting method of the HW parameter can be determined by the game machine manufacturer's own judgment, so that the HW parameter is highly confidential and can be regarded as information inherent to the gaming machine 1 substantially. The intermediate control unit 180 may not perform the error check process when P ≦ N as described above. By doing so, the intermediate control unit 180 is set by the main control unit 110 even if the selection information of the error check value addition function corresponding to the HW parameter has not been negotiated with the main control unit 110 in advance. An error check value output function corresponding to the error check value addition function can be selected. Therefore, even if an unauthorized person analyzes the intermediate control unit 180 itself, it is specified whether the error check process is performed using the error check value output by any of the plurality of error check value output functions. Therefore, the confidentiality of the output function can be ensured, and the security strength of the gaming machine 1 can be further improved.

  Further, in the present embodiment, the input / output control method between each means or each circuit in the test value generation unit 500 is a synchronous interface method. Then, data transmission / reception between each means and each circuit in the inspection value generation unit 500 is performed in synchronization with the clock signal output from the clock pulse generation circuit of the main control unit 110. However, the present invention is not limited to this, and data transmission / reception between each means and each circuit in the test value generation unit 500 may be performed asynchronously with respect to the clock signal. Even in this case, in the test value generation unit 500, if an enable signal or the like is output to the connection destination of the data to be output, the connection destination captures the output data based on the input of the enable signal or the like. This is different from the CPU interface method.

  In this embodiment, the timing for writing the error check value to the transmission buffer 551 of the transmission unit 550 is controlled by adjusting the output timing of the input selection signal output by the control circuit 532 of the adding unit 530. However, the present invention is not limited to this, and the control circuit 512 of the buffer means 510 can be controlled by adjusting the output timing of the operation permission signal output to the control circuit 532. In addition, the control circuit 523 of the generation unit 520 can also perform control by adjusting the output timing of the shift processing signal output to the storage circuit 522 and the output timing of the operation permission signal output to the generation circuit 521. This is because the output timing of the input selection signal output from the control circuit 532 is based on the input of the operation permission signal output from the control circuit 512. This is because the timing at which the error check value is input to the input selection circuit 531 to which the input selection signal is input is based on the input of the shift processing signal and the operation permission signal output from the control circuit 523.

  Note that the output timing of the shift processing signal and the operation permission signal output from the control circuit 523 is also based on the input of the operation permission signal output from the control circuit 512, and further, the operation permission signal output from the control circuit 512. Is based on the input of a write signal to the buffer means 510 output from the main CPU 110a. The write signal output from the main CPU 110a is specified in advance by the execution timing of the command transmission process originally defined in the existing game processing program.

  As described above, in the present invention, the timing at which the test value generation unit 500 writes the error test value to the transmission unit 550 is uniquely determined based on the execution timing of the command transmission process defined by the existing game processing program. Well, timing design is relatively easy. Therefore, according to the present invention, a security function can be added to an existing gaming machine relatively easily, and a relatively large margin can be ensured in designing an error check value write timing. It is easy to ensure accuracy.

  In the present embodiment, the intermediate control unit 180 adds the authentication result data to the control command and transmits it to the effect control unit 120 as a control command with authentication result data. However, the present invention is not limited to this. The control command and the authentication result data may be transmitted separately. In this case, the effect control unit 120 may determine whether or not the authentication result data has been received, and perform authentication result data analysis processing when the authentication result data is received. Note that dummy data may be added to each of the control command and the authentication result data so that the data length is the same. By doing so, it becomes difficult for an unauthorized person to distinguish between the control command and the authentication result data, and the security strength of the gaming machine 1 can be improved.

  In the present embodiment, the intermediate control unit 180 generates authentication result data and transmits it to the effect control unit 120 regardless of whether authentication is successful or unsuccessful. However, the present invention is not limited to this. For example, the intermediate control unit 180 may generate authentication result data only when authentication is unsuccessful, or output a signal indicating unsuccessful authentication and transmit it to the effect control unit 120. The effect control unit 120 may determine whether or not a signal indicating authentication result data or authentication failure has been received and output a notification signal when received.

  In the present embodiment, in the shift amount control unit C responsible for the bit string conversion circuit 525 of the generation unit 520 that constitutes the test value generation unit 500, the shift amount control unit C internally includes control related to update of the shift amount. However, in the present invention, the test value generation unit 500 may be entirely configured by hardware.

  In this embodiment, the inspection value generation unit 500 has a circuit configuration separate from the one-chip microcomputer 110m. However, the present invention is not limited to this, and the inspection value generation unit 500 is a circuit integrated with the one-chip microcomputer 110m. It is good also as a structure, and it is good also as a circuit structure integrated with the transmission part 550. Furthermore, in the present invention, all of the inspection value generation unit 500, the one-chip microcomputer 110m, and the transmission unit 550 may be integrated into a circuit configuration.

In the present embodiment, the intermediate control unit 180 includes a CPU, a ROM, a RAM, and the like. However, the same function may be realized as an integrated circuit such as an LSI.
Moreover, in this embodiment, although the example which applies this invention to a pachinko game machine was shown, it is not limited to this, This invention is a ball game machine other than pachinko game machines, such as a sparrow ball game machine and an arrangement ball. It can also be applied to other gaming machines such as slot machines such as slot machines. Even in these gaming machines, the same effects as in the present embodiment can be obtained by configuring in the same manner as in the present embodiment.

  In the present embodiment, an example in which the present invention is applied to a gaming machine has been described. However, the present invention is not limited thereto, and the present invention includes a plurality of control units such as a gaming machine, and data transmission between these control units. The present invention can also be applied to an electronic device that executes authentication processing and an authentication method thereof. Also in these electronic devices and their authentication methods, the same effects as in the present embodiment can be obtained by configuring in the same manner as in the present embodiment. Moreover, this embodiment can divert each other's technology as long as there is no particular contradiction or problem in its purpose and configuration.

1 gaming machine 110 main control unit 110a main CPU
110b Main ROM
110c Main RAM
110d Boot ROM
120 Production control unit 120a Sub CPU
120b Sub ROM
120c sub RAM
180 Intermediate control unit 180a CPU
180b ROM
180c RAM
300 Peripheral Control Unit 500 Inspection Value Generation Unit 510 Buffer Unit 520 Generation Unit 521 Generation Circuit 525 Bit String Conversion Circuit 530 Addition Unit 540 Determination Unit 550 Transmission Unit 600 Reception Unit 610 Inspection Unit 620 Inspection Value Generation Unit 621 Generation Unit 622 Storage Unit 623 Determination Unit 624 bit string conversion unit 630 addition unit 640 relay transmission unit

Claims (10)

A gaming machine including a main control unit that outputs a control command, a peripheral control unit that performs processing based on the control command, and an intermediate control unit provided between the main control unit and the peripheral control unit. And
The main control unit
An arithmetic processing unit that performs processing according to predetermined game information stored in the storage unit to generate the control command, and outputs the generated control command in a predetermined output control method;
Provided so as to follow to the arithmetic processing unit to generate the error check value for checking the validity of the appended the control command to the control command outputted by the processing unit, the generated error check value Is added to the control command, and is output,
A transmitter that is provided subsequent to the first check value generation unit, and that transmits a control command to which the error check value is added to the intermediate control unit;
With
The intermediate control unit
A second check value generator for generating an error check value for verification corresponding to the error check value generated by the first check value generator;
The error check value transmitted by the transmitter is compared with the error check value generated by the second check value generator, and the validity of the control command transmitted by the transmitter is checked. An inspection unit for outputting result information;
A relay transmission unit that transmits the control command transmitted by the transmission unit to the peripheral control unit and transmits the result information to the peripheral control unit;
With
The peripheral control unit
A processing unit that performs processing based on the control command relayed by the relay transmission unit and performs processing according to the result information transmitted by the relay transmission unit;
The first inspection value generation unit
Buffer means for inputting the control command output by the arithmetic processing unit and outputting the input control command at a predesignated timing;
A control method for inputting a control command output by the buffer means and converting a bit string of an error check value to be added to the input control command, or a control command output by the arithmetic processing unit after the input control command The conversion method used when converting the bit string of the error check value to be added to is determined as one of a plurality of different conversion methods determined in advance based on the input control command, and indicates the determined conversion method Determining means for outputting conversion method information according to the timing;
The control command output by the buffer means is input, and the error check value generated by a predetermined generation method using the control command output by the arithmetic processing unit in the past from the input control command is determined according to the timing. Generating means for outputting,
The error check value output by the generating means and the conversion method information output by the determining means are input, the bit string of the input error check value is converted by the conversion method indicated by the input conversion method information, and the bit string is Conversion means for outputting the converted error check value according to the timing;
The control command output by the buffer means and the error check value output by the conversion means are input, the input error check value is added to the input control command, and the error check value is added. An additional means for outputting the control command in accordance with the timing in the same output control method as the output control method determined in advance in the arithmetic processing unit;
Have
The gaming machine, wherein the transmission unit transmits the control command to which the error check value output by the adding unit is added to the intermediate control unit. The plurality of conversion methods are:
A conversion method for rotating each bit constituting the bit string, wherein a shift amount indicating the number of bits for shifting each bit converts the bit string of the error check value inputted by the conversion means and outputs the bit string to the addition means A first conversion method that can change regularly every time,
A conversion method for rotating each bit constituting the bit string, wherein a shift amount indicating the number of bits for shifting each bit converts the bit string of the error check value inputted by the conversion means and outputs the bit string to the addition means A second conversion method that varies irregularly each time,
The gaming machine according to claim 1, comprising: When the determination unit inputs the control command output by the buffer unit, the determination unit determines whether or not the control command is a control command satisfying a predetermined condition, and the determination result is input. 3. The gaming machine according to claim 2, wherein when the control command indicates that the control command satisfies the condition, a conversion method for converting the bit string is determined as the second conversion method.   The gaming machine according to claim 3, wherein the shift amount in the first conversion method varies based on an error check value obtained by converting a bit string in the second conversion method. When outputting the error check value obtained by converting the bit string by the second conversion method to the adding means, the converting means outputs the error check value to the adding means and then outputs the bit string by the first conversion method. The gaming machine according to claim 4, wherein the shift amount used when converting is updated based on the error check value. The conversion means holds a plurality of different update timings as update timings indicating timings for updating the shift amount used when the bit string is converted by the first conversion method, and at the plurality of update timings. The update can be performed;
The storage unit has a storage area that is accessible when the gaming machine is activated and stores initial setting information of the gaming machine, and the initial setting information includes a plurality of selections corresponding to each of the plurality of update timings. Including information,
The arithmetic processing unit sets specific selection information of the plurality of selection information in the conversion means when the gaming machine is activated,
The gaming machine according to claim 5, wherein the conversion unit executes the update using the specific update timing corresponding to the set specific selection information. The determination means holds a plurality of different conditions, and can execute the determination using the plurality of conditions.
The storage unit has a storage area that is accessible when the gaming machine is activated and stores initial setting information of the gaming machine, and the initial setting information includes a plurality of selection information corresponding to each of the plurality of conditions. Including
The arithmetic processing unit sets specific selection information of the plurality of selection information to the determining means when the gaming machine is activated,
The gaming machine according to any one of claims 3 to 6, wherein the determination unit performs the determination using the specific condition corresponding to the specific selection information that has been set.   The gaming machine according to claim 6 or 7, wherein the selection information included in the initial setting information is the specific selection information set by the arithmetic processing unit when the gaming machine is activated. The first inspection value generation unit is provided between the arithmetic processing unit and the transmission unit,
The arithmetic processing unit and the first inspection value generation unit are connected by a first bus, and the first inspection value generation unit and the transmission unit are connected by a second bus, and the first bus and the second bus Has the same standard bus,
The arithmetic processing unit outputs the generated control command to the buffer means via the first bus,
The gaming machine according to any one of claims 1 to 8, wherein the adding means outputs the control command to which the error check value is added to the transmitting unit via the second bus. The output control method negotiated in advance in the arithmetic processing unit is an output control method negotiated based on the standard,
The buffer means outputs the input control command in a predetermined output control method different from the output control method,
The determining means outputs the conversion method information in the same output control method as the predetermined output control method used by the buffer means,
The generation means outputs the error check value generated by the generation means in the same output control method as the predetermined output control method used by the buffer means,
The gaming machine according to claim 9, wherein the conversion means outputs the error check value obtained by converting the bit string by the conversion means in the same output control method as the predetermined output control method used by the buffer means. .

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