JP5377682B2 - Authentication method for gaming machines and electronic devices - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine, a sparrow ball gaming machine, a ball ball gaming machine such as an arrangement ball, and a revolving gaming machine such as a slot machine. Furthermore, the present invention relates to an authentication method for data transmission between each control unit in an electronic apparatus including a plurality of control units.

Main control that controls basic actions associated with the progress of a game, among illegal acts that are performed on a gaming machine and forcibly pays out medals, game balls, etc. (hereinafter referred to as “game media”) regardless of the game content. Between the main control board on which the control unit is mounted and the peripheral control board on which the peripheral control unit that executes the rendering process based on control command information from the main control unit (hereinafter referred to as “control command”) is mounted. Examples of fraudulent acts include the following.
(1) Replacing an authorized main control board with an unauthorized main control board (2) A ROM storing a legitimate program executed by the CPU mounted on the main control board and an unauthorized program obtained by falsifying the above program are stored. (3) Installation of an illegal board (spoofing board) between the main control board and the peripheral control board

  In order to prevent such illegal acts, the conventional gaming machines include the following. For example, in the gaming machine described in Patent Document 1, the main control board generates a control command and transmits it to the sub-control board, and checks the control command transmitted by the first transmission means within a predetermined period. Second transmission means for transmitting the thumb as a state monitoring command at a predetermined timing. In addition, the sub-control board verifies the validity of the control command transmitted within the predetermined period by comparing the checksum of the control command received within the predetermined period with the state monitoring command received at the predetermined timing. doing. That is, the gaming machine described in Patent Document 1 attempts to prevent the illegal act by transmitting a state monitoring command for verifying the validity of the control command at a predetermined timing.

JP 2002-18095 A

  However, in the gaming machine described in Patent Document 1, a state monitoring command having a data format or data amount different from that of a normal control command is transmitted alone at a predetermined timing. Further, in the gaming machine described in Patent Document 1, a check sum of a control command transmitted within a predetermined period is used as a state monitoring command. For this reason, in the gaming machine described in Patent Document 1, a person who intends to engage in fraud (hereinafter referred to as “illegal person”) can easily know the transmission timing of the state monitoring command and steal and steal it. There is a possibility that the contents of the state monitoring command can be easily analyzed by comparing the monitoring command and the checksum of the control command within a predetermined period.

  In addition, in the gaming machine described in Patent Document 1, in order to realize the addition of the security function, a process different from the normal process of transmitting a state monitoring command is added. It is getting complicated. Therefore, in the gaming machine described in Patent Document 1, the code size of the program executed by the CPU of the main control board increases, and the processing load on the CPU increases. Also, in gaming machines, the ROM and RAM capacities of the main control board are limited due to regulations unique to public games, and more limited resources are allocated to game machine manufacturers for programs related to performance processing. There is a desire to want. Therefore, the problem that the processing load of the CPU of the main control board and the code size of the program increase by adding a security function to the gaming machine cannot be overlooked.

  In addition, when adding the security function by hardware, it is possible to suppress an increase in CPU processing load and code size. However, when a new function is added to the existing main control board by hardware, the configuration of the CPU and peripheral circuits related to the hardware must be changed, which increases the development cost and development time of the gaming machine. Invited, it will be a big burden for game machine manufacturers. For this reason, the conventional technology cannot meet the demands of gaming machine manufacturers who want to add effective security functions to existing gaming machines relatively easily.

  The present invention has been made in view of the above circumstances, and prevents unauthorized acts by simple means to improve the security strength and add relatively easily while suppressing increase in processing load and code size. An object of the present invention is to provide a gaming machine having a security function.

In order to solve the above problems, the present invention is provided between a main control unit that outputs a control command, a peripheral control unit that performs processing based on the control command, and the main control unit and the peripheral control unit a game machine comprising an intermediate control unit, wherein the main control unit, an arithmetic processing unit that generates and sends the control command in accordance with a predetermined control program stored in the storage unit, is sent by the processing unit a transmission unit that transmits the control command to the intermediate control unit has a bus to be connected to the arithmetic processing unit and said transmitting unit, said being connected to the bus, control commands sent by the processing unit And a first check value generation unit that generates an error check value for checking the validity of the control command and converts a bit string of the generated error check value, and the intermediate control unit includes the first check value generation unit . 1 Generating an error check value for verifying that corresponds to the error check value generated by査値generator, the generated bit string of the error check value is converted by previously negotiated conversion method between the main control unit a second check value generator outputting, the control command transmitted by the transmission unit by comparing the error check value output by said second check value generating unit and the error check value transmitted by the transmission unit The inspection unit that performs validity inspection and outputs the result information of the inspection , and relays the control command transmitted by the transmission unit to the peripheral control unit, and transmits the result information to the peripheral control unit and a relay transmitting unit, the peripheral control unit, performs processing based on the control command relayed by the relay transmitting unit, the result information transmitted by the relay transmitting unit Comprising a processing unit that performs processing Flip was, the first check value generating unit, when the control command to the transmitting unit from the processing unit is sent to the bus, the bus control command to said transmitting section obtained from the command acquisition means to output in the pre-specified timing control command said acquired, inputs a control command outputted by the command acquisition unit, the error check value to be added to the control command the input the conversion method used in converting a bit string, a first conversion scheme employing a rotation operation on the bit string of the error check value using the first shift amount that varies regularly, the second shift amount varying irregularly The second conversion method for performing a rotation operation on the bit string of the error check value is determined based on the input control command and indicates the determined conversion method The conversion method information, enter the system determination means to output according to the timing, and a conversion method information output by the control command outputted by the command acquisition unit said method determination means, control command said input The bit string of the error check value generated using the control command sent by the arithmetic processing unit in the past is converted by the conversion method indicated by the input conversion method information, and the error check value converted from the bit string is converted into the error check value. the test value output means to output in response to said timing, enter the error check value outputted the bit string converted by the test value output means, the error check value in which the bit string is transformed that the input In response to a read instruction of the arithmetic processing unit defined in the control program, a test value is transmitted to the arithmetic processing unit via the bus. Has a stage, the said test value output unit, when conversion method information the input indicates the first transformation method, when the reset condition is satisfied for resetting said first shift amount, said first The shift amount is set to a predetermined value, the bit string of the generated error check value is converted, and the arithmetic processing unit sends the error check acquired from the check value sending means to the control command sent to the transmitting unit. A value is added and sent to the transmission unit via the bus, and the second conversion method has the same combination of bits in the bit string before and after converting the bit string, and the second test value generation unit Is characterized in that when the first check value generation unit converts the bit string by the second conversion method, the rotation operation is performed by the number of bit widths of the error check value and is output to the check unit .

  In the present invention, when transmitting the control command to the intermediate control unit, the arithmetic processing unit reads the error check value from the first check value generation unit that is a peripheral circuit of the arithmetic processing unit, adds the error check value to the control command, and transmits the control command. Send to the department. Therefore, in the present invention, when adding a security function to the main control unit, it is only necessary to add an error check value read instruction and a write instruction to the control program, and the arithmetic processing unit increases with the addition of the security function. Processing load and code size can be minimized. Furthermore, the timing at which the arithmetic processing unit adds the error check value to the control command can be arbitrarily defined simply by customizing the control program, and a highly flexible security function can be provided.

  Moreover, the first check value generation unit generates an error check value using a past control command, and uses the generated error check value bit string by using either the first conversion method or the second conversion method. Convert. For this reason, in the present invention, the correspondence relationship between the control command and the error check value can be made more difficult to analyze, and the security strength can be improved. In addition, the first inspection value generation unit resets the first shift amount used in the first conversion method under a predetermined condition. For this reason, in the present invention, even if the fluctuation of the first shift amount is shifted between the main control unit side and the intermediate control unit side due to a communication error or the like, the shift can be appropriately eliminated, and the error check processing can be performed. Accuracy can be improved.

  According to the present invention, the authentication function for the main control unit is included in the intermediate control unit that is independent from the peripheral control unit that performs processing related to normal game progression. Therefore, the processing load and code size that increase due to the addition of the authentication function can be suppressed in the processing unit of the peripheral control unit. And a security function can be added comparatively easily with respect to the existing game machine.

It is a front view which shows the external appearance structure of the game machine which concerns on embodiment of this invention. It is a perspective view which shows the external appearance structure of the state which open | released the glass frame of the game machine which concerns on embodiment of this invention. It is a perspective view which shows the external appearance structure of the back surface side of the game machine which concerns on embodiment of this invention. It is a block diagram which shows the internal structure of the game machine which concerns on embodiment of this invention. It is a block diagram which shows the structure regarding the authentication process of the main control part which comprises the game machine which concerns on embodiment of this invention. It is the schematic for demonstrating the memory map of the main CPU which comprises the main control part which comprises the game machine which concerns on embodiment of this invention. It is a block diagram which shows the internal structure of the test value production | generation part which comprises the main control part which comprises the game machine which concerns on embodiment of this invention. It is a block diagram which shows the structure regarding the authentication process of the intermediate | middle control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the classification of the control command transmitted to the production | presentation control part from the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the main process by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the interruption process by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the special figure special electricity control process by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the special symbol memory | storage determination process by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the boot process at the time of starting by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the command transmission process 1 by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the command transmission process 2 by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the command transmission process 3 by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the main process by the intermediate | middle control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the main process by the production | presentation control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the interruption process by the production | presentation control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the command analysis process 1 by the presentation control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the command analysis process 2 by the production | presentation control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the error check process by the presentation control part which comprises the game machine which concerns on embodiment of this invention. It is the schematic for demonstrating the example of the addition procedure of the error check value to the control command transmitted from the main control part which comprises the game machine which concerns on embodiment of this invention.

  Embodiments for carrying out the present invention will be described with reference to the drawings. Specifically, a pachinko gaming machine 1 (hereinafter referred to as “gaming machine 1”), which is one of the gaming machines according to the embodiment of the present invention, will be described.

[Composition of gaming machine]
Hereafter, the configuration of the gaming machine 1 according to one embodiment of the present invention will be described.
FIG. 1 is a front view showing an external configuration of the gaming machine 1 according to the present embodiment. FIG. 2 is a perspective view showing an external configuration of the gaming machine 1 according to the present embodiment in a state where the glass frame is opened. FIG. 3 is a perspective view showing an external configuration of the back side of the gaming machine 1 according to the present embodiment.

  The gaming machine 1 includes an outer frame 60 attached to an island facility of a game store, and a glass frame 50 that is rotatably supported by the outer frame 60 (see FIGS. 1 and 2). In addition, the outer frame 60 is provided with a game board 2 in which a game area 6 in which the game ball 200 flows down is formed. In the glass frame 50, an operation handle 3 for launching a game ball toward the game area 6 by being rotated, an audio output device 32 including a speaker, an effect lighting device 34 having a plurality of lamps, An effect button 35 for changing the effect mode by a pressing operation is provided.

  Further, the glass frame 50 is provided with a tray 40 for storing a plurality of game balls 200, and the tray 40 has a downward slope so that the game balls 200 flow down toward the operation handle 3. (See FIG. 2). A receiving opening (not shown) for receiving a game ball is provided at the end of the downward slope of the tray 40, and the game ball received in the receiving opening is driven by the ball feed solenoid 4b, so that the glass frame One by one is sent to a ball feed opening 41 provided on the back surface of 50. Then, the game ball sent out to the ball feed opening 41 is guided to the end of the downward slope of the launch rail 42 by the launch rail 42 having a downward slope toward the launching member 4c. A stopper 43 for stopping the game ball is provided above the downwardly inclined end portion of the launch rail 42, and the game ball 200 sent out from the ball feed opening 41 is the downwardly inclined end portion of the launch rail 42. Thus, one game ball is stopped (see FIG. 2).

  When the player rotates the operation handle 3, the launch volume 3b (see FIG. 4) directly connected to the operation handle 3 also rotates, and the launch volume of the game ball is adjusted and adjusted by the launch volume 3b. The launching member 4c directly connected to the firing solenoid 4a (see FIG. 4) rotates with the firing strength. By rotating the launch member 4 c, the game ball 200 stored at the end of the downward slope of the launch rail 42 is launched by the launch member 4 c, and the game ball is launched into the game area 6.

  When the game ball fired as described above rises between the rails 5a and 5b from the launch rail 42 and exceeds the ball return prevention piece 5c, the game ball reaches the game area 6 and then falls in the game area 6. At this time, the game ball falls unpredictably by a plurality of nails and windmills provided in the game area 6.

  The game area 6 is provided with a plurality of general winning awards 12. Each of these general winning awards 12 is provided with a general winning opening detecting switch 12a (see FIG. 4). When this general winning opening detecting switch 12a detects the winning of a game ball, a predetermined winning ball (for example, 10) Game balls).

  Further, in the area below the center of the game area 6, there are a first start port 14 and a second start port 15 that constitute a start area where a game ball can enter, and a second large area where a game ball can enter. A winning opening 17 is provided.

  The second starting port 15 has a pair of movable pieces 15b, a mode in which the pair of movable pieces 15b is maintained in a closed state (hereinafter referred to as “first mode”), and a pair of movable pieces. The movement control is performed so that 15b is in an open state (hereinafter referred to as “second aspect”). When the second starting port 15 is controlled in the first mode, the winning member of the second large winning port 17 located immediately above the second starting port 15 becomes an obstacle, and the game ball Is impossible to accept. On the other hand, when the second start port 15 is controlled to the second mode, the pair of movable pieces 15b function as a tray, and it is easy to win a game ball to the second start port 15. That is, when the second start port 15 is in the first mode, there is no game ball winning opportunity, and when it is in the second mode, the game ball winning opportunity is increased.

  Here, the first start port 14 is provided with a first start port detection switch 14a (see FIG. 4) for detecting the entrance of a game ball, and the second start port 15 is a first for detecting the entrance of a game ball. 2 A start port detection switch 15a (see FIG. 4) is provided. When the first start port detection switch 14a or the second start port detection switch 15a detects the entry of a game ball, a special symbol determination random number value is acquired and a right winning lottery game (to be described later) is executed ( Hereinafter, “Lottery for jackpot” is performed. In addition, when the first start port detection switch 14a or the second start port detection switch 15a detects the entry of a game ball, a predetermined prize ball (for example, three game balls) is paid out.

  Further, the second grand prize winning port 17 is constituted by an opening formed in the game board 2. Below the second grand prize opening 17, there is a second big prize opening / closing door 17b that can protrude from the game board surface side to the glass plate 52 side. It is controlled to move between an open state protruding to the side and a closed state buried in the game board surface. When the second grand prize opening opening / closing door 17b protrudes from the game board surface, it functions as a tray for guiding the game ball into the second big prize opening 17, and the game ball can enter the second big prize opening 17. Become. The second big prize opening 17 is provided with a second big prize opening detection switch 17a (see FIG. 4). When the second big prize opening detection switch 17a detects the entry of a game ball, it is set in advance. Award balls (for example, 15 game balls) are paid out.

Furthermore, in the area on the right side of the game area 6, there are provided a normal symbol gate 13 constituting a normal area through which game balls can pass and a first grand prize winning opening 16 through which game balls can enter.
For this reason, unless the operation handle 3 is rotated to a large extent and the game ball is launched with a strong force, the normal design gate 13 and the first big winning opening 16 are configured such that the game ball does not pass or win. Yes. In particular, even if the short game state, which will be described later, is entered, if the game ball flows down to the left side of the game area 6, the game ball will not normally pass through the symbol gate 13, so that it is at the second start port 15. The pair of movable pieces 15b are not opened, and it is difficult for a game ball to win the second starting port 15.

  The normal symbol gate 13 is provided with a gate detection switch 13a (see FIG. 4) for detecting the passage of the game ball. When the gate detection switch 13a detects the passage of the game ball, the normal symbol determination random number value. Is acquired, and a “normal symbol lottery” to be described later is performed.

  The first grand prize opening 16 is normally kept closed by the first big prize opening opening / closing door 16b, and it is impossible to enter a game ball. On the other hand, when a special game, which will be described later, is started, the first grand prize opening / closing door 16b is opened, and the first big prize opening / closing door 16b puts the game ball in the first grand prize opening 16. It functions as a receiving tray that guides the game ball and can enter the first grand prize opening 16. The first big prize opening 16 is provided with a first big prize opening detection switch 16a (see FIG. 4). When the first big prize opening detection switch 16a detects the entry of a game ball, it is set in advance. Prize balls (for example, 15 game balls) are paid out.

  Further, in the lowermost area of the game area 6 and the lowermost area of the game area 6, the general winning opening 12, the first starting opening 14, the second starting opening 15, the first major winning opening 16, and the second large winning opening. An out port 11 is provided for discharging game balls that have not entered any of the winning ports 17.

In addition, a decoration member 7 that affects the flow of the game ball is provided in the center of the game area 6. A liquid crystal display device 31 is provided at a substantially central portion of the decorative member 7, and an effect driving device 33 in the form of a belt is provided above the liquid crystal display device 31.
In this embodiment, the liquid crystal display device 31 is used as a liquid crystal display. However, an organic EL display may be used, a projector, a reel made of an annular structure, a so-called 7-segment LED, a dot matrix. A display device or the like may be used.

The liquid crystal display device 31 displays an image during standby when no game is being performed, or displays an image according to the progress of the game. Among them, three effect symbols 36 for informing the jackpot lottery result, which will be described later, are displayed, and a combination of specific effect symbols 36 (for example, 777) is stopped and displayed as a jackpot lottery result. A jackpot is announced.
More specifically, when a game ball enters the first starting port 14 or the second starting port 15, the three effect symbols 36 are scroll-displayed, and the scrolling is stopped after a predetermined time, The effect design 36 is stopped and displayed. Further, by displaying various images, characters, and the like during the variation display of the effect symbol 36, a high expectation that the player may win a big hit is given to the player.

  The effect driving device 33 gives a player a sense of expectation according to the operation mode. The effect driving device 33 performs, for example, an operation in which the belt moves downward or a rotating member at the center of the belt rotates. Various operational feelings are given to the player depending on the operation mode of the effect driving device 33.

  Furthermore, in addition to the above-described various production devices, the audio output device 32 outputs background music, sound effects, and the like, and produces productions using sound. The production lighting device 34 includes the illumination direction of each lamp, The luminescent color is changed to produce lighting.

  The effect button 35 is effective only when, for example, a message for operating the effect button 35 is displayed on the liquid crystal display device 31. The effect button 35 is provided with an effect button detection switch 35a (see FIG. 4). When the effect button detection switch 35a detects the player's operation, a further effect is executed in accordance with this operation.

  In the lower right of the game area 6, a first special symbol display device 20, a second special symbol display device 21, a normal symbol display device 22, a first special symbol hold indicator 23, a second special symbol hold indicator 24, a normal A symbol hold indicator 25 is provided.

  The first special symbol display device 20 is for notifying a lottery result obtained when a game ball enters the first start port 14, and is composed of 7-segment LEDs. That is, a plurality of special symbols corresponding to the jackpot lottery result are provided, and the lottery result is notified to the player by displaying the special symbol corresponding to the jackpot lottery result on the first special symbol display device 20. I am doing so. For example, “7” is displayed when the jackpot is won, and “−” is displayed when the player wins. “7” and “−” displayed in this way are special symbols, but these special symbols are not displayed immediately, but are displayed in a stopped state after being displayed for a predetermined time. .

  Here, the “successful lottery” means that when a game ball enters the first start port 14 or the second start port 15, a special symbol determination random value is acquired, and the acquired special symbol determination random value is acquired. Is a random number value corresponding to “big hit” or a random number value corresponding to “small hit”. The jackpot lottery result is not immediately notified to the player, and the first special symbol display device 20 displays a variation such as blinking of the special symbol, and when the predetermined variation time has passed, the jackpot lottery result The special symbol corresponding to is stopped and displayed so that the player is notified of the lottery result. The second special symbol display device 21 is for notifying a lottery result of a jackpot that is performed when a game ball enters the second start port 15, and the display mode is the above-described first display mode. This is the same as the special symbol display mode in the special symbol display device 20.

  Further, in this embodiment, “big hit” means that a right to win a big hit game is obtained in the big hit lottery performed on the condition that a game ball has entered the first start port 14 or the second start port 15 Say what you did. In the “big hit game”, a round game in which the first big prize opening 16 or the second big prize opening 17 is opened is performed a total of 15 times. A predetermined time is set for the maximum opening time of the first grand prize winning opening 16 or the second big winning prize opening 17 in each round game, and during this time, the first big winning prize opening 16 or the second big winning prize opening 17 is set. When a predetermined number of game balls (for example, nine) enter, one round game is completed. In other words, the “big hit game” is a game in which a game ball can enter the first grand prize winning opening 16 or the second big winning prize opening 17 and the player can acquire a prize ball according to the winning prize.

In this embodiment, in the “hit lottery”, two gaming states are set according to the winning probability. That is, the “low probability gaming state” in which the winning probability is set to 1 / 299.5 and the “high probability gaming state” in which the winning probability is set to 1 / 29.95. Also, in the “jackpot game”, a plurality of types of jackpot games are set. For example, in the case of “game per long”, the first big prize opening 16 is released once (× 15 rounds) for 29.000 seconds for each round game. If it is “short win game”, the second big prize opening 17 is opened for 0.052 seconds × 1 time (× 15 rounds) for each round of game. In the case of “game per development”, the second grand prize opening 17 is opened for 0.052 seconds × 3 times in the first round game, and 29.000 seconds × 1 for each round game after the second round. Times (× 14 rounds).
In the case of “small hit”, one gaming state with a winning probability of 1 / 149.75 is set. In addition, if it is a “small hit game”, although it is not a round game, the second big prize opening 17 is opened for 0.052 seconds × 15 times. In the present embodiment, “big hit game” and “small hit game” are collectively referred to as “special game”.

  The normal symbol display device 22 is for notifying the lottery result of the normal symbol that is performed when the game ball passes through the normal symbol gate 13. As will be described in detail later, when the winning symbol is won by the normal symbol lottery, the normal symbol display device 22 is turned on, and then the second start port 15 is controlled to the second mode for a predetermined time.

  Here, “normal symbol lottery” means that when a game ball passes through the normal symbol gate 13, the normal symbol determination random number value is acquired, and the acquired normal symbol determination random value corresponds to “winning”. A process for determining whether or not the value is a random value. The lottery result of the normal symbol is not always notified immediately after the game ball passes through the normal symbol gate 13, but the normal symbol display device 22 displays a variation such as blinking of the normal symbol. When the fluctuation time elapses, the normal symbol corresponding to the lottery result of the normal symbol is stopped and displayed so that the player is notified of the lottery result.

Furthermore, if a game ball enters the first start port 14 or the second start port 15 during special symbol fluctuation display or special game described later, and if the big hit lottery cannot be performed immediately, a certain condition The right to win a jackpot will be withheld. More specifically, the random number value for special symbol determination acquired when the game ball enters the first start port 14 is stored as the first hold, and when the game ball enters the second start port 15 The acquired special symbol determination random number value is stored as the second hold.
For both of these holds, the upper limit hold number is set to 4, and the hold number is displayed on the first special symbol hold indicator 23 and the second special symbol hold indicator 24, respectively. When there is one first hold, the LED on the left side of the first special symbol hold indicator 23 lights up, and when there are two first holds, two LEDs on the first special symbol hold indicator 23 Lights up. In addition, when there are three first holds, the LED on the left side of the first special symbol hold indicator 23 blinks and the right LED lights. When there are four first holds, the first special symbol hold Two LEDs on the display 23 blink. The second special symbol hold indicator 24 also displays the number of second hold on hold in the same manner as described above.
The upper limit reserved number of normal symbols is also set to four, and the reserved number of normal symbols is displayed in the same manner as the first special symbol hold indicator 23 and the second special symbol hold indicator 24. Displayed on the instrument 25.

  The glass frame 50 supports a glass plate 52 that covers the game area 6 so as to be visible in front of the game board 2 (player side). The glass plate 52 is detachably fixed to the glass frame 50.

  The glass frame 50 is connected to the outer frame 60 via a hinge mechanism 51 on one end side in the left-right direction (for example, the left side facing the gaming machine 1), and the left-right direction with the hinge mechanism 51 as a fulcrum. The other end side (for example, the right side facing the gaming machine 1) can be rotated in a direction to release from the outer frame 60. The glass frame 50 covers the game board 2 together with the glass plate 52 and rotates like a door with the hinge mechanism 51 as a fulcrum, thereby opening the inner part of the outer frame 60 including the game board 2. On the other end side of the glass frame 50, a lock mechanism for fixing the other end side of the glass frame 50 to the outer frame 60 is provided. The fixing by the lock mechanism can be released by a dedicated key. The glass frame 50 is also provided with a door opening switch 133 (see FIG. 4) for detecting whether or not the glass frame 50 is opened from the outer frame 60.

  On the back side of the gaming machine 1, a main control board on which the main control unit 110 is mounted, an intermediate control board on which the intermediate control unit 180 is mounted, an effect control board on which the effect control unit 120 is mounted, and a payout control unit 130 are mounted. The payout control board, the power supply board on which the power supply unit 170 is mounted, the game information output terminal board 30 and the like are provided. Further, the power supply unit 170 is provided with a power plug 171 for supplying power to the gaming machine 1 and a power switch (not shown).

[Internal configuration of gaming machine]
Hereafter, the control means which controls the process which concerns on the game progress of the game machine 1 which concerns on embodiment of this invention is demonstrated.
FIG. 4 is a block diagram showing an internal configuration of the gaming machine 1 according to the present embodiment.

  The main control unit 110 is a main control means for controlling the basic operation of the game, and receives various detection signals from the first start port detection switch 14a, etc., and opens and closes the first special symbol display device 20 and the first grand prize opening. The game is controlled by driving the solenoid 16c and the like.

  The main control unit 110 includes a main CPU 110a, a main ROM 110b, a main RAM 110c, a boot ROM 110d, a test value generation unit 500, and a transmission unit 550. The one-chip microcomputer 110m includes a main control input port and an output port ( (Not shown).

  The main control input port includes a payout control unit 130, a general winning port detecting switch 12a for detecting that a gaming ball has entered the general winning port 12, and a game ball having been inserted into the normal symbol gate 13. Gate detection switch 13a to detect, first start port detection switch 14a to detect that a game ball has entered the first start port 14, and second start to detect that a game ball has entered the second start port 15 The mouth detection switch 15a, the first grand prize opening detection switch 16a that detects that a game ball has entered the first grand prize opening 16, and the second that detects that a game ball has entered the second grand prize opening 17 A big prize opening detection switch 17a is connected. Various signals are input to the main control unit 110 through the input port for main control.

  The main control output port includes a payout control unit 130, a start opening / closing solenoid 15c for opening / closing the pair of movable pieces 15b of the second start opening 15, and a first large winning opening opening / closing door 16b. A special winning opening / closing solenoid 16c, a second large winning opening / closing solenoid 17c for operating the second winning opening / closing door 17b, a first special symbol display device 20 and a second special symbol display device 21 for displaying special symbols, and a normal symbol. A normal symbol display device 22 for displaying a symbol, a first special symbol hold indicator 23 and a second special symbol hold indicator 24 for displaying the number of reserved balls for a special symbol, and a normal symbol hold indicator for displaying the number of reserved balls for a normal symbol 25. A game information output terminal board 30 for outputting an external information signal is connected. Various signals are output from the main control output port.

  The main CPU 110a of the main control unit 110 reads out a program stored in the main ROM 110b based on an input signal from each detection switch or a timer (not shown) incorporated as an internal function, and performs arithmetic processing. Depending on the result, a control instruction (hereinafter referred to as “control signal”) for each component constituting the main control unit 110 and a control command for another control unit other than the main control unit 110 are output.

The main ROM 110b of the main control unit 110 stores in advance a game processing program that describes the content and procedure of processing related to game progress, and fixed data and tables necessary for determining various games.
As an example of a table stored in the main ROM 110b, a jackpot determination table referred to in the jackpot lottery, a hit determination table referred to in the normal symbol lottery, a symbol determination table for determining the stop symbol of the special symbol, after the jackpot ends End of jackpot game setting data table for determining the gaming state of the game, special electric accessory operating mode determination table for determining the opening / closing conditions of the special winning opening opening door, determining the opening pattern table of the special winning opening, and the variation pattern of the special symbol There is a variation pattern determination table.

  Further, as will be described later, the main ROM 110b is used when executing an authentication processing program that describes the contents and procedure of processing executed by the main CPU 110a in order to realize addition of a security function, and an authentication processing program. Fixed data and the like are stored in advance.

  In the boot ROM 110d of the main control unit 110, as will be described later, a boot processing program describing the content and procedure of boot processing executed by the main CPU 110a, fixed data used when executing the boot processing program, and the like Is stored in advance. This boot processing program is set to start immediately after the main CPU 110a is activated.

The main RAM 110c of the main control unit 110 functions as a data work area when the main CPU 110a performs arithmetic processing, and has a plurality of storage areas.
As an example of the storage area that the main RAM 110c has, a normal symbol holding number (G) storage area, a normal symbol holding storage area, a normal symbol data storage area, a first special symbol holding number (U1) storage area, a second special symbol Reservation count (U2) storage area, first special symbol random value storage area, second special symbol random value storage area, round game number (R) storage area, number of open times (K) storage area, number of big winning entrances ( C) Storage area, game state storage area (high probability game flag storage area, etc. and short time game flag storage area), high probability game number (X) counter, short time number (J) counter, game state buffer, stop symbol data storage area There are various timer counters such as a storage area for transmission data, a special symbol time counter, and a special game timer counter.

  As will be described later, the test value generation unit 500 of the main control unit 110 is a peripheral circuit of the main CPU 110a. When the main control unit 110 transmits a control command, an error check is added to the control command to be transmitted. This is a circuit having a function of generating a value (hereinafter referred to as “error check value generation function”). The error check value is data for checking the validity of the control command output from the main control unit 110, and is generated using the control command. Then, based on the game processing program, the main CPU 110a transmits a control command to the effect control unit 120, the payout control unit 130, etc. connected to the later-described intermediate control unit 180 (hereinafter, referred to as a transmission command). , The error check value is added to the control command to be transmitted and transmitted to the intermediate control unit 180. The check value generation unit 500 of this embodiment has a plurality of error check value generation functions with different error check value generation modes.

  The transmission unit 550 of the main control unit 110 is particularly connected to a control unit (intermediate control unit 180 described later) that is determined in advance to perform an authentication function for the main control unit 110 among the output ports for main control. , A circuit having functions of an output port and an interface assigned for control command output.

  The game information output terminal board 30 is a board for outputting an external information signal generated by the main control unit 110 to a hall computer or the like of a game store. The game information output terminal board 30 is connected to the main controller 110 by wiring, and is provided with a connector for connecting external information to a hall computer or the like of a game store.

  The power supply unit 170 includes a backup power supply made of a capacitor, supplies a power supply voltage to the gaming machine 1, and monitors a power supply voltage supplied to the gaming machine 1, and when the power supply voltage becomes a predetermined value or less, An electric interruption detection signal is output to the main control unit 110. More specifically, when the power interruption detection signal is at a low level and a certain time has elapsed since the power supply voltage is equal to or lower than a set value, the reset signal is at a low level and the main CPU 110a performs a process of stopping the operation. Thereafter, when the power interruption detection signal becomes a high level because the power supply voltage is equal to or higher than the set value and a predetermined time elapses, the reset signal becomes a high level, and the main CPU 110a performs a process of starting an operation. The backup power source is not limited to a capacitor, and may be a battery, for example, or a capacitor and a battery may be used in combination.

  The intermediate control unit 180 is a control means for mainly realizing an authentication function for the main control unit 110, and includes a CPU 180a, a ROM 180b, and a RAM 180c. The intermediate control unit 180 is provided between the main control unit 110 and a control unit (the effect control unit 120, the payout control unit 130, etc.) to which the main control unit 110 transmits a control command related to the original game process. It has been.

  For example, as shown in FIG. 4, when the intermediate control unit 180 is provided between the main control unit 110 and the effect control unit 120, the intermediate control unit 180 is transferred from the main control unit 110 to the intermediate control unit 180. They are connected so as to be communicable in one direction, and are connected so as to be communicable in one direction from the intermediate control unit 180 to the effect control unit 120. Although not shown, when the intermediate control unit 180 is provided between the main control unit 110 and the payout control unit 130, the intermediate control unit 180 can communicate with the main control unit 110 in both directions. And are connected so as to be able to communicate bidirectionally with the payout control unit 130. Therefore, when the intermediate control unit 180 is interposed, the effect control unit 120, the payout control unit 130, and the like are not transmitted directly from the main control unit 110, but are transmitted via the intermediate control unit 180.

  The CPU 180a reads out a program stored in the ROM 180b based on a control command transmitted from the main control unit 110 or an input signal from a timer (not shown) incorporated as an internal function, and performs arithmetic processing. Then, CPU 180a transmits the corresponding data to subsequent effect control unit 120 and payout control unit 130 based on the processing. The RAM 180c functions as a data work area during the arithmetic processing of the CPU 180a.

  For example, when the CPU 180a of the intermediate control unit 180 receives a control command transmitted from the main control unit 110, the CPU 180a performs error check processing for checking the validity of the control command and authenticating the validity of the main control unit 110. Then, the CPU 180a transmits the authentication result information (hereinafter referred to as “authentication result data”) obtained by the processing to the subsequent effect control unit 120, the payout control unit 130, and the like, and performs processing based on the authentication result data. Let it run. Further, the CPU 180a performs a relay transmission process of transmitting the control command to the subsequent effect control unit 120, the payout control unit 130, or the like while maintaining the specific processing content and the reception order of the received control command.

Further, the ROM 180b has an authentication processing program describing the contents and procedure of the authentication processing including error checking processing for the received control command performed by the CPU 180a, and a fixed used for executing the authentication processing program. Data and information corresponding to the unique information stored in the main ROM 110b of the main control unit 110 are stored in advance.
As described above, the intermediate control unit 180 is obtained by the error checking process, the authentication function for the main control unit 110, the function of relaying the received control command to the subsequent effect control unit 120, the payout control unit 130, and the like. At least a function of transmitting the authentication result data to the subsequent effect control unit 120, payout control unit 130, and the like. In addition, the structure regarding these authentication processes is mentioned later.

  The effect control unit 120 mainly controls each effect such as during a game or standby. The effect control unit 120 includes a sub CPU 120a, a sub ROM 120b, and a sub RAM 120c, and is provided so as to be able to communicate in one direction from the main control unit 110 to the effect control unit 120. As shown in FIG. 4, when the intermediate control unit 180 is provided between the main control unit 110 and the effect control unit 120, the effect control unit 120 is connected to the main control unit 110 via the intermediate control unit 180. To the direction control unit 120 in one direction.

  The sub CPU 120a reads out the program stored in the sub ROM 120b based on the control command transmitted from the main control unit 110, or the input signal from the effect button detection switch 35a and the timer, performs arithmetic processing, and Based on the processing, the corresponding data is transmitted to the lamp control unit 140 or the image control unit 150. The sub RAM 120c functions as a data work area during the arithmetic processing of the sub CPU 120a.

  For example, when the sub CPU 120a in the effect control unit 120 receives a variation pattern designation command indicating a variation pattern of a special symbol, which is one of the control commands transmitted from the main control unit 110, the contents of the received variation pattern designation command are displayed. Analysis is performed to generate data for causing the liquid crystal display device 31, the audio output device 32, the effect driving device 33, and the effect illumination device 34 to execute a predetermined effect, and the data is used for the image control unit 150 and the lamp control unit. 140.

The sub ROM 120b of the effect control unit 120 stores a program for effect control, data necessary for determining various games, and a table.
As an example of the table stored in the sub-ROM 120b, to determine the combination of the effect pattern determination table for determining the effect pattern based on the variation pattern designation command received from the main control unit and the effect symbol 36 to be stopped and displayed. There is a production design determination table.

The sub RAM 120c of the effect control unit 120 functions as a data work area during the arithmetic processing of the sub CPU 120a, and has a plurality of storage areas.
As an example of the storage area that the sub-RAM 120c has, there are a game state storage area, an effect mode storage area, an effect pattern storage area, an effect symbol storage area, and the like.

  The payout control unit 130 controls payout of game balls. The payout control unit 130 includes a one-chip microcomputer including a payout CPU, a payout ROM, and a payout RAM (not shown), and is provided so as to be capable of bidirectional communication with the main control unit 110. . Although not shown, when the intermediate control unit 180 is provided between the main control unit 110 and the payout control unit 130, the payout control unit 130 communicates with the main control unit 110 via the intermediate control unit 180. It becomes possible to communicate in both directions.

  The payout CPU reads out a program stored in the payout ROM based on input signals from the payout ball count switch 132, the door opening switch 133, and the timer that detect whether or not the game ball has been paid out, and performs arithmetic processing. At the same time, the corresponding data is transmitted to the main control unit 110 based on the processing.

  Further, a payout motor 131 of a payout device for paying out a predetermined number of game balls from the game ball storage unit is connected to the output side of the payout control unit 130. The payout CPU reads out a predetermined program from the payout ROM based on a payout number designation command that is one of the control commands transmitted from the main control unit 110, performs arithmetic processing, and controls the payout motor 131 of the payout device. Then, a predetermined game ball is paid out. At this time, the payout RAM functions as a data work area at the time of calculation processing of the payout CPU.

  The lamp control unit 140 controls lighting of the effect lighting device 34 provided on the game board 2 and controls driving of the motor for changing the light irradiation direction. In addition, energization control is performed on a drive source such as a solenoid or a motor that operates the effect driving device 33. The lamp control unit 140 is connected to the effect control unit 120, and performs the above-described controls based on various commands transmitted from the effect control unit 120.

  The image control unit 150 stores a host CPU for performing image display control of the liquid crystal display device 31, a host RAM having a temporary storage area functioning as a work area of the host CPU, a control processing program for the host CPU, and the like. A host ROM, a CGROM storing image data, a VRAM having a frame buffer for drawing image data, a VDP (Video Display Processor) serving as an image processor, and a sound control circuit for controlling sound.

Based on the effect pattern designation command received from the effect control unit 120, the host CPU instructs the liquid crystal display device 31 to display the image data stored in the CGROM in the VDP.
The VDP draws image data stored in the CGROM in the frame buffer of the VRAM based on an instruction from the host CPU. Next, a video signal (RGB signal or the like) is generated based on the image data stored in the display frame buffer in the VRAM, and the generated video signal is output to the liquid crystal display device.

  The sound control circuit includes an audio ROM that stores a large number of audio data. The sound control circuit reads a predetermined program based on a command transmitted from the effect control unit 120, and also outputs the audio output device 32. Audio output control at.

  The launch control unit 160 performs launch control of the game ball. In the firing control unit 160, the touch sensor 3a and the firing volume 3b are connected to the input side, and the firing solenoid 4a and the ball feeding solenoid 4b are connected to the output side. The firing control unit 160 inputs a touch signal from the touch sensor 3a, and performs control to energize the firing solenoid 4a and the ball feed solenoid 4b based on the voltage supplied from the firing volume 3b.

  The touch sensor 3a is provided in the inside of the operation handle 3, and is comprised from the electrostatic capacitance type proximity switch using the change of the electrostatic capacitance by the player touching the operation handle 3. When the touch sensor 3a detects that the player has touched the operation handle 3, the touch sensor 3a outputs a touch signal that permits energization of the firing solenoid 4a to the firing control unit 160 (see FIG. 4). The firing control unit 160 is configured so that the game ball 200 is not fired into the game area 6 unless a touch signal is input from the touch sensor 3a.

  The firing volume 3b is provided directly connected to a rotating portion around which the operation handle 3 rotates, and is composed of a variable resistor. The firing volume 3b divides a constant voltage (for example, 5V) applied to the firing volume 3b by a variable resistor, and supplies the divided voltage to the firing control unit 160 (the voltage to be supplied to the firing control unit 160). Variable). The launch controller 160 energizes the launch solenoid 4a based on the voltage divided by the launch volume 3b, and rotates the launch member 4c directly connected to the launch solenoid 4a, thereby playing the game ball 200 in the game. Fire into area 6.

  The launching solenoid 4a is composed of a rotary solenoid, and a launching member 4c is directly connected to the launching solenoid 4a, and the launching member 4c is rotated by rotating the launching solenoid 4a.

  Here, the rotational speed of the firing solenoid 4a is set to about 99.9 (times / minute) based on the frequency based on the output period of the crystal oscillator provided in the firing control unit 160. As a result, the number of games played per minute is about 99.9 (pieces / minute) because one shot is fired every time the firing solenoid rotates. That is, one game ball is fired about every 0.6 seconds.

  The ball feed solenoid 4b is composed of a linear solenoid, and sends out the game balls in the tray 40 one by one toward the launch member 4c directly connected to the launch solenoid 4a.

  Here, the production control unit 120, the payout control unit 130, the lamp control unit 140, the image control unit 150, the launch control unit 160, and the like having the above-described configuration are based on or in response to control commands from the main control unit 110. A control unit that performs control processing of the gaming machine 1 in accordance with a command generated based on the command, and the control units other than the intermediate control unit 180 are collectively referred to as a “peripheral control unit 300”. In addition, each control board on which each control unit of the peripheral control unit 300 is mounted, such as an effect control board on which the effect control unit 120 is mounted and a payout control board on which the payout control unit 130 is mounted, is collectively referred to as “peripheral control board” " Note that the intermediate control unit 180, the lamp control unit 140, and the image control unit 150 may be mounted on the same substrate as the effect control unit 120. Also, the payout control unit 130 and the firing control unit 160 can be mounted on the same substrate as the main control unit 110.

[Internal configuration related to authentication processing of main controller]
The security function that the gaming machine 1 having the above configuration has for preventing illegal acts will now be described.
The security function of the gaming machine 1 according to the present embodiment is realized by the intermediate control unit 180 checking the validity of the control command transmitted from the main control unit 110 and authenticating the main control unit 110. Therefore, the processing executed by the main control unit 110, the intermediate control unit 180, and the peripheral control unit 300 is referred to as “authentication processing” in a sense that distinguishes it from processing related to normal game progress. In the present embodiment, the intermediate control unit 180 is provided between the effect control unit 120 of the peripheral control unit 300 and the main control unit 110, and the intermediate control unit 180 is connected to the main control unit 110. It is assumed that an authentication function is provided.

First, an outline of the authentication process performed between the main control unit 110 and the intermediate control unit 180 will be described.
When transmitting a control command to the intermediate control unit 180 in the current command transmission process, the main CPU 110a of the main control unit 110 adds an error check value to the transmitted control command and transmits it. This error check value is independently generated by the check value generation unit 500, which is a peripheral circuit of the main CPU 110a, instead of an instruction from the main CPU 110a. When adding an error check value, the main CPU 110a reads the error check value generated in advance by the check value generation unit 500, adds it to the control command, and sends it to the transmission unit 550. The transmission unit 550 transmits the control command to which the error check value is added to the intermediate control unit 180.

  The test value generation unit 500 acquires a control command sent from the main CPU 110a to the transmission unit 550, and generates an error check value using a control command sent in the past from the control command sent in the current command transmission process. To do. In the present embodiment, the control command sent in the past is the control sent to the sending unit 550 by the main CPU 110a during the command sending process N times before the current command sending process (N: positive integer). Suppose that it is a command. That is, the check value generation unit 500 generates an error check value using the control command transmitted N times before the control command transmitted from the main CPU 110a to the intermediate control unit 180 in the current command transmission process.

  On the other hand, the CPU 180a of the intermediate control unit 180 also receives the control command transmitted from the main control unit 110, and generates an error check value for verification using the received control command. When an error check value is added to the control command received this time, the CPU 180a uses the error check value added to the control command received this time and the control command received in the past from the control command. Check the generated error check value. If the two match, the validity of the control command received this time is authenticated, and it is determined that the main control unit 110 has been successfully authenticated. Then, the CPU 180a transmits the obtained authentication result to the effect control unit 120. The sub CPU 120a of the effect control unit 120 receives the authentication result transmitted from the intermediate control unit 180, and performs processing according to the received authentication result.

  Normally, an error check value such as a checksum is added to the control command of the generation source and used for a communication error check. On the other hand, in the present embodiment, since the check value generation unit 500 generates an error check value using a control command sent in the past, it is added to the control command that is the generation source of the error check value. There is no. By using such a new and simple method that has not been available in the past, even if an unauthorized person steals a control command and an error check value, the correspondence between the control command and the error check value cannot be easily analyzed. The security strength of the gaming machine 1 can be improved.

  In the present embodiment, the main control unit 110 adds an error check value generated using a control command transmitted in the past to the control command transmitted this time and transmits the error check value to the intermediate control unit 180. Then, the intermediate control unit 180 performs an error check process on the control command received this time with the error check value generated using the control command received in the past. Thereby, the intermediate control unit 180 can not only authenticate the validity of the control command received this time, but also the control command received in the past, that is, the control command that is the generation source of the error check value added this time. Can also authenticate the legitimacy. That is, it is possible to authenticate the continuity of the control command, and it becomes easier to detect fraud, and the security strength of the gaming machine 1 can be improved.

Next, a configuration related to the authentication process of the main control unit 110 will be described with reference to FIGS. 5 and 6.
FIG. 5 is a block diagram showing a functional configuration related to authentication processing of the main control unit 110 according to the present embodiment. FIG. 6 is a schematic diagram for explaining a memory map of the main CPU according to the present embodiment, and is a memory map related to (a) the entire map, (b) the main ROM 110b, and (c) the boot ROM 110d. In FIG. 6, areas other than the characteristic areas of the present invention are omitted, and the positional relationship between the areas is also an example.

  As described above, the main control unit 110 has a test value generation unit 500 having an error check value generation function and a function of transmitting a control command to the intermediate control unit 180 in addition to the main CPU 110a, the main ROM 110b, and the boot ROM 110d. And at least a transmission unit 550. A predetermined clock signal output from a clock pulse generation circuit (not shown) is input to each component of the main controller 110. Each component of the main control unit 110 is connected by an internal bus 400.

  The internal bus 400 includes at least a data bus 400a, an address bus 400b, and a control bus 400c as shown in FIG. The internal bus 400 controls the allocation of data passing on the bus based on the control signal sent from each component of the main control unit 110 so as not to cause data collision. It is possible to send and receive signals.

  The data bus 400a of the internal bus 400 may be a bus having a bit width equal to or greater than the data length of the smaller one of the control command and the error check value. For example, if the control command is data of 2 bytes and the error check value is data of 1 byte, the bit width of the data bus 400a may be at least 1 byte. In this case, the main CPU 110a first outputs the upper 1 byte of the 2-byte control command to the data bus 400a, and then outputs the lower 1 byte to the data bus 400a. Subsequently, the check value generation unit 500 outputs a 1-byte error check value to the data bus 400a. The bus standard for the internal bus 400 may be a known standard.

  The main CPU 110a executes the process related to the game progress as described above, and also executes the authentication process of the main control unit 110. The main CPU 110a executes various arithmetic processes using an authentication processing program and various fixed data stored in the main ROM 110b. Further, the main CPU 110a executes various arithmetic processes using a boot processing program stored in the boot ROM 110d and various initial values stored in the main ROM 110b. Then, the main CPU 110a performs a process of sending control signals and control commands to the internal bus 400 according to the results of these arithmetic processes.

  For example, the main CPU 110a sends data to be sent to the data bus 400a of the internal bus 400 when performing data transmission / reception with each component of the main control unit 110 connected via the internal bus 400. Then, address data designating the destination component is sent to the address bus 400b, and a control signal is sent to the control bus 400c. As shown in the memory map of FIG. 6A, the address data is defined in advance so that each component of the main control unit 110 can be uniquely specified. Then, the address data is converted into a chip select signal via the decoder and input to the component of the main control unit 110 specified by the address data. In the main control unit 110 to which the chip select signal is input, the transmitted data is fetched from the data bus 400a or the data to be held is sent to the data bus 400a according to the contents of the control signal. be able to. In the present embodiment, a data transmission / reception method via the internal bus 400 performed between the components of the main control unit 110 is referred to as a “CPU interface method”.

  Further, when performing the command transmission process, the main CPU 110a controls the address data specifying the control command to the data bus 400a of the internal bus 400 and the transmission unit 550 (specifically, a transmission buffer 551 to be described later) to the address bus 400b. A control signal (hereinafter referred to as “write signal”) for writing a control command to the bus 400c is transmitted. Address data designating the transmission unit 550 is converted into a chip select signal via the decoder and input to the transmission unit 550. When the chip select signal and the write signal become active, the transmission unit 550 can take in a control command on the data bus 400a. In the present embodiment, the activation of a control signal such as a chip select signal or a write signal is also referred to as “control signal input”. Further, the address data is converted into a chip select signal and then input to each component of the designated main control unit 110, and description of the conversion from the address data into the chip select signal is omitted.

  Further, when performing the command transmission process, the main CPU 110a calls the authentication processing program according to the timing specified in the game processing program, and checks the error for the control command to be transmitted based on the called program. A process of adding a value (hereinafter referred to as “inspection value adding process”) is performed. Specifically, when it is time to execute the test value addition process during the command transmission process, the main CPU 110a sends a test value generation unit 500 (specifically, a generation unit 520 to be described later) to the address bus 400b of the internal bus 400. The address data specifying the circuit 527) and a control signal (hereinafter referred to as “read signal”) for reading the error check value are sent to the control bus 400c. When the designated address data (chip select signal) and read signal are input, the test value generation unit 500 sends the error check value generated in advance to the data bus 400a. Then, the main CPU 110a takes in the error check value from the data bus 400a and acquires the error check value to be added. Then, the main CPU 110a sends an error check value to the data bus 400a, address data designating the transmission unit 550 to the address bus 400b, and a write signal for writing the error check value to the control bus 400c.

  In the main ROM 110b, as shown in FIG. 6B, in addition to the game processing program and data as described above, an authentication processing program for the main CPU 110a to execute authentication processing in the gaming machine 1 is stored in advance. Has been. In the game processing program, an instruction for calling the authentication processing program is described at the timing when the main CPU 110a executes the test value addition processing during the command transmission processing. In the authentication processing program, an instruction for the main CPU 110a to execute the inspection value addition processing is described. Specifically, in the authentication processing program, an instruction for reading an error check value from the check value generation unit 500 and an instruction for writing the read error check value to the transmission unit 550 are described.

  In this embodiment, the command transmission process is basically executed as a timer interrupt process of the main control unit 110 as will be described later, and the program code related to the timer interrupt process is described in the game processing program. ing. In the present embodiment, in the game processing program, the timing for executing the authentication processing program call instruction is defined to be performed within the execution period of the timer interrupt processing, and is previously determined with the intermediate control unit 180. Basically it is optional if agreed.

  In other words, in the present embodiment, the timing at which the main CPU 110a executes the test value addition processing is performed by adding an authentication processing program calling instruction to the program code related to the command transmission processing in the game processing program. It is prescribed by For this reason, the game machine manufacturer can specify the timing of adding the error check value to the control command simply by adding the calling instruction of the authentication processing program to the desired position of the game processing program, so that the design freedom A high-level authentication function can be added relatively easily. In addition, since the gaming machine manufacturer can change the correspondence between the control command and the error check value added thereto simply by customizing the position where the calling instruction for the authentication processing program is described, the gaming machine 1 Security strength can be flexibly changed.

  If dummy data having the same data length as that of the error check value is prepared and the dummy data is added to the control command instead of the error check value, the intermediate control unit 180 can be used when no error check value is added. The transmission data to be transmitted is transmission data having the same data length as that when the error check value is added. For this reason, it is difficult for an unauthorized person to analyze the timing at which the error check value is transmitted to the intermediate control unit 180, and it is difficult to steal the error check value. For this reason, it becomes difficult to analyze the correspondence between the control command and the error check value added thereto, and the security strength of the gaming machine 1 can be improved.

  When the check value addition process is executed within the execution period of the timer interrupt process, an error check value is written immediately after the control command written to the transmission unit 550 for each execution period. For this reason, on the transmission unit 550 side, the error check value is written continuously to the control command, and the error check value is added immediately after the control command. As a result, the transmission unit 550 can transmit the control command and the error check value to the intermediate control unit 180 as a series of transmission data (a control command to which the error check value is added).

  The main ROM 110b stores unique information of the gaming machine 1 that is used as an error check value added to a control command that is output for the first time after the main control unit 110 is initialized. The unique information is not particularly limited as long as it is unique to the gaming machine 1 held by the main control unit 110. In FIG. 6B, the unique information is a part of the fixed data in the main ROM 110b. For example, the unique information is specific to the checksum value at a specific address in the area where the program code is stored or the main CPU 110a. An identification number (ID) given to the product, product information such as a manufacturer code and a model code, and the like can be used. In addition, the unique information can be dummy data of an error check value that is negotiated with the intermediate control unit 180 in advance. These data may be values obtained by performing four arithmetic operations or logical operations. The unique information may be stored in storage means (memory cell, ROM, etc.) separate from the main ROM 110b.

  In the present embodiment, in the current command transmission process, the control command used by the check value generation unit 500 to generate the error check value is a control command transmitted N times before the control command. The inspection value generation unit 500 stores at least N control commands in a storage circuit 522 described later as control commands transmitted in the past. However, since the past control command stored in the storage circuit 522 is cleared when the main control unit 110 is initialized as when the gaming machine 1 is reset, an error check value is generated using this. Can not do it. Therefore, in the present embodiment, when the past control command stored in the storage circuit 522 is cleared, unique information stored in advance in the main ROM 110b is used as an initial setting value for the storage circuit 522. . In the present embodiment, at least N pieces of unique information are stored in the main ROM 110b as unique information. In the present embodiment, an error check value generated using unique information without using a control command is also referred to as an “initial check value”.

  The main ROM 110b also stores initial values (so-called hardware) that are set for the built-in registers and peripheral circuits of the main CPU 110a during the boot process of the main control unit 110 that is performed when the gaming machine 1 is reset such as when the power is turned on. Wear parameter) is stored in advance. In the present embodiment, one of the initial values that is set in the inspection value generation unit 500 is referred to as “HW parameter”.

  A plurality of HW parameters are prepared in advance in association with a plurality of error check value generation functions of the check value generation unit 500, respectively. In the boot process of the main control unit 110, when the main CPU 110a sets the HW parameter in the check value generation unit 500, the error check value generation function corresponding to the set HW parameter becomes effective in the check value generation unit 500. . That is, the HW parameter is selection information for selecting which error check value generation function the main CPU 110a adopts. In FIG. 6B, the area for storing the initial value and the HW parameter is an area in the main ROM 110b. However, the present invention is not limited to this, and the area is stored in a memory cell separate from the main ROM 110b. It can also be configured to store in the boot ROM 110d. That is, in the present invention, the storage area for the initial value and the HW parameter and the storage area for the game processing program, fixed data, etc. may be mounted on the same storage means (memory cell, ROM, etc.). It may be mounted on different storage means.

  As shown in FIG. 6C, the boot ROM 110d stores in advance a boot processing program and fixed data used when the boot processing program is executed. The boot processing program is set in advance to be read from the boot ROM 110d into a boot processing dedicated RAM (not shown) immediately after the main CPU 110a is started, and to be executed by the main CPU 110a. Controls diagnosis processing, initialization of built-in registers and peripheral circuits of the main CPU 110a (including the test value generation unit 500) and setting processing of initial values (including HW parameters) (hereinafter referred to as “initial value setting processing”). Is. In the present embodiment, a program other than the boot processing program such as a game processing program and an authentication processing program executed after the boot processing is referred to as a “user program”.

  The boot processing program is a program developed and implemented by a CPU manufacturer, and access to the boot ROM 110d in which these programs are stored is limited to access from the main CPU 110a during boot processing after the gaming machine 1 is shipped. . On the other hand, the user program is a program developed and implemented by a gaming machine manufacturer, and access to the main ROM 110b in which these are stored is accessed from the main CPU 110a every time a game process is executed.

  However, even in the storage area of the main ROM 110b, a storage area (such as an area in which the initial value or HW parameter is stored) other than an area in which a user program, fixed data, or the like (including unique information) is stored is a boot processing program. This area is defined only in the game area and does not appear at all on the user program related to the game process. That is, the storage area other than the area where the user program, fixed data, and the like are stored is an area that is substantially restricted so that it cannot be accessed from the user program after the boot process is completed.

  However, in consideration of the case where unauthorized access is attempted, the following additional access restriction is applied, so that the confidentiality of the HW parameter obtained only during the boot process can be further improved. For example, in order to restrict access to the boot ROM 110d and the main ROM 110b, an execution address monitoring unit (not shown) is provided in the main control unit 110, and the execution address monitoring unit is activated after the boot process is completed. If an attempt is made to access an area exceeding the range, a reset signal may be output to the main CPU 110a to put the main CPU 110a in an operation stop state. Further, a notification signal indicating that an abnormality has been detected may be output before the reset signal is output.

  A plurality of methods are conceivable for mounting the HW parameters in the main ROM 110b. For example, a plurality of HW parameters corresponding to each of a plurality of error check value generation functions prepared in advance in the check value generation unit 500 are prepared in advance and mounted in the main ROM 110b. In the initial value setting process, a program for selecting which HW parameter to use is installed in the boot ROM 110d, and any error check value generation function is arbitrarily selected for each boot process. It can be configured to be able to. When implemented in this manner, the error check value generation function is changed every time the boot process is performed, the confidentiality of the error check value generation function can be improved, and the security strength of the gaming machine 1 can be improved.

  On the other hand, although a plurality of error check value generation functions of the check value generation unit 500 are prepared in advance, only a specific HW parameter is mounted on the main ROM 110b, and only a specific error check value generation function corresponding to this is adopted. It can also be configured. When implemented in this way, it is not necessary to newly provide a program associated with the HW parameter selection process in the boot process, and the code size of the program is not increased. In addition, when implemented in this way, even if the gaming machine manufacturer wants to adopt only a specific error check value generation function, the HW corresponding to the desired error check value generation function in the program implementation process performed by the gaming machine manufacturer. Only the parameters need be mounted on the main ROM 110b, and the usage and preference of the gaming machine manufacturer can be flexibly dealt with.

  Even in this case, since the HW parameter is stored in a storage area that is not accessed except when the initial value is set during the boot process of the main control unit 110, the contents of the error check value generation function are known from the outside. I can't. For this reason, it is difficult for an unauthorized person to analyze the error check value generation function employed in the gaming machine 1, and the confidentiality of the error check value generation function of the gaming machine 1 is ensured. In addition, by changing the HW parameters used for design / verification work during the development stage of the gaming machine 1 and the HW parameters that are actually mounted thereafter, it is possible to know which HW parameters are finally mounted. The person who obtains it is limited, and the confidentiality of the error check value generation function is further improved. In the present embodiment, description will be made assuming that only a specific HW parameter corresponding to a specific error check value generation function is mounted in the main ROM 110b.

  The main RAM 110c functions as a data work area at the time of arithmetic processing of the main CPU 110a, and also has a storage area for authentication processing in addition to a plurality of storage areas for executing processing related to game progress as described above. . Specifically, the main RAM 110c stores the number of control commands generated by the main CPU 110a each time a command transmission process is performed, and the generated control commands transmitted to the transmission unit 550 (hereinafter referred to as “transmission number”). It has a sending number storage area (P). The number of transmissions (P; a positive integer) indicates how many control commands have been generated and sent to the transmission unit 550 immediately after the main control unit 110 is initialized, such as when the gaming machine 1 is reset. Is a value indicating

  The value P of the number to be sent may be counted by a known counter circuit or the like, and the main CPU 110a updates the value in the sending number storage area (P) by adding 1 at the time of command transmission processing. When the main control unit 110 is initialized, the control command stored in the storage circuit 522 of the test value generation unit 500 is cleared. Therefore, the main CPU 110a refers to the value of the transmission number storage area (P) of the main RAM 110c during the command transmission process, and the value of the transmission number storage area (P) is a value immediately after initialization (for example, P = 1). ), It is determined that it is necessary to set unique information in the storage circuit 522 immediately after the control command stored in the storage circuit 522 is cleared. Then, the main CPU 110a reads unique information from the main ROM 110b and sets the unique information in the storage circuit 522 as an initial setting value.

  The transmission unit 550 has a function of transmitting a control command or error check value sent from the main CPU 110a to the intermediate control unit 180, and includes at least a transmission buffer 551 and a transmission circuit 552. The transmission buffer 551 is a buffer circuit for temporarily holding data to be transmitted to the intermediate control unit 180. The transmission circuit 552 converts data to be transmitted to the intermediate control unit 180 into a data format corresponding to a data transmission format (serial transmission format or parallel transmission format) between the main control unit 110 and the intermediate control unit 180. It has functions.

  The transmission unit 550 includes a write signal for writing data (control command or error check value) transmitted from the main CPU 110a via the internal bus 400 to the transmission unit 550 (specifically, the transmission buffer 551), and a transmission unit When address data specifying 550 is input, the transmission data is taken into the transmission buffer 551 from the data bus 400 a of the internal bus 400. Then, the transmission unit 550 immediately transfers the data fetched into the transmission buffer 551 to the transmission circuit 552. Then, the transmission unit 550 performs the data format conversion process on the data transferred to the transmission circuit 552 to generate transmission data, and immediately transmits the transmission data to the intermediate control unit 180.

  The check value generation unit 500 is a circuit having an error check value generation function provided as a peripheral circuit of the main CPU 110a. The check value generation unit 500 is connected to the internal bus 400, acquires a control command sent from the main CPU 110a to the transmission unit 550 from the internal bus 400, and generates an error check value using the acquired control command. Then, when the error check value read signal is input from the main CPU 110a, the check value generation unit 500 sends the error check value to the main CPU 110a.

  Specifically, the test value generation unit 500 includes an acquisition unit 510 to which the same address as the address that designates the transmission unit 550 is assigned. When the main CPU 110a performs the command transmission process, when address data specifying the transmission unit 550 is sent to the address bus 400b of the internal bus 400 and a write signal is sent to the control bus 400c, the address data and the write signal are Also input to the acquisition means 510.

  Then, when the address data and the write signal are input, the test value generation unit 500 takes in the control command from the data bus 400a and acquires the control command. Then, when the check value generation unit 500 generates an error check value using the acquired control command, the check value generation unit 500 stores the error check value. Then, when the main CPU 110a performs the test value addition process during the command transmission process, the test value generation unit 500 adds the test value generation unit 500 (details of the generation unit 520 described later in detail) to the address bus 400b of the internal bus 400. When a read signal is sent to the address data specifying the sending circuit 527) and the control bus 400c, the stored error check value is sent to the data bus 400a.

  As shown in FIG. 5, the inspection value generation unit 500 includes at least an acquisition unit 510, a determination unit 540, and a generation unit 520. These units constituting the inspection value generation unit 500 are wired logic control methods. And generates an error check value without receiving an instruction from the main CPU 110a. In the present embodiment, data transmission / reception between each means in the test value generation unit 500 and between each circuit in each means is performed in synchronization with the clock signal output from the clock pulse generation circuit of the main control unit 110. . In the present embodiment, the input / output control method of each means and each circuit in the test value generation unit 500 is referred to as a “synchronous interface method”. In the synchronous interface method, when an enable signal or the like is output to a connection destination of data to be output, the connection destination takes in the output data based on inputs of the enable signal and the clock signal. The synchronous interface method is different from the CPU interface method, which is a method for data transmission / reception via the internal bus 400 performed between the components of the main control unit 110.

[Configuration of inspection value generator]
Hereafter, the test value generation unit 500 having an error check value generation function provided for realizing the authentication function for the main control unit 110 will be described.
First, an outline of the error check value generation function of the check value generation unit 500 will be described.

  The test value generation unit 500 acquires the control command sent from the main CPU 110 a to the transmission unit 550 in the current command transmission process from the internal bus 400. Then, the test value generation unit 500 stores the control command acquired this time in the storage circuit 522, and checks the error using the control command acquired N times before the acquired control command and stored in the storage circuit 522. Generate a value.

  Here, in the present embodiment, the control command sent in the current command transmission process is the control command (P), and the control command sent N times before the control command (P) is the control command (PN). ). That is, in the present embodiment, the control command (1) means a control command that is first transmitted immediately after the main control unit 110 is initialized, and the control command (P) is Pth after the initialization. Means the control command sent to. In the present embodiment, the error check value generated using the control command (PN) is set as the error check value (PN).

  The value of N is a value indicating the number of previous control commands sent in response to the control command sent in the current command sending process to generate an error check value (hereinafter, N is "Retrospective number"). The possible range of the retroactive number N is limited by the storage capacity of the storage circuit 522 (and the storage unit 622 to be described later of the intermediate control unit 180) that stores the past control commands. Is optional. If the value of N is large, it becomes more difficult for an unauthorized person to analyze the relationship between a control command and an error check value added to the control command, and illegal acts can be further prevented.

  The check value generation unit 500 generates an error check value (PN) using the control command (PN), and then performs a bit operation on the bit string of the generated error check value (PN). And processing for appropriately converting the bit string of the error check value (PN) (hereinafter referred to as “bit string conversion process”). In the present embodiment, when performing bit string conversion processing on the error check value (PN), a bit operation method (hereinafter referred to as “conversion method”) performed on the bit string of the error check value (PN). As a method, a bit rotation operation is performed on the bit string of the error check value (PN) to convert the bit string.

  In addition, in the check value generation unit 500, a plurality of conversion methods are prepared in advance as conversion methods when performing bit string conversion processing on the error check value (PN). The number of conversion methods prepared in advance is not particularly limited in the present invention, but in this embodiment, two conversion methods are prepared in advance. Specifically, in this embodiment, in a bit rotation operation performed in one bit string conversion process, a method of determining a “shift amount” that indicates how many bits each bit constituting the bit string is shifted. Accordingly, two conversion methods are prepared in advance.

  More specifically, a conversion method (hereinafter referred to as “conversion method A”) in which the shift amount regularly varies according to a rule determined in advance with the intermediate control unit 180, and the shift amount is determined in advance by the intermediate control unit. There are two conversion methods, namely, a conversion method that is not negotiated with 180 and changes randomly (hereinafter referred to as “conversion method B”). In the present embodiment, the shift amount used in the bit rotation operation when performing the bit string conversion processing by the conversion method A is referred to as “shift amount A”, and is used in the bit rotation operation when performing the bit sequence conversion processing by the conversion method B. The shift amount is referred to as “shift amount B”.

  Then, the check value generation unit 500 performs bit string conversion processing on the error check value (PN) while properly using the two conversion methods prepared in advance as appropriate. Specifically, it is determined that one of conversion method A and conversion method B is used as the default conversion method. Then, when the test value generation unit 500 acquires the control command (P) sent from the main CPU 110a in the current command transmission process, the inspection value generation unit 500 determines a predetermined conversion method change rule (P) based on the acquired control command (P). Hereinafter, the conversion method set up to the present is changed to a new conversion method in accordance with “change protocol”.

  In the present embodiment, the determination unit 540 described later determines the conversion method used in the bit string conversion process. However, the determination unit 540 determines the conversion method, and the bit string conversion process is performed using the determined conversion method. A process for setting the generation unit 520 described later is referred to as a “conversion method setting process”. In addition, a condition for the control command (P) sent to the transmission unit 550 in the current command transmission process to be a control command for changing the conversion method is referred to as a “change condition”. A plurality of change conditions are prepared in advance.

  In the present embodiment, the generation unit 520 described later updates the shift amount used in the bit rotation calculation when performing the bit string conversion processing. However, the generation unit 520 updates the shift amount, and the updated shift amount is used as a bit. A process for setting a rotate arithmetic unit that bears a bit string conversion circuit 525, which will be described later, so that the rotate calculation is performed is referred to as a “shift amount setting process”. In the shift amount setting process, the shift amount A is appropriately updated in order to change the shift amount A regularly, and the shift amount B is appropriately updated in order to randomly change the shift amount B. In the present embodiment, as conditions for defining at what timing the shift amounts A and B are updated (hereinafter referred to as “update timing conditions”), there are a plurality of update timing conditions related to the shift amount A. Is prepared in advance, and one condition is prepared in advance for the update timing condition related to the shift amount B.

  In the present embodiment, when the bit string conversion process is performed on the error check value (PN) by the conversion method A, the shift amount A used in the conversion method A is reset. Specifically, in this embodiment, when the bit string conversion process is performed by the conversion method A on the error check value (PN) added to the control command (P) sent in the command transmission process this time. If the acquired control command (P) is a control command satisfying a predetermined condition (hereinafter referred to as “reset condition”), a predetermined set value is given to the shift amount A, and the shift amount A is reset to the set value. Set. By resetting the shift amount A, the transition of the regular fluctuation of the shift amount A due to the update so far is once reset. The reset condition of the present embodiment is prepared in advance as a plurality of reset conditions related to the shift amount A, and the reset condition related to the shift amount B is not prepared. I will not.

  As described above, as a specific embodiment of the plurality of error check value generation functions of the check value generation unit 500, in the present embodiment, a plurality of change conditions, a plurality of update timing conditions related to the shift amount A, and the shift amount A plurality of reset conditions according to A are prepared in advance. That is, the type of control command that satisfies the change condition changes depending on which change condition is adopted. When the type of the control command that satisfies the change condition changes, the conversion method used when the bit string conversion process is performed for the error check value added to the control command transmitted at a certain time also changes. As a result, since the bit string of the error check value added to the control command changes depending on which change condition is adopted, a plurality of change conditions are prepared in advance. Furthermore, depending on which update timing condition is adopted, the timing at which the shift amount A when the bit string conversion process is performed in the conversion method A changes, and an error added to a control command transmitted at a certain time For the inspection value, the shift amount used in the bit rotation operation of the conversion method A also changes. As a result, since the bit string of the error check value added to the control command changes depending on which update timing condition is adopted, a plurality of update timing conditions related to the shift amount A are prepared in advance. . In addition, depending on which reset condition is adopted, the change transition of the shift amount A when performing the bit string conversion processing in the conversion method A also changes, and an error check value added to a control command transmitted at a certain time Therefore, the shift amount used in the bit rotation operation of the conversion method A also changes. As a result, since the bit string of the error check value added to the control command changes depending on which reset condition is adopted, a plurality of reset conditions are prepared in advance.

  In this embodiment, a plurality of change conditions are associated with a plurality of HW parameters that are selection information of the error check value generation function, and are stored in advance in the determination unit 540 of the check value generation unit 500. Yes. In the present embodiment, a plurality of update timing conditions related to the shift amount A are associated with a plurality of HW parameters, respectively, and stored in advance in the generation unit 520 of the test value generation unit 500. In the present embodiment, a plurality of reset conditions related to the shift amount A are associated with a plurality of HW parameters, respectively, and stored in advance in the generation unit 520 of the inspection value generation unit 500. When the main CPU 110a sets a specific HW parameter in the test value generation unit 500 during the initial value setting process during the boot process, the test value generation unit 500 confirms the set HW parameter and sets the HW parameter. Corresponding change conditions, update timing conditions, and reset conditions are set as default conditions.

  In the present embodiment, in the setting process performed by the main CPU 110a, even in the initial value setting process during the boot process, a process for setting a specific HW parameter in the test value generation unit 500 is particularly referred to as “HW parameter setting process”. That's it. Further, in the present embodiment, a setting process performed by the inspection value generation unit 500, a default change condition is determined along with the HW parameter setting process, and a determination unit 540 described later that configures the inspection value generation unit 500 is used. The process of setting the determined change condition is referred to as “change condition setting process”. Further, in the present embodiment, it is a setting process performed by the inspection value generation unit 500, and a default update timing condition related to the shift amount A is determined along with the HW parameter setting process, and the inspection value generation unit 500 is configured later. The process of setting the determined update timing condition for the generation unit 520 is referred to as “update timing condition setting process”. Further, in the present embodiment, a setting process performed by the inspection value generation unit 500, which is described later, which determines a default reset condition related to the shift amount A in accordance with the HW parameter setting process and configures the inspection value generation unit 500. A process for setting the determined reset condition for the generation unit 520 is referred to as a “reset condition setting process”.

  Then, the test value generation unit 500 acquires the control command (P) sent from the main CPU 110a to the sending unit 550 in the current command transmission process, and the control value sent N times before the acquired control command (P). An error check value (PN) is generated using the command (PN). Further, the check value generation unit 500 converts the bit string of the error check value (PN) using either the conversion method A or the conversion method B. At this time, if the acquired control command (P) is a control command that satisfies the change condition, the check value generation unit 500 changes the conversion method that has been set up to the present time to a new conversion method, and then checks the error check value. The bit string of (PN) is converted. Further, the check value generation unit 500, the shift amount A used in the bit rotation operation of the conversion method A, and the shift amount B used in the bit rotation operation of the conversion method B are updated appropriately. At this time, if the acquired control command (P) is a control command that satisfies the reset condition related to the shift amount A, the predetermined value is given to the shift amount A that has been updated up to now and shifted. Reset amount A. When a read signal for reading an error check value is input from the main CPU 110a, the check value generation unit 500 sends the error check value (PN) obtained by converting the bit string to the data bus 400a of the internal bus 400. Send it out.

Next, the configuration of the check value generation unit 500 provided to realize the error check value generation function will be described with reference to FIG.
FIG. 7 is a block diagram showing an internal configuration of the inspection value generation unit 500 constituting the main control unit 110.

  The inspection value generation unit 500 includes at least an acquisition unit 510, a determination unit 540, and a generation unit 520. The acquisition unit 510 is a circuit that acquires a control command sent from the main CPU 110 a to the internal bus 400. The generation means 520 is a circuit that generates an error check value using a control command, converts the bit string, and sends it to the internal bus 400. The determining unit 540 is a circuit that controls a conversion method used for bit string conversion of the error check value performed by the generating unit 520.

  The acquisition unit 510 includes a data determination circuit 511 that determines the content of data sent from the main CPU 110 a to the internal bus 400, and a control circuit 512 that controls the operation of the data determination circuit 511. The input side of the data discriminating circuit 511 is connected to the data bus 400a of the internal bus 400, and the output side of the data discriminating circuit 511 is a determination circuit 541 described later of the determining unit 540, a storage circuit 522 of the generating unit 520, and a reset. The determination circuit 528 and the data line are connected to each other. The input side of the control circuit 512 is connected to the address bus 400b and the control bus 400c of the internal bus 400, and the output side of the control circuit 512 is connected to the data discrimination circuit 511 via a control line. The output side of the control circuit 512 is connected to a determination circuit 541 of the determination unit 540 and a control circuit 523 (described later) of the generation unit 520 through control lines.

  During the command transmission process, the main CPU 110a sends data (control command or error check value) to be transmitted to the intermediate control unit 180 by the transmission unit 550 to the data bus 400a of the internal bus 400, and transmits the data to the address bus 400b. 550 is sent to address data for designating, and a write signal to the transmission unit 550 is sent to the control bus 400c. The address data and the write signal are input to the control circuit 512. Based on the input of the write signal, the control circuit 512 is an enable signal (hereinafter referred to as “actuation”) that causes the data determination circuit 511 to capture data transmitted to the data bus 400a (hereinafter referred to as “transmission data”). Output a permission signal). The data discriminating circuit 511 takes in the transmission data from the data bus 400a based on the input of the operation permission signal.

  The data discrimination circuit 511 discriminates whether or not the fetched transmission data is a control command. In the present embodiment, as will be described later with reference to FIG. 9, the control command for the production control unit 120 transmitted from the main control unit 110 includes information on “MODE” in the upper byte and “DATA” in the lower byte. It consists of information. In the example of FIG. 9, “E0H” to “EEH” are assigned to the information of the upper byte “MODE” of the control command, and the 4 bits from the most significant are the same value. Therefore, for example, if the data length of the error check value is the same data length as that of the control command, and the 4 bits from the most significant error check value are different bit patterns from “E0H” to “EEH”, the data discriminating circuit 511 If it is determined whether or not the fetched transmission data is a control command based on whether or not the value from the most significant 4 bits of the fetched transmission data matches the value of the most significant 4 bits of the control command Good. If the data length of the error check value is set to a data length (for example, 1 byte) different from the data length of the control command (2 bytes in the example of FIG. 9), the data discriminating circuit 511 has a data length of the fetched transmission data. Whether or not the fetched transmission data is a control command may be determined based on whether or not it matches the data length of the control command. In any case, the data discrimination circuit 511 discriminates whether or not the bit pattern of the fetched transmission data indicates a control command.

  If the fetched transmission data is a control command, the data determination circuit 511 outputs the transmission data to the determination circuit 541 of the subsequent determination unit 540, the storage circuit 522 of the generation unit 520, and the reset determination circuit 528. On the other hand, if the fetched transmission data is not a control command, the data determination circuit 511 discards the transmission data (error check value) and does not output the transmission data to the determination circuit 541, the storage circuit 522, and the reset determination circuit 528. . Then, the control circuit 512 includes a subsequent determination circuit 541 and a generation unit 520 so that the transmission data (control command) output from the data determination circuit 511 can be input by the determination circuit 541, the storage circuit 522, and the reset determination circuit 528. The operation permission signal is output to the control circuit 523. Note that the timing at which the control circuit 512 outputs each operation permission signal is determined so that each unit operates normally in synchronization with the input of the clock signal, taking into account the operation time of each unit in the test value generation unit 500. The timing is set in advance so that it can be performed.

  In the present embodiment, as described above, does the main CPU 110a need to set unique information in the storage circuit 522 of the generation unit 520 with reference to the value of the transmission number storage area (P) of the main RAM 110c? The acquisition unit 510 may determine whether to provide a transmission number storage area (P) in the acquisition unit 510. For example, when P = 1, the obtaining unit 510 may output a control signal for requesting the main CPU 110a to output unique information, and output the unique information stored in the main ROM 110b. Good.

  In this way, the acquisition unit 510 acquires the transmission data transmitted from the main CPU 110a to the transmission unit 550 from the internal bus 400. If the acquired transmission data is a control command, the determination unit 540 and the generation unit 520 that follow. Output to.

  The determination unit 540 includes at least a determination circuit 541 that determines whether or not the acquired control command is a control command that satisfies the change condition, and a determination circuit 542 that determines a conversion method according to the determination result.

  The determination circuit 541 receives the control command output from the data determination circuit 511 of the acquisition unit 510, executes a determination process as to whether or not the input control command is a control command that satisfies the change condition, and displays the determination result. This circuit notifies the decision circuit 542. The input side of the determination circuit 541 is connected to the determination circuit 542 via a data line, and the change condition corresponding to the HW parameter set from the main CPU 110a is determined from the determination circuit 542 during the change condition setting process during the boot process. When output, the change condition is taken in and set as a default change condition.

  The input side of the determination circuit 541 is connected to the data determination circuit 511 of the acquisition unit 510 via a data line, and is connected to the control circuit 512 of the acquisition unit 510 via a control line. The output side of the determination circuit 541 is connected to the determination circuit 542 through a control line. The determination circuit 541 controls the control command (P) output from the data determination circuit 511 of the acquisition unit 510 based on the input of the operation permission signal output from the control circuit 512 during the command transmission processing after the boot processing. ). Then, the determination circuit 541 compares the bit pattern of the input control command (P) with the bit pattern of the change condition set in advance by the determination circuit 542. Then, the determination circuit 541 compares the input control command (P) with the change condition, and if both match, the control command (P) output from the acquisition unit 510 is a control command that satisfies the change condition. If it is determined that they do not match, it is determined that the control command (P) output from the acquisition unit 510 is not a control command that satisfies the change condition.

  Then, the determination circuit 541 outputs a control signal corresponding to the determination result (hereinafter referred to as “determination result signal”) to the subsequent determination circuit 542. Specifically, if the determination circuit 541 determines that the control command (P) output from the acquisition unit 510 is a control command that satisfies the change condition, a determination result signal indicating that is sent to the determination circuit 542. Output. On the other hand, if the determination circuit 541 determines that the control command (P) output from the acquisition unit 510 is not a control command that satisfies the change condition, the determination circuit 541 outputs a determination result signal indicating that to the determination circuit 542.

  The change condition is basically arbitrary if it is agreed with the intermediate control unit 180 in advance. For example, in this embodiment, it is possible to set various conditions such as whether or not the number of control command inputs (that is, the number P of control command transmissions) output from the acquisition unit 510 is a predetermined number. In the present embodiment, it is set as a change condition whether or not the type of the control command output from the acquisition unit 510 corresponds to a predetermined control command. The changing conditions in this embodiment will be described below.

  Various gaming states that appear as the game progresses are set in the gaming machine 1, and the main control unit 110 performs control processing in various operation modes according to the gaming state. Then, during a predetermined operation mode period, a predetermined control command group corresponding to the operation mode is generated and transmitted to the intermediate control unit 180. At this time, the predetermined control command group includes control commands that can confirm the transition of the operation mode by the main control unit 110 and the intermediate control unit 180, such as a control command indicating the start and end of the operation mode period. Yes.

  For example, as will be described later with reference to FIG. 9, in the operation mode of the jackpot state, an opening designation command indicating the start of various jackpot states (in FIG. 9, a control command whose information of “MODE” is “EBH”) ) And an ending designation command (control command in which “MODE” information is “ECH” in FIG. 9) indicating the end of various jackpot states are respectively generated and transmitted to the intermediate control unit 180. Further, for example, in the operation mode of the short-time gaming state, the short-time operation gaming state designation command (in FIG. 9, the information of “MODE” is “EEH”) in accordance with the transition from the non-short-time gaming state to the short-time gaming state. And a control command whose information of “DATA” is “01H” is generated and transmitted to the intermediate control unit 180. Then, along with the transition from the short-time gaming state to the non-short-time gaming state, the short-time non-operating gaming state designation command (in FIG. 9, “MODE” information is “EEH” and “DATA” information is “00H”. A certain control command) is generated and transmitted to the intermediate control unit 180.

  In this embodiment, during the period of the predetermined operation mode, that is, during the period during which the predetermined control command group is transmitted, the conversion method of the error check value used in the bit string conversion processing is the conversion method B, and the others The conversion method is referred to as conversion method A. Therefore, in this embodiment, the default conversion method is determined as the conversion method A, and the conversion method is changed to the conversion method B at the time of command transmission processing related to the control command generated first in the predetermined control command group. Decide to change. Then, it is determined that the conversion method is returned to the conversion method A in the command transmission process related to the control command generated first after the generation of the predetermined control command group is completed. In other words, in the present embodiment, the type of the control command (P) output from the acquisition unit 510 is the first control command generated in the predetermined control command group, and the generation of the predetermined control command group has been completed. The change condition is whether or not one of the first control commands generated later is applicable. In this manner, in the bit string conversion processing of the present embodiment, the conversion method A is used as the default conversion method, the conversion method B is used when the predetermined operation mode period starts, and the predetermined operation mode is changed. When the period ends, conversion method A is used.

  In the present embodiment, as a type of the predetermined control command group, a control command group that can predict how each control command constituting the control command group will appear during a predetermined operation mode period. Use. By using a control command group in which the appearance of each control command can be predicted, the intermediate control unit 180 side suppresses the number of trials when performing a bit string conversion process on the received error check value (PN). Can do.

  Further, as the type of the predetermined control command group, for example, a control command group having a high appearance frequency can be adopted. In this case, since the period in which the conversion method B is adopted frequently arrives, an error check value that has been subjected to bit string conversion processing with a random shift amount is frequently transmitted. For this reason, it is difficult to analyze the correspondence between the control command and the error check value, and the security strength can be improved. Further, as the type of the predetermined control command group, for example, a control command group with a low appearance frequency can be employed. In this case, since the period of adopting the conversion method B only arrives at a low frequency, the opportunity for stealing the control command and the error check value using the conversion method B is reduced. For this reason, it is difficult for an unauthorized person to steal a control command and an error check value with a sufficient number of samples to analyze the correspondence between the control command and the error check value. It becomes difficult to analyze, and the security strength can be improved.

  The predetermined control command group type may be a single control command group type or a plurality of control command group types. Adopting multiple types of control command groups means that the period for adopting conversion method B increases, so that the correspondence between control commands and error check values becomes more difficult to analyze, and security strength can be improved. it can.

  On the other hand, the determination circuit 542 determines a default change condition according to the HW parameter set from the main CPU 110a, and sets the determination circuit 541 so that the determination circuit 541 executes the determination process according to the determined change condition. It is a circuit which performs. In addition, the determination circuit 542 determines a conversion method according to the determination result signal of the determination circuit 541, and performs a setting to the generation unit 520 so that the generation unit 520 performs the bit string conversion process according to the determined conversion method. It is.

  The input side of the determination circuit 542 is connected to the determination circuit 541 through a control line, and receives the determination result signal output from the determination circuit 541. Although the input side of the determination circuit 542 is omitted in FIG. 7, it is connected to the internal bus 400, and the HW parameter that the main CPU 110 a sets in the determination unit 540 during the HW parameter setting process is transmitted from the data bus 400 a. Can be captured.

  The output side of the determination circuit 542 is connected to the determination circuit 541 through a data line, and is connected to the control circuit 523 of the generation unit 520 through a control line. Then, the determination circuit 542 outputs one of a plurality of change conditions prepared in advance to the determination circuit 541 according to the HW parameter set from the main CPU 110a. In addition, the determination circuit 542 determines a conversion method according to the determination result signal output from the determination circuit 541 and outputs a control signal for setting the determined conversion method to the generation unit 520.

  Specifically, the determination circuit 542 is provided with a data table that shows the correspondence between a plurality of change conditions prepared in advance and a plurality of HW parameters. Then, the determination circuit 542 can uniquely determine a specific change condition based on the captured HW parameter. Then, the determination circuit 542 stores the change condition corresponding to the HW parameter set from the main CPU 110a as the default change condition in the change condition storage area (CC) as the change condition setting process during the boot process. The change condition stored in the change condition storage area (CC) is output to the determination circuit 541.

  The determination circuit 542 generates conversion method information that is information indicating the conversion method determined according to the determination result signal output from the determination circuit 541. The conversion method information may be a value such as an identification number that can identify the conversion methods A and B which are the two conversion methods prepared in advance. The determination circuit 542 is provided with a conversion method information storage area (CM) for storing the conversion method information. (CM).

  In the present embodiment, a specific mode of the conversion method is represented by a plurality of rotate arithmetic units (in FIG. 7, rotate arithmetic units 525a and 525b) provided in a bit string conversion circuit 525 described later of the generation unit 520. ing. Specifically, the conversion method A corresponds to the rotate calculator 525a, and the conversion method B corresponds to the rotate calculator 525b. The determination circuit 542 is provided with a data table that shows the correspondence between the conversion method information and the plurality of rotation calculators.

  The determination circuit 542 stores the conversion method information indicating the default conversion method A in the conversion method information storage area (CM) during the conversion method setting process during the boot process. Then, the determination circuit 542 calculates the error check value that has been subjected to the bit string conversion processing by the rotation calculator 525a corresponding to the default conversion method A based on the value stored in the conversion method information storage area (CM). A control signal (hereinafter referred to as “conversion method control signal”) to be output from the bit string conversion circuit 525 to the adding unit 530 is output to the control circuit 523 of the generation unit 520.

  In the conversion method information storage area (CM), when the conversion method is changed, the value of the conversion method information indicating the conversion method after the change (hereinafter, the value of the conversion method information after the change is “ CM '") is stored. When the conversion circuit is changed in the current command transmission process, the determination circuit 542 refers to the value of the conversion method information storage area (CM) that stores the conversion method information indicating the conversion method after the change. In the command transmission process, the generation unit 520 can grasp the conversion method when the error check value is subjected to the bit string conversion process.

  Further, the determination circuit 542 changes the conversion method according to the conversion method change protocol negotiated with the intermediate control unit 180 in advance in the conversion method setting process after the boot process. Specifically, the determination circuit 542 confirms the determination result signal output from the determination circuit 541 and grasps whether or not the control command (P) output from the acquisition unit 510 is a control command that satisfies the change condition. To do. If the control command (P) output from the acquisition unit 510 is a control command that satisfies the change condition, the determination circuit 542 changes the value of the conversion method information storage area (CM) according to a predetermined change method. That is, the change protocol includes at least the change condition for determining whether or not to change the conversion method and the change method of the conversion method.

  As described above, in the present embodiment, the change condition is such that the control command (P) output from the acquisition unit 510 is generated first in a predetermined control command group, and the predetermined control command group. Whether or not one of the first control commands generated after the generation of is satisfied.

  The conversion method change method is basically arbitrary as long as it is agreed with the intermediate control unit 180 in advance. In this embodiment, two conversion methods A and B are prepared, and the default conversion method is the conversion method A. At this time, for example, every time a control command that satisfies the change condition is output, a method of determining the conversion method from conversion method A → conversion method B and conversion method B → conversion method A can be considered. Further, for example, every time a control command that satisfies the change condition is output, a method of operating a random number generation circuit prepared in advance and determining a conversion method corresponding to the obtained random number value can be considered. However, when using a random number generation circuit, it is necessary to notify the intermediate control unit 180 of the obtained random number value or to prepare a random number generation circuit that operates in synchronization with the random number generation circuit in the intermediate control unit 180 as well. . As the change method negotiated in the present embodiment, a method of determining the conversion method as conversion method A → conversion method B and conversion method B → conversion method A every time a control command that satisfies the change condition is output is adopted. Yes.

  In this way, the determination unit 540 determines whether or not the control command (P) output from the acquisition unit 510 is a control command that satisfies the change condition, and the bit string conversion of the generation unit 520 is performed according to the determination result. Determine the conversion method used in the process. Then, the determination circuit 542 can set the generation unit 520 according to the determined conversion method by outputting the conversion method control signal to the control circuit 523 of the generation unit 520. Therefore, the generation unit 520 converts the bit string of the error check value using the conversion method determined by the determination unit 540.

  The generation unit 520 generates an error check value using the storage circuit 522 that stores the control command output from the acquisition unit 510 and the control command that has been output from the acquisition unit 510 and stored in the storage circuit 522 in the past. A generation circuit 521, a bit string conversion circuit 525 that converts the bit string of the error check value output from the generation circuit 521, a storage circuit 526 that stores the error check value converted from the bit string output from the bit string conversion circuit 525, The input selection circuit 524 that selectively switches the connection between the bit string conversion circuit 525 and the storage circuit 526, and the error check value stored in the storage circuit 526 in accordance with the error check value read signal sent from the main CPU 110a. The control circuit output from the transmission circuit 527 and the acquisition unit 510 to be transmitted to the bus 400 is reset. The operation of each circuit in the generation unit 520 is controlled based on the input of the reset determination circuit 528 that determines whether or not the control command satisfies the default condition and the control signal output from the acquisition unit 510 and the determination unit 540. And a control circuit 523.

  The storage circuit 522 is a circuit that stores the control command output from the acquisition unit 510. The storage circuit 522 is composed of N stages of storage circuits corresponding to at least the retroactive N value. Each storage circuit that bears the storage circuit 522 is connected so as to have a pipeline configuration, and has at least a function of an N-stage shift register (FIFO memory) corresponding to the value of N in the retroactive number. ing.

  In the storage circuit 522, the main CPU 110 a sends to the internal bus 400, the acquisition unit 510 acquires from the internal bus 400, and the control command (P) output to the determination unit 540 and the generation unit 520 in the past. The control command sent by can be stored. Specifically, the storage circuit 522 has N control commands (P-1) to (PN) sent from the main CPU 110a in the past from the control command (P) output from the acquisition unit 510. Control commands can be stored. In the present embodiment, among the storage circuits that bear the storage circuit 522, the storage circuit (P-1) is the first storage circuit, and the storage circuit (PN) is the final storage circuit. Each storage circuit that bears the storage circuit 522 is referred to as a storage circuit (P-1) to a storage circuit (PN).

  The input side of the storage circuit (P-1) at the first stage of the storage circuit 522 is connected to the data discrimination circuit 511 of the acquisition means 510 through a data line. The storage circuits (P-1) to (PN) are connected to the control circuit 523 through control lines. The control circuit 523 sequentially shifts the data stored in the storage circuits (P-1) to (PN) based on the input of the operation permission signal output from the control circuit 512 of the acquisition unit 510. Control signal (hereinafter referred to as “shift processing signal”) for output. The output side of the storage circuit (PN) at the final stage of the storage circuit 522 is connected to the generation circuit 521 through a data line.

  When the shift processing signal is input from the control circuit 523, each of the storage circuits (P-1) to (P-N) sequentially shifts the control commands stored therein to the storage circuit of the next stage and stores the previous stage. Stores control commands shifted from the circuit. At this time, the first-stage storage circuit (P-1) newly takes in and stores the control command (P) output from the data discrimination circuit 511 of the acquisition unit 510 in response to the input of the shift processing signal. Further, the storage circuit (PN) in the final stage shifts the control command (PN) stored therein in accordance with the input of the shift processing signal, and outputs it to the subsequent generation circuit 521.

  The generation circuit 521 operates the control command output from the storage circuit 522 by a predetermined calculation method for error check value generation (hereinafter referred to as “generation method”) to generate an error check value, This is a circuit that outputs the generated error check value to the subsequent bit string conversion circuit 525.

  The input side of the generation circuit 521 is connected to the final storage circuit (PN) of the storage circuit 522 through a data line, and is connected to the control circuit 523 through a control line. The output side of the generation circuit 521 is connected to the bit string conversion circuit 525 through a data line. Then, based on the operation permission signal output from the control circuit 512 of the acquisition unit 510, the control circuit 523 outputs an operation permission signal for inputting a control command to perform arithmetic processing to the generation circuit 521. To do.

  When the operation permission signal is input from the control circuit 523, the generation circuit 521 inputs a control command (PN) that is output along with the shift processing signal to the storage circuit 522 of the control circuit 523. Then, the generation circuit 521 performs arithmetic processing on the input control command (PN) using a preset generation method, and generates an error check value (PN). Then, the generation circuit 521 outputs the generated error check value (PN) to the subsequent bit string conversion circuit 525.

  The generation method is not particularly limited as long as it is agreed with the intermediate control unit 180 in advance. As a generation method, for example, a known method such as a checksum method, a CRC method, an odd parity method, an even parity method, a group count check method, a vertical parity method, a horizontal parity method, or a Hamming code method can be used. Note that the generation circuit 521 can be configured to input and calculate the control command output from the storage circuit 522 as it is, or to input and calculate only a part of the control command output from the storage circuit 522. It can also be configured. For example, the control command is composed of 1-byte “MODE” information and 1-byte “DATA” information as will be described later, but only the “MODE” information of the output control command is input. It can be configured to operate.

  The reset determination circuit 528 receives the control command output from the acquisition unit 510, executes a determination process as to whether or not the input control command is a control command that satisfies the reset condition related to the shift amount A, and the determination result Is notified to the bit string conversion circuit 525.

  Although not shown in FIG. 7, the input side of the reset determination circuit 528 is connected to the internal bus 400, and takes in the HW parameter set by the main CPU 110 a in the generation unit 520 from the data bus 400 a during the HW parameter setting process. be able to. In addition, the reset determination circuit 528 is provided with a data table in which a correspondence relationship between a plurality of reset conditions relating to the shift amount A prepared in advance and a plurality of HW parameters is provided, and a specific reset condition is determined by the captured HW parameters. Can be determined uniquely.

  The reset determination circuit 528 takes in the HW parameter output from the main CPU 110a from the data bus during the HW parameter setting process during the boot process. Then, as a reset condition setting process during the boot process, the reset determination circuit 528 uses a reset condition corresponding to the HW parameter set from the main CPU 110a as a default reset condition related to the shift amount A as a reset condition storage area (RC). Remember it.

  In addition, the input side of the reset determination circuit 528 is connected to the data determination circuit 511 of the acquisition unit 510 via a data line, and is connected to the control circuit 523 via a control line. The output side of the reset determination circuit 528 is connected to a shift amount control unit 525c (described later) of the bit string conversion circuit 525 through a control line. Then, the control circuit 523 operates to input the control command and perform the determination process based on the input of the operation permission signal output from the control circuit 512 of the acquisition unit 510 during the command transmission process after the boot process. An operation permission signal for causing the reset determination circuit 528 to output the operation permission signal.

  When the operation permission signal is output from the control circuit 523, the reset determination circuit 528 inputs the control command (P) output from the data determination circuit 511 of the acquisition unit 510 based on the input of the operation permission signal. . Then, the reset determination circuit 528 compares the bit pattern of the input control command (P) with the bit pattern of the reset condition stored in advance in the reset condition storage area (RC). Then, the reset determination circuit 528 compares the input control command (P) with the reset condition, and if both match, the control command (P) output from the acquisition unit 510 sets the reset condition related to the shift amount A. If it is determined that the control command is satisfied and the two do not match, it is determined that the control command (P) output from the acquisition unit 510 is not a control command that satisfies the reset condition related to the shift amount A.

  When the reset determination circuit 528 determines that the control command (P) output from the acquisition unit 510 is a control command that satisfies the reset condition related to the shift amount A, the reset determination circuit 528 resets the shift amount A. A control signal (hereinafter referred to as “shift amount A reset signal”) is output to the shift amount control unit 525 c of the subsequent bit string conversion circuit 525. Accordingly, the shift amount control unit 525c of the bit string conversion circuit 525 can reset the shift amount A based on the control command (P) output from the acquisition unit 510. On the other hand, when the reset determination circuit 528 determines that the control command (P) output from the acquisition unit 510 is not a control command that satisfies the reset condition related to the shift amount A, the reset amount control unit 525c resets the shift amount A. No signal is output.

  The timing at which the reset determination circuit 528 outputs the shift amount A reset signal is the bit string for the error check value added to the control command (P) to be determined, that is, the control command (P) output from the acquisition means 510. In the conversion process, adjustment is performed in advance so that the shift amount A after resetting is used.

  The reset condition is negotiated with the intermediate control unit 180 in advance, and in the period in which the shift amount A is used, that is, in the period in which the error check value in which the bit string is converted by the conversion method A is added to the control command. It is basically arbitrary as long as the shift amount A is reset and the variation transition of the shift amount A is reset. In the present embodiment, the period during which the error check value obtained by converting the bit string by the conversion method A is added to the control command is a period other than the period of the predetermined operation mode as described above, and other than the predetermined control command group This is a period during which the control command is transmitted. Therefore, the reset condition of the present embodiment is that the control command (P) output from the acquisition unit 510 is a control command determined in advance from control commands other than a predetermined control command group. In this embodiment, it is assumed that a plurality of reset conditions related to the shift amount A are prepared in advance according to the type of control command determined from control commands other than the predetermined control command group.

  Note that the type of control command predetermined as the reset condition of the present embodiment may be one control command type for one reset condition, or may be a plurality of control command types. Employing a plurality of types of control commands means that the number of times that the shift amount A is reset and the variation transition of the shift amount A is reset increases. For this reason, it becomes difficult to analyze the correspondence between the control command and the error check value, and the security strength can be further improved. Even if the shift amount A varies due to a communication error or the like between the main control unit 110 side and the intermediate control unit 180 side, the shift of the shift amount A is reset to eliminate the shift. Since the opportunity increases, the accuracy of the error checking process can be further improved.

  The bit string conversion circuit 525 is a circuit that receives the error check value output from the generation circuit 521 and performs bit string conversion processing on the input error check value. Specifically, the bit string conversion circuit 525 includes a plurality of rotation calculators that perform a bit rotation operation on the bit string of the input error check value, and a shift amount control unit 525c that controls a shift amount used in the bit rotation operation. Is provided.

  The plurality of rotation arithmetic units that carry the bit string conversion circuit 525 perform the bit rotation calculation using the rotation calculation unit 525a that performs the bit rotation calculation using the shift amount A that regularly changes, and the shift amount B that randomly changes. And a rotate calculator 525b. The rotate calculators 525a and 525b are each composed of a shift register or the like having a bit width equivalent to the error check value. The input sides of the rotation calculators 525a and 525b are connected to the generation circuit 521 through data lines, and are connected to the shift amount control unit 525c through control lines, respectively. The output sides of the rotation calculators 525a and 525b are connected to the input selection circuit 524 through data lines. Furthermore, the output side of the rotation calculator 525b is connected to the shift amount control unit 525c via a data line.

  Then, the rotation calculators 525a and 525b input the error check value output along with the operation permission signal to the generation circuit 521 of the control circuit 523, and perform bit rotation operation on the bit string of the input error check value. After that, each calculation result is output to the subsequent input selection circuit 524. At this time, the rotation calculator 525a performs a bit rotation calculation with the shift amount A set by the shift amount control unit 525c, and the rotation calculation unit 525b performs a bit rotation calculation with the shift amount B set by the shift amount control unit 525c. I do.

  In the shift register constituting the rotate arithmetic units 525a and 525b, the output of the last flip-flop of each flip-flop constituting the shift register is fed back and directly connected to the input of the first flip-flop. When each of the bits constituting the bit string of the error check value is input to the rotation calculators 525a and 525b, the shift amounts A and B set by the shift amount control unit 525c are set in synchronization with the clock signal. Shifting is performed in a predetermined direction (hereinafter referred to as “shift direction”) by the number of bits shown. Then, the rotation calculators 525a and 525b feed back the output bits output from the final flip-flop as input bits to the first flip-flop.

  Note that the shift direction is either the direction from the most significant bit of the bit string to the least significant bit or the direction from the least significant bit to the most significant bit. In the present embodiment, the shift direction is basically arbitrary as long as it is determined in advance with the intermediate control unit 180 even if the rotation directions are different in the rotation calculators 525a and 525b.

  On the other hand, during the boot process, the shift amount control unit 525c determines and determines the default update timing condition related to the shift amount A based on the HW parameter set from the main CPU 110a as the update timing condition setting process. Set according to the update timing conditions. Further, during the boot process, the shift amount control unit 525c performs a process of setting predetermined default shift amounts A and B in the rotate computing units 525a and 525b as a shift amount setting process. Further, the shift amount control unit 525c performs error check values obtained by converting the bit string output from the rotation computing unit 525b as the shift amount setting processing in the bit conversion processing performed in the command transmission processing after the boot processing. Based on the above, the shift amounts A and B are updated to new shift amounts A and B as necessary, and the updated shift amounts A and B are set in the rotation calculators 525a and 525b, and the reset determination is performed. Based on the determination result of the circuit 528, the shift amount A is reset.

  The shift amount control unit 525c has a shift amount storage area (S) for storing the shift amounts A and B set in the rotation calculators 525a and 525b, and an update timing condition storage area for storing update timing conditions. (UT). The input side of the shift amount control unit 525c is connected to the rotation calculator 525b via a data line, and is connected to the control circuit 523 via a control line. Further, the output side of the shift amount control unit 525c is connected to the rotation calculators 525a and 525b through control lines. Further, the shift amount control unit 525c is connected to the internal bus 400.

  The default shift amounts A and B are basically arbitrary as long as they are values determined in advance with the intermediate control unit 180, and may be the same or different values between the shift amount A and the shift amount B. It is often stored in a predetermined storage area of the main ROM 110b. During the initial value setting process during the boot process, the main CPU 110a reads the default shift amounts A and B from the main ROM 110b and stores them in the shift amount storage area (S) of the shift amount control unit 525c.

  The shift amount control unit 525c takes in the HW parameter output from the main CPU 110a from the data bus 400a during the HW parameter setting process during the boot process. The shift amount control unit 525c is provided with a data table in which correspondence relationships between a plurality of update timing conditions and a plurality of HW parameters related to a shift amount A prepared in advance are known. Then, the shift amount control unit 525c can uniquely determine a specific update timing condition based on the captured HW parameter. Then, as the update timing condition setting process during the boot process, the shift amount control unit 525c uses the update timing condition corresponding to the HW parameter set from the main CPU 110a as the default update timing condition related to the shift amount A. Store in the storage area (UT). In FIG. 7, only random values are shown for data transmission / reception between the shift amount control unit 525c and the internal bus 400, and the HW parameter is omitted.

  In addition, the control circuit 523 determines the shift amount to be set in the rotation calculator based on the input of the conversion method control signal output from the determination circuit 542 of the determination unit 540 during the conversion method setting process during the boot process. A control signal (hereinafter referred to as “shift amount setting control signal”) to be controlled by the shift amount control unit 525c is output to the shift amount control unit 525c. The shift amount control unit 525c performs a shift amount setting process for the shift amounts A and B based on the input of the shift amount setting control signal output from the control circuit 523. Specifically, the shift amount control unit 525c sets the shift amount A stored in the shift amount storage area (S) in the rotation calculator 525a as the shift amount setting process related to the shift amount A during the boot process. The control signal (hereinafter referred to as “shift amount A setting signal”) is output to the rotation calculator 525a, and the default shift amount A stored in the shift amount storage area (S) is set in the rotation calculator 525a. Further, the shift amount control unit 525c outputs a shift amount B setting signal to the rotate calculator 525b as a shift amount setting process related to the shift amount B during the boot process, and stores the default stored in the shift amount storage area (S). Is set in the rotation calculator 525b.

  As described above, the conversion method of the present embodiment is changed from the conversion method A to the conversion method B by the conversion method setting process of the determination unit 540 when the period of the predetermined operation mode starts. When the processing is completed, the conversion method B is changed to the conversion method A by the conversion method setting process of the determination unit 540. At this time, the shift amount control unit 525c updates the shift amount A used in the bit rotation calculation when performing the bit string conversion processing by the conversion method A (hereinafter referred to as the update method previously determined with the intermediate control unit 180). Update according to the "update method".

  The update method related to the shift amount A is basically arbitrary as long as it is negotiated with the intermediate control unit 180 in advance and the shift amount A varies regularly. For example, a method may be employed in which the shift amount control unit 525c accumulates a predetermined value with respect to the default shift amount A every time the update timing arrives. In addition, the shift amount control unit 525c uses an arithmetic function such as a parity check or checksum provided in an existing game machine for the default shift amount A, and uses the error check value output from the rotate arithmetic unit 525b. A method of calculating and accumulating the obtained results every time the update timing arrives can be adopted. In this case, in the method of accumulating the error check value output from the rotation calculator 525b and the result obtained by using the calculation function provided in the existing gaming machine, a predetermined value that is fixed data is set in advance to the main control unit 110. This is preferable because it is not necessary to hold the data in a static manner and there is no possibility of illegal analysis by a static analysis method.

  Although omitted in FIG. 7, a parity check circuit or the like that realizes an arithmetic function such as a parity check provided in these existing gaming machines is provided in the generation unit 520 according to the arrival of the update timing related to the shift amount A. The value obtained from the parity check circuit or the like can be used. In this case, the update of the shift amount A can be realized only by the internal processing of the generation unit 520 configured by a wired logic control type hardware. For this reason, the processing load and code size of the main control unit 110 that increase with the addition of security functions can be suppressed, which is preferable. In any case, the update method related to the shift amount A is consistent with the intermediate control unit 180, and the shift amount A regularly varies based on the error check value output from the rotation calculator 525b. Any method can be used.

  An update timing condition that defines the update timing is basically arbitrary as long as it is negotiated with the intermediate control unit 180 in advance and the shift amount A is updated so as to change regularly. . For example, the shift amount control unit 525c is connected to the data discriminating circuit 511 of the acquisition unit 510 via a data line, and it is counted whether or not the number P of control commands output from the acquisition unit 510 is a predetermined number. Then, when the number P of control commands output from the acquisition unit 510 exceeds a predetermined number, the shift amount A can be updated by performing the shift amount setting process.

  The update timing condition relating to the shift amount A of the present embodiment is that the shift amount A is regular each time the conversion method set by the conversion method setting process of the determination unit 540 is changed from the conversion method B to the conversion method A. It is assumed that the shift amount A is defined to be updated so as to vary. Specifically, in this embodiment, the period of the predetermined operation mode starts, and the shift amount A is updated while the bit string conversion processing in the conversion method B is performed. After the above is completed, an update timing condition is defined such that the bit string conversion processing in the conversion method A is performed using the updated shift amount A.

  In this case, the update timing condition related to the shift amount A is defined based on the error check value that can be added to the control command after the bit string conversion processing is performed by the conversion method B during the period of the predetermined operation mode. Is basically arbitrary. The error check value that can be added to the control command is stored in the storage circuit 526 via the input selection circuit 524 after the bit string is converted by the conversion method B during the period of the predetermined operation mode, and sent out. This is an error check value that can be output to 527. In the present embodiment, the shift amount A depends on the error check value stored in the storage circuit 526 during the period of the predetermined operation mode according to the error check value stored in the period. It is assumed that a plurality of update timing conditions are prepared in advance. For example, it is defined based on the update timing condition defined based on the error check value first stored in the storage circuit 526 or the error check value stored last in the storage circuit 526 during a predetermined operation mode. It is assumed that a plurality of update timing conditions and a plurality of update timing conditions defined based on the error check value stored in the storage circuit 526 in a predetermined order are prepared.

  Among these, in the present embodiment, during the update timing condition setting process during the boot process, the error first stored in the storage circuit 526 as the update timing condition corresponding to the HW parameter during the period of the predetermined operation mode. An update timing condition defined based on the inspection value is set. That is, in this embodiment, the period of the predetermined operation mode starts after the boot process, and the error check value output from the rotation calculator 525b is shifted to the storage circuit 526 for the first time during the period. The quantity A shall be updated.

  More specifically, when the command transmission process is performed for the first time during the predetermined operation mode period after the boot process, the control circuit 523 of the generation unit 520 includes the determination unit 540. A conversion system control signal is output from the determination circuit 542. The control circuit 523 outputs a shift amount setting control signal to the shift amount control unit 525c based on the input of the conversion method control signal. Based on the input of the shift amount setting control signal output from the control circuit 523, the shift amount control unit 525c can detect that the period of the predetermined operation mode has started.

  For example, a counter circuit that counts the number of times the shift amount setting control signal output from the control circuit 523 is input is provided in the shift amount control unit 525c, and 1 is added each time the shift amount setting control signal is input. . Then, the shift amount control unit 525c detects that the value of the counter circuit or the like has shifted to an even number or an odd number, so that the shift amount control unit 525c detects that the period of the predetermined operation mode has started or ended. can do. For example, if the initial value of the counter circuit or the like is 0 and 1 is added by the shift amount setting control signal output by the conversion method setting process during the boot process, the value of the counter circuit or the like transitions to an even number. Then, it indicates that the period of the predetermined operation mode has started, and then when the value of the counter circuit or the like transitions to an odd number, it indicates that the period of the predetermined operation mode has ended. Therefore, the shift amount control unit 525c detects that the period of the predetermined operation mode has started or ended based on the input of the shift amount setting control signal, and determines whether or not the current period is in the period of the predetermined operation mode. Can be judged. That is, the shift amount control unit 525c can determine the update timing of the shift amounts A and B based on the input of the shift amount setting control signal.

  When the shift amount control unit 525c detects that the period of the predetermined operation mode has started, it performs a shift amount setting process to update the shift amount A. That is, the shift amount control unit 525c performs the shift amount setting process related to the shift amount A based on the error check value output from the rotate computing unit 525b and the shift amount A stored in the shift amount storage area (S). The value is updated according to a predetermined update method related to the shift amount A. Then, the shift amount control unit 525c outputs a shift amount A setting signal to the rotate calculator 525a, and sets the updated shift amount A stored in the shift amount storage area (S) in the rotate calculator 525a.

  Note that during the subsequent period of the predetermined operation mode, an error check value is output from the rotate computing unit 525b to the shift amount control unit 525c, but the error check value is the first in the period of the predetermined operation mode. Therefore, the update timing condition for the shift amount A is not satisfied, and the shift amount A is not updated. Thereafter, after the period of the predetermined operation mode ends, the error check value obtained by converting the bit string by the bit rotation operation using the shift amount A is output to the storage circuit 526, and then the predetermined operation mode period again. When the conversion method control signal is output from the determination unit 540, the shift amount control unit 525c updates the shift amount A again as described above.

  Note that during the period when the period of the predetermined operation mode ends and the error check value in which the bit string is converted by the bit rotation operation using the shift amount A is output to the storage circuit 526, the shift amount control unit 525c includes The shift amount A reset signal is input from the reset determination circuit 528. The shift amount control unit 525c resets the shift amount A based on the input of the shift amount A reset signal output from the reset determination circuit 528 during the period. Specifically, based on the input of the shift amount A reset signal, the shift amount control unit 525c overwrites a predetermined set value prepared in advance on the shift amount A stored in the shift amount storage area (S). Remember. Then, the shift amount control unit 525c outputs a shift amount A setting signal to the rotate calculator 525a, and sets the overwritten shift amount A stored in the shift amount storage area (S) in the rotate calculator 525a.

  The predetermined set value prepared in advance in the shift amount control unit 525c is basically arbitrary as long as it is negotiated with the intermediate control unit 180 in advance. The set value may be the same value as the default shift amount A, or may be a different value, and may be stored in advance in a predetermined storage area of the main ROM 110b. Then, in the initial value setting process during the boot process, the main CPU 110a may read the set value from the main ROM 110b and store it in a predetermined storage area of the shift amount control unit 525c.

  On the other hand, the shift amount B is not negotiated with the intermediate control unit 180 in advance, and is set to a value that varies randomly. The update method related to the shift amount B is not a method in which the shift amount varies regularly like the shift amount A, but a method in which a random value is used for the shift amount B. As this random number value, a special symbol determination random number value or a jackpot symbol random number value provided in an existing gaming machine stored in a predetermined random number value storage area of the main RAM 110c can be used. In this case, it is not necessary to newly provide a random number generation circuit in the inspection value generation unit 500, and the circuit configuration of the inspection value generation unit 500 can be relatively simplified.

  Although the random number value is omitted in FIG. 7, a random number generation circuit provided in the existing gaming machine is provided in the generation unit 520 and is acquired from the random number generation circuit when the update timing related to the shift amount B arrives. This value can be used as the value of the shift amount B. In this case, the update of the shift amount B can be realized only by the internal processing of the generation unit 520 configured with a wired logic control type hardware. For this reason, it is possible to suppress the processing load and code size of the main control unit 110 that increase as security functions are added, which is preferable. In any case, the random number value used as the update method of the shift amount B is not a value negotiated with the intermediate control unit 180. It is sufficient that it does not operate in synchronization with the random number generation circuit provided in the unit 180.

  Further, the update timing condition related to the shift amount B in the present embodiment is that a period of a predetermined operation mode starts, and an error check value subjected to bit string conversion processing by the conversion method B can be added to the control command. It is assumed that the shift amount B is updated every time. That is, each time the error check value that has been subjected to the bit string conversion processing by the conversion method B is stored in the storage circuit 526 via the input selection circuit 524 and can be output to the transmission circuit 527, the shift amount B is updated. It is prescribed as follows.

  More specifically, when a command transmission process is performed for the first time during the start of a predetermined operation mode period, the control circuit 523 inputs the conversion method control signal output from the determination unit 540. The shift amount setting control signal is output to the shift amount control unit 525c based on the above. Based on the input of the shift amount setting control signal output from the control circuit 523, the shift amount control unit 525c can detect that the period of the predetermined operation mode has started.

  When the shift amount control unit 525c detects that the period of the predetermined operation mode has started, it performs a shift amount setting process to update the shift amount B. That is, the shift amount control unit 525c performs the shift stored in the shift amount storage area (S) every time the error check value output from the rotation calculator 525b is input as the shift amount setting process related to the shift amount B. The value of the amount B is updated according to a predetermined update method related to the shift amount B. Then, the shift amount control unit 525c outputs a shift amount B setting signal to the rotate calculator 525b, and sets the updated shift amount B stored in the shift amount storage area (S) in the rotate calculator 525b. The updated shift amount B is reflected when the rotation calculator 525b performs a bit rotation calculation in the next command transmission process performed during the period of the predetermined operation mode.

  During the subsequent predetermined operation mode, the control circuit 523 does not output the shift amount setting control signal to the shift amount control unit 525c because the conversion method control signal is not output, but is output from the rotation calculator 525b. The error check value is output to the storage circuit 526 and input to the shift amount control unit 525c each time. For this reason, the shift amount control unit 525c only needs to acquire a new random value and update the shift amount B each time based on the input of the error check value output from the rotation calculator 525b.

  When the predetermined operation mode period ends, the control circuit 523 outputs a shift amount setting control signal to the shift amount control unit 525c based on the input of the conversion method control signal. Based on the input of the shift amount setting control signal output from the control circuit 523, the shift amount control unit 525c can detect that the period of the predetermined operation mode has ended.

  When the shift amount control unit 525c detects that the period of the predetermined operation mode has ended, it is not necessary to perform the shift amount setting process. That is, the shift amount control unit 525c only needs to discard the error check value output from the rotation calculator 525b, and does not need to update the shift amount B. After that, after the error check value in which the bit string is converted by the bit rotation operation using the shift amount A is output to the storage circuit 526, if the predetermined operation mode period starts again, the shift amount control unit 525c The shift amount B is updated again as follows.

  Note that the shift amount control unit 525c may update the shift amount B even after the period of the predetermined operation mode ends, but as an update method related to the shift amount B, the shift amount control unit 525c stores the random amount value storage area of the main RAM 110c. When the stored random number value is used, unnecessary processing related to data transmission / reception of the random number value occurs with the main CPU 110a. In this case, since an extra processing load is applied to the main CPU 110a, it is preferable not to update the shift amount B when it is detected that the period of the predetermined operation mode has ended. Further, as a method for updating the shift amount B, if a random number value is acquired by a random number generation circuit provided in the generation unit 520, processing related to data transmission / reception of the random value does not occur. Regardless of whether or not to update, the load on the main CPU 110a is minimized. In addition, when designing the update timing condition related to the shift amount B, the degree of freedom in design is not restricted by considering the load on the main CPU 110a, which is preferable.

  In this way, the shift amount A is updated based on a predetermined update method and update timing conditions that have been negotiated with the intermediate control unit 180 in advance and fluctuates regularly. On the other hand, the shift amount B is updated with a random value that has not been negotiated with the intermediate control unit 180 in advance, and varies randomly. For this reason, in the rotation calculator 525b that performs the bit rotation operation using the shift amount B, “rotate” indicating how many positions of the respective bits constituting the bit string have moved as a result before and after one bit string conversion process. The “number” also varies randomly.

  However, in the rotate computing unit 525b, the shift amount B is randomly varied for each bit string conversion process, but each bit is only regularly shifted in one bit string conversion process. The combination of the values of each bit does not change every time. Therefore, if the bit rotation operation is performed a plurality of times on the intermediate control unit 180 side, the bit string can be restored to the bit string of the error check value (hereinafter referred to as “original error check value”) that has not been converted. The number of rotations indicates how many bits have moved as a result of the position of each bit constituting the bit string before and after one bit string conversion process. For this reason, the possible range of the rotation number is defined by the bit width of the bit string of the error check value.

  For example, when the bit length of the error check value is 1 byte (8 bits), the range that the rotation number can take is an integer of 0 to 8, and if the bit rotation operation is performed at least 8 times, the original error check value It can be converted back to a bit string. Therefore, for example, even if the range of random values used as the shift amount B is 0 to 255, if the bit width of the error check value is 1 byte (8 bits), the bit rotation operation is performed at least 8 times. It is possible to return to the bit string of the original error check value only by performing.

  In particular, in the rotation computing unit 525b in which the shift amount B varies randomly, the error check value of the same bit string may be output after the bit string conversion process even if the bit string of the original error check value is different. In general, the fact that an error detection code added to transmission data takes a duplicated value for each transmission data is an event that should be avoided as lowering the reliability of error detection, which is a problem. However, in the present embodiment, even if a duplicate value occurs every bit string conversion, it is possible to return to the original error check value, and the original error check value itself has the reliability of error detection. Must not. Rather, if a duplicate value occurs in each bit string conversion, when an unauthorized person steals multiple control commands and error check values, analyze whether there is regularity regarding shift amount fluctuations or whether the conversion method has changed. This makes it difficult to analyze the correspondence between the control command and the error check value, which is preferable.

  In this way, in the bit string conversion circuit 525, the rotation calculators 525a and 525b using the shift amounts A and B having the above-described configuration with respect to the bit string of the error check value output from the generation circuit 521 during the command transmission process. The bit rotation operation is performed at, and the error check value obtained by converting the bit string is output to the subsequent input selection circuit 524, respectively.

  In the present embodiment, since the bit string conversion circuit 525 is configured by the rotation calculators 525a and 525b that can be realized by a shift register having a relatively simple circuit configuration, after the circuit of the rotation calculator 525a is designed, the circuit data is converted to the circuit data. The rotation calculator 525b can also be used. For this reason, in this embodiment, it is possible to suppress the development man-hours and development difficulty related to circuit design and verification work. That is, in this embodiment, the effect that the correspondence relationship between the control command and the error check value becomes difficult to analyze and the security strength is improved by providing a plurality of conversion methods is smaller than the number of conversion methods provided. It can be obtained simply by designing the computing unit, and a large fraud prevention effect can be obtained with a small development cost.

  In this embodiment, the rotation calculator 525b randomly shifts the shift amount B. Therefore, each bit of the error check value whose bit string is converted by the rotation calculator 525b is irregularly shifted for each bit string conversion process. To do. For this reason, it is difficult for an unauthorized person to analyze how much the bit string is converted by the error check value added to the control command. Therefore, it becomes difficult to analyze the correspondence between the control command and the error check value, and the security strength can be further improved.

  Further, in the present embodiment, the arithmetic unit in which the shift amount varies randomly is only the rotate arithmetic unit 525b. Further, even when the error check value obtained by converting the bit string by the rotate computing unit 525b is added to the control command and transmitted to the intermediate control unit 180, it is also during a predetermined operation mode period, that is, a predetermined control command group. Is limited to a period during which is transmitted to the intermediate control unit 180. Therefore, when returning to the original error check value bit string in the error check process on the intermediate control unit 180 side, the tendency that the number of trials of the bit string conversion process increases by changing the shift amount at random is maximized. Can be suppressed.

  In this embodiment, the shift amount A used in the rotation calculator 525a is regularly changed. Specifically, in the present embodiment, the rotation is performed even during a period other than the period in which the error check value whose bit string has been converted by the rotation calculator 525b is added to the control command, that is, during a period other than the predetermined operation mode period. The shift amount A used in the computing unit 525a is changed every period other than the period of the predetermined operation mode. For this reason, in this embodiment, an unauthorized person transmits a bit string converted by the error check value added to the control command in a period other than the predetermined operation mode period. This also makes it difficult to perform the error check value, and can further improve the security strength.

  Further, in the rotate computing unit 525a, the regularity regarding the update of the shift amount A depends on the update method and the update timing condition related to the shift amount A, and the update timing condition is set to an initial value at the time of boot processing of the main control unit 110. It is determined based on the value of the HW parameter stored in a specific storage area of the main ROM 110b that is not accessed except at times. Therefore, it becomes difficult for an unauthorized person to analyze the regularity regarding the update of the shift amount A, and the security strength can be further improved.

  Further, in the rotate computing unit 525a, the regularity related to the update of the shift amount A also depends on the reset condition related to the shift amount A. It is determined based on the value of the HW parameter stored in a specific storage area of the main ROM 110b. Therefore, it becomes difficult for an unauthorized person to analyze the regularity regarding the update of the shift amount A, and the security strength can be further improved.

  In addition, when the reset condition is satisfied, a predetermined set value is given to the shift amount A, the shift amount A is reset, and the change transition of the shift amount A by the update so far is once reset. For this reason, in this embodiment, even if the shift amount A varies between the main control unit 110 and the intermediate control unit 180 due to a communication error or the like, the shift amount A varies due to the resetting of the shift amount A. By resetting the transition, the deviation can be eliminated as appropriate, and the accuracy of the error checking process can be improved.

  The input selection circuit 524 is configured by a multiplexer or the like, and is a circuit having a function of selectively switching connection between the bit string conversion circuit 525 and the storage circuit 526. Specifically, the input side of the input selection circuit 524 is connected to a plurality of rotation arithmetic units (in FIG. 7, the rotation arithmetic units 525a and 525b) that bear the bit string conversion circuit 525 through data lines, and controls the control circuit 523. Connected with wires. The output side of the input selection circuit 524 is connected to the storage circuit 526 through a data line. The input selection circuit 524 is preset so that the connection with the rotation calculator 525a that outputs an error check value that has been subjected to the bit string conversion processing by the conversion method A is enabled, and is output from the rotation calculator 525a. The error check value thus obtained is captured and output to the storage circuit 526.

  The control circuit 523 validates the connection with one of the rotation calculators 525a and 525b of the input selection circuit 524 based on the input of the conversion method control signal output from the determination circuit 542 of the determination unit 540 in the conversion method setting process. A control signal (hereinafter referred to as “input selection signal”) is output to the input selection circuit 524. This input selection signal is valid only for connection with a rotation operator corresponding to the conversion method so that only error check values that have been subjected to bit string conversion processing in the specific conversion method indicated by the conversion method control signal are input. Is a signal for For example, when an input selection signal that validates the connection with the rotation computing unit 525b is input from the control circuit 523, the input selection circuit 524 switches so as to validate only the connection with the rotation computing unit 525b. Then, the input selection circuit 524 takes in the error check value that has been subjected to the bit string conversion processing by the conversion method B output from the rotation calculator 525 b and outputs the error check value to the storage circuit 526.

  The storage circuit 526 includes a register or the like, and stores an error check value obtained by converting the bit string output from the bit string conversion circuit 525. The input side of the storage circuit 526 is connected to the input selection circuit 524 through a data line, and is connected to the transmission circuit 527 through a control line. Further, the output side of the storage circuit 526 is connected to the sending circuit 527 by a data line. The storage circuit 526 stores the error check value obtained by converting the bit string output from the bit string conversion circuit 525 via the input selection circuit 524. Then, when an operation permission signal for outputting the stored error check value to the transmission circuit 527 is input, the storage circuit 526 receives the stored error check value based on the input of the operation permission signal. It outputs to the subsequent sending circuit 527.

  In addition, the storage circuit 526 receives a new error check value from the bit string conversion circuit 525 even when the operation permission signal is not input from the transmission circuit 527 and the error check value is not output to the transmission circuit 527. Sometimes, the new error check value is overwritten and saved, and a new error check value is saved for each command transmission process. Therefore, if the control command output from the acquisition unit 510 in the current command transmission process is a control command (P), the storage circuit 526 generates a bit string using the control command (PN). The error check value (P-N) converted from is stored.

  The sending circuit 527 is a circuit that sends the error check value stored in the storage circuit 526 to the internal bus 400 in accordance with the error check value read signal sent from the main CPU 110a. The sending circuit 527 is connected to the internal bus 400, and the input side of the sending circuit 527 is connected to the storage circuit 526 through a data line. When the main CPU 110a performs the test value addition process during the command transmission process, when the address data specifying the transmission circuit 527 is sent to the address bus 400b of the internal bus 400 and the read signal is sent to the control bus 400c, the transmission circuit 527 outputs the operation permission signal to the storage circuit 526 to fetch the stored error check value, and sends the read error check value to the data bus 400a.

  In this way, the generation unit 520 stores the control command (P) output from the acquisition unit 510 during command transmission processing, and uses the control command (PN) stored in the past to generate an error. A test value (PN) is generated. Then, the generation unit 520 can perform bit string conversion processing on the generated error check value (PN) by a plurality of conversion methods. Then, the generation unit 520 inputs an input selection signal corresponding to the conversion method control signal to the input selection circuit 524, so that the error check value obtained by converting the bit string using the conversion method determined by the determination unit 540 is used. Only (PN) is stored in the storage circuit 526. At this time, the generation unit 520 appropriately updates the shift amount A used in the bit rotation operation of the conversion method A and the shift amount B used in the bit rotation operation of the conversion method B, and is output from the acquisition unit 510. The shift amount A is reset according to the control command (P). When the error check value read signal is sent from the main CPU 110a, the generation unit 520 converts the error check value obtained by converting the bit string stored in the storage circuit 526 based on the input of the read signal. (PN) is sent to the data bus 400a.

  Therefore, the error check value (PN) read from the generating unit 520 by the main CPU 110a is the control command (PN) N times before the control command (P) sent from the main CPU 110a to the transmission unit 550. It becomes an error check value (PN) generated by using. Further, the error check value (P−N) is an error check value (P−N) obtained by converting a bit string by a bit rotation operation using either a regularly varying shift amount A or a randomly varying shift amount B. -N). Moreover, the shift transition of the shift amount A is appropriately reset based on the control command (P) sent from the main CPU 110a to the transmission unit 550.

[Internal configuration related to authentication processing of intermediate control unit]
The configuration related to the authentication process of the intermediate control unit 180 having an authentication function for the main control unit 110 will now be described.
FIG. 8 is a block diagram illustrating a configuration related to the authentication process of the intermediate control unit 180 according to the present embodiment.

  The intermediate control unit 180 has at least functions of a reception unit 600, an inspection unit 610, an inspection value generation unit 620, an addition unit 630, and a relay transmission unit 640 as functional configurations related to authentication processing. Further, the check value generation unit 620 includes a storage unit 622 that stores the received control command, a generation unit 621 that generates an error check value, a bit string conversion unit 624 that performs bit string conversion processing on the generated error check value, and a bit string It has at least a function with a conversion unit used in the conversion unit 624 and a determination unit 623 that controls the shift amount.

  The control command (P) transmitted from the transmission unit 550 of the main control unit 110 is received by the reception unit 600 of the intermediate control unit 180. The receiving unit 600 has a function of performing a process corresponding to the data format conversion process on the transmission data from the main control unit 110 to generate a control command (P) and storing the control command (P) in its own reception buffer. In addition, the receiving unit 600 outputs a signal indicating that a control command (P) reception interrupt request has been made, or sets a flag indicating that the reception of the control command (P) is completed, so that the CPU 180a. However, it has a function that makes it possible to detect that the reception of the control command (P) transmitted from the main control unit 110 has been completed.

  The receiving unit 600 has a function of outputting the control command (P) to the test value generating unit 620 unless an error check value (PN) is added to the received control command (P). is there. Further, if the error check value (PN) is added to the received control command (P), the receiving unit 600 adds the error check value (from the received control command (P) with the error check value ( P−N) is extracted and output to the checking unit 610, and the control command (P) after extracting the error check value (P−N) is output to the check value generating unit 620. Note that specific means for realizing the function of the receiving unit 600 includes a part of the CPU 180a, a part of the ROM 180b, a part of the RAM 180c, a command receiving input port (not shown), and the like shown in FIG. be able to.

  The inspection value generation unit 620 has a function of storing the control command (P) output from the reception unit 600 in the storage unit 622. Also, the check value generation unit 620 uses the control command (PN) stored in the storage unit 622 in the past to generate an error check value (P− N). The error check value generated by this function is used to verify the validity of the received control command (P). Also, the check value generation unit 620 performs bit string conversion processing by the bit string conversion unit 624 on the error check value (PN) generated by the generation unit 621 by the conversion method determined by the determination unit 623, and checks This has a function of outputting to the unit 610. Also, the test value generation unit 620 has a function for the determination unit 623 to determine a specific conversion method to be set in the bit string conversion unit 624 from among a plurality of conversion methods previously determined with the main control unit 110. It is what you have. In addition, the test value generation unit 620 determines the shift amount A when the bit string conversion unit 624 performs the bit string conversion process by the conversion method A in accordance with the update method and the update timing condition previously determined with the main control unit 110. It has a function controlled by the determination unit 623. Further, the inspection value generation unit 620 has a function of controlling the resetting of the shift amount A by the determination unit 623 in accordance with the reset condition relating to the shift amount A that has been negotiated with the main control unit 110 in advance. .

  That is, a function of the check value generation unit 620 that generates an error check value using a control command stored in the past, converts a bit string, and outputs it to the check unit 610 (hereinafter, “error check value output function”). Is the same as the error check value generation function of the check value generation unit 500 of the main control unit 110. The check value generation unit 620 has a plurality of error check value output functions in advance, like the main control unit 110, and as a specific embodiment thereof, the change condition and the shift amount are the same as those of the main control unit 110. A plurality of update timing conditions related to A and a plurality of reset conditions related to the shift amount A are prepared in advance. The selection information for the error check value output function is also the same as the HW parameter of the main control unit 110, and a specific change condition, update timing condition, and reset condition according to the HW parameter set during the boot process. Is set as a default change condition, an update timing condition, and a reset condition. The error check value output function and the selection information thereof of the intermediate control unit 180 are negotiated between the main control unit 110 and the intermediate control unit 180 in advance.

  And in the function in which the determination part 623 changes a conversion system based on the control command (P) output from the receiving part 600, it is the same as the function which changes the conversion system which the determination means 540 of the main control part 110 has. Is. In other words, the determination unit 623 determines whether or not the control command is a control command satisfying the change condition (corresponding to the determination circuit 541 of the main control unit 110), and determines the conversion method according to the determination result. A function (corresponding to the determination circuit 542 of the main control unit 110) is set in the bit string conversion unit 624. In addition, every time the conversion method set in the bit string conversion unit 624 is changed from the conversion method B to the conversion method A, the determination unit 623 sets the update method and the update timing condition negotiated with the main control unit 110 in advance. Based on this, the shift amount A is updated, and the shift amount A is regularly varied (the shift amount control unit 525c of the main control unit 110). Further, the determination unit 623 determines whether or not the control command is a control command that satisfies the reset condition related to the shift amount A (corresponding to the reset determination circuit 528 of the main control unit 110), and the determination result The shift amount A is provided with a predetermined set value to reset the shift amount A (corresponding to the shift amount control unit 525c of the main control unit 110).

  The update method related to the shift amount A included in the determination unit 623 is defined based on the error check value that has been subjected to the bit string conversion processing by the conversion method B, similarly to the shift amount control unit 525c of the main control unit 110. The error check value that has been subjected to the bit string conversion processing by the conversion method B is the error output from the receiving unit 600 among the plurality of error check values (PN) output from the bit string converting unit 624 to the checking unit 610. The error check value (PN) coincides with the check value. Of the plurality of update timing conditions related to the shift amount A included in the determination unit 623, the update timing condition corresponding to the HW parameter set during the boot process is the same as the shift amount control unit 525c of the main control unit 110. Suppose that it is defined based on an error check value first added to the control command during a predetermined operation mode. Of the plurality of reset conditions related to the shift amount A included in the determination unit 623, the reset condition corresponding to the HW parameter set during the boot process is set for the reset determination circuit 528 of the main control unit 110. The same as the reset condition.

  In order to realize the function of the determination unit 623, the RAM 180c corresponds to a storage area corresponding to the change condition storage area (CC) of the main control unit 110 and a transmission number storage area (P) of the main control unit 110. A reception number storage area (P) is provided. The same applies to the conversion method information storage area (CM), the update timing condition storage area (UT), and the shift amount storage area (S).

  The storage unit 622 stores the control command (P) output from the receiving unit 600 and also outputs the control command (PN) stored in the past to the generation unit 621. This is the same function as the storage circuit 522 of the unit 110. Further, when the main control unit 110 or the intermediate control unit 180 is initialized and the past control command stored in the storage unit 622 is cleared, the CPU 180a reads the unique information from the ROM 180b and sets it as an initial setting value. The function to be set in the storage unit 622 is the same as that of the main control unit 110.

  Further, the generation unit 621 generates an error check value (PN) by a preset generation method using the control command (PN) output from the storage unit 622 and outputs the error check value (PN) to the bit string conversion unit 624. The function to perform is the same as the function of the generation circuit 521 of the main control unit 110.

  In addition, the bit string conversion unit 624 has a plurality of conversion methods (conversion method A and conversion method B), sets a specific conversion method by the conversion method control of the determination unit 623, and checks the error output from the generation unit 621. The function of performing bit string conversion processing on the value (PN) by the set conversion method and outputting the value to the checking unit 610 is the same as the function of the bit string conversion circuit 525 of the main control unit 110. The bit string conversion unit 624 also has a function of resetting the shift amount A by giving a predetermined set value to the shift amount A by the shift amount control of the determination unit 623. Is the same.

  Note that the shift amount A when the conversion method is the conversion method A is a value that regularly varies according to the update method that is negotiated with the main control unit 110 in advance. In this case, the bit string conversion unit 624 performs a bit rotation operation on the bit string of the error check value (PN) using the shift amount A determined by the determination unit 623 according to the update method, and the original error check value The bit string is returned and output to the inspection unit 610. Further, the shift amount B when the conversion method is the conversion method B is a value that randomly varies and is not negotiated with the main control unit 110 in advance. In this case, the bit string conversion unit 624 performs bit rotation operation on the bit string of the error check value (PN) by the number of rotations that can be taken by the rotation number defined by the bit width of the bit string. Then, the bit string conversion unit 624 outputs error check values (PN) corresponding to the number of ranges that can be taken by the rotation number, to which the bit string is converted, to the checking unit 610, respectively.

  Specific means for realizing the functions of the determination unit 623, the storage unit 622, the generation unit 621, and the bit string conversion unit 624 include a part of the CPU 180a, a part of the ROM 180b, a part of the RAM 180c, and the like shown in FIG. be able to.

  The checking unit 610 has a function of performing an error checking process for collating the error check value output from the receiving unit 600 with the error check value output from the bit string conversion unit 624 of the check value generating unit 620. In the error check process, the error check value output from the receiving unit 600 is compared with the error check value output from the bit string conversion unit 624. If the two match, it is determined that the check result is normal, If they do not match, it is determined that the test result is not normal. Note that when the error checking value is not output from the receiving unit 600, the checking unit 610 does not perform the matching process.

  When the conversion method B is set in the bit string conversion unit 624, error checking values are output from the bit string conversion unit 624 to the number of rotations that can be taken from the bit string conversion unit 624. In this case, checking section 610 compares all error check values output from bit string conversion section 624 with error check values output from receiving section 600. Then, when any error check value output from the bit string conversion unit 624 matches the error check value output from the reception unit 600, the check unit 610 determines that the check result is normal, and any error is detected. If the inspection value does not match the error inspection value output from the receiving unit 600, it is determined that the inspection result is not normal.

  When it is determined that the inspection result is normal, the inspection unit 610 generates the control command (P) to which the currently received error check value (PN) is added and the current error check value (PN) generation source. It is determined that the validity of the control command (PN) is authenticated and the validity of the main control unit 110 can be authenticated. Then, the inspection unit 610 generates authentication result data indicating successful authentication and outputs the generated authentication result data to the adding unit 630.

  In addition, when the inspection unit 610 determines that the inspection result is normal, the conversion method B is set, and a plurality of errors (the number of ranges that the rotation number can take) output from the bit string conversion unit 624 to the inspection unit 610 are detected. Among the check values (PN), the error check value (PN) that matches the error check value output from the receiving unit 600 is output to the determining unit 623. Note that even when no error check value is output from the receiving unit 600, the checking unit 610 is output from the bit string conversion unit 624 to the checking unit 610 if the current operation period starts. The error check value (PN) is output to the determination unit 623. Then, the determination unit 623 updates the shift amount A based on the error check value (PN) output from the check unit 610 at the timing for updating the shift amount A.

  On the other hand, when the inspection result is not determined to be normal, the inspection unit 610 determines that the legitimacy of the main control unit 110 could not be authenticated due to an illegal act or a communication error. Then, the inspection unit 610 generates authentication result data indicating unsuccessful authentication and outputs it to the adding unit 630. The data format of the authentication result data is not particularly limited, but may be a data format having the same data length as the error check value added to the received control command. Further, specific means for realizing the function of the inspection unit 610 can be configured from a part of the CPU 180a, a part of the ROM 180b, a part of the RAM 180c, and the like shown in FIG.

  The adding unit 630 adds the authentication result data output from the checking unit 610 to the control command (P) extracted from the error check value (PN) output from the receiving unit 600, and includes the authentication result data. It has a function of generating a control command (P). The adding unit 630 has a function of outputting the generated control command (P) with authentication result data to the relay transmitting unit 640. Note that specific means for realizing the function of the adding unit 630 can be configured from a part of the CPU 180a, a part of the ROM 180b, a part of the RAM 180c, and the like shown in FIG.

  The relay transmission unit 640 has a function of transmitting the control command (P) output from the reception unit 600 to which the error check value (PN) is not added to the effect control unit 120. Further, the relay transmission unit 640 has a function of transmitting the control command (P) with authentication result data output from the adding unit 630 to the effect control unit 120. The control command (P) with authentication result data transmitted from the relay transmission unit 640 to the effect control unit 120 indicates an effect process having the same content as the control command (P) received by the receiving unit 600. That is, the control command (P) received by the reception unit 600 is output to the relay transmission unit 640 in a state where the specific processing content and the reception order are maintained, and the relay transmission unit 640 transmits to the effect control unit 120. Will be sent. Note that specific means for realizing the function of the relay transmission unit 640 includes a part of the CPU 180a, a part of the ROM 180b, a part of the RAM 180c, and a command transmission output port (not shown) shown in FIG. can do.

  When transmitting the generated authentication result data to the effect control unit 120, the intermediate control unit 180 adds the received authentication result data to the effect control unit 120 and adds it to the received control command. That is, the authentication result data is not transmitted by the authentication result data alone, but is transmitted to the effect control unit 120 integrally with the control command which is other transmission data. If the authentication result data and the error check value are in a data format having the same data length, transmission data transmitted from the main control unit 110 to the intermediate control unit 180 and transmission from the intermediate control unit 180 to the effect control unit 120 are transmitted. The transmission data may have a data format having the same data length. By doing so, an unauthorized person can steal transmission data between the intermediate control unit 180 and the production control unit 120 and illegally analyze the transmission timing of the authentication result data to the production control unit 120. It becomes difficult and the security strength of the gaming machine 1 can be improved.

[Explanation of control commands]
Hereinafter, the types of control commands transmitted from the main control unit 110 of the gaming machine 1 according to the embodiment of the present invention to the effect control unit 120 will be described.
FIG. 9 is a diagram showing the types of control commands transmitted from the main control unit 110 to the effect control unit 120 constituting the gaming machine 1 according to the present embodiment. The control command shown in FIG. 9 is an example, and the control command according to the present invention is not limited to this.

  The control command transmitted from the main control unit 110 to the effect control unit 120 via the intermediate control unit 180 is composed of 1-byte data, and a 1-byte “ID” for identifying the control command classification. “MODE” information and 1-byte “DATA” information indicating the detailed control contents of each control command. The “MODE” information and the “DATA” information are stored in advance in the main ROM 110b as described above.

  In the main control unit 110, when it is the transmission timing of the control command, the main CPU 110a reads the “MODE” information and the “DATA” information from the main ROM 110b, generates a control command, and stores it in the transmission data storage area of the main RAM 110c. set. Then, during the command transmission process, the main CPU 110a sends the control command set in the transmission data storage area to the internal bus 400, writes it to the transmission unit 550, and transmits it to the intermediate control unit 180 by the transmission unit 550. To do. At this time, an error check value is added to the control command as necessary. Then, it is transmitted to the effect control unit 120 by the relay transmission process of the intermediate control unit 180. In the following description, it is assumed that each control command is transmitted from the main control unit 110 to the effect control unit 120 via the intermediate control unit 180 in this way, and each control command is stored in the main RAM 110c for transmission data. The description of the processing after being set in the area is omitted. Further, in the following description, the expression “transmit a control command” includes transmitting the control command with an error check value, and the expression “transmitting to the effect control unit 120”. Includes transmission to the effect control unit 120 via the intermediate control unit 180.

The “designation designating command” indicates the type of the special symbol that is stopped and displayed. The “MODE” information is set as “E0H”, and the “DATA” information is set according to the special symbol type. ing. Since the special symbol type eventually determines the jackpot type and gaming state, the effect symbol designation command can also be said to indicate the jackpot type and gaming state.
In the effect symbol designation command, when various special symbols are determined and the variation display of the special symbol is started, an effect symbol designation command corresponding to the determined special symbol is transmitted to the effect control unit 120. Specifically, when the lottery result of the jackpot is determined, various special symbols are determined, and the variation display of the special symbols is started, an effect designating command corresponding to the determined special symbol is transmitted to the main RAM 110c. Set in the data storage area.
The process related to the jackpot lottery related to the production symbol designation command will be described later.

  Here, among the effect designating commands, the “losing effect designating command” set with “DATA” information being “00H” is a control for stopping and displaying the result of the losing when the lottery result is losing. It is a command. That is, it is a control command that is surely transmitted from the main control unit 110 to the effect control unit 120 when the lose design symbol designation command is a loss. Hereinafter, the lose effect designating command is also referred to as a “lose command” as a command for executing a process in case of loss.

The “first special symbol memory designation command” indicates the number of reserved memories stored in the first special symbol reservation number (U1) storage area, and the information of “MODE” is set to “E1H”, “DATA” information is set according to the number of memories.
This first special symbol memory designation command is effect-controlled by the first special symbol memory designation command corresponding to the number of reserved memories when the number of reserved memories stored in the first special symbol reservation number (U1) storage area is switched. Is transmitted to the unit 120. Specifically, when the value stored in the first special symbol hold number (U1) storage area is increased or decreased when determining the result of entering the first start port 14 or the big win lottery result, the reserved memory after the increase or decrease is stored. The first special symbol storage designation command corresponding to the number is set in the transmission data storage area of the main RAM 110c.

The “second special symbol memory designation command” indicates the number of reserved memories stored in the second special symbol reservation number (U2) storage area, and the information of “MODE” is set to “E2H”, “DATA” information is set according to the number of memories.
This second special symbol memory designation command is directed by the second special symbol memory designation command corresponding to the number of reserved memories when the number of reserved memories stored in the second special symbol reservation number (U2) storage area is switched. Is transmitted to the unit 120. Specifically, when the value stored in the second special symbol holding number (U2) storage area is increased or decreased in determining the result of entering the second starting port 15 or the jackpot lottery result, the holding storage after the increase / decrease is performed. The second special symbol storage designation command corresponding to the number is set in the transmission data storage area of the main RAM 110c.
In the present embodiment, the “first special symbol memory designation command” and the “second special symbol memory designation command” are collectively referred to as “special symbol memory designation command”.

The “symbol confirmation command” indicates that the special symbol is stopped and displayed, and “MODE” information is set to “E3H” and “DATA” information is set to “00H”.
This symbol confirmation command is transmitted to the effect control unit 120 when the special symbol is stopped and displayed. Specifically, after determining the jackpot lottery result and the special symbol change time has elapsed, when the special symbol is stopped and displayed on the first special symbol display device 20 or the second special symbol display device 21, the symbol confirmation command Is set in the transmission data storage area of the main RAM 110c.

The “power-on designation command” indicates that the gaming machine 1 is powered on, the “MODE” information is set to “E4H”, and the “DATA” information is set to “00H”. ing.
The power-on designation command is transmitted to the effect control unit 120 when the gaming machine 1 is powered on. When the gaming machine 1 is powered on and the initialization process of the main control unit 110 is performed, if the backup information of the main RAM 110c generated when the power is turned off (hereinafter referred to as “power interruption”) is not valid, The work area in the RAM 110c is cleared and a new work area is set. Thereafter, a power-on designation command is set in the transmission data storage area of the main RAM 110c.
The initialization process related to the power-on designation command and the like will be described later.

The “RAM clear designation command” indicates that the information stored in the main RAM 110c has been cleared. The “MODE” information is set to “E4H” and the “DATA” information is set to “01H”. Has been.
A RAM clear button (not shown) is provided on the back side of the gaming machine 1. When the gaming machine 1 is turned on while pressing the RAM clear button, a system reset occurs in the main control unit 110 and initialization processing is performed. . After the work area of the main RAM 110c is cleared and a new work area is set and a power-on designation command is transmitted, the RAM clear designation command is set in the transmission data storage area of the main RAM 110c.

The “power recovery designation command” indicates that the gaming machine 1 has been powered on and has been restored normally. The “MODE” information is set to “E4H” and is matched according to the gaming state at the time of power interruption. "DATA" information is set.
This power supply restoration designation command is transmitted to the effect control unit 120 when the gaming machine 1 is turned on and normally restored. Specifically, when the gaming machine 1 is turned on and the initialization process is performed, if the backup information of the main RAM 110c generated at the time of power interruption is valid, the power is restored according to the gaming state indicated by the backup information. A designated command is generated, and the generated power supply restoration designation command is set in the transmission data storage area of the main RAM 110c.

  When the power is turned on, at least one of a power-on designation command, a RAM clear designation command, and a power restoration designation command is transmitted from the main control unit 110 to the effect control unit 120. That is, the above-described control command group in which “MODE” information is set to “E4H” is a command for executing a process at power-on. Hereinafter, the control command group in which the “MODE” information is set to “E4H” is also referred to as “power-on command”.

The “demonstration designation command” indicates that the first special symbol display device 20 or the second special symbol display device 21 is not in operation, the information of “MODE” is set to “E5H”, and “DATA” Is set to “00H”.
This demonstration designation command is used for effect control when there is no special symbol holding storage of the first special symbol display device 20 or the second special symbol display device 21 and a non-game state in which there is no operation by the player has elapsed for a predetermined time. Is transmitted to the unit 120. Specifically, when performing the jackpot lottery, the special electric game, and the control of the gaming state, either the first special symbol hold number (U1) storage area or the second special symbol hold number (U2) storage area In addition, when a state in which one or more data is not set continues for a predetermined time, the demo designation command is set in the transmission data storage area of the main RAM 110c.

  Note that the demo designation command may be transmitted immediately when there is no special symbol holding storage of the first special symbol display device 20 or the second special symbol display device 21. In this case, after receiving the demonstration designation command, the effect control unit 120 executes the demonstration effect when no other control command is received for a predetermined time, that is, when the non-game state has elapsed for a predetermined time.

The “variable pattern designation command for the first special symbol” indicates the variation time (variation mode) of the special symbol in the first special symbol display device 20, the information of “MODE” is set as “E6H”, and various “DATA” information is set in accordance with the fluctuation pattern.
The first special symbol variation pattern designation command is a first special symbol variation pattern corresponding to the variation pattern of the special symbol determined when the special symbol variation display of the first special symbol display device 20 is started. A designation command is transmitted to the effect control unit 120. Specifically, the variation pattern for the first special symbol corresponding to the determined variation pattern of the special symbol when the variation pattern of the special symbol is determined and the variation display of the special symbol is started by judging the lottery result of the jackpot The designated command is set in the transmission data storage area of the main RAM 110c.

The “variable pattern designation command for the second special symbol” indicates the variation time (variation mode) of the special symbol in the second special symbol display device 21, and the information of “MODE” is set to “E7H”. “DATA” information is set in accordance with the fluctuation pattern.
The second special symbol variation pattern designation command is a second special symbol variation pattern corresponding to the variation pattern of the special symbol determined when the special symbol variation display of the second special symbol display device 21 is started. A designation command is transmitted to the effect control unit 120. Specifically, the variation pattern for the second special symbol corresponding to the determined variation pattern of the special symbol when the variation pattern of the special symbol is determined and the variation display of the special symbol is started by judging the lottery lottery result The designated command is set in the transmission data storage area of the main RAM 110c.
In the present embodiment, the “first special symbol variation pattern designation command” and the “second special symbol variation pattern designation command” are collectively referred to as a “variation pattern designation command”.

  Here, among the variation pattern designation commands, the control command group in which the information of “DATA” is set to “01H”, “02H”, “03H”, “04H”, “05H” is a control for executing the reach effect. It is a command. Hereinafter, a control command group in which “MODE” information is set as “E6H” and “DATA” information is set as “01H” to “05H” is also referred to as “reach command”.

The “big prize opening opening designation command” indicates the number of rounds of jackpots according to various types of jackpots, and “MODE” information is set as “EAH”, and “DATA” is set according to the number of rounds of jackpots. Information is set.
With regard to the special winning opening opening designation command, when the big hit round is started, the big winning opening opening designation command corresponding to the started round number is transmitted to the effect control unit 120. Specifically, when the first big prize opening / closing door 16b (or the second big prize opening / closing door 17b) is opened in the big hit game process, a big prize opening opening designation command corresponding to the number of rounds to be opened is provided. It is set in the transmission data storage area of the main RAM 110c.
Note that the command group in which the information of “MODE” is set to “EAH” is a command for executing processing corresponding to each round of jackpot. Hereinafter, a command group in which “MODE” information is set to “EAH” is also referred to as a “hit command”.

The “opening designation command” indicates that various jackpots start, “MODE” information is set as “EBH”, and “DATA” information is set according to the jackpot type.
As for this opening designation command, when various jackpots start, an opening designation command corresponding to the type of jackpot is transmitted to the effect control unit 120. Specifically, at the start of the jackpot game process, an opening designation command corresponding to the jackpot type is set in the transmission data storage area of the main RAM 110c.
Note that the command group in which the information of “MODE” is set to “EBH” is a command for starting the big hit state processing. Hereinafter, a command group in which “MODE” information is set to “EBH” is also referred to as a “big hit start command”.

The “ending designation command” indicates that various types of jackpots have ended, “MODE” information is set as “ECH”, and “DATA” information is set according to the jackpot type.
As for this ending designation command, when various jackpots are finished, an ending designation command corresponding to the jackpot type is transmitted to the effect control unit 120. Specifically, at the start of the jackpot game end process, an ending designation command corresponding to the jackpot type is set in the transmission data storage area of the main RAM 110c.
Note that the command group in which the “MODE” information is set to “ECH” is a command for ending the jackpot state process. Hereinafter, a command group in which “MODE” information is set to “ECH” is also referred to as a “hit end command”.

The “gaming state designation command” indicates the contents of the gaming state, the information of “MODE” is set as “EDH”, and the information of “DATA” is set according to the contents of the gaming state.
As for the gaming state designation command, a gaming state designation command corresponding to the gaming state is transmitted to the effect control unit 120 at the start and end of variation of the special symbol or at the beginning and end of the big hit game. Specifically, when the special symbol variation display is started, when the special symbol is stopped and displayed, when the high probability game flag, the high probability game number, the short time game flag, and the short time game number (J) are cleared, the high probability When a game flag, a high probability game count, a short-time game flag, and a short-time game count (J) are set, a game state designation command corresponding to the current game state is set in the transmission data storage area of the main RAM 110c.

[Control processing of main control unit]
Hereafter, the control process of the main control part 110 of the gaming machine 1 according to the embodiment of the present invention will be described. First, main processing of the main control unit 110 will be described.
FIG. 10 is a flowchart showing main processing by the main control unit 110 according to the present embodiment.

  When the gaming machine 1 is powered on and powered by the power supply unit 170, a system reset occurs in the main control unit 110, and the main CPU 110a performs initialization processing (processing from step S1 to step S17 in FIG. 10). ) And random number value update processing (steps S20 and S30 in FIG. 10).

In step S1, the main CPU 110a performs a boot process as a premise of the initialization process of the main control unit 110. In this boot process, the main CPU 110a performs its own self-diagnosis process, initialization of built-in circuits and peripheral circuits, and setting of initial values. Details of the boot process will be described later.
In step S2, the main CPU 110a sets permission to access the main RAM 110c.
In step S3, the main CPU 110a determines whether or not the RAM clear switch is on. If it is determined that the RAM clear switch is on, the main CPU 110a shifts the processing to step S10 to perform RAM clear. On the other hand, if the RAM clear switch is not determined to be on, the process proceeds to step S4.

In step S4, the main CPU 110a generates a checksum in a predetermined storage area of the main RAM 110c when the power is turned on.
In step S5, the main CPU 110a compares the generated checksum with the checksum in the predetermined storage area of the main RAM 110c generated at the time of power interruption. If they match, it is determined to be normal, and the process proceeds to step S6. If they do not match, it is determined to be an error, and the process proceeds to step S10.

In step S <b> 6, the main CPU 110 a adjusts the start timing of the operation after activation with the peripheral control unit 300 including the effect control unit 120 and the intermediate control unit 180. Specifically, after all the peripheral control unit 300 and the intermediate control unit 180 are activated and become in a stable state, the system waits for a certain period of time so that the rendering process and the like can be started at substantially the same timing.
In step S7, the main CPU 110a sets an initial value in a work area of the main RAM 110c that requires an initial value upon recovery from power interruption, and performs a RAM setting process when backup is valid.

In step S8, the main CPU 110a reads the backup information of the main RAM 110c generated at the time of power interruption in order to restore the gaming state at the time of power interruption. Specifically, the game state information is read from the game state storage area of the main RAM 110c that is backed up.
In step S9, the main CPU 110a determines a power restoration designation command based on the read gaming state information, and sets the decided power restoration designation command in the transmission data storage area of the main RAM 110c.

In step S10, the main CPU 110a performs timing adjustment with the peripheral control unit 300 and the intermediate control unit 180 in the same manner as in step S6.
In step S11, the main CPU 110a clears the used area of the main RAM 110c.
In step S12, the main CPU 110a sets initial values in the work area of the main RAM 110c that requires initial values when initializing the gaming machine 1, including setting initial values of various random numbers, and backup is not valid. In this case, the main RAM 110c is set.

In step S13, the main CPU 110a generates a power-on designation command, and sets the generated power-on designation command in the transmission data storage area of the main RAM 110c.
In step S <b> 14, the main CPU 110 a performs a command transmission process for transmitting the control command set in the transmission data storage area to the intermediate control unit 180. That is, a power-on designation command is transmitted to the intermediate control unit 180. In the command transmission process in steps S14 and S16, the test value generation unit 500 performs a conversion method setting process, a test value generation process, a bit string conversion process, and a shift amount setting process. Further, the command transmission processing in step S14 and step S16 involves processing in which the main CPU 110a sets unique information as an initial setting value in the storage circuit 522. Details of the command transmission process will be described later.

In step S15, the main CPU 110a generates a RAM clear designation command, and sets the generated RAM clear designation command in the transmission data storage area of the main RAM 110c.
In step S16, the main CPU 110a performs a command transmission process for transmitting a control command set in the transmission data storage area of the main RAM 110c to the intermediate control unit 180. That is, the control command of either the power supply restoration designation command or the RAM clear designation command is transmitted to the intermediate control unit 180.
In step S17, the main CPU 110a sets the interrupt permission and sets the execution period (α, for example, 4 milliseconds) of the timer interrupt program.

  Note that the command transmission processing in step S14 and step S16 may be performed in the timer interrupt processing performed after interrupt permission in step S17. At this time, it is determined in advance that the transmission order of each control command is not changed.

In step S20, the main CPU 110a performs an effect random number update process for updating the reach determination random number value and the special figure variation random value for determining the variation mode (variation time) of the special symbol.
In step S30, the main CPU 110a performs an initial random number value update process for updating the initial random number value for special symbol determination, the initial random number value for jackpot symbol, the initial random number value for small bonus symbol, and the initial random number value for normal symbol determination. Thereafter, the processes in steps S20 and S30 are repeated until a predetermined interrupt process is performed.

Next, interrupt processing of the main control unit 110 will be described.
FIG. 11 is a flowchart showing interrupt processing by the main control unit 110 according to the present embodiment.
The main CPU 110a executes a timer interrupt process of the main control unit 110 at every predetermined cycle (α) based on a clock signal output from a clock pulse generation circuit provided in the main control unit 110.

  First, in step S100, the main CPU 110a saves the information stored in the register of the main CPU 110a to the stack area.

  In step S110, the main CPU 110a updates the special symbol time counter, updates the special game timer counter such as the opening time of the special electric accessory, updates the normal symbol time counter, and updates the normal power release time counter. A time control process for updating various timer counters is performed. Specifically, a process of subtracting 1 from a special symbol time counter, a special game timer counter, a normal symbol time counter, and a general electricity open time counter is performed.

In step S120, the main CPU 110a performs a random number update process for the special symbol determination random number value, the big hit symbol random number value, the small hit symbol random number value, and the normal symbol determination random number value.
Specifically, 1 is added to each random number value and random number counter to be updated. When the added random number counter exceeds the maximum value in the random number range (when the random number counter makes one revolution), the random number counter is returned to 0, and each random number value is newly updated from the initial random number value at that time. .

  In step S130, as in step S30, the main CPU 110a updates the initial random number value for updating the special symbol determining initial random value, the big hit symbol initial random value, the small hit symbol initial random value, and the normal symbol determining initial random value. Perform update processing.

  In step S200, the main CPU 110a performs input control processing. In this process, the main CPU 110a includes a general winning opening detection switch 12a, a first large winning opening detection switch 16a, a second large winning opening detection switch 17a, a first starting opening detection switch 14a, a second starting opening detection switch 15a, a gate. An input process for determining whether or not there is an input to each switch of the detection switch 13a is performed.

  Specifically, various detection signals from the general winning opening detecting switch 12a, the first big winning opening detecting switch 16a, the second large winning opening detecting switch 17a, the first starting opening detecting switch 14a, and the second starting opening detecting switch 15a. Is inputted, predetermined data is added to a prize ball counter used for a prize ball provided for each winning opening and updated.

  Further, when a detection signal is input from the first start port detection switch 14a, if the data set in the first special symbol hold number (U1) storage area is less than 4, the first special symbol hold number ( U1) Add 1 to the storage area to obtain special symbol determination random number value, jackpot symbol random number value, small hit symbol random number value, reach determination random number value, and special symbol variation random value The random number value is stored in a predetermined storage unit (0th storage unit to 4th storage unit) in the first special symbol random value storage area.

  Similarly, when a detection signal is input from the second start port detection switch 15a, if the data set in the second special symbol hold number (U2) storage area is less than 4, the second special symbol hold number (U2) 1 is added to the storage area, and a random number value for special symbol determination, a random number value for big hit symbol, a random number value for small hit symbol, a random number value for reach determination, and a random number value for special symbol variation are acquired. Various random numbers are stored in a predetermined storage unit (0th storage unit to 4th storage unit) in the second special symbol random number value storage area.

  When a detection signal is input from the gate detection switch 13a, if the data set in the normal symbol hold number (G) storage area is less than 4, the normal symbol hold number (G) storage area is set to 1. It adds, acquires the random number value for normal symbol determination, and memorize | stores the acquired random number value for normal symbol determination in the predetermined memory | storage part (0th memory | storage part-4th memory | storage part) in a normal symbol holding | maintenance storage area.

  Further, when a detection signal from the first grand prize opening detection switch 16a or the second big prize opening detection switch 17a is input, the number of game balls won in the first big prize opening 16 or the second big prize opening 17 is counted. 1 is added to the number of entries (C) storage area for the big winning opening to update.

  In step S300, the main CPU 110a, based on the input control process in step S200, performs a special symbol / special electric accessory control process (hereinafter referred to as “a special jackpot lottery, a special electric accessory, and a gaming state control”). Special figure special electricity control process ”). Details of the special figure special electric control process will be described later with reference to FIG.

In step S400, the main CPU 110a performs a normal symbol / ordinary electric accessory control process (hereinafter referred to as a “general-purpose electric power control process”) for performing the normal symbol lottery and the control of the ordinary electric accessory.
Specifically, it is first determined whether or not 1 or more data is set in the normal symbol hold count (G) storage area, and 1 or more data must be set in the normal symbol hold count (G) storage area. If this is the case, the current ordinary power transmission control process is terminated.

If 1 or more data is set in the normal symbol holding number (G) storage area, after subtracting 1 from the value stored in the normal symbol holding number (G) storage area, the data is in the normal symbol holding storage area. The normal symbol determination random numbers stored in the first storage unit to the fourth storage unit are shifted to the previous storage unit. At this time, the normal symbol determination random value already written in the 0th storage unit is overwritten and erased.
Then, referring to the hit determination table, a process is performed to determine whether or not the normal symbol determination random number value stored in the 0th storage unit of the normal symbol hold storage area is a random value corresponding to “win”. Thereafter, the normal symbol display device 22 displays the normal symbol variation display, and when the normal symbol variation time has elapsed, the normal symbol corresponding to the result of the normal symbol lottery display is stopped. If the random number for normal symbol determination referred to is “winning”, the start opening / closing solenoid 15c is driven to control the second start opening 15 to the second mode for a predetermined opening time.
Here, in the non-short-time gaming state, the variation time of the normal symbol is set to 29 seconds, and if it is “winning”, the second start port 15 is controlled to the second mode for 0.2 seconds. On the other hand, in the short-time gaming state, the variation time of the normal symbol is set to 3 seconds, and if it is “winning”, the second start port 15 is controlled to the second mode for 3.5 seconds.

  In step S500, the main CPU 110a performs a payout control process. In this payout control process, the main CPU 110 a refers to each prize ball counter, generates payout number designation commands corresponding to various winning ports, and transmits the generated payout number designation commands to the payout control unit 130. To do.

  In step S600, the main CPU 110a, external information data, start opening / closing solenoid data, first big prize opening opening / closing solenoid data, second big prize opening opening / closing solenoid data, special symbol display device data, normal symbol display device data, the number of memories Performs data creation for the specified command.

In step S700, the main CPU 110a performs output control processing. In this process, port output processing is performed for outputting signals of the external information data, the start opening / closing solenoid data, the first big prize opening / closing solenoid data, and the second big prize opening / closing solenoid data created in step S600.
The special symbol display device data and the normal symbol display device data created in S600 are used to turn on the LEDs of the first special symbol display device 20, the second special symbol display device 21 and the normal symbol display device 22. Display device output processing is performed.

  In step S710, the main CPU 110a performs a command transmission process of transmitting a control command set in the transmission data storage area of the main RAM 110c to the intermediate control unit 180. Note that in the command transmission process in step S710 as well, the test value generation unit 500 performs the conversion method setting process, the test value generation process, the bit string conversion process, and the shift amount setting process, as described above. It will be described later.

  In step S800, the main CPU 110a restores the information saved in step S100 to the register of the main CPU 110a.

Next, the special figure special electric control process of the main control unit 110 will be described.
FIG. 12 is a flowchart showing a special figure special power control process by the main control unit 110 according to the present embodiment.

  In step S301, the main CPU 110a reads the value of the special figure special electricity processing data. This “Special Figure Special Electric Processing Data” is a value assigned to the address of the storage area in which each subroutine of the special figure special electric control process is stored, and which subroutine is processed by referring to the special figure special electric processing data. You can identify what to do. The special figure special electricity processing data is set as necessary in each subroutine of the special figure special electricity control processing as will be described later, and the subroutine necessary for the game is appropriately processed.

  In step S302, the main CPU 110a refers to the branch address from the read special figure special processing data, and if special figure special electric treatment data = 0, the main CPU 110a moves the processing to the special symbol storage determination process (step S310). If data = 1, the process moves to the special symbol variation process (step S320), and if the special figure special electricity process data = 2, the process moves to the special symbol stop process (step S330), and the special figure special electricity process data = 3. If there is, the process is transferred to the jackpot game process (step S340). If the special figure special electric processing data = 4, the process is transferred to the jackpot game end process (step S350). The processing is moved to processing (step S360).

  In the special symbol memory determination process in step S310, the main CPU 110a performs a jackpot determination process, a special symbol determination process for determining a special symbol to be stopped and displayed, a variation time determination process for determining a variation time of the special symbol, and the like. Here, the specific content of the special symbol memory determination process will be described with reference to FIG.

  FIG. 13 is a flowchart in the special symbol memory determination process by the main control unit 110 according to the present embodiment.

In step S311, the main CPU 110a determines whether one or more data is set in the first special symbol hold count (U1) storage area or the second special symbol hold count (U2) storage area.
If one or more data is not set in any storage area of the first special symbol hold count (U1) storage area or the second special symbol hold count (U2) storage area, the special figure special electricity processing data = 0. The special symbol variation process of this time is terminated while holding.
On the other hand, if one or more data is set in the first special symbol hold count (U1) storage area or the second special symbol hold count (U2) storage area, the process proceeds to step S312.

In step S312, the main CPU 110a performs a jackpot determination process.
Specifically, when one or more data is set in the second special symbol hold count (U2) storage area, 1 is calculated from the value stored in the second special symbol hold count (U2) storage area. After the subtraction, the various random numbers stored in the first to fourth storage units in the second special symbol random number storage area are shifted to the previous storage unit. At this time, various random values already written in the 0th storage unit are overwritten and deleted. Then, referring to the jackpot determination table, whether the special symbol determination random number value stored in the 0th storage unit of the second special symbol random value storage area is a random value corresponding to “big hit” or “small hit” It is determined whether it is a random value corresponding to.

  In addition, when one or more data is not set in the second special symbol hold number (U2) storage area and one or more data is set in the first special symbol hold number (U1) storage area, Various random numbers stored in the first to fourth storage units in the first special symbol random number storage area after subtracting 1 from the value stored in the first special symbol hold number (U1) storage area Is shifted to the previous storage unit. Also at this time, various random numbers already written in the 0th storage unit are overwritten and deleted. Then, referring to the jackpot determination table, whether the special symbol determination random number value stored in the 0th storage unit of the first special symbol random number storage area is a random value corresponding to “big hit” or “small hit” It is determined whether it is a random value corresponding to.

  In the present embodiment, the random number value stored in the second special symbol random value storage area is shifted (digested) with priority over the first special symbol random value storage area. However, the first special symbol storage area or the second special symbol storage area may be shifted in the order of winning in the starting opening, and the first special symbol storage area is shifted with priority over the second special symbol storage area. You may let them.

In step S313, the main CPU 110a performs a special symbol determination process for determining the type of special symbol to be stopped and displayed.
In this special symbol determination process, when it is determined as “big hit” in the jackpot determination process (step S312), the symbol determination table is referred to and stored in the 0th storage unit of the first special symbol random value storage area. The jackpot symbol (special symbol 1 to special symbol 6) is determined based on the random number value for the jackpot symbol. In addition, when it is determined as “small hit” in the jackpot determination process (step S312), the small hit stored in the 0th storage unit of the first special symbol random value storage area with reference to the symbol determination table Based on the symbol random number value, the small hit symbol (special symbol A, special symbol B) is determined. Further, when it is determined as “losing” in the jackpot determination process (step S312), the symbol determining table (special symbol 0) is determined with reference to the symbol determining table.
Then, stop symbol data corresponding to the determined special symbol is stored in the stop symbol data storage area.

In step S314, the main CPU 110a performs special symbol variation time determination processing.
Specifically, referring to the variation pattern determination table, based on the reach determination random number value and the special diagram variation random value stored in the 0th storage unit of the first special symbol random value storage area, the special symbol Determine the variation pattern. Thereafter, the variation time of the special symbol corresponding to the determined variation pattern of the special symbol is determined. Then, a process of setting a counter corresponding to the determined variation time of the special symbol in the special symbol time counter is performed.

In step S315, the main CPU 110a sets variable display data for causing the first special symbol display device 20 or the second special symbol display device 21 to perform variable symbol display (LED blinking) in a predetermined processing area. . As a result, when the variable display data is set in the predetermined processing area, the LED lighting / extinguishing data is appropriately created in step S600, and the created data is output in step S700. Variation display of the special symbol display device 20 or the second special symbol display device 21 is performed.
Further, the main CPU 110a, when the special symbol variation display is started, the special symbol variation pattern designation command (the first special symbol variation pattern designation command) corresponding to the special symbol variation pattern determined in step S314. Alternatively, a second special symbol variation pattern designation command) is set in the transmission data storage area of the main RAM 110c.

  In step S316, the main CPU 110a sets the special symbol special electricity processing data = 0 to the special symbol special electric treatment data = 1, prepares to move to the special symbol variation processing subroutine, and ends the special symbol memory determination processing.

Again, the description of the special figure special electric control process shown in FIG. 12 will be returned.
In the special symbol variation process of step S320, the main CPU 110a performs a process of determining whether or not the special symbol variation time has elapsed.
Specifically, it is determined whether or not the variation time of the special symbol determined in step S314 has elapsed (special symbol time counter = 0), and if it is determined that the variation time of the special symbol has not elapsed The special symbol variation process is terminated while the special symbol special electricity processing data = 1 is held. Note that the special symbol variation time counter set in step S314 is subtracted in step S110.

If it is determined that the variation time of the special symbol has elapsed, the special symbol determined in step S313 is stopped and displayed on the first special symbol display device 20 or the second special symbol display device 21. Thereby, the special symbol is stopped and displayed on the first special symbol display device 20 or the second special symbol display device 21, and the player is notified of the jackpot determination result.
Also, when the number of time reduction (J)> 0, 1 is subtracted from the time reduction (J) counter and updated. When the number of time reduction (J) = 0, the time reduction game flag is cleared and the number of high probability games (X )> 0 is updated by subtracting 1 from the high probability game number (X) counter, and if the high probability game number (X) = 0, the high probability game flag is cleared.
Finally, the special symbol special power processing data = 1 is set to the special symbol special power processing data = 2, preparation is made to move to a special symbol stop processing subroutine, and the special symbol variation processing is terminated.

In the special symbol stop process in step S330, the main CPU 110a performs a process of determining whether the special symbol that is stopped and displayed is a “big hit symbol”, a “small bonus symbol”, or a “losing symbol”. Do.
If it is determined that the game is a jackpot symbol, the data stored in the gaming state storage area is referred to and data (00H to 03H) indicating the current gaming state is set in the gaming state buffer. Thereafter, data (high probability game flag and short time game flag) stored in the game state storage area (high probability game flag storage area and the like and short time game flag storage area), high probability game number (X) counter, short time number (J) Clear the counter. Further, the special figure special power processing data = 2 is set to the special figure special electric processing data = 3, preparation is made to move to the jackpot game processing subroutine, and the special symbol stop processing is terminated.

In addition, when it is determined that the small winning symbol, the data stored in the game state storage area is not cleared, and the special figure special electric processing data = 2 to the special figure special electric treatment data = 5 is set. The special symbol stop process is completed by making preparations for transferring to a winning game process subroutine.
On the other hand, if it is determined that the symbol is a lost symbol, the special symbol special electric processing data = 2 is set to special special electric symbol processing data = 0, and the special symbol memory determination processing subroutine is prepared for the special symbol stop processing. finish.

In the jackpot game process of step S340, the main CPU 110a determines which jackpot of the long hit or short hit is to be executed, and performs a process of controlling the determined jackpot.
Specifically, first, with reference to the special electric accessory operating mode determination table, the jackpot release mode is determined based on the type of jackpot symbol (stop symbol data) determined in step S313.

Next, in order to execute the determined jackpot opening mode, the bonus game opening mode table is referred to, the opening time corresponding to the type of jackpot is set in the special game timer counter, and the first jackpot opening / closing solenoid The drive data of 16c (or the second big prize opening / closing solenoid 17c) is outputted to open the first big prize opening / closing door 16b (or the second big prize opening / closing door 17b). At this time, 1 is added to the round game count (R) storage area.
When a specified number of game balls enter during the opening or when the opening time of the grand prize opening has elapsed (the number of the big prize opening (C) = 9 or the special game timer counter = 0), The output of the drive data of the big prize opening / closing solenoid 16c (or the second big prize opening / closing solenoid 17c) is stopped, and the first big prize opening / closing door 16b (or the second big prize opening / closing door 17b) is closed. Thereby, one round game is completed. This round game control is repeated 15 times.

  When the 15 round games are completed (round game count (R) = 15), the data stored in the round game count (R) storage area and the number of winning prize entrance (C) storage areas are cleared, The special figure special electric processing data = 3 is set to the special figure special electric treatment data = 4, preparation is made to move to the big hit game end processing subroutine, and the big hit game processing is ended.

In the jackpot game ending process in step S350, the main CPU 110a determines the probability game state of either the high probability game state or the low probability game state, and changes the game state of either the short-time game state or the non-short-time game state. Perform the decision process.
Specifically, with reference to the jackpot game end setting data table, based on the data stored in the game state buffer and the type of jackpot symbol (stop symbol data) determined in step S313, the high probability game A flag is set, a high probability game count (X) is set, a short-time game flag is set, and a short-time count (J) is set. For example, in the case of the special symbol 1, the high probability game flag is set in the high probability game flag storage area, and the high probability game number (X) counter is set to 10,000 times. Further, the time-shortage game flag is set in the time-shortage game flag storage area, and the time-shortage number (J) counter is set to 10,000 times.
After that, the special symbol special power processing data = 4 is set to the special symbol special power processing data = 0, preparation is made to move to a special symbol memory determination processing subroutine, and the jackpot game end processing is terminated.

In the small hit game process of step S360, the main CPU 110a first refers to the special electric accessory operation mode determination table, and based on the type of small hit symbol (stop symbol data) determined in step S313 above, Determine the opening mode.
Next, in order to execute the determined small winning opening mode, the large winning opening opening mode table is referred to, the small winning opening time is set in the special game timer counter, and the second large winning port opening / closing solenoid 17c is set. The drive data is output to open the second big prize opening / closing door 17b. At this time, 1 is added to the number-of-releases (K) storage area.
When the small winning opening time elapses (special game timer counter = 0), the drive data output of the second big prize opening / closing solenoid 17c is stopped and the second big prize opening / closing door 17b is closed. The opening / closing control of the second big prize opening opening / closing door 17b is repeated 15 times.

  Then, the opening / closing control of the second grand prize opening / closing door 17b is performed 15 times, or a predetermined number of game balls enter the second big prize opening 17 (the number of times of opening (K) = 15 or the grand prize opening entrance) Number (C) = 9), in order to end the small hit game, the output of the driving data of the second large winning opening / closing solenoid 17c is stopped, and the number of times of opening (K) storage area and the number of winning winning openings (C) Clear the data stored in the storage area, set special figure special electricity processing data = 5 to special figure special electricity treatment data = 0, and prepare to move to the special symbol memory judgment processing subroutine. The winning game process is terminated.

[Control processing related to authentication processing of the main control unit]
Hereafter, the control process regarding the authentication process of the main control part 110 of the gaming machine 1 according to the embodiment of the present invention will be described. First, the boot process of the main control unit 110 will be described.
FIG. 14 is a flowchart showing a boot process by the main control unit 110 according to the present embodiment. 14A is a process performed by the main CPU 110a, and the boot process 2 illustrated in FIG. 14B is a process performed by the inspection value generation unit 500.

  When the gaming machine 1 is turned on, a system reset occurs in the main control unit 110, and the main CPU 110a performs the following step S51 as the boot process 1 based on the boot process program stored in the boot ROM 110d in advance. The process shown in step S54 is performed.

In step S51, the main CPU 110a sets the internal state to interrupt prohibition.
In step S52, the main CPU 110a performs a self-diagnosis process for checking whether or not the main CPU 110a itself can operate normally after initialization. As a result of the self-diagnosis process, if the normal operation is possible, the process proceeds to step S53.

  In step S53, the main CPU 110a performs an initial value setting process for a built-in register, a peripheral circuit, and the like. Specifically, the main CPU 110a sets a stack point designation address in the stack pointer, initializes built-in registers and peripheral circuits, and initializes input / output ports. The main CPU 110a sets various initial values in these built-in registers and peripheral circuits that require initial values. At this time, the main CPU 110a performs the same process on each component of the inspection value generation unit 500 to perform an initial value setting process on the inspection value generation unit 500.

  In step S54, the main CPU 110a performs HW parameter setting processing on the inspection value generation unit 500. Specifically, the main CPU 110a sends to the internal bus 400 a read signal for reading the HW parameters for the test value generation unit 500 and address data for designating a storage area in which the HW parameters of the main ROM 110b are stored. Then, the main CPU 110a takes in the HW parameters output from the main ROM 110b by the read signal from the internal bus 400.

  Subsequently, the main CPU 110 a sends to the internal bus 400 a write signal for writing the fetched HW parameter to the determination unit 540 of the test value generation unit 500 and address data specifying the determination circuit 542 of the determination unit 540. Further, the main CPU 110a sends a write signal for writing the fetched HW parameter to the generation unit 520, and address data for designating the shift amount control unit 525c and the reset determination circuit 528 that are responsible for the bit string conversion circuit of the generation unit 520, respectively. 400. When this process ends, the boot process 1 ends.

  Note that the HW parameter setting process in step S54 is a special feature of the process of setting the HW parameter in the test value generation unit 500 among the initial value setting processes performed by the main CPU 110a. Therefore, as part of the initial value setting process, It is also possible to configure so as to be performed in step S53.

  The inspection value generation unit 500 takes in the HW parameters sent from the main CPU 110a from the internal bus 400 based on the input of the write signal from the main CPU 110a. Then, the HW parameter is set to the determination circuit 542 of the determination unit 540 and the shift amount control unit 525c and the reset determination circuit 528 that are responsible for the bit string conversion circuit 525 of the generation unit 520. And the test value production | generation part 500 performs the process shown to the following steps S61-S65 as the boot process 2 based on the HW parameter set from the main CPU110a.

  In step S61, the inspection value generation unit 500 performs a change condition setting process. Specifically, the determination circuit 542 of the determination unit 540 confirms to which change condition the set HW parameter corresponds to a change condition among a plurality of change conditions prepared in advance. Then, the determination circuit 542 sets the change condition corresponding to the set HW parameter in the change condition storage area (CC) as a default change condition. Then, the determination circuit 542 sets the change condition set in the change condition storage area (CC) in the determination circuit 541 of the determination unit 540.

  Accordingly, the determination unit 540 can determine whether or not the control command output from the acquisition unit 510 is a control command that satisfies the change condition during the command transmission process, and the conversion according to the determination result. System setting processing can be performed.

  In step S62, the inspection value generation unit 500 performs an update timing condition setting process. Specifically, the shift amount control unit 525c responsible for the bit string conversion circuit 525 of the generation unit 520 determines that the set HW parameter has a value corresponding to which update timing condition among a plurality of update timing conditions prepared in advance. Check if it exists. Then, the shift amount control unit 525c sets the update timing condition corresponding to the set HW parameter in the update timing condition storage area (UT) as a default condition. Then, it is assumed that the shift amount control unit 525c updates the shift amount A according to the update timing condition set in the update timing condition storage area (UT).

  In step S63, the inspection value generation unit 500 performs a reset condition setting process. Specifically, the reset determination circuit 528 of the generation unit 520 confirms which reset condition the set HW parameter corresponds to among the plurality of reset conditions related to the shift amount A prepared in advance. To do. Then, the reset determination circuit 528 sets a reset condition corresponding to the set HW parameter in the reset condition storage area (RC) as a default condition. The reset determination circuit 528 outputs a shift amount A reset signal according to the reset condition set in the reset condition storage area (RC).

  In step S64, the inspection value generation unit 500 performs conversion method setting processing. Specifically, the determination circuit 542 of the determination unit 540 sets the conversion method information indicating the conversion method A, which is the default conversion method determined in advance, in the conversion method information storage area (CM) as a default value. Based on the value set in the conversion method information storage area (CM), the determination circuit 542 performs the bit string conversion process by the rotation calculator 525a among the plurality of rotate calculators that bear the bit string conversion circuit 525 of the generation unit 520. The conversion method control signal is output to the control circuit 523 of the generation unit 520 so that the error check value subjected to is output. The control circuit 523 of the generation unit 520 outputs an input selection signal corresponding to the conversion method control signal to the input selection circuit 524.

  In step S65, the inspection value generation unit 500 performs a shift amount setting process. Specifically, the control circuit 523 of the generation unit 520 outputs a shift amount setting control signal to the shift amount control unit 525c that takes charge of the bit string conversion circuit 525 based on the input of the conversion method control signal. Based on the input of the shift amount setting control signal output from the control circuit 523, the shift amount control unit 525c responsible for the bit string conversion circuit 525 sends a shift amount A setting signal to the rotate computing unit 525a responsible for the bit string conversion circuit 525. And the default shift amount A stored in the shift amount storage area (S) is set in the rotate calculator 525a. In addition, the shift amount control unit 525c outputs a shift amount B setting signal to the rotate computing unit 525b responsible for the bit string conversion circuit 525 based on the input of the shift amount setting control signal output from the control circuit 523, The default shift amount B stored in the shift amount storage area (S) is set in the rotate calculator 525b.

  Accordingly, the generation unit 520 saves the error check value that has been subjected to the bit rotation operation by the rotation operation unit corresponding to the conversion method information stored in the conversion method information storage area (CM) during the bit string conversion process. 526 can be output. Further, the error check value can be an error check value obtained by converting the bit string by performing the bit rotation operation using the shift amount stored in the shift amount storage area (S). At this time, the shift amount A stored in the shift amount storage area (S) is reset with the reset condition stored in the reset condition storage area (RC). In the command transmission process after the boot process, the main CPU 110a can add the error check value obtained by converting the bit string with the conversion method and the shift amount to the control command when executing the check value addition process. . When this process ends, the boot process 2 ends.

Next, command transmission processing of the main control unit 110 will be described.
FIG. 15 is a flowchart showing the command transmission process 1 in the main control unit 110 according to the present embodiment. FIG. 16 is a flowchart showing command transmission processing 2 in the main control unit 110 according to the present embodiment. FIG. 17 is a flowchart showing the command transmission process 3 in the main control unit 110 according to the present embodiment.

  The command transmission process 1 shown in FIG. 15 is a process performed by the main CPU 110a. Also, the command transmission process 2 shown in FIG. 16 is performed by the inspection value generation unit 500 when transmission data (control command or error inspection value) is transmitted from the main CPU 110a to the transmission unit 550 via the internal bus 400. Process. The command transmission process 3 shown in FIG. 17 is a process performed by the test value generation unit 500 when the main CPU 110a performs the test value addition process, and responds to the process of the main CPU 110a shown in step S77 of FIG. It is done.

First, the command transmission process 1 will be described with reference to FIG.
The main CPU 110a reads "MODE" information and "DATA" information from the main ROM 110b, generates a control command, and sets it in the transmission data storage area of the main RAM 110c. Then, the main CPU 110a performs the process shown in the following steps S71 to S78 as the command transmission process 1.

In step S71, the main CPU 110a updates the transmission number storage area (P) of the main RAM 110c by adding 1.
In step S72, the main CPU 110a determines whether or not the control command (P) set in the transmission data storage area corresponds to the control command (1). Specifically, the main CPU 110a refers to the value of the sending number storage area (P) and determines whether P = 1. If P = 1, the process proceeds to step S73, and if P = 1, the process proceeds to step S75.

In step S73, the main CPU 110a reads the unique information stored in the main ROM 110b.
In step S 74, the main CPU 110 a sends the read unique information to the inspection value generation unit 500 via the internal bus 400, and the read unique information is stored in the initial stage of the storage circuit 522 serving as the generation unit 520 of the inspection value generation unit 500. Set as a setting value. At this time, in the inspection value generation unit 500, the unique information sent from the main CPU 110 a is taken in from the internal bus 400 by the acquisition unit 510 and output to the generation unit 520. Then, the unique information output from the acquisition unit 510 is stored in each of the storage circuits (P-1) to (P-N) serving as the storage circuit 522 by the generation unit 520.

  In step S75, the main CPU 110a writes the control command (P) set in the transmission data storage area to the transmission unit 550. Specifically, the main CPU 110a sends a control command (P) to the data bus 400a of the internal bus 400, address data designating the transmission unit 550 to the address bus 400b, and a write signal of the control command (P) to the control bus 400c. To do.

  In the transmission unit 550, when the control command (P) write signal sent from the main CPU 110a and the address data designating the transmission unit 550 are input, the control command (P) is sent from the data bus 400a to the transmission buffer 551. The captured control command (P) is transferred to the transmission circuit 552 and transmitted to the intermediate control unit 180.

  In step S76, the main CPU 110a determines whether or not the current command transmission process is a timing for adding an error check value to the transmitted control command (P). It is determined whether or not it is time to add the error check value depending on whether or not a call instruction for the authentication processing program is described in the game processing program. The main CPU 110a moves the process to step S77 if the current command transmission process is the timing for adding the error check value to the control command (P), and the command transmission process 1 if it is not the timing for adding the error check value. Exit.

The main CPU 110a performs the processing shown in the following steps S77 to S78 as the check value addition processing at the timing for adding the error check value to the control command (P) written in the transmission unit 550.
In step S77, the main CPU 110a reads an error check value from the check value generation unit 500. Specifically, the main CPU 110a sends the address data specifying the sending circuit 527 responsible for the generating means 520 of the check value generating unit 500 to the address bus 400b of the internal bus 400 and the error check value read signal to the control bus 400c. .

  The check value generation unit 500 performs processing for sending the error check value stored in the storage circuit 526 in advance to the main CPU 110a based on the input of the read signal from the main CPU 110a. This process will be described later with reference to FIG. Then, the main CPU 110a fetches the error check value (PN) read from the check value generation unit 500 from the data bus 400a, sets it in the transmission data storage area of the main RAM 110c, and moves the process to step S78.

  In step S78, the main CPU 110a writes the error check value (PN) set in the transmission data storage area to the transmission unit 550. Specifically, the main CPU 110a writes the error check value (PN) to the data bus 400a of the internal bus 400, the address data designating the transmission unit 550 to the address bus 400b, and the error check value to the control bus 400c. Send a write signal. When this process ends, the command transmission process 1 ends.

  In the transmission unit 550, when an error check value (PN) write signal sent from the main CPU 110a and address data designating the transmission unit 550 are input, an error check value (PN) is transmitted from the data bus 400a. ) In the transmission buffer 551, the fetched error check value (PN) is transferred to the transmission circuit 552 and transmitted to the intermediate control unit 180.

  In step S78, the timing at which the main CPU 110a writes the error check value (PN) to the transmission unit 550 is within the execution period of the timer interrupt process, and the control command (P) is written to the transmission buffer 551. The timing is set such that writing of the error check value (PN) to the transmission buffer 551 is started after the time required for completion has elapsed. As a result, the error check value (PN) is written into the transmission buffer 551 so that the error check value (PN) is written immediately after the control command (P) written in the transmission buffer 551. The timing will be right.

  By setting the write timing of the error check value to the transmission unit 550 as described above, an overrun or underrun of the transmission buffer 551 occurs, and an error check to be added to the control command (P) to be transmitted The possibility that the value (P−N) is not appropriately added can be suppressed. This is because the error check value actually added and transmitted during the error check process in the intermediate control unit 180 is not consistent with the error check value to be originally added. It is possible to suppress a possibility that the inspection result is not determined to be normal, and to improve the accuracy of the error inspection process.

  In addition, by setting the write timing of the error check value to the transmission unit 550 as described above, the write timing of the error check value (PN) to be added this time to the transmission buffer 551 and the control command (P) The positional relationship on the time axis of the write timing to the transmission buffer 551 is clarified, and the error check value (PN) is reliably added immediately after the control command (P) and transmitted as one transmission data. It will be. Thereby, the error check value (PN) is not transmitted to the intermediate control unit 180 as a single error check value (PN). Therefore, it becomes difficult for an unauthorized person to steal transmission data between the main control unit 110 and the intermediate control unit 180 and reuse the error check value (PN), and the security strength of the gaming machine 1 is improved. can do.

Next, the command transmission process 2 will be described with reference to FIG.
In the command transmission process 1 of FIG. 15, the test value generation unit 500 receives the command transmission process 2 when transmission data (control command or error check value) is transmitted from the main CPU 110 a to the transmission unit 550 via the internal bus 400. As shown in FIG.

In step S81, the test value generation unit 500 determines whether transmission data (control command or error check value) has been written from the main CPU 110a to the transmission unit 550. Specifically, the acquisition unit 510 of the test value generation unit 500 has received a write signal sent from the main CPU 110 a to the transmission unit 550 and also input from the control bus 400 c of the internal bus 400 to the control circuit 512 of the acquisition unit 510. Judge whether or not. The control circuit 512 waits until the write signal is input, and when the write signal is input, the process proceeds to step S82.
In step S <b> 82, the test value generation unit 500 takes in the transmission data transmitted from the main CPU 110 a to the transmission unit 550 from the data bus 400 a of the internal bus 400. Specifically, the control circuit 512 of the acquisition unit 510 operates to cause the data determination circuit 511 of the acquisition unit 510 to capture the transmission data transmitted to the data bus 400a based on the input of the write signal. Output permission signal. The data discriminating circuit 511 takes in the transmission data from the data bus 400a based on the input of the operation permission signal.

In step S83, the test value generation unit 500 determines whether or not the fetched transmission data is a control command (P). Specifically, the data determination circuit 511 of the acquisition unit 510 determines whether or not the bit pattern of the transmission data fetched from the data bus 400a of the internal bus 400 indicates a control command (P). If the bit pattern of the fetched transmission data indicates the control command (P), the data discrimination circuit 511 moves to step S85, and the bit pattern of the fetched transmission data indicates the control command (P). If not, the process proceeds to step S84.
In step S84, the test value generation unit 500 discards the fetched transmission data. Specifically, if the fetched transmission data is not a control command (P), the data determination circuit 511 of the acquisition unit 510 discards the transmission data and ends the command transmission process 2. Note that the transmission data in this case is an error check value sent to the data bus 400a for the main CPU 110a to perform a check value addition process and write it to the transmission unit 550.

  In step S85, the inspection value generation unit 500 outputs the acquired control command (P) to the determination unit 540 and the generation unit 520 inside the inspection value generation unit 500. Specifically, the control circuit 512 of the acquisition unit 510 outputs an operation permission signal to the data determination circuit 511 after a predetermined time delay from the input of the write signal sent from the main CPU 110a. The data determination circuit 511 outputs the captured control command (P) to the determination unit 540 and the generation unit 520 based on the input of the operation permission signal. Subsequently, the control circuit 512 outputs an operation permission signal to these means so that the control command output from the data determination circuit 511 can be input by the determination means 540 and the generation means 520.

  In step S86, the inspection value generation unit 500 determines whether or not the fetched control command (P) is a control command that satisfies the change condition. Specifically, the determination circuit 541 of the determination unit 540 determines that the control command (P) is the first in a predetermined control command group based on the input of the operation permission signal output from the control circuit 512 of the acquisition unit 510. It is determined whether or not any of the control command generated at the first time and the control command generated first after the generation of the predetermined control command group is completed. The determination circuit 541 determines that the control command (P) output from the acquisition unit 510 is a control command satisfying the change condition if the control command (P) is a control command corresponding to one of the control commands. The signal is output to the determination circuit 542, and the process proceeds to step S87. On the other hand, the determination circuit 541 determines that the control command (P) output from the acquisition unit 510 is not a control command that satisfies the change condition unless the control command (P) is a control command corresponding to any of the above. The result signal is output to the decision circuit 542, and the process proceeds to step S88.

  In step S87, the check value generation unit 500 changes the conversion method used when converting the bit string of the error check value. Specifically, the determination circuit 542 of the determination unit 540 changes the CM value indicating the conversion method information stored in the conversion method information storage area (CM) in order to change the conversion method. Specifically, the decision circuit 542 changes the CM value indicating the conversion method information in accordance with a predetermined change method, and sets CM ′, which is the CM value indicating the changed conversion method information, as a conversion method information storage area. Store in (CM). Then, the determination circuit 542 generates a conversion method control signal based on the changed CM ′ value stored in the conversion method information storage area (CM) so as to set the changed conversion method in the generation unit 520. It outputs to the control circuit 523 of 520.

  The control circuit 523 of the generation unit 520 is based on the conversion method control signal output from the determination circuit 542, and the specific rotation arithmetic unit and the generation unit among the plurality of rotation arithmetic units responsible for the bit string conversion circuit 525 of the generation unit 520 An input selection signal that enables only the connection with the input selection circuit 524 of 520 is output to the input selection circuit 524. Based on the input selection signal, the input selection circuit 524 sets a connection with a specific rotation calculator. When the input selection signal is input to the input selection circuit 524, the generation unit 520 converts the error check value obtained by converting the bit string by the specific rotation arithmetic unit according to the conversion method after the change into the input selection circuit 524. The data can be stored in the storage circuit 526 via In addition, the control circuit 523 of the generation unit 520 outputs a shift amount setting control signal to the shift amount control unit 525c that takes charge of the bit string conversion circuit 525 based on the input of the conversion method control signal output from the determination circuit 542. Accordingly, the shift amount control unit 525c can detect that the period of the predetermined operation mode has started or ended.

  In step S88, the test value generation unit 500 determines whether or not the fetched control command (P) is a control command that satisfies the reset condition. Specifically, the reset determination circuit 528 of the generation unit 520 determines that the control command (P) is a control command other than a predetermined control command group based on the input of the operation permission signal output from the control circuit 523. To determine whether or not a predetermined control command is satisfied. If the control command (P) corresponds to the predetermined control command, the reset determination circuit 528 outputs a shift amount A reset signal to the bit string conversion circuit 525, and proceeds to step S89. On the other hand, if the control command (P) does not correspond to the predetermined control command, the reset determination circuit 528 proceeds to step S90 without outputting the shift amount A reset signal.

  In step S89, the inspection value generation unit 500 resets the shift amount A. Specifically, the shift amount control unit 525c responsible for the bit string conversion circuit 525 of the generation unit 520 stores the shift amount in the shift amount storage area (S) based on the input of the shift amount A reset signal output from the reset determination circuit 528. A predetermined set value prepared in advance is overwritten and stored in the shift amount A. Then, the shift amount control unit 525c outputs a shift amount A setting signal to the rotate calculator 525a, and sets the overwritten shift amount A stored in the shift amount storage area (S) in the rotate calculator 525a. In the bit string conversion circuit 525, the error check value subjected to the bit string conversion processing by the conversion method A using the reset shift amount A can be stored in the storage circuit 526 via the input selection circuit 524.

  In step S90, the test value generation unit 500 stores the acquired control command (P) and outputs the control command (PN) stored in the past to the internal generation circuit 521. Specifically, the control circuit 523 of the generation unit 520 outputs a shift processing signal to the storage circuit 522 based on the input of the operation permission signal output from the control circuit 512 of the acquisition unit 510. Based on the input of the shift processing signal output from the control circuit 523, the storage circuit 522, from among the storage circuits (P-1) to (PN), from the storage circuit (PN) at the final stage, The control command (PN) stored in the storage circuit is output to the generation circuit 521. At the same time, the storage circuit 522 sequentially shifts the control commands stored in the storage circuits (P-1) to (PN) to the next stage and controls the data output from the data determination circuit 511 of the acquisition unit 510. The command (P) is newly fetched and stored in the first stage storage circuit (P-1).

  In step S91, the check value generation unit 500 generates an error check value (PN) using the control command (PN) stored in the past, and outputs the error check value (PN) to the internal bit string conversion circuit 525. Specifically, the generation circuit 521 of the generation unit 520 takes in the control command (PN) output from the storage circuit 522 based on the input of the operation permission signal output from the control circuit 523 of the generation unit 520. . Then, the generation circuit 521 generates an error check value (PN) by a preset generation method using the fetched control command (PN), and outputs the error check value (PN) to the bit string conversion circuit 525.

  In step S <b> 92, the check value generation unit 500 performs bit string conversion processing on the generated error check value (PN), and outputs it to the storage circuit 526 via the internal input selection circuit 524. Specifically, the rotation calculator 525a that takes charge of the bit string conversion circuit 525 of the generation unit 520 takes in the error check value (PN) output from the generation circuit 521, and takes in the error check value (PN). The bit rotation calculation is performed with a shift amount A set in advance in the bit string. Then, the rotation calculator 525a uses the error check value (PN) that has been subjected to the bit rotation calculation with the shift amount A as the error check value (PN) that has been subjected to the bit string conversion processing by the conversion method A. The data is output to the input selection circuit 524. In addition, the rotation calculator 525b of the bit string conversion circuit 525 takes in the error check value (PN) output from the generation circuit 521, and shifts a preset bit string of the fetched error check value (PN). A bit rotate operation is performed with the quantity B. Then, the rotation calculator 525b uses the error check value (PN) that has been subjected to the bit rotation calculation with the shift amount B as the error check value (PN) that has been subjected to the bit string conversion processing by the conversion method B. The data is output to the input selection circuit 524 and the shift amount control unit 525c.

  In step S93, the check value generation unit 500 stores the error check value (PN) obtained by converting the bit string. Specifically, the input selection circuit 524 of the generation unit 520 effectively operates only the connection with any one of the rotation calculators 525a and 525b based on the input selection signal output from the control circuit 523. Therefore, the bit string conversion circuit 525 uses only the error check value output from the specific rotation operator whose connection with the input selection circuit 524 is effectively operated as the error check value (PN) obtained by converting the bit string. The data is output to the storage circuit 526. The storage circuit 526 stores the error check value (PN) obtained by converting the bit string output from the bit string conversion circuit 525 via the input selection circuit 524.

  In step S94, the inspection value generation unit 500 determines whether or not it is a shift amount update timing. Specifically, the shift amount control unit 525c responsible for the bit string conversion circuit 525 of the generation unit 520 starts or ends the period of the predetermined operation mode based on the input of the shift amount setting control signal output from the control circuit 523. Is detected, and it is determined whether or not the present operation is in a predetermined operation mode. Then, the shift amount control unit 525c determines that it is time to update the shift amount A and the shift amount B at the time when the current period of the predetermined operation mode starts, and moves the process to step S95. . In addition, if the current time is during the predetermined operation mode, the shift amount control unit 525c determines that it is now the time to update only the shift amount B, and moves the process to step S95. In addition, the shift amount control unit 525c determines that the current timing is when the update of the shift amount B is stopped if the current operation period ends, and the process proceeds to step S95. On the other hand, the shift amount control unit 525c is not currently at the timing to update the shift amount unless it is the time when the current period of the predetermined operation mode starts or ends, or the current time is not during the period of the predetermined operation mode. The command transmission process 2 is terminated.

  In step S95, the inspection value generation unit 500 controls the shift amount. Specifically, the shift amount control unit 525c responsible for the bit string conversion circuit 525 of the generation unit 520 updates the shift amount A and the shift amount B when the current period of the predetermined operation mode starts. That is, the shift amount control unit 525c performs the shift amount setting process related to the shift amount A based on the error check value output from the rotate computing unit 525b and the shift amount A stored in the shift amount storage area (S). The value is updated according to a predetermined update method related to the shift amount A. Then, the shift amount control unit 525c outputs a shift amount A setting signal to the rotate calculator 525a, and sets the updated shift amount A stored in the shift amount storage area (S) in the rotate calculator 525a. In addition, the shift amount control unit 525c acquires a random value as a shift amount setting process related to the shift amount B, and updates the value of the shift amount B stored in the shift amount storage area (S) using the random number value. Then, the shift amount control unit 525c outputs a shift amount B setting signal to the rotate calculator 525b, and sets the updated shift amount B stored in the shift amount storage area (S) in the rotate calculator 525b.

  In addition, the shift amount control unit 525c updates only the shift amount B if the current time is during the predetermined operation mode. That is, as the shift amount setting process for the shift amount B, the shift amount control unit 525c acquires a random number value, updates the value of the shift amount B stored in the shift amount storage area (S), and sets the shift amount B. A signal is output and the updated shift amount B is set in the rotate calculator 525b. In addition, the shift amount control unit 525c discards the error check value output from the rotation computing unit 525b without updating the shift amount B when the current period of the predetermined operation mode ends. When this process ends, the command transmission process 2 ends.

  Note that the process of step S90 only needs to be performed between step S85 and step S91, and need not be performed immediately after step S89. Moreover, the process of step S88 and step S89 should just be performed between step S85 to step S92, and does not need to be performed immediately after step S87.

Next, the command transmission process 3 will be described with reference to FIG.
In the command transmission process 1 in FIG. 15, the test value generation unit 500 responds to the error check value read signal sent from the main CPU 110 a when the main CPU 110 a performs the test value addition process. The following steps S101 to S103 are performed.

In step S <b> 101, the test value generation unit 500 receives an error check value read signal sent from the main CPU 110 a and address data designating the sending circuit 527 serving as the generation means 520 of the check value generation unit 500. Then, the process proceeds to step S102.
In step S <b> 102, the sending circuit 527 of the check value generation unit 500 outputs an operation permission signal to the storage circuit 526 and takes in the error check value (PN) stored in the storage circuit 526.

  In step S103, the sending circuit 527 of the check value generation unit 500 sends the fetched error check value (PN) to the data bus 400a. Thus, the main CPU 110a can acquire the error check value (PN) stored in the storage circuit 526. Note that the error check value (P−N) stored in the storage circuit 526 is an error check value obtained by converting the bit string by either the conversion method A or the conversion method B by the bit string conversion circuit 525, and the control command (P ) Is added with an error check value (PN) obtained by converting the bit string by either the conversion method A or the conversion method B. When this process ends, the command transmission process 3 ends.

[Control processing of intermediate control unit]
Hereafter, the control process of the intermediate control unit 180 of the gaming machine 1 according to the embodiment of the present invention will be described.
FIG. 18 is a flowchart showing main processing by the intermediate control unit 180 according to the present embodiment.

  In step S4010, the CPU 180a performs initialization processing. In this process, the CPU 180a reads a program code related to the main process from the ROM 180b in response to power-on. At the same time, the CPU 180a initializes a flag and the like stored in the RAM 180c and performs a process of setting a setting value.

  In step S4010, processing for setting an error check value output function corresponding to the error check value generation function of the main control unit 110 to the check value generation unit 620 is performed. That is, the CPU 180a performs the HW parameter setting process, the change condition setting process, the update timing condition setting process, the reset condition setting process, the conversion method setting process, and the shift amount setting process executed during the boot process in the main control unit 110. Similar processing is performed. At that time, the CPU 180a determines the default conversion method, the update timing condition related to the shift amount A, and the reset condition related to the shift amount A by the determination unit 623, and according to the determined conversion method, update timing condition, and reset condition. The bit string conversion unit 624 is set. If this process ends, the process moves to a step S4020.

In step S4020, CPU 180a determines whether or not the control command transmitted from main control unit 110 has been received.
When the reception unit 600 of the intermediate control unit 180 receives the control command transmitted from the main control unit 110 and stores it in its own reception buffer, it indicates that the main control unit 110 has received a control command reception interrupt request. A signal is output to generate a control command reception interrupt process.
In step S4020, the CPU 180a waits until the reception interrupt request signal from the reception unit 600 is input. When the signal from the reception unit 600 is input, the CPU 180a stores the control command stored in the reception buffer. Error check processing is performed on Specifically, it is the process of the next step S4030 to step S4230.

In step S4030, when a signal indicating that a control command reception interrupt request has been made is output from the reception unit 600, the CPU 180a updates the value of the reception number storage area (P) of the RAM 180c.
In step S4040, the CPU 180a determines whether or not the control command (P) stored in the reception buffer of the reception unit 600 corresponds to the control command (1). Specifically, the CPU 180a refers to the value of the received number storage area (P) and determines whether P = 1. If P = 1, the process proceeds to step S4050, and if P = 1, the process proceeds to step S4070.

In step S4050, the CPU 180a reads unique information stored in the ROM 180b. Then, the CPU 180a outputs the read unique information to the inspection value generation unit 620.
In step S4060, the CPU 180a stores the unique information output to the inspection value generation unit 620 in the storage unit 622 in the inspection value generation unit 620, and sets it as an initial setting value.

  In step S4070, CPU 180a determines whether or not an error check value is added to the control command (P) stored in the reception buffer of reception unit 600. The CPU 180a, for example, checks the error in the control command (P) based on whether or not the data length has increased due to the addition of the error check value, or whether or not there is an identification bit identifying that the error check value has been added. It can be determined whether or not a value is added. If an error check value is added to the control command (P) stored in the reception buffer of the reception unit 600, the CPU 180a moves the process to step S4090.

On the other hand, if an error check value is not added to the control command (P) stored in the reception buffer of the receiving unit 600, the CPU 180a sends the control command (P) to the storage unit 622 and the determining unit of the check value generating unit 620. 623 and the relay transmission unit 640, and the process proceeds to step S4080.
In step S4080, CPU 180a immediately transmits control command (P) as transmission data to effect control unit 120 at relay transmission unit 640, and proceeds to step S4110.

In step S4090, the CPU 180a extracts the error check value (PN) added to the control command (P) from the control command (P) stored in the reception buffer of the reception unit 600.
In step S4100, the CPU 180a outputs the extracted error check value (PN) to the check unit 610, and outputs the control command (P) after extracting the error check value (PN) to the check value generation unit 620. The data is output to the storage unit 622, the determination unit 623, and the addition unit 630.

  In step S4110, the CPU 180a takes in the control command (P) output from the receiving unit 600, and the determining unit 623 determines whether the control command (P) is a control command that satisfies the change condition. Specifically, the CPU 180a controls the control command (P) to be generated first after the control command generated first in the predetermined control command group and the generation of the predetermined control command group is finished. It is determined whether it corresponds to one of the commands. If the control command (P) is one of the control commands, the CPU 180a determines that the extracted control command (P) is a control command that satisfies the change condition, and moves the process to step S4120. On the other hand, if the control command (P) is not a control command corresponding to any of the control commands, the CPU 180a determines that the extracted control command (P) is not a control command satisfying the change condition, and moves the process to step S4130. .

  In step S4120, the CPU 180a changes the conversion method, and sets the changed conversion method in the bit string conversion unit 624. Specifically, the CPU 180a changes the conversion method information stored in the conversion method information storage area (CM) according to a predetermined change method, and converts the changed conversion method information into the conversion method information storage area (CM). Remember me. Then, the CPU 180a sets the conversion method corresponding to the converted conversion method information stored in the conversion method information storage area (CM) in the bit string conversion unit 624 by the determination unit 623. In the bit string conversion unit 624, an error check value that has been subjected to the bit string conversion processing by the conversion method after the change can be output to the check unit 610.

  In step S4130, the CPU 180a takes in the control command (P) output from the receiving unit 600, and the determining unit 623 determines whether the control command (P) is a control command that satisfies the reset condition related to the shift amount A. To do. Specifically, the CPU 180a determines whether or not the control command (P) corresponds to a predetermined control command from control commands other than a predetermined control command group. If the control command (P) corresponds to the predetermined control command, the CPU 180a determines that the extracted control command (P) is a control command that satisfies the reset condition related to the shift amount A, and step S4140. Move processing to. On the other hand, if the control command (P) does not correspond to the predetermined control command, the CPU 180a determines that the extracted control command (P) is not a control command that satisfies the reset condition related to the shift amount A, The process moves to step S4150.

  In step S4140, the CPU 180a resets the shift amount A. Specifically, the CPU 180a overwrites and stores a predetermined set value prepared in advance on the shift amount A stored in the shift amount storage area (S). Then, the CPU 180a sets the overwritten shift amount A stored in the shift amount storage area (S) in the bit string conversion unit 624 by the determination unit 623. In the bit string conversion unit 624, an error check value that has been subjected to the bit string conversion processing by the conversion method A using the reset shift amount A can be output to the check unit 610.

In step S4150, the CPU 180a stores the control command (P) output from the receiving unit 600 in the storage unit 622 and generates the control command (PN) stored in the past from the storage unit 622. Output to 621.
In step S4160, the CPU 180a uses the control command (PN) output from the storage unit 622 to generate an error check value (PN) using the preset generation method in the generation unit 621. The data is output to the bit string conversion unit 624.

  In step S4170, the CPU 180a performs a bit string conversion process on the error check value (PN) generated by the generation unit 621 by the bit string conversion unit 624, and outputs the result to the check unit 610. Specifically, if the conversion method set by the determination unit 623 is conversion method A, the CPU 180a uses a bit amount of a preset shift amount A with respect to the bit sequence of the error check value (PN). The conversion unit 624 performs a bit rotation operation. Then, the CPU 180a outputs the error check value (PN) returned to the original bit string, which is the obtained calculation result, to the check unit 610.

  In addition, when the conversion method set by the determination unit 623 is conversion method B, the CPU 180a, for the bit string of the error check value (PN), the bit of the bit string of the error check value (PN). The bit string conversion unit 624 performs bit rotation calculation for the number of rotations that can be taken by the number of rotations defined by the width. Then, the CPU 180a outputs error check values (PN) corresponding to the number of ranges that can be taken by the rotation number, to which the bit string is converted, to the check unit 610, respectively.

  In step S4180, if the error check value (PN) is output from the receiving unit 600, the CPU 180a and the error check value (P-N) output from the bit string converting unit 624 and the error check value (P-N) are output. -N) is compared by the inspection unit 610 and collated. If the two match, the CPU 180a determines that the inspection result of the error inspection is normal. On the other hand, if the two do not match, the CPU 180a determines that the inspection result is not normal. Although illustration is omitted, if the error checking value (PN) is not output from the receiving unit 600, the CPU 180a does not perform the matching process in the checking unit 610 and moves the process to step S4220.

  When the conversion method B is set and the error check values (PN) are output from the bit string conversion unit 624 for the number of rotations that can be taken, the CPU 180a outputs all the error checks that have been output. The value (P−N) is compared with the error check value output from the receiving unit 600 and collated. At this time, if any error check value (PN) output from the bit string conversion unit 624 matches the error check value output from the reception unit 600, the CPU 180a determines that the check result is normal. If any error check value (PN) does not match the error check value output from the receiving unit 600, it is determined that the check result is not normal.

  In step S4190, CPU 180a determines whether or not the inspection result is normal in inspection unit 610. When it is determined that the inspection result is normal, the CPU 180a generates the control command (P) to which the currently received error check value (PN) is added and the current error check value (PN). It is determined that the validity of the main control unit 110 has been authenticated because the validity of the original N previous control commands (PN) has been authenticated. Then, the CPU 180a determines that the gaming machine 1 is operating normally, and moves the process to step S4200. On the other hand, if it is determined that the test result is not normal, the CPU 180a determines that the validity of the main control unit 110 has not been authenticated. Then, the CPU 180a determines that there is a possibility that an illegal act or the like has occurred in the gaming machine 1, and moves the process to step S4210.

In step S4200, CPU 180a generates authentication result data indicating successful authentication in inspection unit 610, outputs the generated authentication result data to adding unit 630, and moves the process to step S4220.
In step S4210, the CPU 180a generates authentication result data indicating unsuccessful authentication in the inspection unit 610, outputs the generated authentication result data to the adding unit 630, and shifts the processing to step S4240.

  In step S4220, CPU 180a determines in decision unit 623 whether or not the present time is the timing for updating the shift amount. Specifically, CPU 180a determines that it is now time to update shift amount A at the time when the period of the predetermined operation mode starts, and moves to step S4230. . CPU 180a determines that it is not the time to update shift amount A at the current time unless the current period of the predetermined operation mode starts, and determines that determination unit 623 moves the process to step S4230.

  In step S4230, the CPU 180a controls the shift amount. Specifically, the CPU 180a sets the conversion method B at the time when the period of the predetermined operation mode starts, and sets the conversion method B and outputs a plurality of (rotate counts) output from the bit string conversion unit 624 to the inspection unit 610. The error check value (PN) that matches the error check value output from the receiving unit 600 among the error check values (PN) of the number of obtained ranges) is output to the determining unit 623. Further, the CPU 180a does not output an error check value (PN) from the receiving unit 600 to the checking unit 610, and even if the collation process is not performed in step S4180, the CPU 180a is currently in a predetermined operation mode. When the period starts, the error check value (PN) output from the bit string conversion unit 624 to the check unit 610 is output to the determination unit 623. Then, CPU 180a updates shift amount A in accordance with a predetermined update method based on the error check value, and moves the process to step S4240.

In step S4240, the CPU 180a adds the authentication result data output from the inspection unit 610 to the control command (P) output from the receiving unit 600, and adds a control command with authentication result data. (P) is output to the relay transmission unit 640, and the process proceeds to step S4250.
In step S4250, CPU 180a immediately transmits control command (P) with authentication result data as transmission data to effect control unit 120 at relay transmission unit 640. Thereafter, the processes after step S4020 are repeated until a predetermined interrupt process is performed.

  Note that the process of step S4150 only needs to be performed between step S4100 and step S4160, and need not be performed immediately after step S4140. Moreover, the process of step S4130 and step S4140 should just be performed between step S4100 to step S4170, and does not need to be performed immediately after step S4120. Further, the processes in step S4220 and step S4230 may be performed after step S4180, and need not be performed immediately after step S4200. Further, after the process of step S4210, the process may be transferred to step S4220 instead of the process to step S4240.

[Control processing of production control unit]
Hereafter, the control process of the production control unit 120 of the gaming machine 1 according to the embodiment of the present invention will be described. First, the main process of the production control unit 120 will be described.
FIG. 19 is a flowchart showing main processing by the effect control unit 120 according to the present embodiment.

  In step S1000, the sub CPU 120a performs an initialization process. In this process, the sub CPU 120a reads the program code related to the main process from the sub ROM 120b in response to power-on. At the same time, the sub CPU 120a performs processing for initializing a flag and the like stored in the sub RAM 120c and setting a setting value. If this process ends, the process moves to a step S1100.

  In step S1100, the sub CPU 120a performs an effect random number update process. In this process, the sub CPU 120a performs a process of updating the effect random number value, effect design determining random number, effect mode determining random number and the like stored in the sub RAM 120c. Thereafter, the process of step S1100 is repeated until a predetermined interrupt process is performed.

Next, the interruption process of the production control unit 120 will be described.
FIG. 20 is a flowchart showing interrupt processing by the effect control unit 120 according to the present embodiment.
Based on a clock signal output from a clock pulse generation circuit (not shown) provided in the effect control unit 120, the sub CPU 120a performs timer allocation of the effect control unit 120 every predetermined period (for example, 2 milliseconds). Execute the included process.

In step S1200, the sub CPU 120a saves the information stored in the register of the sub CPU 120a to the stack area.
In step S1300, the sub CPU 120a performs update processing of various timer counters used in the effect control unit 120.

  In step S1500, the sub CPU 120a performs command analysis processing. In this process, the sub CPU 120a performs a process of analyzing the type of control command stored in the received data storage area of the sub RAM 120c.

When the receiving unit (not shown) of the effect control unit 120 receives the control command transmitted from the intermediate control unit 180 and stores it in its own reception buffer, there is a control command reception interrupt request from the intermediate control unit 180. A signal indicating that the control command has been received is generated, and a control command reception interrupt process is generated.
Then, the sub CPU 120a performs an authentication result data analysis process for analyzing the contents of the authentication result data added to the received control command. When the sub-CPU 120a confirms that the validity of the control command has been authenticated by the intermediate control unit 180 in the authentication result data analysis process, the sub-CPU 120a takes the control command from the reception buffer into the reception data storage area of the sub RAM 120c and stores it. To do. Then, the sub CPU 120a analyzes the type of the control command stored in the received data storage area, and performs processing according to the type of the control command. Details of the command analysis process will be described later.

In step S <b> 1700, the sub CPU 120 a checks the signal of the effect button detection switch 35 a, and performs effect input control processing related to input from the effect button 35.
In step S1800, the sub CPU 120a performs an effect output control process that is a process for transmitting the control command and various data set in the transmission data storage area of the sub RAM 120c to the lamp control unit 140 and the image control unit 150. Do.
In step S1900, the sub CPU 120a restores the information saved in step S1200 to the register of the sub CPU 120a.

Next, command analysis processing of the effect control unit 120 will be described.
21 and 22 are flowcharts showing command analysis processing by the effect control unit 120 according to the present embodiment. Note that the command analysis processing 2 in FIG. 22 is performed subsequent to the command analysis processing 1 in FIG.

In step S1501, the sub CPU 120a checks whether a control command is stored in the reception buffer of the receiving unit 600, and determines whether the control command has been received.
If the control command is stored in the reception buffer, the sub CPU 120a moves the process to step S1650, and if the control command is not stored in the reception buffer, the sub CPU 120a ends the command analysis process.

  In step S1650, the sub CPU 120a performs an authentication result data analysis process on the authentication result data added to the control command stored in the reception buffer. Then, when the sub controller 120a can confirm that the validity of the control command has been authenticated by the intermediate control unit 180, the sub CPU 120a takes the received control command into the received data storage area and moves the process to step S1510. The details of the authentication result data analysis process will be described later.

In step S1510, the sub CPU 120a checks whether or not the control command stored in the received data storage area is a demo designation command.
If the control command stored in the received data storage area is a demo designation command, the sub CPU 120a moves the process to step S1511, and if not, moves the process to step S1520.

In step S1511, the sub CPU 120a performs a demonstration effect pattern determination process for determining a demonstration effect pattern.
Specifically, the demonstration effect pattern is determined, the determined demonstration effect pattern is set in the effect pattern storage area, and information on the determined demonstration effect pattern is transmitted to the image control unit 150 and the lamp control unit 140. An effect pattern designation command based on the demo effect pattern is set in the transmission data storage area of the sub-RAM 120c.

In step S1520, sub CPU 120a checks whether or not the control command stored in the reception data storage area is a special symbol storage designation command.
If the control command stored in the received data storage area is the special symbol storage designation command, the sub CPU 120a moves the process to step S1521, and moves to step S1530 if it is not the special symbol storage designation command.

  In step S1521, the sub CPU 120a analyzes the special symbol storage designation command to determine the number of reserved images of special symbols to be displayed on the liquid crystal display device 31 (hereinafter referred to as “special diagram reserved images”). The special symbol display number designation command corresponding to the display number of the special figure reserved images is transmitted to the image control unit 150 and the lamp control unit 140, and a special symbol storage number determination process is performed.

In step S1530, the sub CPU 120a checks whether or not the control command stored in the received data storage area is an effect designating command.
If the control command stored in the storage area for received data is an effect designating command, the sub CPU 120a moves the process to step S1531, and moves to step S1540 if it is not an effect designating command.

In step S1531, the sub CPU 120a performs an effect symbol determination process for determining an effect symbol 36 to be stopped and displayed on the liquid crystal display device 31 based on the content of the received effect symbol designation command.
Specifically, the effect designating command is analyzed, the effect symbol data constituting the combination of the effect symbols 36 is determined according to the presence / absence of jackpot and the type of jackpot, and the determined effect symbol data is stored in the effect symbol storage area In addition, in order to transmit the effect symbol data to the image control unit 150 and the lamp control unit 140, a stop symbol designation command indicating the effect symbol data is set in the transmission data storage area of the sub RAM 120c.

  In step S1532, the sub CPU 120a acquires one random value from the effect mode determination random value updated in step S1100, and based on the acquired effect mode determination random value and the received effect designating command, An effect mode determination process for determining one effect mode from a plurality of effect modes (for example, a normal effect mode and a chance effect mode) is performed. Further, the determined effect mode is set in the effect mode storage area.

In step S1540, the sub CPU 120a checks whether or not the control command stored in the received data storage area is a variation pattern designation command.
If the control command stored in the storage area for received data is a variation pattern designation command, the sub CPU 120a proceeds to step S1541 and proceeds to step S1550 if it is not a variation pattern designation command.

In step S1541, the sub CPU 120a acquires one random number value from the effect random number value updated in step S1100, and is set in the acquired effect random number value, the received variation pattern designation command, and effect mode storage area. Based on the effect mode being performed, a variation effect pattern determination process for determining one variation effect pattern from a plurality of variation effect patterns is performed.
Specifically, in the normal effect mode, the variation effect pattern determination table is referred to, one change effect pattern is determined based on the acquired effect random number value, and the determined change effect pattern is stored in the effect pattern storage area. At the same time, in order to transmit the determined variation effect pattern information to the image control unit 150 and the lamp control unit 140, an effect pattern designation command based on the determined variation effect pattern is set in the transmission data storage area of the sub RAM 120c.
Thereafter, based on the effect pattern, the liquid crystal display device 31, the audio output device 32, the effect drive device 33, and the effect illumination device 34 are controlled. Note that the variation mode of the effect symbol 36 is determined based on the variation effect pattern determined here.

In step S1550, the sub CPU 120a checks whether or not the control command stored in the received data storage area is a symbol determination command.
If the control command stored in the received data storage area is the symbol confirmation command, the sub CPU 120a moves the process to step S1551, and moves to step S1560 if it is not the symbol confirmation command.

  In step S1551, the sub CPU 120a performs an effect symbol stop display process for setting a stop designation command for stopping the effect symbol in the transmission data storage area of the sub RAM 120c in order to stop the effect symbol 36.

In step S1560, the sub CPU 120a determines whether or not the control command stored in the received data storage area is a gaming state designation command.
If the control command stored in the received data storage area is a gaming state designation command, the sub CPU 120a moves the process to step S1561, and moves to step S1570 if it is not a gaming state designation command.

  In step S1561, the sub CPU 120a sets data indicating the gaming state based on the received gaming state designation command in the gaming state storage area in the sub RAM 120c.

In step S1570, the sub CPU 120a checks whether or not the control command stored in the received data storage area is an opening designation command.
If the control command stored in the received data storage area is an opening designation command, the sub CPU 120a moves the process to step S1571, and if not the opening command, moves the process to step S1580.

In step S1571, the sub CPU 120a performs a hit start effect pattern determination process for determining a hit start effect pattern.
Specifically, the hit start effect pattern is determined based on the opening designation command, the determined hit start effect pattern is set in the effect pattern storage area, and information on the determined hit start effect pattern is stored in the image controller 150 and the lamp. In order to transmit to the control unit 140, an effect pattern designation command based on the determined hit start effect pattern is set in the transmission data storage area of the sub RAM 120c.

In step S1580, the sub CPU 120a confirms whether or not the control command stored in the received data storage area is a special winning opening opening designation command.
If the control command stored in the received data storage area is a big prize opening release designation command, the sub CPU 120a moves the process to step S1581, and if it is not a big prize opening opening designation command, the sub CPU 120a moves the process to step S1590.

In step S1581, the sub CPU 120a performs a jackpot effect pattern determination process for determining a jackpot effect pattern.
Specifically, the jackpot effect pattern is determined based on the big winning opening opening designation command, the determined jackpot effect pattern is set in the effect pattern storage area, and information on the determined jackpot effect pattern is stored in the image controller 150 and the lamp. In order to transmit to the control unit 140, an effect pattern designation command based on the determined jackpot effect pattern is set in the transmission data storage area of the sub RAM 120c.

In step S1590, the sub CPU 120a checks whether or not the control command stored in the received data storage area is an ending designation command.
If the control command stored in the received data storage area is an ending designation command, the sub CPU 120a moves the process to step S1591, and ends the command analysis process if it is not an ending designation command.

In step S1591, the sub CPU 120a performs a hit end effect pattern determination process for determining a hit end effect pattern.
Specifically, the winning end effect pattern is determined based on the ending designation command, the determined hit end effect pattern is set in the effect pattern storage area, and information on the determined hit end effect pattern is stored in the image control unit 150 and the lamp. In order to transmit to the control unit 140, an effect pattern designation command based on the determined winning end effect pattern is set in the transmission data storage area of the sub RAM 120c. When this process ends, the command analysis process ends.

Next, the authentication result data analysis process of the production control unit 120 will be described.
FIG. 23 is a flowchart showing authentication result data analysis processing by the effect control unit 120 according to the present embodiment.

In step S1651, the sub CPU 120a determines whether or not authentication result data is added to the control command stored in the reception buffer of the reception unit constituting the effect control unit 120. If the authentication result data is added, the sub CPU 120a moves the process to step S1652. If the authentication result data is not added to the control command, the sub CPU 120a ends the authentication result data analysis process.
In step S1652, the sub CPU 120a extracts authentication result data from the control command stored in the reception buffer, and the process proceeds to step S1653.

In step S1653, the sub CPU 120a determines whether or not the extracted authentication result data indicates that the inspection result of the error inspection process performed by the intermediate control unit 180 is normal and the validity of the main control unit 110 can be authenticated. Determine. Then, the sub CPU 120a determines that the gaming machine 1 is operating normally when the authentication result data is a result indicating a successful authentication. Then, the sub CPU 120a outputs the received control command to the received data storage area of the sub RAM 120c, and ends the authentication result data analysis process so as to perform processing according to the control command. On the other hand, if the authentication result data is a result indicating that the authentication is unsuccessful, the sub CPU 120a determines that there is a possibility that an illegal act or the like has occurred in the gaming machine 1, and moves the process to step S1654.
In step S1654, if the sub CPU 120a determines that there is a possibility that an illegal act or the like has occurred in the gaming machine 1, the sub CPU 120a outputs a notification signal to notify that fact, and ends the authentication result data analysis processing.

  The sub CPU 120a transmits the generated notification signal to, for example, the lamp control unit 140, the image control unit 150, or a hall computer that manages the gaming machine 1. Based on the received notification signal, the lamp control unit 140, the image control unit 150, and the like perform an effect that notifies that there is a possibility that an illegal act has occurred in the gaming machine 1. This effect is, for example, causing a character that does not normally appear on the liquid crystal display device 31 to appear, or causing a character that normally appears to appear by a method different from normal. In addition, the brightness of the liquid crystal display device 31 may be changed, the color may be changed, or the lamp controller 140 may be controlled to display a predetermined lamp. In any case, when the employee of the game shop passes in front of the gaming machine 1, it is only necessary to notice the state. This effect may be an effect that the customer does not notice the state or an effect that the customer can easily notice. If the production is easily noticed by the customer, fraud can be efficiently suppressed.

  Moreover, you may include the information regarding the gaming state or jackpot type of the gaming machine 1 in the notification signal. Based on these pieces of information, it may be determined whether a fraudulent act is being performed by a hall computer or the like that manages the gaming machine 1. For example, the “high probability gaming state” may be normal even if prize balls are concentrated. Therefore, during the high-probability gaming state, it is preferable to determine whether or not there is a risk of fraudulent behavior under conditions different from the other states. Moreover, you may make it output the information regarding a gaming state or jackpot type as a separate signal without including it in a notification signal. In this case, the employee determines whether or not there is a possibility of fraud based on both the notification signal and the information regarding the gaming state and the jackpot type.

  The authentication process when the intermediate control unit 180 is provided between the main control unit 110 and the other control units of the peripheral control unit 300 is an intermediate control between the main control unit 110 and the effect control unit 120. Since the procedure is almost the same as the authentication process when the unit 180 is provided, the description is omitted.

  As described above, in this embodiment, the test value generation unit 500 that generates an error check value is provided as a peripheral circuit of the main CPU 110a. Then, when transmitting the control command to the intermediate control unit 180, the main CPU 110a reads the error check value from the check value generation unit 500 as necessary, adds it to the control command, and sends it to the transmission unit 550. Therefore, in this embodiment, when adding a security function to the main control unit 110, an authentication processing program in which an error check value read command and a write command are described is added to a game processing program provided in an existing gaming machine. Just add.

  For this reason, in this embodiment, the processing load of the main CPU 110a and the code size of the game processing program that increase with the addition of the security function can be suppressed to the maximum. Moreover, since the timing at which the main CPU 110a adds the error check value to the control command can be arbitrarily defined simply by customizing the game processing program, the correspondence between the control command and the error check value can be specified for each model or machine manufacturer. It is relatively easy to change every time, and a highly flexible security function can be provided.

  In the present embodiment, the check value generation unit 500 generates an error check value using a control command sent in the past. Normally, an error check value such as a checksum is added to the control command of the generation source and used for a communication error check. On the other hand, in the present embodiment, the error check value generated using the control command sent in the past is not added to the control command that is the generation source of the error check value. By using such a new and simple method that has not been available in the past, even if an unauthorized person steals a control command and an error check value, the correspondence between the control command and the error check value cannot be easily analyzed. The security strength of the gaming machine 1 can be improved.

  In the present embodiment, the main control unit 110 adds an error check value generated using a control command transmitted in the past to the control command transmitted this time and transmits the error check value to the intermediate control unit 180. Then, the intermediate control unit 180 performs an error check process on the control command received this time with the error check value generated using the control command received in the past. Thereby, the intermediate control unit 180 can not only authenticate the validity of the control command received this time, but also the control command received in the past, that is, the control command that is the generation source of the error check value added this time. Can also authenticate the legitimacy. That is, it is possible to authenticate the continuity of the control command, and it becomes easier to detect fraud, and the security strength of the gaming machine 1 can be improved.

  In the present embodiment, the error check value is set to a value unique to the gaming machine 1 by adding unique information unique to the gaming machine 1 to the control command transmitted when P ≦ N. Can do. As a result, even if an unauthorized person who does not know the specific information steals a part of the control command, the error check value cannot be analyzed, and the security strength of the gaming machine 1 can be further improved.

  In this embodiment, an error check value that is normally used for communication error check is used as a check value for detecting fraud. In this way, by using the error check value conventionally used for communication error check, it is possible to detect fraud without having to newly develop a test value generation means for detecting fraud. Strength can be improved. That is, the security strength can be improved while an authentication function for the main control unit 110 can be added with a relatively simple configuration.

  In the present embodiment, the test value generation unit 500 added as a specific aspect of the security function to be added to the main control unit 110 is configured by a wired logic control type hardware, and the processing load of the main CPU 110a And does not increase code size. Therefore, according to the present embodiment, while the gaming machine 1 has the security function, the processing load and code size of the CPU of the main control unit 110, which increase by having the security function, can be suppressed to the maximum. At the same time, according to the present embodiment, a security function having such a feature can be added to an existing gaming machine relatively easily.

  In the present embodiment, the check value generation unit 500 further performs bit string conversion processing on the error check value generated using the control command sent in the past. In addition, the test value generation unit 500 includes a plurality of conversion methods used for the bit string conversion processing, and changes appropriately based on the acquired control command. Therefore, even if an unauthorized person steals a plurality of control commands and error check values, it becomes more difficult to analyze the correspondence between the control commands and error check values. Therefore, the confidentiality of the error check value generation function of the gaming machine 1 can be improved, and the security strength of the gaming machine 1 can be further improved.

  Further, in the present embodiment, the check value generation unit 500 includes a plurality of error check value generation functions in advance by providing a plurality of change conditions that are conditions for appropriately changing the conversion method used for the bit string conversion processing. Yes. Based on what change condition the conversion method is changed, the HW parameter stored in a specific storage area of the main ROM 110b that is not accessed except when the initial value is set during the boot process of the main control unit 110 Is determined based on the value of. Therefore, even if an unauthorized person steals multiple control commands and error check values, it is difficult to analyze under what change conditions the conversion method is changed. It becomes more difficult to analyze. Therefore, the confidentiality of the error check value generation function of the gaming machine 1 can be improved, and the security strength of the gaming machine 1 can be further improved.

  In the present embodiment, although a plurality of types of error check value generation functions and HW parameters as selection information thereof are prepared in advance, only specific HW parameters are implemented. Therefore, it is not necessary to newly provide a program associated with the HW parameter selection process in the boot process, and the code size of the program is not increased. Even if a gaming machine manufacturer wants to adopt only a specific error check value generation function, only the HW parameter corresponding to the desired error check value generation function needs to be implemented. Can respond flexibly. Therefore, even diverse security functions can be added relatively easily, and a highly versatile security function can be provided. In addition, by changing the HW parameters used for design / verification work during the development stage of the gaming machine 1 and the HW parameters that are actually mounted before the gaming machine 1 is shipped, which HW parameters are finally adopted. The number of persons who can know whether or not the game has been made can be limited, and the confidentiality of the error check value generation function of the gaming machine 1 can be further improved.

  In the present embodiment, as a plurality of conversion methods used for the bit string conversion process, a conversion method A in which the shift amount regularly varies and a conversion method B in which the shift amount varies randomly are provided. In the conversion method B, since the shift amount varies randomly, each bit of the error check value that has been subjected to the bit string conversion processing using the conversion method B is irregularly shifted every bit string conversion processing. Therefore, even if an unauthorized person steals a plurality of control commands and error check values, it becomes difficult to analyze the shift amount by which the bit string is converted. It becomes more difficult to analyze. Therefore, the confidentiality of the error check value generation function of the gaming machine 1 can be improved, and the security strength of the gaming machine 1 can be further improved.

  In particular, in the conversion method B in which the shift amount is randomly changed, even if the bit string of the original error check value is different, a duplicate value may be output for each bit string conversion process. Even if multiple values are stolen, it is difficult to analyze whether there is regularity regarding the shift amount variation and whether the conversion method has been changed, and it is even more difficult to analyze the correspondence between control commands and error check values. . Therefore, the confidentiality of the error check value generation function of the gaming machine 1 can be improved, and the security strength of the gaming machine 1 can be further improved.

  In this embodiment, only the conversion method B is the conversion method in which the shift amount varies randomly. The error check value obtained by converting the bit string by the conversion method B is added to the control command and transmitted to the intermediate control unit 180 during a predetermined operation mode, that is, when a predetermined control command group is The period is limited to the period transmitted to the intermediate control unit 180. Therefore, when returning to the original error check value bit string in the error check process on the intermediate control unit 180 side, the tendency that the number of trials of the bit string conversion process increases by changing the shift amount at random is maximized. Can be suppressed. In other words, in this embodiment, it is difficult to analyze the correspondence between the control command and the error check value by randomly changing the shift amount, and while increasing the security strength, the processing load that is increased by adding the security function is maximized. Can be limited. Moreover, the increase in processing load is borne not by the main control unit 110 having limited resources but by the intermediate control unit 180 having a relatively large amount of resources, and a large fraud prevention effect can be obtained with a small load.

  In this embodiment, as a specific embodiment of the conversion method, the test value generation unit 500 includes the bit string conversion circuit 525, and the bit string conversion circuit 525 is configured with a shift register having a relatively simple circuit configuration. For this reason, in this embodiment, after designing the circuit of the rotate computing unit 525a, the circuit data can be diverted to the rotate computing unit 525b. The difficulty level can be suppressed. That is, in this embodiment, the effect that the correspondence relationship between the control command and the error check value becomes difficult to analyze and the security strength is improved by providing a plurality of conversion methods is smaller than the number of conversion methods provided. It can be obtained simply by designing the computing unit, and a large fraud prevention effect can be obtained with a small development cost.

  In the present embodiment, the error check value generated using a control command sent in the past is not subjected to encryption processing using an encryption key, but is subjected to bit string conversion processing. As a conversion method, a rotation operation unit is used to perform a bit rotation operation. In the method of performing the encryption process using the encryption key, it is necessary to store the encryption key information, which is fixed data, in the main control unit 110, and there is a possibility that it is easily analyzed illegally by a static analysis method. . In addition, in order to configure the encryption key information to be analyzed only by a dynamic analysis method, it is necessary to newly provide complicated processing such as encryption key exchange, sharing, and synchronization. On the other hand, in this embodiment, the bit string conversion circuit 525 that performs the bit string conversion processing calculates the shift amount A using the error check value output from the internal rotation calculator 525b and the parity check provided in the existing gaming machine. Update the function. In addition, the bit string conversion circuit 525 updates the shift amount B by using a random value used in an existing game machine. In other words, in this embodiment, the shift amounts A and B, which are the key in the bit string conversion process, are changed by a simple method of using and updating the configuration provided in the existing game machine, thereby providing dynamic configuration security. The function is realized. In addition, the rotation calculators 525a and 525b are composed of shift registers having a relatively simple circuit configuration, and are overwhelmingly compared with an arithmetic circuit that performs encryption processing using encryption key information. Less is. For this reason, in the present embodiment, in circuit design and verification work, it is possible to suppress adverse effects on the determination of the operating frequency, die size, and the like due to circuit placement adjustment and delay time adjustment by wiring resources.

  In this embodiment, the shift amount A is changed not only when the bit string conversion process is performed by the conversion method B but also when the bit string conversion process is performed by the conversion method A. Specifically, in the present embodiment, the conversion method A is used even when the error check value obtained by converting the bit string by the conversion method B is not included in the period when the error check value is added to the control command. The shift amount A used in 1 is varied every period other than the period of the predetermined operation mode. For this reason, in this embodiment, an unauthorized person transmits a bit string converted by the error check value added to the control command in a period other than the predetermined operation mode period. This also makes it difficult to perform the error check value, and can further improve the security strength.

  Further, in the present embodiment, a plurality of error check value generation functions are provided in advance by providing a plurality of update timing conditions related to the shift amount A defined in order to regularly vary the shift amount A used in the conversion method A. I have prepared it. The update timing condition based on which update amount A is updated is stored in a specific storage area of the main ROM 110b that is not accessed except when an initial value is set during the boot process of the main control unit 110. It is determined based on the value of the HW parameter. Therefore, even if an unauthorized person steals a plurality of control commands and error check values, it is difficult to analyze the regularity regarding the update of the shift amount A, and it is further possible to analyze the correspondence between the control commands and error check values. It becomes difficult. Therefore, the confidentiality of the error check value generation function of the gaming machine 1 can be improved, and the security strength of the gaming machine 1 can be further improved.

  In the present embodiment, when the shift amount A used in the conversion method A is transmitted as a predetermined control command from among control commands other than the predetermined control command group, a predetermined set value is set for the shift amount A. And the shift amount A is reset. Therefore, in the present embodiment, during the period in which the error check value obtained by converting the bit string by the conversion method A is added to the control command, it is possible to reset the change transition of the shift amount A due to the update so far. When the shift amount A shifts between the main control unit 110 and the intermediate control unit 180 due to a communication error or the like, the conversion method changes from the conversion method A to the conversion method B unless the change transition of the shift amount A is reset. The deviation will not be resolved until changed to. However, in this embodiment, the conversion method A is used by resetting the change transition of the shift amount A during the period in which the error check value in which the bit string is converted by the conversion method A is added to the control command. The shift can be eliminated even during the period. For this reason, in this embodiment, the accuracy of the error checking process on the intermediate control unit 180 side can be improved. At the same time, the shift amount A is reset in the period when the error check value in which the bit string is converted by the conversion method A is added to the control command, that is, in the period other than the period of the predetermined operation mode. It is difficult to analyze the correspondence between the command and the error check value, and the security strength can be further improved.

  In the present embodiment, a plurality of error check value generation functions are prepared in advance by providing a plurality of reset conditions, which are conditions for resetting the shift amount A used in the conversion method A, in advance. The reset condition based on which reset amount A is reset is stored in a specific storage area of the main ROM 110b that is not accessed except when the initial value is set during the boot process of the main control unit 110. It is determined based on the value of the HW parameter. Therefore, even if an unauthorized person steals a plurality of control commands and error check values, it becomes difficult to analyze the regularity regarding the resetting of the shift amount A, and the correspondence relationship between the control commands and error check values can be analyzed. It becomes even more difficult. Therefore, the confidentiality of the error check value generation function of the gaming machine 1 can be improved, and the security strength of the gaming machine 1 can be further improved.

  In the present embodiment, the authentication function for the main control unit 110 is provided in the intermediate control unit 180 that is independent of the peripheral control unit 300 that performs processing related to normal game progression. Therefore, for example, when the intermediate control unit 180 is provided between the main control unit 110 and the effect control unit 120, the authentication process is executed by the effect control unit 120 from the authentication result data from the intermediate control unit 180. Is only received. That is, the processing load of the sub CPU 120a of the effect control unit 120 increases only when the authentication result data is received by performing the authentication process, and thus the rate at which the processing load of the effect control unit 120 increases is suppressed. Can do. Further, it is only necessary to add a program code related to the authentication result data analysis process to the program executed by the effect control unit 120. Therefore, since it is not necessary to perform a new timing design over the entire program executed by the effect control unit 120, the mounting and verification work when adding the authentication function can be performed more easily and with less work man-hours. In this case, the authentication result data analysis process executed by the effect control unit 120 is mainly a process of determining whether or not the authentication process is successful in the intermediate control unit 180. For this reason, the production control unit 120 does not have to be equipped with an error check value output function corresponding to the error check value generation function of the main control unit 110 such as error check value generation, bit string conversion, and shift amount update. Good. Therefore, when developing the production control unit 120, it is not necessary to disclose the error check value generation function of the main control unit 110 and the error check value output function of the intermediate control unit 180, and the error check value generation function and the error check value output function are not disclosed. The confidentiality can be further improved, and the security strength of the gaming machine 1 can be further improved.

  In the present embodiment, since the intermediate control unit 180 is provided between the main control unit 110 and the effect control unit 120, the main CPU 110 a configuring the main control unit 110 and the sub CPU 120 a configuring the effect control unit 120. In the intermediate control unit 180, the difference in processing capacity between the main ROM 110b and the main RAM 110c constituting the main control unit 110 and the storage capacity difference between the sub ROM 120b and the sub RAM 120c constituting the effect control unit 120 Can be absorbed. Thereby, even when there is a difference in processing capacity and storage capacity between the main control unit 110 and the effect control unit 120, the security strength between the main control unit 110 and the effect control unit 120 can be maintained. This also applies to the case where the intermediate control unit 180 is provided between the main control unit 110 and another control unit of the peripheral control unit 300.

  In this embodiment, the data discrimination circuit 511 of the acquisition unit 510 and the storage circuit 522 of the generation unit 520 are connected, and the data discrimination circuit 511 is disposed on the input side of the storage circuit 522, and the output side of the storage circuit 522 is connected. The circuit configuration is such that the generation circuit 521 is arranged. That is, in the present embodiment, the object to be stored in the storage circuit 522 is the control command output from the acquisition unit 510. However, the present invention is not limited to this, and the storage circuit 522 may be provided on the output side of the generation circuit 521 so that an object to be stored in the storage circuit 522 may be an error check value. In the intermediate control unit 180 as well, the object stored in the storage unit 622 may be an error check value or a control command. Further, the storage target in the main control unit 110 and the storage target in the intermediate control unit 180 may be different.

  Further, at this time, the storage circuit 522 is not provided on the output side of the generation circuit 521, and the storage circuit 526 is configured by a FIFO memory having N storage areas corresponding to the N values of retroactive numbers, and N bit strings. It is also possible to store the converted error check value. By doing so, the storage circuit 522 is not necessary, and the circuit configuration of the test value generation unit 500 can be further simplified. At this time, an address may be assigned to each storage area of the FIFO memory so that the main CPU 110a can read the error check value from an arbitrary storage area. By doing so, the main CPU 110a can change the value of the retroactive number N only by customizing the authentication processing program. For this reason, it is relatively easy to change the correspondence between the control command and the error check value for each model or for each gaming machine manufacturer, and a highly flexible security function can be provided.

  Further, in the present embodiment, the timing at which the main CPU 110a adds the error check value to the control command has been described as being defined by an authentication processing program call instruction defined in the game processing program. This includes that the test value adding process may be executed every time the main CPU 110a performs the command transmission process. That is, in the present invention, the main CPU 110a may add an error check value to the transmitted control command every time. In this case, the process of step S76 in FIG. 15 and the process of step S4070 in FIG. 18 are not necessary. Since the intermediate control unit 180 performs an error check process every time it receives a control command, it can always check for fraud.

  Even when the main CPU 110a adds an error check value to the control command to be transmitted every time, the main CPU 110a immediately writes the error check value read from the check value generation unit 500 to the transmission unit 550 and transmits the control command. It is not necessary to add to. That is, when the control command to be transmitted this time is the control command (P) and the error check value read from the check value generation unit 500 is the error check value (PN), the main CPU 110a reads the error check value ( P−N) is saved. Then, the main CPU 110a may add the stored error check value (P−N) to the control command (P + Q) transmitted after Q (Q: non-negative integer).

An example of the procedure for adding an error check value in this case is shown in FIG. FIG. 24 shows an example of control commands (control command (1) to control command (11)) output eleventh after the stored control command is cleared. Also, in FIG. 24, the bit string conversion process performed by the conversion method A on the error check value (P) is expressed as “error check value (PA)”, and the bit string conversion process is performed by the conversion method B. Is expressed as “error check value (PB)”. Further, the shift amount A used when performing the bit string conversion process is updated as appropriate, but the bit string conversion process using the default shift amount A before the update is referred to as “error check value (PA ₀ )”. .., “Error check value (PA ₁ )”, “Error check value (PA ₂ )”,... The same applies to the error check value (PB). Further, in FIG. 24, a bit string conversion process that uses the reset shift amount A is also expressed as “error check value (PA ₀ )”. N = 2 and Q = 1.

  In FIG. 24, the default conversion method is the conversion method A. That is, in the conversion method information storage area (CM), a value of conversion method information corresponding to the conversion method A is stored, but in FIG. 24, CM = A is shown for convenience. In FIG. 24, the control command that satisfies the change condition is the control command that is generated first among the predetermined control command group and the control command that is generated first after the generation of the predetermined control command group is completed. Either. As the change method, a method is adopted in which the conversion method is determined as conversion method A → conversion method B and conversion method B → conversion method A every time a control command that satisfies the change condition is generated. As for the shift amount A, the updated shift amount A is used every time the conversion method is changed from conversion method B to conversion method A, and the shift amount B is updated after each command transmission process. It is assumed that the shift amount B is used.

  In the case of transmitting the control command (1), in FIG. 24, N = 2 and P = 1 (P ≦ N) at present, so the error check value read from the check value generation unit 500 is unique. This is the initial inspection value (1) generated using the information. Since Q = 1, the initial inspection value (1) is held without being added to the control command (1) to be transmitted this time, and is added to the control command (2) to be transmitted next time. In FIG. 24, dummy data is added to the control command (1) instead of the initial inspection value (1).

  When the control command (2) is transmitted, the error check value read from the check value generation unit 500 becomes the initial check value (2) generated using the unique information. Similarly to the above, the initial inspection value (2) is held without being added to the control command (2) to be transmitted this time, and is added to the control command (3) to be transmitted next time. The previously read initial inspection value (1) is added to the control command (2) transmitted this time.

When transmitting the control command (3), the error check value read from the check value generation unit 500 is an error check value generated using the control command (1), and the bit string is converted by the default conversion method A. Error check value (1A ₀ ). Similarly to the above, the error check value (1A ₀ ) is held without being added to the control command (3) to be transmitted this time, and is added to the control command (4) to be transmitted next time. The previously read initial inspection value (2) is added to the control command (3) transmitted this time. The same applies when transmitting the control command (4), and an error check value (1A ₀ ) is added to the control command (4).

When transmitting the control command (5), since the control command (5) is a control command generated at the beginning of a predetermined control command group, the conversion method is changed from the default conversion method A to the conversion method B. . Therefore, the error check value read from the check value generation unit 500 is an error check value generated using the control command (3), and an error check value (3B ₀ ) obtained by converting the bit string by the conversion method B. Become. Similarly to the above, the error check value (3B ₀ ) is retained without being added to the control command (5) transmitted this time, and is added to the control command (6) transmitted next time. Then, the previously read error check value (2A ₀ ) is added to the control command (5) transmitted this time.

When the control command (6) is transmitted, since the control command (6) is a control command of a predetermined control command group, the conversion method is maintained as the conversion method B. However, in the conversion method B, a shift is performed each time. The quantity B is updated. Therefore, the error check value read from the check value generation unit 500 is an error check value generated using the control command (4), and is an error check value (4B ₁ ) in which the bit string is converted by the conversion method B. Become. Similarly to the above, the error check value (4B ₁ ) is held without being added to the control command (6) to be transmitted this time, and is added to the control command (7) to be transmitted next time. Then, the previously read error check value (3B ₀ ) is added to the control command (6) transmitted this time. The same applies when transmitting the control command (7), and an error check value (4B ₁ ) is added to the control command (7).

When transmitting the control command (8), since the control command (8) is a control command that is generated first after generation of a predetermined control command group, the conversion method is changed from conversion method B to conversion method A. The shift amount A is also updated. Therefore, the error check value read from the check value generation unit 500 is an error check value generated using the control command (6), and the error check value (6A ₁ ) obtained by converting the bit string by the conversion method A. Become. Similarly to the above, the error check value (6A ₁ ) is held without being added to the control command (8) to be transmitted this time, and is added to the control command (9) to be transmitted next time. Then, the previously read error check value (5B ₂ ) is added to the control command (8) transmitted this time. The same applies when the control command (9) is transmitted, and an error check value (6A ₁ ) is added to the control command (9).

When the control command (10) is transmitted, the shift command A is reset because the control command (10) is a control command that satisfies the reset condition of the shift program A. Therefore, the error check value read from the check value generation unit 500 is an error check value generated using the control command (8), and is an error check value (8A ₀ ) obtained by converting the bit string by the conversion method A. Become. Similarly to the above, the error check value (8A ₀ ) is held without being added to the control command (10) to be transmitted this time, and is added to the control command (11) to be transmitted next time. Then, the previously read error check value (7A ₁ ) is added to the control command (10) transmitted this time. The same applies when the control command (11) is transmitted, and an error check value (8A ₀ ) is added to the control command (11). Thereafter, an error check value is added while performing the same processing.

  As described above, in this embodiment, since the error check value read from the check value generation unit 500 and the error check value actually added to the control command can be made different from each other, It becomes difficult to analyze the correspondence relationship with the inspection value, and the security strength of the gaming machine 1 can be further improved.

  In the present embodiment, the HW parameter is defined as selection information for determining a default change condition, an update timing condition related to the shift amount A, and a reset condition related to the shift amount A. It is not limited. For example, the HW parameter can be defined as selection information for determining a default conversion method. When the conversion method is determined by the HW parameter, the determination circuit 542 prepares a plurality of conversion methods in advance and associates them with the HW parameter. The determination circuit 542 stores conversion method information indicating a specific conversion method corresponding to the HW parameter set by the main CPU 110a in the conversion method information storage area (CM) during the boot process, and controls the conversion method. A signal may be output and setting to the generation unit 520 may be performed.

  The HW parameter can also be defined as selection information for determining a change method used by the determination unit 540. For example, when the change method is determined by the HW parameter, the determination circuit 542 prepares a plurality of change methods for defining a change order of predetermined conversion methods and associates them with the HW parameter. Then, the determination circuit 542 stores a specific change method corresponding to the HW parameter set from the main CPU 110a in a predetermined storage area during the boot process, and changes the conversion method according to the stored change method. I'll do it.

  The HW parameter can also be defined as selection information for determining an update method related to the shift amount B used by the generation unit 520. For example, when the update timing condition related to the shift amount B is determined by the HW parameter, the shift amount control unit 525c responsible for the bit string conversion circuit 525 can acquire random number values from a plurality of random number generation circuits provided in an existing gaming machine. Each of the random number generation circuits and the HW parameters are associated with each other. In the boot process, the shift amount control unit 525c effectively operates only the connection with the specific random number generation circuit corresponding to the HW parameter set by the main CPU 110a, and is acquired from the specific random number generation circuit. The shift amount B may be updated using a random value.

  The HW parameter can also be defined as selection information for determining the predetermined set value used for resetting the shift amount A. For example, when the set value is determined by the HW parameter, a plurality of set values are prepared in the shift amount control unit 525c that bears the bit string conversion circuit 525 and associated with the HW parameter. Then, the shift amount control unit 525c stores a specific setting value corresponding to the HW parameter set from the main CPU 110a in a predetermined storage area during the boot process, and shifts using the stored setting value. The amount A may be reset.

  In other words, in the present invention, the HW parameter is not limited to the change condition used in the determination unit 540 or the selection information for determining the update timing condition and the reset condition related to the shift amount A used in the generation unit 520, and is related to the conversion method. It can be defined as selection information for determining a rule relating to updating and resetting of a change protocol and shift amount. That is, the HW parameter is selection information for the error check value generation function in which the change protocol related to the conversion method and the rule related to update and reset of the shift amount are implemented.

  As described above, in the present invention, the error check value generation function is based on the value of the HW parameter stored in the specific storage area of the main ROM 110b that is not accessed except when the initial value is set during the boot process of the main control unit 110. Determined. Therefore, even if an unauthorized person steals a plurality of control commands and error check values, it becomes difficult to analyze what error check value generation function is installed in the gaming machine 1, and the error check value generation function The confidentiality of the game machine 1 is improved, and the security strength of the gaming machine 1 can be further improved.

  In the present embodiment, when the control command output from the acquisition unit 510 satisfies the change condition, the determination circuit 541 generates a determination result signal indicating that the control command is a control command that satisfies the change condition. It is not necessary to output every time. That is, even if the control command output from the acquisition unit 510 is a control command that satisfies the change condition, the determination circuit 541 does not change the conversion method in the determination circuit 542, and the unauthorized person sets the conversion method change condition. It becomes more difficult to analyze.

  Furthermore, the determination circuit 541 does not have to output the determination result signal itself every time a control command is input. In this case, the control circuit 512 of the acquisition unit 510 and the determination circuit 542 are directly connected by a control line, and an operation permission signal is output from the control circuit 512 to the determination circuit 542. The determination circuit 542 may perform the conversion method setting process based on the input of the operation permission signal. Further, the control circuit 512 of the acquisition unit 510 is not connected to the determination circuit 541 and the determination circuit 542 of the determination unit 540, but is connected to the control circuit 523 of the generation unit 520 and the determination circuit is connected to the determination circuit. The operation permission signal may be output to 541 or the determination circuit 542.

  In this embodiment, the reset determination circuit 528 is provided in the generation unit 520 as a determination circuit separate from the determination circuit 541. However, the present invention is not limited to this, and the reset determination circuit 528 is determined by the determination unit 540. The determination circuit 541 may be integrated with the determination circuit 541. At this time, the determination circuit 541 uses the change condition and the reset condition as the determination conditions used by the determination circuit 541, and the output side of the determination circuit 541 is connected to the shift amount control unit 525c serving as the bit string conversion circuit 525 through a control line. If the control command output from the acquiring unit 510 is a control command that satisfies the reset condition, a shift amount A reset signal may be output to the shift amount control unit 525c. The determination circuit 542 prepares a plurality of reset conditions in advance and associates them with HW parameters. The determination circuit 542 may output a specific reset condition corresponding to the HW parameter set from the main CPU 110a to the determination circuit 541 during the boot process.

  In the present embodiment, the reset condition that is the determination condition used by the reset determination circuit 528 is that the control command output from the acquisition unit 510 is a control command determined in advance from control commands other than a predetermined control command group. It was decided that. However, the present invention is not limited to this, and a predetermined error check value can also be used as the reset condition. For example, during a period in which an error check value whose bit string has been converted by the conversion method A is added to the control command, the error check value output from the rotate arithmetic unit 525b serving as the bit string conversion circuit 525 is the input selection circuit 524. Is not output to the storage circuit 526, but is output to the shift amount control unit 525c. The error check value output from the rotation calculator 525b, that is, the error check value in which the bit string is converted in the conversion method B during the period in which the error check value in which the bit string is converted in the conversion method A is added to the control command. However, if it is a predetermined error check value, it may be determined that the shift amount A is reset. The shift amount control unit 525c includes a determination unit corresponding to the reset determination circuit 528, and the reset condition is a period in which an error check value obtained by converting the bit string by the conversion method A is added to the control command. In this case, it may be determined that the error check value obtained by converting the bit string by the conversion method B is a predetermined error check value.

  In the present embodiment, the unique information is set in the generation unit 520 as an initial setting value when P = 1. When P ≦ N, the main control unit 110 adds an initial check value to the control command (P) and transmits it, and the intermediate control unit 180 uses the corresponding initial check value to perform error check processing. However, the present invention is not limited to this, and the intermediate control unit 180 does not perform error check processing when P ≦ N, and performs error check processing only after P> N. Also good.

  In the present embodiment, the intermediate control unit 180 is the determination unit 623 having the same function as the function of changing the conversion method of the main control unit 110, but the present invention is not limited to this. For example, the intermediate control unit 180 collates the error check value added to the received control command with the error check value obtained by converting the bit string in all the conversion methods of the bit string conversion unit 624, and performs error check processing. It may be done. In this case, the intermediate control unit 180 may authenticate the validity of the received control command and the validity of the main control unit 110, assuming that the inspection result is normal if it matches any error check value.

  In this embodiment, when P = 1, the unique information is set as the initial setting value in the storage circuit 522. However, the present invention is not limited to this. For example, time measuring means is provided in the main control unit 110, or using the time measuring means provided in advance in the main control unit 110, the elapsed time from the power-on to the transmission timing of the control command is acquired as time-lapse information and acquired. Time information may be used as an initial inspection value. Since the value of the acquired time-lapse information is a fluctuation value having randomness, it is difficult to reuse the initial inspection value generated by using this, and the security strength of the gaming machine 1 is further improved. Can do. At this time, the intermediate control unit 180 may not perform the error check process when P ≦ N as described above.

  At this time, if N ≧ 2 is determined in advance, the intermediate control unit 180 determines whether or not the temporal information added to the control command has continuity in time series between the temporal information transmitted continuously. In other words, the error checking process may be performed by confirming whether or not the value of the time information transmitted continuously increases in accordance with the transmission order. The time information may be an absolute time acquired by using a time measuring means as a real time clock circuit or the like, or may be a relative time counted from the reset time. In any case, the time-lapse information changes to various values as the timing of acquisition is irregular, so that it can be regarded as information inherent to the gaming machine 1 substantially. Further, when N ≧ 2, the time information may be obtained from the time measuring means for each control command transmission timing, or a plurality of time information acquired at the transmission timing of the first generated control command may be used. It may be used for control commands. Also, for example, the initial setting value that is the source of the error check value added to the first generated control command uses the identification number (ID) of the main CPU 110a, which is a fixed value, and is added to subsequent control commands. The initial setting value from which the error check value is generated can be a combination of a fixed value and a variation value, such as using time-lapse information that is a variation value.

  Further, as an initial setting value set in the storage circuit 522, for example, an HW parameter that is selection information of an error check value generation function of the main control unit 110 may be used. That is, the determination unit 540 constituting the inspection value generation unit 500 of the main control unit 110 stores the HW parameter set in its determination circuit 542 during the boot process even after the HW parameter setting process. The determination circuit 542 is provided with a transmission number storage area (P), and the determination circuit 542 determines whether it is necessary to set unique information in the storage circuit 522. At this time, the control circuit 512 of the acquisition unit 510 and the determination circuit 542 are connected by a control line, and an operation permission signal is output from the control circuit 512. The determination circuit 542 updates the value of the transmission number storage area (P) based on the input of the operation permission signal, and if the value of the transmission number storage area (P) is P = 1, the value is output from the acquisition unit 510. The control command is determined to be a control command first sent out by the main CPU 110a after the control command stored in the storage circuit 522 is cleared. Then, the determination circuit 542 may set the HW parameter stored in the storage circuit 522 and use it as an initial setting value.

  The content and mounting method of the HW parameter can be determined by the game machine manufacturer's own judgment, so that the HW parameter is highly confidential and can be regarded as information inherent to the gaming machine 1 substantially. The intermediate control unit 180 may not perform the error check process when P ≦ N as described above. By doing in this way, the intermediate control unit 180 is set by the main control unit 110 even if the selection information of the error check value generation function corresponding to the HW parameter is not negotiated with the main control unit 110 in advance. An error check value output function corresponding to the error check value generation function can be selected. Therefore, even if an unauthorized person analyzes the intermediate control unit 180 itself, it is specified whether the error check process is performed using the error check value output by any of the plurality of error check value output functions. Therefore, the confidentiality of the output function can be ensured, and the security strength of the gaming machine 1 can be further improved.

  Further, in the present embodiment, the input / output control method between each means or each circuit in the test value generation unit 500 is a synchronous interface method. Then, data transmission / reception between each means and each circuit in the inspection value generation unit 500 is performed in synchronization with the clock signal output from the clock pulse generation circuit of the main control unit 110. However, the present invention is not limited to this, and data transmission / reception between each means and each circuit in the test value generation unit 500 may be performed asynchronously with respect to the clock signal. Even in this case, in the test value generation unit 500, if an enable signal or the like is output to the connection destination of the data to be output, the connection destination captures the output data based on the input of the enable signal or the like. This is different from the CPU interface method.

  In the present embodiment, the timing at which each means in the test value generation unit 500 operates is controlled by adjusting the output timing of each operation permission signal output from the control circuit 512 of the acquisition means 510. However, the present invention is not limited to this, and the control circuit 523 of the generation unit 520 adjusts the output timing of the shift processing signal output to the storage circuit 522 and the output timing of the operation permission signal output to the generation circuit 521. Can also be controlled. The output timing of the shift processing signal and the operation permission signal output from the control circuit 523 is based on the input of the operation permission signal output from the control circuit 512. Furthermore, the output timing of the operation permission signal output by the control circuit 512 is based on the input of the write signal to the transmission unit 550 sent from the main CPU 110a. The write signal sent out by the main CPU 110a is designated in advance by the execution timing of the command transmission process originally defined in the existing game processing program.

  As described above, in the present invention, the timing at which each means in the test value generation unit 500 operates may be uniquely determined based on the execution timing of the command transmission process defined by the existing game processing program. It is possible to design timing easily. Therefore, according to the present invention, a security function can be added to an existing gaming machine relatively easily, and the main CPU 110a can ensure a relatively large margin in the design of the output timing of an error check value read signal. This makes it easy to ensure the accuracy of error checking processing.

  In the present embodiment, in the shift amount control unit 525c that bears the bit string conversion circuit 525 of the generation unit 520 constituting the inspection value generation unit 500, an algorithm that the shift amount control unit 525c includes control related to update of the shift amount therein. However, in the present invention, the test value generation unit 500 may be entirely configured by hardware.

  In the present embodiment, the intermediate control unit 180 adds the authentication result data to the control command and transmits it to the effect control unit 120 as a control command with authentication result data. However, the present invention is not limited to this. The control command and the authentication result data may be transmitted separately. In this case, the effect control unit 120 may determine whether or not the authentication result data has been received, and perform authentication result data analysis processing when the authentication result data is received. Note that dummy data may be added to each of the control command and the authentication result data so that the data length is the same. By doing so, it becomes difficult for an unauthorized person to distinguish between the control command and the authentication result data, and the security strength of the gaming machine 1 can be improved.

  In the present embodiment, the intermediate control unit 180 generates authentication result data and transmits it to the effect control unit 120 regardless of whether authentication is successful or unsuccessful. However, the present invention is not limited to this. For example, the intermediate control unit 180 may generate authentication result data only when authentication is unsuccessful, or output a signal indicating unsuccessful authentication and transmit it to the effect control unit 120. The effect control unit 120 may determine whether or not the authentication result data or a signal indicating unsuccessful authentication has been received and output the notification signal when received.

  In the present embodiment, the inspection value generation unit 500 is integrated with the one-chip microcomputer 110m as a peripheral circuit of the main CPU 110a. However, the present invention is not limited to this, and the inspection value generation unit 500 is replaced with the one-chip microcomputer. It is good also as a circuit structure separate from 110m. Also, the transmission unit 550 may have a circuit configuration separate from the one-chip microcomputer 110m. In the present embodiment, the intermediate control unit 180 includes a CPU, a ROM, a RAM, and the like. However, a similar function may be realized as an integrated circuit such as an LSI.

  Moreover, in this embodiment, although the example which applies this invention to a pachinko game machine was shown, it is not limited to this, This invention is a ball game machine other than pachinko game machines, such as a sparrow ball game machine and an arrangement ball. It can also be applied to other gaming machines such as slot machines such as slot machines. Even in these gaming machines, the same effects as in the present embodiment can be obtained by configuring the same as in the present embodiment.

  In the present embodiment, an example in which the present invention is applied to a gaming machine has been described. However, the present invention is not limited thereto, and the present invention includes a plurality of control units such as a gaming machine, and data transmission between these control units. The present invention can also be applied to an electronic device that executes authentication processing and an authentication method thereof. Also in these electronic devices and their authentication methods, the same effects as in this embodiment can be obtained by configuring in the same manner as in this embodiment. Moreover, this embodiment can divert each other's technique as long as there is no particular contradiction or problem in its purpose and configuration.

1 gaming machine 110 main control unit 110a main CPU
110b Main ROM
110c Main RAM
110d Boot ROM
120 Production control unit 120a Sub CPU
120b Sub ROM
120c sub RAM
180 Intermediate control unit 180a CPU
180b ROM
180c RAM
DESCRIPTION OF SYMBOLS 300 Peripheral control part 400 Internal bus 500 Test value generation part 510 Acquisition means 520 Generation means 521 Generation circuit 525 Bit string conversion circuit 526 Storage circuit 527 Transmission circuit 528 Reset determination circuit 540 Determination means 550 Transmission part 600 Reception part 610 Inspection part 620 Inspection value Generation unit 621 Generation unit 622 Storage unit 623 Determination unit 624 Bit string conversion unit 630 Addition unit 640 Relay transmission unit

Claims (10)

A gaming machine including a main control unit that outputs a control command, a peripheral control unit that performs processing based on the control command, and an intermediate control unit provided between the main control unit and the peripheral control unit. And
The main control unit
An arithmetic processing unit that generates and sends out the control command according to a predetermined control program stored in the storage unit;
A transmission unit for transmitting the control command transmitted by the arithmetic processing unit to the intermediate control unit;
A bus connecting the arithmetic processing unit and the transmission unit;
An error check value that is connected to the bus and added to the control command sent by the arithmetic processing unit to check the validity of the control command is generated , and a bit string of the generated error check value is converted . 1 inspection value generator,
With
The intermediate control unit
A verification error check value corresponding to the error check value generated by the first check value generation unit is generated, and a bit string of the generated error check value is converted in advance with the main control unit. A second inspection value generator for converting and outputting ;
The error check value transmitted by the transmitter is compared with the error check value output by the second check value generator to check the validity of the control command transmitted by the transmitter, and An inspection unit for outputting result information;
A relay transmission unit that transmits the control command transmitted by the transmission unit to the peripheral control unit and transmits the result information to the peripheral control unit;
With
The peripheral control unit
A processing unit that performs processing based on the control command relayed by the relay transmission unit and performs processing according to the result information transmitted by the relay transmission unit;
The first inspection value generation unit
When a control command from the arithmetic processing unit to the transmission unit is sent to the bus, a command for acquiring the control command to the transmission unit from the bus and outputting the acquired control command at a predetermined timing Acquisition means;
Enter the control command outputted by the command obtaining means, the conversion method used in converting a bit string of the error check value to be added to the control command the input, with the first shift amount that varies regularly Either a first conversion method that performs a rotation operation on a bit string of an error check value or a second conversion method that performs a rotation operation on a bit string of an error check value using a second shift amount that fluctuates irregularly. A method determining means for determining the conversion method information based on the input control command and outputting the conversion method information indicating the determined conversion method according to the timing;
The control command output by the command acquisition means and the conversion method information output by the method determination means are input and generated using the control command sent by the arithmetic processing unit in the past from the input control command. A check value output means for converting a bit string of an error check value by a conversion method indicated by the input conversion method information, and outputting an error check value converted from the bit string according to the timing;
The error check value converted from the bit string output by the check value output means is input, and the error check value converted from the input bit string is read out from the arithmetic processing unit defined in the control program In response to the test value sending means for sending to the arithmetic processing unit via the bus,
Have
The inspection value output means sets the first shift amount to a predetermined value when a reset condition for resetting the first shift amount is satisfied when the input conversion method information indicates the first conversion method. Set, convert the bit string of the generated error check value,
The arithmetic processing unit adds an error check value acquired from the check value sending means to the control command sent to the transmitting unit, and sends the control command to the transmitting unit via the bus ,
In the second conversion method, the combination of each bit in the bit string is the same before and after converting the bit string,
When the first check value generation unit converts the bit string using the second conversion method, the second check value generation unit performs the rotation operation by the number of bit widths of the error check value and outputs the result to the check unit A gaming machine characterized by that. The reset condition is that the control command output by the command acquisition means is a predetermined control command,
The inspection value output means inputs the control command output by the command acquisition means, and executes a determination as to whether or not the input control command is a control command that satisfies the reset condition. The gaming machine according to claim 1. The reset condition is that the error check value converted by the second conversion method is a predetermined error check value;
The said check value output means performs determination whether the error check value converted by the said 2nd conversion system is an error check value which satisfy | fills this resetting condition. Gaming machine.   The check value output means outputs the error check value to the check value sending means while outputting the error check value whose bit string is converted by the second conversion method to the check value sending means. The gaming machine according to claim 2 or 3, wherein the first shift amount used when the input conversion method information indicates the first conversion method is updated based on the error check value.   When the control command output by the command acquisition unit is input, the method determination unit performs a method determination determination as to whether or not the control command is a control command that satisfies a predetermined method determination condition. When the determination condition is satisfied, the conversion method when converting the bit string is determined as the second conversion method, and when the method determination condition is not satisfied, the conversion method when converting the bit string is The gaming machine according to any one of claims 2 to 4, wherein the first conversion method is determined. The inspection value output means holds a plurality of different reset conditions, and can execute the determination under the plurality of reset conditions,
The storage unit has a storage area that is accessible when the gaming machine is activated and stores initial setting information of the gaming machine, and the initial setting information includes a plurality of reset conditions corresponding to each of the plurality of reset conditions. Including selection information,
The arithmetic processing unit sets specific selection information of the plurality of selection information in the inspection value output means when the gaming machine is activated,
The gaming machine according to claim 2, wherein the inspection value output unit executes the determination using the specific reset condition corresponding to the set specific selection information. . The inspection value output means holds a plurality of different update timings as update timings indicating the timing of executing the update of the first shift amount, and is capable of executing the update at the plurality of update timings,
The storage unit has a storage area that is accessible when the gaming machine is activated and stores initial setting information of the gaming machine, and the initial setting information includes a plurality of selections corresponding to each of the plurality of update timings. Including information,
The arithmetic processing unit sets specific selection information of the plurality of selection information in the inspection value output means when the gaming machine is activated,
The gaming machine according to claim 4, wherein the inspection value output unit executes the update using the specific update timing corresponding to the specific selection information that has been set. The method determining means is capable of holding a plurality of different method determination conditions and performing the method determination determination using the plurality of method determination conditions,
The storage unit has a storage area that is accessible when the gaming machine is activated and stores initial setting information of the gaming machine, and the initial setting information includes a plurality of methods corresponding to each of the plurality of method determination conditions. Including selection information,
The arithmetic processing unit sets specific selection information of the plurality of selection information in the method determination means when the gaming machine is activated,
The gaming machine according to claim 5, wherein the method determination unit executes the method determination determination using the specific method determination condition corresponding to the set specific selection information.   9. The selection information included in the initial setting information is the specific selection information that is set by the arithmetic processing unit when the gaming machine is activated. Gaming machine. In an electronic device including a main control unit that outputs a control command, a peripheral control unit that performs processing based on the control command, and an intermediate control unit provided between the main control unit and the peripheral control unit, An electronic device authentication method for authenticating validity of data transmission performed between the main control unit and the intermediate control unit,
The main control unit
An arithmetic processing step of generating and sending out the control command according to a predetermined control program stored in the storage unit;
A transmission step of transmitting the control command sent by the arithmetic processing step to the intermediate control unit;
A first check value generation step of generating an error check value to be added to the control command sent by the arithmetic processing step and checking the correctness of the control command, and converting a bit string of the generated error check value ;
Run
The intermediate control unit
A verification error check value corresponding to the error check value generated by the first check value generation step is generated, and a bit string of the generated error check value is converted in advance with the main control unit. A second inspection value generation step of converting and outputting ;
The error check value transmitted by the transmission step and the error check value output by the second check value generation step are compared to check the validity of the control command transmitted by the transmission step, and An inspection process for outputting the result information;
A relay transmission step of relaying the control command transmitted by the transmission step to the peripheral control unit and transmitting the result information to the peripheral control unit;
Run
The peripheral control unit
Performing a process based on the control command relayed by the relay transmission process and performing a process according to the result information transmitted by the relay transmission process;
The first inspection value generation step includes:
A first step of acquiring a control command sent out by the arithmetic processing step and outputting the acquired control command at a timing specified in advance;
Enter the control command outputted by the first step, the conversion method used in converting a bit string of the error check value to be added to the control command the input, with the first shift amount that varies regularly Either a first conversion method that performs a rotation operation on a bit string of an error check value, or a second conversion method that performs a rotation operation on a bit string of an error check value using a second shift amount that fluctuates irregularly. A second step of determining based on the input control command and outputting conversion method information indicating the determined conversion method in accordance with the timing;
The control command output by the first step and the conversion method information output by the second step are input, and the control command generated by the control processing process sent in the past from the input control command is generated. A third step of converting the bit string of the error check value by the conversion method indicated by the input conversion method information, and outputting the error check value converted from the bit string according to the timing;
A fourth step of inputting an error check value obtained by converting the bit string output by the third step and sending the error check value converted by the input bit string according to the control program;
Have
In the third step, when the input conversion method information indicates the first conversion method and the reset condition for resetting the first shift amount is satisfied, the first shift amount is set to a predetermined value. And converting the generated error check value bit string,
In the arithmetic processing step, the error check value transmitted in the fourth step is added to the control command to be transmitted, and the process proceeds to the transmission step .
In the second conversion method, the combination of each bit in the bit string is the same before and after converting the bit string,
In the second check value generation step, when the bit string is converted by the second conversion method in the first check value generation step, the rotation operation is performed by the number of bit widths of the error check value and output. An electronic device authentication method.

Images