JP5202681B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine, a sparrow ball gaming machine, a ball ball gaming machine such as an arrangement ball, and a revolving type gaming machine such as a slot machine installed in a gaming shop such as a pachinko shop.

Main control that controls basic actions associated with the progress of a game, among illegal acts that are performed on a gaming machine and forcibly pays out medals, game balls, etc. (hereinafter referred to as “game media”) regardless of the game content. As for the peripheral control board on which the peripheral control unit that executes the rendering process and the like based on the control command information (hereinafter referred to as “control command”) from the main control board on which the unit is mounted, is there.
(1) Replacing an authorized main control board with an unauthorized main control board (2) A ROM storing a legitimate program executed by the CPU mounted on the main control board and an unauthorized program obtained by falsifying the above program are stored. (3) An illegal board (impersonated board) is provided between the main control board and the peripheral control board, and the ROM of (2) above is replaced.

  In order to prevent such illegal acts, the conventional gaming machines include the following. For example, in the gaming machine described in Patent Document 1, the main control board generates a control command and transmits it to the sub-control board, and checks the control command transmitted by the first transmission means within a predetermined period. Second transmission means for transmitting the thumb as a state monitoring command at a predetermined timing. In addition, the sub-control board verifies the validity of the control command transmitted within the predetermined period by comparing the checksum of the control command received within the predetermined period with the state monitoring command received at the predetermined timing. doing. That is, the gaming machine described in Patent Document 1 attempts to prevent the illegal act by transmitting a state monitoring command for verifying the validity of the control command at a predetermined timing.

JP 2002-18095 A

  However, in the gaming machine described in Patent Document 1, a state monitoring command having a data format or data amount different from that of a normal control command is transmitted alone at a predetermined timing. Therefore, there is a fear that a person who intends to perform an illegal act (hereinafter referred to as “illegal person”) can easily know the timing of sending the state monitoring command and steal it. Further, in the gaming machine described in Patent Document 1, a checksum of a control command transmitted within a predetermined period is used as a state monitoring command. Therefore, there is a possibility that an unauthorized person who knows the transmission timing of the state monitoring command can easily analyze the contents of the state monitoring command by acquiring and comparing the control command and its checksum within a predetermined period. there were.

  In addition, in the gaming machine described in Patent Document 1, in order to realize the addition of the security function, a process different from the normal process of transmitting a state monitoring command is added. It is getting complicated. Therefore, in the gaming machine described in Patent Document 1, the code size of the program executed by the CPU of the main control board increases, and the processing load of the CPU increases. Also, in gaming machines, the ROM and RAM capacities of the main control board are limited due to regulations unique to public games, and more limited resources are allocated to game machine manufacturers for programs related to performance processing. There is a desire to want. Therefore, the problem that the processing load of the CPU of the main control board and the code size of the program increase by adding a security function to the gaming machine cannot be overlooked.

  In addition, when adding security functions by hardware, it is possible to suppress an increase in processing load and code size. However, when a new function is added to the existing main control board by hardware, the configuration of the CPU and peripheral circuits related to the hardware must be changed, which increases the development cost and development time of the gaming machine. Invited, it will be a big burden for game machine manufacturers. For this reason, the conventional technology cannot meet the demands of gaming machine manufacturers who want to add effective security functions to existing gaming machines relatively easily.

  The present invention has been made in view of the above circumstances, and is relatively simple while preventing the above-mentioned fraud by improving the security strength by suppressing the increase in processing load and code size. It is an object to provide a gaming machine having a security function that can be added to the game machine.

  The present invention has been made in view of the above circumstances, and can improve the security strength by preventing illegal acts by a simple means that has not been conventionally used, and can be used for general purposes while suppressing an increase in processing load and code size. An object of the present invention is to provide a gaming machine having a highly secure security function.

In order to solve the above problems, the present invention provides a main control unit that outputs a control command, a peripheral control unit that performs processing based on the control command, a post-stage control unit that is provided subsequent to the peripheral control unit, a game machine comprising, the main control unit in accordance with a predetermined control program stored in the storage unit, for allowed to transmit a control command generates said control command carried out operation in accordance with predetermined game information first outputs a transmission instruction, an arithmetic processing unit for outputting the generated control command in a predetermined output control method, is provided so as to follow to the arithmetic processing unit, based on the first transmission instruction, since allowed to transmit the control command to said error Ri test values to generate the error check value is added for checking the validity of the added control command to the control command outputted by the processing unit And outputs a second transmission instruction, and the first check value generating unit which outputs the control command in which the error check value is added at the predetermined output control method, provided subsequent to the first test value generator is and, based on the second transmission instruction, and a first transmission unit that transmits to the subsequent stage controller via the peripheral control unit of the control commands to said error check value is added, the The subsequent control unit includes a second check value generation unit that generates an error check value for verification corresponding to the error check value generated by the first check value generation unit, and the error check transmitted by the first transmission unit. by comparing the error check value generated by the value second check value generator inspects the validity of control commands sent by the first transmission unit, the inspection unit for generating a result information of the test When the said result information peripheral control unit And a second transmission unit for transmitting, the peripheral control unit, performs processing based on the control command outputted from the main controller, in accordance with the result information transmitted by said second transmission unit comprising a processing unit for performing processing, the first check value generation unit, the arithmetic processing unit receives the output control command by, entered該制the first transmission instruction defined for your command in the control program a buffer means to output at a timing based, the inputs a control command outputted by the buffer means, the entered plurality of error check values corresponding to a plurality of control command outputted by the processing unit from the past control command The error check value to be added to the control command output by the buffer means is N (N is a positive integer) from the input control command. ) Determine the error check value corresponding to the control command previously output by the arithmetic processing unit, and use the determined information about the N control commands used for generating the error check value to be added at the timing. a determining means to corresponding output, with inputs the information relating to the control command of the N-th previous output by the output control command to the determining means, for storing the control commands entered by said buffer means input Out of the plurality of control commands previously output by the arithmetic processing unit and stored in advance from the control command, the control command indicated by the input information related to the N previous control command is output according to the timing. a storage unit, and inputs the output control commands by said storing means, corresponding to the input control command The error check value is generated by calculating a control command by a predetermined operation method that a generation means to output in response to the timing the generated error check value, a control command outputted by said buffer means said The error check value output by the generating means is input, the error check value input is added to the input control command, and the second transmission instruction is output to the first transmitter according to the timing. , the control command said error Ri test values are added, anda additional means to output to the first transmission unit in accordance with prior Symbol timing at the predetermined output control method, the determination unit, the A plurality of N values for determining an error check value to be added are stored in advance, and the storage unit has a storage area that is accessible when the gaming machine is activated and stores initial setting information of the gaming machine The initial setting information includes a plurality of selection information corresponding to each of the plurality of N values, and the arithmetic processing unit selects a specific selection of the selection information when the gaming machine is activated. The information is set in the determining means, and the determining means sets the specific N value corresponding to the specific selection information set and the error check value to be added when the gaming machine is activated. When the control command output by the buffer means is input after the gaming machine is activated after the game machine is started, the set value of N is set based on the input control command. It is characterized by changing .

  According to the present invention, in order to add an authentication function for the main control unit as a security function, the error check value adding function provided in the main control unit is configured by hardware, and the control command to be transmitted is earlier than the control command. An error check value of the generated control command is added and transmitted. By applying such an unprecedented simple method, it becomes difficult for an unauthorized person to analyze the relationship between the control command and the error check value added thereto, and the security strength of the gaming machine is improved by a simple method. be able to. Further, the processing load and code size of the CPU of the main control unit, which increase with the addition of the security function, can be suppressed to the maximum. And a security function can be added comparatively easily with respect to the existing game machine.

It is a front view which shows the external appearance structure of the game machine which concerns on embodiment of this invention. It is a perspective view which shows the external appearance structure of the state which open | released the glass frame of the game machine which concerns on embodiment of this invention. It is a perspective view which shows the external appearance structure of the back surface side of the game machine which concerns on embodiment of this invention. It is a block diagram which shows the internal structure of the game machine which concerns on embodiment of this invention. It is a block diagram which shows the structure regarding the authentication process of the main control part which comprises the game machine which concerns on embodiment of this invention. It is the schematic for demonstrating the memory map of main ROM and boot ROM of the main control part which comprises the game machine which concerns on embodiment of this invention. It is the schematic for demonstrating the addition procedure of the error check value to the control command which the main control part which comprises the game machine which concerns on embodiment of this invention outputs. It is a block diagram which shows the structure regarding the authentication process of the production | presentation control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the classification of the control command transmitted to the production | presentation control part from the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the main process by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the interruption process by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the special figure special electricity control process by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the special symbol memory | storage determination process by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the boot process at the time of starting by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the command transmission process by the main control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the main process by the production | presentation control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the interruption process by the production | presentation control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the command analysis process 1 by the presentation control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the command analysis process 2 by the production | presentation control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the authentication result data analysis process by the presentation control part which comprises the game machine which concerns on embodiment of this invention. It is a figure which shows the flowchart in the main process by the back | latter stage control part which comprises the game machine which concerns on embodiment of this invention. It is a block diagram which shows the other Example in the structure of the test value production | generation part of the main control part which comprises the game machine which concerns on embodiment of this invention. It is a block diagram which shows the other Example in the structure of the hardware parameter regarding the authentication process of the main control part which comprises the game machine which concerns on embodiment of this invention, and a determination circuit.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. Specifically, a pachinko gaming machine 1 (hereinafter referred to as “gaming machine 1”), which is one of the gaming machines according to the embodiment of the present invention, will be described.

[Composition of gaming machine]
The configuration of the gaming machine 1 according to one embodiment of the present invention will be described below.
FIG. 1 is a front view showing an external configuration of the gaming machine 1 according to the present embodiment. FIG. 2 is a perspective view showing an external configuration of the gaming machine 1 according to the present embodiment in a state where the glass frame is opened. FIG. 3 is a perspective view showing an external configuration of the back side of the gaming machine 1 according to the present embodiment.

  The gaming machine 1 includes an outer frame 60 attached to an island facility of a game store, and a glass frame 50 that is rotatably supported by the outer frame 60 (see FIGS. 1 and 2). In addition, the outer frame 60 is provided with a game board 2 in which a game area 6 in which the game ball 200 flows down is formed. In the glass frame 50, an operation handle 3 for launching a game ball toward the game area 6 by being rotated, an audio output device 32 including a speaker, an effect lighting device 34 having a plurality of lamps, An effect button 35 for changing the effect mode by a pressing operation is provided.

  Further, the glass frame 50 is provided with a tray 40 for storing a plurality of game balls 200, and the tray 40 has a downward slope so that the game balls 200 flow down toward the operation handle 3. (See FIG. 2). A receiving opening (not shown) for receiving a game ball is provided at the end of the downward slope of the tray 40, and the game ball received in the receiving opening is driven by the ball feed solenoid 4b, so that the glass frame One by one is sent to a ball feed opening 41 provided on the back surface of 50. Then, the game ball sent out to the ball feed opening 41 is guided to the end of the downward slope of the launch rail 42 by the launch rail 42 having a downward slope toward the launching member 4c. A stopper 43 for stopping the game ball is provided above the downwardly inclined end portion of the launch rail 42, and the game ball 200 sent out from the ball feed opening 41 is the downwardly inclined end portion of the launch rail 42. Thus, one game ball is stopped (see FIG. 2).

  When the player rotates the operation handle 3, the launch volume 3b (see FIG. 4) directly connected to the operation handle 3 also rotates, and the launch volume of the game ball is adjusted and adjusted by the launch volume 3b. The launching member 4c directly connected to the firing solenoid 4a (see FIG. 4) rotates with the firing strength. By rotating the launch member 4 c, the game ball 200 stored at the end of the downward slope of the launch rail 42 is launched by the launch member 4 c, and the game ball is launched into the game area 6.

  When the game ball fired as described above rises between the rails 5a and 5b from the launch rail 42 and exceeds the ball return prevention piece 5c, the game ball reaches the game area 6 and then falls in the game area 6. At this time, the game ball falls unpredictably by a plurality of nails and windmills provided in the game area 6.

  The game area 6 is provided with a plurality of general winning awards 12. Each of these general winning awards 12 is provided with a general winning opening detecting switch 12a (see FIG. 4). When this general winning opening detecting switch 12a detects the winning of a game ball, a predetermined winning ball (for example, 10) Game balls).

  Further, in the area below the center of the game area 6, there are a first start port 14 and a second start port 15 that constitute a start area into which game balls can enter, and a second large area in which game balls can enter. A winning opening 17 is provided.

  The second starting port 15 has a pair of movable pieces 15b, a mode in which the pair of movable pieces 15b is maintained in a closed state (hereinafter referred to as “first mode”), and a pair of movable pieces. The movement control is performed so that 15b is in an open state (hereinafter referred to as “second aspect”). When the second starting port 15 is controlled in the first mode, the winning member of the second large winning port 17 located immediately above the second starting port 15 becomes an obstacle, and the game ball Is impossible to accept. On the other hand, when the second start port 15 is controlled to the second mode, the pair of movable pieces 15b function as a tray, and it is easy to win a game ball to the second start port 15. That is, when the second start port 15 is in the first mode, there is no game ball winning opportunity, and when it is in the second mode, the game ball winning opportunity is increased.

  Here, the first start port 14 is provided with a first start port detection switch 14a (see FIG. 4) for detecting the entrance of a game ball, and the second start port 15 is a first for detecting the entrance of a game ball. 2 A start port detection switch 15a (see FIG. 4) is provided. When the first start port detection switch 14a or the second start port detection switch 15a detects the entry of a game ball, a special symbol determination random number value is acquired, and a right acquisition lottery (to be described later) Hereinafter, “Lottery for jackpot” is performed. Also, when the first start port detection switch 14a or the second start port detection switch 15a detects the entry of a game ball, a predetermined prize ball (for example, three game balls) is paid out.

  In addition, the second grand prize winning port 17 is configured by an opening formed in the game board 2. Below the second grand prize opening 17, there is a second big prize opening / closing door 17b that can protrude from the game board surface side to the glass plate 52 side. It is controlled to move between an open state protruding to the side and a closed state buried in the game board surface. When the second grand prize opening opening / closing door 17b protrudes from the game board surface, it functions as a tray for guiding the game ball into the second big prize opening 17, and the game ball can enter the second big prize opening 17. Become. The second big prize opening 17 is provided with a second big prize opening detection switch 17a (see FIG. 4). When the second big prize opening detection switch 17a detects the entry of a game ball, it is set in advance. Award balls (for example, 15 game balls) are paid out.

Furthermore, in the area on the right side of the game area 6, there are provided a normal symbol gate 13 constituting a normal area through which game balls can pass and a first grand prize opening 16 through which game balls can enter.
For this reason, unless the game ball is a game ball that has been driven by a strong force by turning the operation handle 3 greatly, the normal design gate 13 and the first big winning opening 16 are configured so that the game ball will not pass or win. Yes.

  The normal symbol gate 13 is provided with a gate detection switch 13a (see FIG. 4) for detecting the passage of the game ball. When the gate detection switch 13a detects the passage of the game ball, the normal symbol determination random number value. Is acquired, and a “normal symbol lottery” to be described later is performed.

  The first grand prize opening 16 is normally kept closed by the first big prize opening opening / closing door 16b, and it is impossible to enter a game ball. In contrast, when a special game, which will be described later, is started, the first grand prize opening opening / closing door 16b is opened, and the first big prize opening opening / closing door 16b puts the game ball in the first big winning opening 16; It functions as a receiving tray that guides the game ball and can enter the first grand prize opening 16. The first big prize opening 16 is provided with a first big prize opening detection switch 16a (see FIG. 4). When the first big prize opening detection switch 16a detects the entry of a game ball, it is set in advance. Prize balls (for example, 15 game balls) are paid out.

  Furthermore, in the lowermost area of the game area 6 and the lowermost area of the game area 6, the general winning opening 12, the first starting opening 14, the second starting opening 15, the first major winning opening 16, and the second large winning opening. An out port 11 is provided for discharging game balls that have not entered any of the winning ports 17.

In addition, a decoration member 7 that affects the flow of the game ball is provided in the center of the game area 6. A liquid crystal display device 31 is provided at a substantially central portion of the decorative member 7, and an effect driving device 33 in the form of a belt is provided above the liquid crystal display device 31.
In this embodiment, the liquid crystal display device 31 is used as a liquid crystal display. However, an organic EL display may be used, a projector, a reel made of an annular structure, a so-called 7-segment LED, a dot matrix. A display device or the like may be used.

The liquid crystal display device 31 displays an image during standby when no game is being performed, or displays an image according to the progress of the game. Among them, three effect symbols 36 for informing the jackpot lottery result, which will be described later, are displayed, and a combination of specific effect symbols 36 (for example, 777) is stopped and displayed as a jackpot lottery result. A jackpot is announced.
More specifically, when a game ball enters the first start port 14 or the second start port 15, the three effect symbols 36 are scroll-displayed, and the scroll is stopped after a predetermined time, The effect design 36 is stopped and displayed. Further, by displaying various images, characters, and the like during the variation display of the effect symbol 36, a high expectation that the player may win a big hit is given to the player.

  The effect driving device 33 gives a player a sense of expectation according to the operation mode. The effect driving device 33 performs, for example, an operation in which the belt moves downward or a rotating member at the center of the belt rotates. Various operational feelings are given to the player depending on the operation mode of the effect driving device 33.

  Furthermore, in addition to the above-described various production devices, the audio output device 32 outputs background music, sound effects, and the like, and produces productions using sound. The production lighting device 34 includes the illumination direction of each lamp, The luminescent color is changed to produce lighting.

  The effect button 35 is effective only when, for example, a message for operating the effect button 35 is displayed on the liquid crystal display device 31. The effect button 35 is provided with an effect button detection switch 35a (see FIG. 4). When the effect button detection switch 35a detects the player's operation, a further effect is executed in accordance with this operation.

  In the lower right of the game area 6, a first special symbol display device 20, a second special symbol display device 21, a normal symbol display device 22, a first special symbol hold indicator 23, a second special symbol hold indicator 24, a normal A symbol hold indicator 25 is provided.

  The first special symbol display device 20 is for notifying a lottery result obtained when a game ball enters the first start port 14, and is composed of 7-segment LEDs. That is, a plurality of special symbols corresponding to the jackpot lottery result are provided, and the lottery result is notified to the player by displaying the special symbol corresponding to the jackpot lottery result on the first special symbol display device 20. I am doing so. For example, “7” is displayed when the jackpot is won, and “−” is displayed when the player wins. “7” and “−” displayed in this way are special symbols, but these special symbols are not displayed immediately, but are displayed in a stopped state after being displayed for a predetermined time. .

  Here, the “successful lottery” means that when a game ball enters the first starting port 14 or the second starting port 15, a special symbol determining random number value is acquired, and the acquired special symbol determining random value is acquired. Is a random number value corresponding to “big hit” or a random number value corresponding to “small hit”. The jackpot lottery result is not immediately notified to the player, and the first special symbol display device 20 displays a variation such as blinking of the special symbol, and when the predetermined variation time has passed, the jackpot lottery result The special symbol corresponding to is stopped and displayed so that the player is notified of the lottery result. The second special symbol display device 21 is for notifying a lottery result of a jackpot that is performed when a game ball enters the second start port 15, and the display mode is the above-described first display mode. This is the same as the special symbol display mode in the special symbol display device 20.

  Further, in this embodiment, “big hit” means that a right to win a big hit game is obtained in a big win lottery performed on condition that a game ball has entered the first start port 14 or the second start port 15 Say what you did. In the “hit game”, a round game in which the first big prize opening 16 or the second big prize opening 17 is opened is performed 15 times in total. A predetermined time is set for the maximum opening time of the first grand prize port 16 or the second grand prize port 17 in each round game, and during this time, the first grand prize port 16 or the second grand prize port 17 is set. When a predetermined number of game balls (for example, nine) enter, one round game is completed. In other words, the “big hit game” is a game in which a game ball can enter the first grand prize winning opening 16 or the second big winning prize opening 17 and the player can acquire a winning ball according to the winning prize.

In this embodiment, in the “hit lottery”, two gaming states are set according to the winning probability. That is, the “low probability gaming state” in which the winning probability is set to 1 / 299.5 and the “high probability gaming state” in which the winning probability is set to 1 / 29.95. Also, in the “jackpot game”, a plurality of types of jackpot games are set. For example, in the case of “game per long”, the first grand prize opening 16 is released once (× 15 rounds) for 29.000 seconds for each round game. If it is “short win game”, the second big prize opening 17 is opened for 0.052 seconds × 1 time (× 15 rounds) for each round game. In the case of “game per development”, the second grand prize opening 17 is opened for 0.052 seconds × 3 times in the first round game, and after the second round, 29.000 seconds × 1 for each round game. Times (× 14 rounds).
In the case of “small hit”, one gaming state with a winning probability of 1 / 149.75 is set. In addition, if it is a “small hit game”, although it is not a round game, the second big prize opening 17 is opened for 0.052 seconds × 15 times. In the present embodiment, “big hit game” and “small hit game” are collectively referred to as “special game”.

  The normal symbol display device 22 is for notifying the lottery result of the normal symbol that is performed when the game ball passes through the normal symbol gate 13. As will be described in detail later, when the winning symbol is won by the normal symbol lottery, the normal symbol display device 22 is turned on, and then the second start port 15 is controlled to the second mode for a predetermined time.

  Here, “normal symbol lottery” means that when a game ball passes through the normal symbol gate 13, the normal symbol determination random number value is acquired, and the acquired normal symbol determination random value corresponds to “winning”. A process for determining whether or not the value is a random value. The lottery result of the normal symbol is not always notified immediately after the game ball passes through the normal symbol gate 13, but the normal symbol display device 22 displays a variation such as blinking of the normal symbol. When the fluctuation time elapses, the normal symbol corresponding to the lottery result of the normal symbol is stopped and displayed so that the player is notified of the lottery result.

Furthermore, if a game ball enters the first start port 14 or the second start port 15 during special symbol fluctuation display or a special game to be described later, and if the big hit lottery cannot be performed immediately, a certain condition The right to win a jackpot will be withheld. More specifically, the random number value for special symbol determination acquired when the game ball enters the first start port 14 is stored as the first hold, and when the game ball enters the second start port 15 The acquired special symbol determination random number value is stored as the second hold.
For both of these holds, the upper limit hold number is set to 4, and the hold number is displayed on the first special symbol hold indicator 23 and the second special symbol hold indicator 24, respectively. When there is one first hold, the LED on the left side of the first special symbol hold indicator 23 lights up, and when there are two first holds, two LEDs on the first special symbol hold indicator 23 Lights up. In addition, when there are three first holds, the LED on the left side of the first special symbol hold indicator 23 blinks and the right LED is lit, and when there are four first holds, the first special symbol hold. Two LEDs on the display 23 blink. The second special symbol hold indicator 24 also displays the number of second hold on hold in the same manner as described above.
The upper limit reserved number of normal symbols is also set to four, and the reserved number of normal symbols is displayed in the same manner as the first special symbol hold indicator 23 and the second special symbol hold indicator 24. Displayed on the instrument 25.

  The glass frame 50 supports a glass plate 52 that covers the game area 6 so as to be visible in front of the game board 2 (player side). The glass plate 52 is detachably fixed to the glass frame 50.

  The glass frame 50 is connected to the outer frame 60 via the hinge mechanism 51 on one end side in the left-right direction (for example, the left side facing the gaming machine 1). The other end side (for example, the right side facing the gaming machine 1) can be rotated in a direction to release from the outer frame 60. The glass frame 50 covers the game board 2 together with the glass plate 52, and can be opened like a door with the hinge mechanism 51 as a fulcrum to open the inner part of the outer frame 60 including the game board 2. On the other end side of the glass frame 50, a lock mechanism for fixing the other end side of the glass frame 50 to the outer frame 60 is provided. The fixing by the lock mechanism can be released by a dedicated key. The glass frame 50 is also provided with a door opening switch 133 (see FIG. 4) for detecting whether or not the glass frame 50 is opened from the outer frame 60.

  On the back surface of the gaming machine 1, a main control board on which the main control unit 110 is mounted, an effect control board on which the effect control unit 120 is mounted, a rear control board on which the rear control unit 180 is mounted, and a payout control unit 130 The payout control board, the power board on which the power supply unit 170 is mounted, the game information output terminal board 30 and the like are provided. Further, the power supply unit 170 is provided with a power plug 171 for supplying power to the gaming machine 1 and a power switch (not shown).

[Internal configuration of gaming machine]
Hereinafter, control means for controlling processing related to game progress of the gaming machine 1 according to the embodiment of the present invention will be described.
FIG. 4 is a block diagram showing an internal configuration of the gaming machine 1 according to the present embodiment.

  The main control unit 110 is a main control means for controlling the basic operation of the game, and receives various detection signals from the first start port detection switch 14a, etc., and opens and closes the first special symbol display device 20 and the first grand prize opening. The game is controlled by driving the solenoid 16c and the like.

  The main control unit 110 includes a one-chip microcomputer 110m including at least a main CPU 110a, a main ROM 110b, a main RAM 110c, and a boot ROM 110d, a test value generation unit 500, a transmission unit 550, an input port and an output port for main control. (Not shown).

  The main control input port includes a payout control unit 130, a general winning port detecting switch 12a for detecting that a gaming ball has entered the general winning port 12, and a game ball having been inserted into the normal symbol gate 13. Gate detection switch 13a to detect, first start port detection switch 14a to detect that a game ball has entered the first start port 14, and second start to detect that a game ball has entered the second start port 15 The mouth detection switch 15a, the first grand prize opening detection switch 16a that detects that a game ball has entered the first grand prize opening 16, and the second that detects that a game ball has entered the second grand prize opening 17 A big prize opening detection switch 17a is connected. Various signals are input to the main control unit 110 through the input port for main control.

  The main control output port includes a payout control unit 130, a start opening / closing solenoid 15c for opening / closing the pair of movable pieces 15b of the second start opening 15, and a first large winning opening opening / closing door 16b. A special winning opening / closing solenoid 16c, a second large winning opening / closing solenoid 17c for operating the second winning opening / closing door 17b, a first special symbol display device 20 and a second special symbol display device 21 for displaying special symbols, and a normal symbol. A normal symbol display device 22 for displaying a symbol, a first special symbol hold indicator 23 and a second special symbol hold indicator 24 for displaying the number of reserved balls for a special symbol, and a normal symbol hold indicator for displaying the number of reserved balls for a normal symbol 25. A game information output terminal board 30 for outputting an external information signal is connected. Various signals are output from the main control output port.

  The main CPU 110a of the main control unit 110 reads out a program stored in the main ROM 110b based on an input signal from each detection switch or a timer (not shown) incorporated as an internal function, and performs arithmetic processing. Depending on the result, a control instruction (hereinafter referred to as “control signal”) for each component constituting the main control unit 110 and a control command for another control unit other than the main control unit 110 are output.

The main ROM 110b of the main control unit 110 stores in advance a game processing program that describes the content and procedure of processing related to game progress, and fixed data and tables necessary for determining various games.
As an example of a table stored in the main ROM 110b, a jackpot determination table referred to in the jackpot lottery, a hit determination table referred to in the normal symbol lottery, a symbol determination table for determining the stop symbol of the special symbol, after the jackpot ends End of jackpot game setting data table for determining the gaming state of the game, special electric accessory operating mode determination table for determining the opening / closing conditions of the special winning opening opening door, determining the opening pattern table of the special winning opening, and the variation pattern of the special symbol There is a variation pattern determination table.

  Further, the main ROM 110b is used when executing an authentication processing program describing the content and procedure of processing for transmitting a control command from the transmission unit 550 via the inspection value generation unit 500, and an authentication processing program. Fixed data and the like are stored in advance. The main ROM 110b also stores initial values set for the built-in circuit and peripheral circuits of the one-chip microcomputer 110m during the boot process of the main control unit 110 performed when the gaming machine 1 is reset such as when the power is turned on. So-called hardware parameters) are stored in advance. In addition, unique information that is unique to the gaming machine 1 is stored in the main ROM 110b in advance.

  The boot ROM 110d of the main control unit 110 includes a boot executed by the main CPU 110a, including initialization of internal circuits and peripheral circuits of the one-chip microcomputer 110m and initial value setting processing (hereinafter referred to as “initial value setting processing”). A boot processing program describing the contents and procedure of processing, and fixed data used when executing the boot processing program are stored. This boot processing program is set to start immediately after the main CPU 110a is activated.

The main RAM 110c of the main control unit 110 functions as a data work area during the arithmetic processing of the main CPU 110a, and has a plurality of storage areas.
As an example of the storage area that the main RAM 110c has, a normal symbol holding number (G) storage area, a normal symbol holding storage area, a normal symbol data storage area, a first special symbol holding number (U1) storage area, a second special symbol Reservation count (U2) storage area, first special symbol random value storage area, second special symbol random value storage area, round game number (R) storage area, number of open times (K) storage area, number of big winning entrances ( C) Storage area, game state storage area (high probability game flag storage area, etc.), high probability game count (X) counter, game state buffer, stop symbol data storage region, transmission data storage region, special symbol time counter, special There are various timer counters such as game timer counters.

  The inspection value generation unit 500 of the main control unit 110 is provided between the main CPU 110a and the transmission unit 550. When the main control unit 110 transmits a control command, the check value generation unit 500 checks the validity of the control command and generates an error check value for authenticating the validity of the main control unit 110. Has a function (hereinafter referred to as “error check value addition function”). Specifically, the inspection value generation unit 500 receives a control command from the main CPU 110a when the main CPU 110a performs a process of transmitting a control command by the transmission unit 550 (hereinafter referred to as “command transmission process”). Then, the check value generation unit 500 performs a process of generating an error check value of the received control command (hereinafter referred to as “check value generation process”). Then, check value generation unit 500 performs processing for adding the generated error check value to the control command (hereinafter referred to as “check value addition processing”), and then outputs the control command with the error check value to transmission unit 550. To do.

  The transmission unit 550 of the main control unit 110 is a control command to a control unit (a later stage control unit 180 to be described later) that is determined in advance to perform an authentication function for the main control unit 110 among the output ports for main control. Used for output. Specifically, the transmission unit 550 is provided subsequent to the inspection value generation unit 500, and the control command with an error inspection value output from the inspection value generation unit 500 is transmitted to the effect control unit 120 and the payout control unit 130. Etc. to the subsequent stage control unit 180.

  The game information output terminal board 30 is a board for outputting an external information signal generated by the main control unit 110 to a hall computer or the like of a game store. The game information output terminal board 30 is connected to the main controller 110 by wiring, and is provided with a connector for connecting external information to a hall computer or the like of a game store.

  The power supply unit 170 includes a backup power source composed of a capacitor, supplies a power supply voltage to the gaming machine 1, and monitors a power supply voltage supplied to the gaming machine 1, and when the power supply voltage becomes a predetermined value or less, An electric interruption detection signal is output to the main control unit 110. More specifically, when the power interruption detection signal is at a low level and a certain time has elapsed since the power supply voltage is equal to or lower than a set value, the reset signal is at a low level and the main CPU 110a performs a process of stopping the operation. Thereafter, when the power interruption detection signal becomes a high level because the power supply voltage is equal to or higher than the set value and a predetermined time elapses, the reset signal becomes a high level, and the main CPU 110a performs a process of starting an operation. The backup power source is not limited to a capacitor, and may be a battery, for example, or a capacitor and a battery may be used in combination.

  The effect control unit 120 mainly controls each effect such as during a game or standby. The effect control unit 120 includes a sub CPU 120a, a sub ROM 120b, and a sub RAM 120c, and is connected to the main control unit 110 so as to be able to communicate in one direction from the main control unit 110 to the effect control unit 120. Has been.

  The sub CPU 120a reads out the program stored in the sub ROM 120b based on the control command transmitted from the main control unit 110 or the input signal from the effect button detection switch 35a and the timer, performs arithmetic processing, and Based on the processing, the corresponding data is transmitted to the lamp control unit 140 or the image control unit 150. The sub RAM 120c functions as a data work area during the arithmetic processing of the sub CPU 120a.

  For example, when the sub CPU 120a in the effect control unit 120 receives a variation pattern designation command indicating a variation pattern of a special symbol, which is one of the control commands transmitted from the main control unit 110, the contents of the received variation pattern designation command are displayed. Analysis is performed to generate data for causing the liquid crystal display device 31, the audio output device 32, the effect driving device 33, and the effect illumination device 34 to execute a predetermined effect, and the data is used for the image control unit 150 and the lamp control unit. 140.

  As will be described later, when the rear control unit 180 is connected to the effect control unit 120, when the sub CPU 120a receives the control command transmitted from the main control unit 110, the sub CPU 120a receives the control command received. A relay transmission process is performed in which the control command is transmitted to the succeeding post-control unit 180 while maintaining the specific processing contents and the reception order. When the latter control unit 180 is connected to the payout control unit 130, a payout CPU described later has a configuration related to the relay transmission process of the effect control unit 120.

The sub ROM 120b of the effect control unit 120 stores a program for effect control, data necessary for determining various games, and a table.
As an example of the table stored in the sub-ROM 120b, to determine a combination of an effect pattern determination table for determining an effect pattern based on a variation pattern designation command received from the main control unit and an effect symbol 36 to be stopped and displayed. There is a production design determination table.

The sub RAM 120c of the effect control unit 120 functions as a data work area during the arithmetic processing of the sub CPU 120a, and has a plurality of storage areas.
As an example of the storage area that the sub-RAM 120c has, there are a game state storage area, an effect mode storage area, an effect pattern storage area, an effect symbol storage area, and the like.

  The post-stage control unit 180 is a control means for mainly realizing an authentication function for the main control unit 110, and includes a CPU 180a, a ROM 180b, and a RAM 180c. The post-stage control unit 180 is subsequent to the control unit (the production control unit 120, the payout control unit 130, etc.) to which the main control unit 110 transmits a control command related to the original game process, as viewed from the main control unit 110. It is provided to do.

  For example, as shown in FIG. 4, when the rear control unit 180 is provided to follow the effect control unit 120, the rear control unit 180 can communicate with the effect control unit 120 in both directions. So connected. Although not shown, when the rear stage control unit 180 is provided to follow the payout control unit 130, the rear stage control unit 180 is connected so as to be capable of bidirectional communication with the payout control unit 130. Has been. Therefore, the post-stage control unit 180 does not transmit a control command directly from the main control unit 110, but transmits it via the effect control unit 120, the payout control unit 130, and the like.

  The CPU 180a stores in the ROM 180b based on a control command transmitted from the main control unit 110 via the effect control unit 120 or the payout control unit 130 or an input signal from a timer (not shown) incorporated as an internal function. The read program is read out and arithmetic processing is performed. Then, the CPU 180a transmits corresponding data to the effect control unit 120, the payout control unit 130, and the like based on the processing. The RAM 180c functions as a data work area during the arithmetic processing of the CPU 180a.

  For example, when the CPU 180a of the post-stage control unit 180 receives the control command relayed from the effect control unit 120 or the payout control unit 130 as described above, the CPU 180a checks the legitimacy of the control command and performs the control of the main control unit 110. An error check process for authenticating the correctness is performed. Then, the CPU 180a transmits authentication result information (hereinafter referred to as “authentication result data”) obtained by the processing to the effect control unit 120, the payout control unit 130, and the like, and executes processing based on the authentication result data. . In addition, the CPU 180a performs a relay transmission process in which the control command is relay-transmitted to the effect control unit 120, the payout control unit 130, and the like while maintaining the specific processing contents and the reception order of the received control command.

Further, the ROM 180b has an authentication processing program describing the contents and procedure of authentication processing including error checking processing for the received control command performed by the CPU 180a, and a fixed used for executing the authentication processing program. Data and information corresponding to the unique information stored in the main ROM 110b of the main control unit 110 are stored in advance.
As described above, the post-stage control unit 180 is obtained by the error checking process, the authentication function for the main control unit 110, the function of relaying the received control command again to the effect control unit 120, the payout control unit 130, and the like. It has at least a function of transmitting the authentication result data to the effect control unit 120, the payout control unit 130, and the like. In addition, the structure regarding these authentication processes is mentioned later.

  The payout control unit 130 controls payout of game balls. The payout control unit 130 includes a one-chip microcomputer including a payout CPU, a payout ROM, and a payout RAM (not shown), and is connected to the main control unit 110 so as to be capable of bidirectional communication. .

  The payout CPU reads out a program stored in the payout ROM based on input signals from the payout ball count switch 132, the door opening switch 133, and the timer that detect whether or not the game ball has been paid out, and performs arithmetic processing. At the same time, the corresponding data is transmitted to the main control unit 110 based on the processing.

  Further, a payout motor 131 of a payout device for paying out a predetermined number of game balls from the game ball storage unit is connected to the output side of the payout control unit 130. The payout CPU reads out a predetermined program from the payout ROM based on a payout number designation command that is one of the control commands transmitted from the main control unit 110, performs arithmetic processing, and controls the payout motor 131 of the payout device. Then, a predetermined game ball is paid out. At this time, the payout RAM functions as a data work area at the time of calculation processing of the payout CPU.

  The lamp control unit 140 controls lighting of the effect lighting device 34 provided on the game board 2 and controls driving of the motor for changing the light irradiation direction. In addition, energization control is performed on a drive source such as a solenoid or a motor that operates the effect driving device 33. The lamp control unit 140 is connected to the effect control unit 120, and performs the above-described controls based on various commands transmitted from the effect control unit 120.

  The image control unit 150 stores a host CPU for performing image display control of the liquid crystal display device 31, a host RAM having a temporary storage area functioning as a work area of the host CPU, a control processing program for the host CPU, and the like. A host ROM, a CGROM storing image data, a VRAM having a frame buffer for drawing image data, a VDP (Video Display Processor) serving as an image processor, and a sound control circuit for controlling sound.

Based on the effect pattern designation command received from the effect control unit 120, the host CPU instructs the liquid crystal display device 31 to display the image data stored in the CGROM in the VDP.
The VDP draws image data stored in the CGROM in the frame buffer of the VRAM based on an instruction from the host CPU. Next, a video signal (RGB signal or the like) is generated based on the image data stored in the display frame buffer in the VRAM, and the generated video signal is output to the liquid crystal display device.

  The sound control circuit includes an audio ROM that stores a large number of audio data. The sound control circuit reads a predetermined program based on a command transmitted from the effect control unit 120 and also outputs the audio output device 32. Audio output control at.

  The launch control unit 160 performs launch control of the game ball. In the firing control unit 160, the touch sensor 3a and the firing volume 3b are connected to the input side, and the firing solenoid 4a and the ball feeding solenoid 4b are connected to the output side. The firing control unit 160 inputs a touch signal from the touch sensor 3a and performs control to energize the firing solenoid 4a and the ball feed solenoid 4b based on the voltage supplied from the firing volume 3b.

  The touch sensor 3a is provided in the inside of the operation handle 3, and is comprised from the electrostatic capacitance type proximity switch using the change of the electrostatic capacitance by the player touching the operation handle 3. When the touch sensor 3a detects that the player has touched the operation handle 3, the touch sensor 3a outputs a touch signal that permits energization of the firing solenoid 4a to the firing control unit 160 (see FIG. 4). The firing control unit 160 is configured so that the game ball 200 is not fired into the game area 6 unless a touch signal is input from the touch sensor 3a.

  The firing volume 3b is provided directly connected to a rotating portion around which the operation handle 3 rotates, and is composed of a variable resistor. The firing volume 3b divides a constant voltage (for example, 5V) applied to the firing volume 3b by a variable resistor, and supplies the divided voltage to the firing control unit 160 (the voltage to be supplied to the firing control unit 160). Variable). The launch controller 160 energizes the launch solenoid 4a based on the voltage divided by the launch volume 3b, and rotates the launch member 4c directly connected to the launch solenoid 4a, thereby playing the game ball 200 in the game. Fire into area 6.

  The launching solenoid 4a is composed of a rotary solenoid, and a launching member 4c is directly connected to the launching solenoid 4a, and the launching member 4c is rotated by rotating the launching solenoid 4a.

  Here, the rotational speed of the firing solenoid 4a is set to about 99.9 (times / minute) based on the frequency based on the output period of the crystal oscillator provided in the firing control unit 160. As a result, the number of games played per minute is about 99.9 (pieces / minute) because one shot is fired every time the firing solenoid rotates. That is, one game ball is fired about every 0.6 seconds.

  The ball feed solenoid 4b is composed of a linear solenoid, and sends out the game balls in the tray 40 one by one toward the launch member 4c directly connected to the launch solenoid 4a.

  Here, based on the control command from the main control unit 110 such as the effect control unit 120, the payout control unit 130, the lamp control unit 140, the image control unit 150, and the launch control unit 160 having the above-described configuration, or based on the control command. A control unit that performs control processing of the gaming machine 1 in accordance with a command generated based on the command, and the control units other than the subsequent control unit 180 are collectively referred to as a “peripheral control unit 300”. In addition, each control board on which each control unit of the peripheral control unit 300 is mounted, such as an effect control board on which the effect control unit 120 is mounted and a payout control board on which the payout control unit 130 is mounted, is collectively referred to as “peripheral control board” " Note that the rear stage control unit 180, the lamp control unit 140, and the image control unit 150 can be mounted on the same substrate as the effect control unit 120. Further, the payout control unit 130 and the firing control unit 160 can be mounted on the same substrate as the main control unit 110.

[Internal configuration related to authentication processing of gaming machines]
Hereinafter, control means for realizing the security function that the gaming machine 1 having the above configuration has for preventing fraud will be described.
The security function of the gaming machine 1 according to the present embodiment is realized by the post-stage control unit 180 checking the validity of the control command transmitted from the main control unit 110 and authenticating the main control unit 110. Then, the authentication result obtained by the latter control unit 180 is transmitted to the peripheral control unit 300, and processing according to the authentication result received by the peripheral control unit 300 is performed. Therefore, the processing executed by the main control unit 110, the subsequent control unit 180, and the peripheral control unit 300 is referred to as “authentication processing” in a sense that distinguishes it from processing related to normal game progress. In the present embodiment, the rear control unit 180 is connected subsequent to the effect control unit 120, and the authentication result obtained by the rear control unit 180 is sent to the effect control unit 120 in the peripheral control unit 300. The transmission control unit 120 will be described as performing processing according to the authentication result.

  Specifically, when the main control unit 110 generates a control command and transmits the control command to the subsequent control unit 180 via the effect control unit 120, the main control unit 110 checks the error of the control command generated before (in the past) the control command. A value is generated and added to the control command to be transmitted this time. The post-stage control unit 180 collates the error check value added to the control command received this time with the error check value generated in advance using the control command received before the control command. If the two match, the validity of the control command received this time is authenticated, and it is determined that the main control unit 110 has been successfully authenticated. The rear control unit 180 transmits the obtained authentication result for the main control unit 110 to the effect control unit 120. The effect control unit 120 confirms the authentication result transmitted from the subsequent control unit 180, and performs a process according to the authentication result.

  FIG. 5 is a functional block diagram showing an internal configuration related to authentication processing of the main control unit 110 according to the present embodiment. FIG. 6 is a schematic diagram for explaining a memory map of (a) main ROM 110b and (b) boot ROM 110d according to the present embodiment. FIG. 7 is a schematic diagram for explaining a procedure for adding an error check value to a control command according to the present embodiment. In FIG. 6, areas other than the characteristic area of the present invention are omitted. The address notation such as “xxxFH” is provided for convenience in order to indicate the division of each region, and the positional relationship between the regions is not limited to the positional relationship shown in FIG. .

  The main control unit 110, in addition to the main CPU 110a, the main ROM 110b, and the boot ROM 110d as described above, and a test value generation unit 500 that performs error check value generation processing and addition processing based on control instructions from the main CPU 110a, And a transmission unit 550 that performs a process of transmitting a control command to the control unit 120. Each component of the main control unit 110 is connected by a bus (not shown) so that various data and signals output from the main control unit 110 can be transmitted and received.

  The bus has at least the functions of an address bus, a data bus, and a control bus, assigns data passing on the bus based on control signals output from each component of the main control unit 110, and does not cause data collision So that it is controlled. In FIG. 5, for convenience, it is not shown in the form of a bus, but is represented as a signal line that connects each component of the main control unit 110, and only the characteristic ones are shown. In addition, a predetermined clock signal output from a clock pulse generation circuit (not shown) is input to each component of the main control unit 110.

  The main CPU 110a executes processing related to game progress as described above, and also executes authentication processing in the gaming machine 1. The main CPU 110a executes various arithmetic processes using an authentication processing program and various fixed data stored in the main ROM 110b. Further, the main CPU 110a executes various arithmetic processes using a boot processing program stored in the boot ROM 110d and various initial values stored in the main ROM 110b. Then, the main CPU 110a outputs a control signal and a control command according to the result of these arithmetic processes.

  For example, when the main CPU 110a performs a command transmission process of a control command to be transmitted to the effect control unit 120 based on the authentication processing program, the main CPU 110a writes a control signal ( (Hereinafter referred to as “write signal”), and the control command is transmitted by the transmitter 550 via the test value generator 500.

  Further, the main CPU 110a, when performing initial value setting processing during boot processing based on the boot processing program, reads control signals (hereinafter referred to as “read signals”) for reading various initial values stored in the main ROM 110b. To obtain various initial values, and outputs the obtained initial values to the configuration circuit corresponding to each of the obtained initial values to perform various initial value settings.

  When the main CPU 110a needs to set unique information (described later) in the test value generation unit 500 during the initialization process of the main control unit 110, the main CPU 110a outputs a read signal for reading the unique information stored in the main ROM 110b. A process of outputting and acquiring the unique information and setting the acquired unique information in the inspection value generation unit 500 is performed.

  In addition to the game processing program and data as described above, the main ROM 110b stores in advance an authentication processing program for the main CPU 110a to execute the authentication processing in the gaming machine 1 (FIG. 6A). (Region of “xxx0H” to “xxxzFH”). The main ROM 110b stores unique information of the gaming machine 1 used as an error check value added to a control command that is output for the first time after the main control unit 110 is initialized (in FIG. 6A). “Xyz0H” to “xzzFH”). Further, the main ROM 110b outputs an authentication processing program code, unique information, and the like in response to a read signal from the main CPU 110a.

  The unique information is not particularly limited as long as it is unique to the gaming machine 1 held by the main control unit 110. In FIG. 6A, the unique information is data (for example, control) in a specific address (area “xyz0H” to “xzzFH” in FIG. 6A) in the area where the fixed data of the main ROM 110b is stored. Command data), for example, a checksum value at a specific address in an area (the area from “0000H” to “xxxFH” in FIG. 6A) in which the program code of the main ROM 110b is stored, An identification number (ID) uniquely assigned to the main CPU 110a, product information such as a manufacturer code and a model code, and the like can be used. Further, the unique information can be dummy data of an error check value that is negotiated with the subsequent control unit 180 in advance. These data may be values obtained by performing four arithmetic operations or logical operations. The unique information may be stored in storage means (memory cell, ROM, etc.) separate from the main ROM 110b.

  When the control command output by the main control unit 110 is transmitted to the effect control unit 120, as shown in FIG. 7, the error check value of the control command generated before (past) the control command to be transmitted this time. Is added. The error check value to be added is stored in a predetermined storage area (a storage circuit 522 described later).

  However, when the main control unit 110 is initialized at the time of resetting the gaming machine 1 such as immediately after the power is turned on, an error check value to be added stored in the storage area (a storage circuit 522 described later) is also included. Cleared. At this time, after the error check value to be added is cleared, specific information stored in advance in the main ROM 110b is used as an error check value to be added to the first generated control command or the like (hereinafter referred to as “initial check value”). Use. Depending on the contents of the error check value adding procedure described later, a plurality of initial check values (N; N is a positive integer) is necessary, so that the specific information is prepared in advance for at least the required number of initial check values. Has been.

  Here, immediately after the error check value is cleared as described above, the control command generated first is referred to as “control command (1)”, and the error check value generated using the control command (1) is referred to as “control command (1)”. This is referred to as “error check value (1)”. Similarly, the control command generated Pth (P is a positive integer) after the error check value is cleared as described above is called “control command (P)” and is generated using the control command (P). The error check value thus obtained is referred to as “error check value (P)”. The value of P indicates the number of generated control commands immediately after the error check value is cleared as described above, and may be counted by a known counter circuit or the like (hereinafter, P is referred to as “number of generated”). .

  In the present embodiment, a generated number storage area (P) is provided in the main RAM 110c, and the main CPU 110a updates the value of the generated number storage area (P) by adding 1 during command transmission processing. As a result, the main CPU 110a is the control command that is output at the time of command transmission processing, and is the control command that is generated after the main control unit 110 is initialized and the error check value to be added is cleared. I can understand. If P = 1, the main CPU 110a outputs the unique information stored in advance in the main ROM 110b to the inspection value generation unit 500 as an initial inspection value.

  In the present embodiment, the control command actually output in the current command transmission process is the control command (P), and the control command generated N times before the control command (P) is the control command (P -N). Then, the error check value (PN) of the control command (PN) generated N times before is added to the control command (P). Then, the control command (P) and the error check value (PN) are transmitted to the effect control unit 120. The value of N is a number determined in advance as to how many error check values of the previously generated control command are added to the control command to be transmitted this time (hereinafter, N is referred to as “retroactive number”). ").

  In addition, if the main control unit 110 generates a control command (P) and transmits it to the effect control unit 120, N is a control command transmitted before the control command transmitted this time. It can be considered that this is a predetermined number of whether or not to add an error check value. The present invention includes such a concept. That is, in this case, the error check value (PN) is the error check value of the control command (PN) transmitted N times before the control command (P) transmitted this time. In the present embodiment, the expressions “error check value” and “error check value (P−N)” include initial check values (initial check values) added when P ≦ N, unless otherwise specified. Any one of the values (1) to the initial inspection value (N) will be described.

  The main ROM 110b is one of the initial values (so-called hardware parameters) of the built-in circuit and peripheral circuits of the one-chip microcomputer 110m as described above, and is a hardware parameter set in the inspection value generation unit 500. (Hereinafter referred to as “HW parameter”) is stored in advance (regions “yyy0H” to “yyzFH” in FIG. 6A). The HW parameter is selection information for selecting which error check value addition function is to be adopted from among the functions (error check value addition function) for generating and adding a plurality of error check values that the check value generation unit 500 has. is there. The error check value addition function and the selection information thereof are determined in advance between the main control unit 110 and the subsequent control unit 180.

  In the present embodiment, the test value generation unit 500 has, as a specific embodiment of a plurality of error check value addition functions, a retroactive number that is information indicating an error check value to be added to the control command transmitted this time. A plurality are prepared in advance. In the present embodiment, during the initial value setting process during the boot process, a specific retroactive number among a plurality of retroactive numbers prepared in advance for the inspection value generation unit 500 is set. The HW parameter is selection information for selecting which value of N is adopted as the specific retroactive number.

  For example, a plurality of HW parameters associated with each of a plurality of retroactive numbers are prepared, and the test value generation unit 500 is provided with a data table in which the correspondence between the retroactive number and the HW parameters is known in advance. When the main CPU 110a sets a specific HW parameter in the test value generation unit 500 during the initial value setting process during the boot process, the test value generation unit 500 confirms the set HW parameter and sets the HW parameter. Use the corresponding retroactive number as the default value.

  In the present embodiment, in the setting process performed by the main CPU 110a and the initial value setting process during the boot process, the process of setting a specific HW parameter in the test value generation unit 500 is particularly referred to as “HW parameter setting process”. Further, in the present embodiment, the setting process performed by the check value generation unit 500 determines the retroactive number indicating the error check value to be added to the control command at the time of command transmission processing, and according to the determined retroactive number The process of setting the generation means 520 described later so that the error check value is output is called “retroactive number setting process”. Details of the retroactive number setting process will be described later.

  The area for storing the initial value and the HW parameter is the area in the main ROM 110b in FIG. 6, but the present invention is not limited to this, and the area is stored in a memory cell separate from the main ROM 110b or the boot ROM 110d. It can also be configured to be stored in. That is, in the present invention, the storage area for the initial value and the HW parameter and the storage area for the game processing program, fixed data, etc. may be mounted on the same storage means (memory cell, ROM, etc.). It may be mounted on different storage means.

  The boot ROM 110d stores a boot processing program and fixed data used when executing the boot processing program in advance (regions “zxx0H” to “zyzFH” in FIG. 6B). The boot processing program is set in advance to be read from the boot ROM 110d into a boot processing dedicated RAM (not shown) immediately after the main CPU 110a is started, and to be executed by the main CPU 110a. It controls diagnosis processing, initialization of a built-in circuit of the one-chip microcomputer 110m on which the main CPU 110a is mounted, peripheral circuits including the test value generation unit 500, and initial value setting processing (that is, initial value setting processing). In the present embodiment, a program other than the boot processing program such as a game processing program executed after the boot processing is referred to as a “user program”.

  The boot processing program is a program developed and implemented by a CPU manufacturer, and access to the boot ROM 110d in which these programs are stored is limited to access from the main CPU 110a during boot processing after the gaming machine 1 is shipped. . On the other hand, the user program is a program developed and implemented by a gaming machine manufacturer, and access to the main ROM 110b in which these are stored is accessed from the main CPU 110a every time a game process is executed.

  However, even in the storage area of the main ROM 110b, user programs, fixed data, etc. (such as areas in which initial values (including HW parameters) such as built-in circuits of the one-chip microcomputer 110m and peripheral circuits including the test value generation unit 500 are stored) A storage area other than the area in which the unique information is stored (for example, an area from “xxx0H” to “yyzFH” in FIG. 6A) is an area defined only in the boot processing program, It is an area that does not appear at all on the user program related to game processing. That is, after the boot process is completed, the above-mentioned area ("xxx0H" to "yyzFH" in FIG. 6A) is an area that is substantially restricted so that it cannot be accessed from the user program. ing.

  However, in consideration of the case where unauthorized access is attempted, the following additional restrictions can be applied to further improve the confidentiality of the HW parameters obtained only during the boot process.

  To restrict access to the boot ROM 110d and the main ROM 110b, for example, an execution address monitoring unit (not shown) is provided in the main control unit 110, and the execution address monitoring unit is activated after the boot process is completed. If an attempt is made to access an area exceeding (for example, the area from “0000H” to “xzyFH” in FIG. 6A), a reset signal is output to the main CPU 110a to stop the operation of the main CPU 110a. Good. Further, a notification signal indicating that an abnormality has been detected may be output before the reset signal is output.

  A plurality of methods are conceivable for mounting the HW parameters in the main ROM 110b. For example, a plurality of HW parameters corresponding to each of a plurality of retroactive numbers prepared in advance in the inspection value generation unit 500 are prepared in advance and mounted on the main ROM 110b. A program for selecting which HW parameter to use in the HW parameter setting process is installed in the boot ROM 110d so that it is possible to arbitrarily select which retroactive number is used every time the boot process is performed. Can be configured. When implemented in this way, the retroactive number is changed every time the boot process is performed, the confidentiality of the error check value addition function can be improved, and the security strength of the gaming machine 1 can be improved.

  On the other hand, although a plurality of retroactive numbers and HW parameters provided in the inspection value generation unit 500 are prepared in advance, only specific HW parameters are mounted on the main ROM 110b, and only a specific retroactive number corresponding thereto is adopted. It can also be configured. When implemented in this way, it is not necessary to newly provide a program associated with the HW parameter selection process in the boot process, and the code size of the program is not increased. Also, when implemented in this way, even if the gaming machine manufacturer wants to adopt only a specific retroactive number, only the HW parameter corresponding to the desired retroactive number is stored in the main ROM 110b in the program implementation process performed by the gaming machine manufacturer. What is necessary is just to mount, and it can respond flexibly to the use and preference of the gaming machine manufacturer.

  Even in this case, since the HW parameter is stored in a storage area that is not accessed except when the initial value is set during the boot process of the main control unit 110, the contents of the retroactive number cannot be known from the outside. . Therefore, it is difficult for an unauthorized person to analyze the retroactive number indicating the error check value to be added adopted by the gaming machine 1, and the confidentiality of the error check value adding function of the gaming machine 1 is ensured. In addition, by changing the HW parameters used for design / verification work during the development stage of the gaming machine 1 and the HW parameters that are actually mounted thereafter, it is possible to know which HW parameters are finally mounted. The person who obtains it is limited, and the confidentiality of the error check value adding function is further improved. In the present embodiment, description will be made assuming that only a specific HW parameter corresponding to a specific retroactive number is mounted on the main ROM 110b.

  The inspection value generation unit 500 is provided between the main CPU 110a and the transmission unit 550. The connection between the main CPU 110a and the inspection value generation unit 500 and the connection between the inspection value generation unit 500 and the transmission unit 550 are bus-connected as described above, and the buses used for each connection are the same standard. It has become a bus. That is, a method (hereinafter referred to as “input / output control format”) for controlling data transmission / reception between each of the input interface on the main CPU 110a side of the inspection value generation unit 500 and the input interface on the inspection value generation unit 500 side of the transmission unit 550. “)” Is a method corresponding to the input / output control method set in the output interface on the inspection value generation unit 500 side of the main CPU 110a. As the bus standard, a known standard may be used.

  In the present embodiment, the input / output control method of the output interface on the inspection value generation unit 500 side of the main CPU 110a is referred to as “CPU interface method”. The CPU interface method may use a known input / output control method determined based on the above bus standard, and the bus standard between the main CPU 110a and the transmission unit 550 before the test value generation unit 500 is added. The input / output control method determined based on The output interface on the transmission unit 550 side of the inspection value generation unit 500 is also configured by the CPU interface method.

  The CPU interface system of this embodiment will be specifically described. For example, when the main CPU 110a outputs a control command to the test value generation unit 500, the main CPU 110a uses the control command as the data bus, the address data specifying the predetermined storage area of the test value generation unit 500 as the address bus, and the control bus. Outputs a write signal. This address data is converted into a chip select signal via a decoder and input to the inspection value generation unit 500. When the chip select signal and the write signal become active (in this embodiment, when the control signal becomes active, “the control signal is input”), the inspection value generation unit 500 takes in the control command on the data bus. With such an input / output control method, a control command is output from the main CPU 110 a to the inspection value generation unit 500. The same applies when the main CPU 110a outputs the HW parameter to the inspection value generation unit 500.

  Also, when the test value generation unit 500 outputs a control command to the transmission unit 550, the test value generation unit 500 also includes address data that specifies a control command for the data bus and a predetermined storage area of the transmission unit 550 for the address bus, A write signal is output to the control bus. Then, when the chip select signal and the write signal of the address data are input, the transmission unit 550 takes in the control command on the data bus, and the control command is transferred from the test value generation unit 500 to the transmission unit 550. The same applies when the inspection value generation unit 500 outputs the error inspection value to the transmission unit 550.

  In the present embodiment, the output address data is converted to a chip select signal and then input to a designated component in the main control unit 110. Conversion from address data to a chip select signal Description of is omitted. In this embodiment, a bus having a bit width equal to or greater than the data length of the smaller one of the control command and the error check value may be provided.

  For example, if the control command is 2-byte data and the error check value is 1-byte data, the bit width of the data bus may be at least 1 byte. In this case, the main CPU 110a and the test value generation unit 500 first output the upper 1 byte of the 2-byte control command to the data bus, and then output the lower 1 byte to the data bus. Subsequently, the check value generation unit 500 outputs a 1-byte error check value to the data bus.

  The inspection value generation unit 500 performs a function of adding an error inspection value to the control command output from the main CPU 110a and outputting it to the transmission unit 550. The retroactive number setting process, the inspection value generation process, and the inspection value addition process These are circuits that execute the overall processing of the main control unit 110 related to realizing the security function of the gaming machine 1. Specifically, the inspection value generation unit 500 includes at least a buffer unit 510, a determination unit 540, a generation unit 520, and an addition unit 530. Each means of the inspection value generation unit 500 is configured by a wired logic control system.

  In the present embodiment, data transmission / reception between each means in the test value generation unit 500 and between each circuit in each means is performed in synchronization with the clock signal output from the clock pulse generation circuit of the main control unit 110. . For this reason, in this embodiment, the input / output control method of each means and each circuit in the test value generation unit 500 is referred to as a “synchronous interface method”. In the synchronous interface method, when an enable signal or the like is output to a connection destination of data to be output, the connection destination takes in the output data based on inputs of the enable signal and a clock signal. Therefore, the synchronous interface method is different from the CPU interface method that requires address data (chip select signal) and a write signal transmitted via the bus.

  The buffer unit 510 is a circuit that inputs and temporarily holds a control command or unique information output from the main CPU 110a in command transmission processing after boot processing. The buffer unit 510 is a circuit that outputs the held control command to the subsequent determination unit 540, generation unit 520, and addition unit 530. When the unique information is input, it is output only to the generation means 520. That is, the buffer unit 510 temporarily holds a control command transmitted from the main CPU 110a to the effect control unit 120, the execution timing of the command transmission process of the main CPU 110a, the retroactive number setting process of the subsequent determination unit 540, and the generation unit It plays a role of adjusting each execution timing of the inspection value generation process 520 and the inspection value addition process of the adding means 530.

  Further, data transmission / reception is controlled between the input side of the buffer means 510 and the main CPU 110a by the input / output control method corresponding to the CPU interface method as described above. On the other hand, on the output side of the buffer unit 510, data transmission / reception is controlled by the synchronous interface method with the subsequent determination unit 540, generation unit 520, and addition unit 530. That is, the buffer unit 510 has different input / output control methods on its input side and output side, and plays a role of matching the CPU interface method of the main CPU 110a with the synchronous interface method in the test value generation unit 500. Yes.

  The buffer unit 510 includes at least a data buffer 511 and a control circuit 512. The data buffer 511 is a circuit that captures and holds control commands and unique information output from the main CPU 110a via a data bus. The control circuit 512 is a circuit that controls the operation of the data buffer 511 based on a control signal output from the main CPU 110a.

  Specifically, the control circuit 512 receives a write signal for writing a control command or unique information output from the main CPU 110 a into the data buffer 511 of the buffer unit 510 and address data designating the buffer unit 510. Then, an enable signal (hereinafter referred to as “operation permission signal”) for operating the data buffer 511 to take in a control command and specific information on the data bus is output. The data buffer 511 takes in a control command and unique information on the data bus based on the input of the operation permission signal.

  In addition, the control circuit 512 outputs an operation permission signal for causing the control command and the unique information fetched by the data buffer 511 to be output to the determining unit 540, the generating unit 520, or the adding unit 530. Based on the input of the operation permission signal, the data buffer 511 outputs the captured control command to the determination unit 540, the generation unit 520, and the addition unit 530, and outputs the captured unique information to the generation unit 520.

  The control circuit 512 controls the determination circuit 541 of the determination unit 540 and the generation unit 520 so that the control command output from the data buffer 511 can be input by the determination unit 540, the generation unit 520, and the addition unit 530. An operation permission signal is output to the circuit 523 and the control circuit 532 of the adding means 530. Note that the timing at which the control circuit 512 outputs each operation permission signal is determined by each unit to input the control signal and the clock signal from the main CPU 110a while taking into account the operation time of each unit in the test value generation unit 500. The timing is set in advance so that it can operate normally in synchronization with the timing.

  Further, the control circuit 512 outputs an operation permission signal to the control circuit 523 of the generation unit 520 so that the unique information output from the data buffer 511 can be input by the generation unit 520. In FIG. 5, only the control command is described in the data line output from the data buffer 511 to the generation unit 520, but the unique information also includes a generation circuit from the data buffer 511 via the data line. The data is output to the storage circuit 522 via 521. In this case, the generation circuit 521 may or may not perform arithmetic processing on the unique information, and in any case, the value set as the initial inspection value is consistent with the subsequent control unit 180. Arrange in advance as follows. Although omitted in FIG. 5, the data buffer 511 and the storage circuit 522 of the generation unit 520 are separately connected by a data line, and the unique information is directly output from the data buffer 511 to the storage circuit 522. Good.

  The determination unit 540 is a circuit that determines an error check value to be added to the control command output from the buffer unit 510 and sets the generation unit 520 so that the determined error check value is added to the control command. is there. That is, the determination unit 540 plays a role of executing the retroactive number setting process of the inspection value generation unit 500. Specifically, the determination unit 540 determines a default retroactive number based on the HW parameter set from the main CPU 110a in the HW parameter setting process during the boot process, and generates a later-described generation unit according to the determined retroactive number 520 is set. Further, the determination unit 540 receives the control command output from the buffer unit 510 in the command transmission process after the boot process, and based on the input control command, a predetermined retroactive number change rule (hereinafter, “ The default retroactive number is changed in accordance with “change protocol”, and the generation unit 520 is set according to the new retroactive number.

  Specifically, the determination unit 540 includes at least a determination circuit 541 and a determination circuit 542. The determination circuit 541 inputs the control command output from the buffer means 510, and the input control command satisfies a predetermined condition (hereinafter referred to as “change condition”) for changing the current retroactive number. It is a circuit that determines whether or not it is, and notifies the determination circuit 542 of the determination result.

  The input side of the determination circuit 541 is connected to the data buffer 511 of the buffer means 510 via a data line, and is connected to the control circuit 512 of the buffer means 510 via a control line. The output side of the determination circuit 541 is connected to the determination circuit 542 in the determination means 540 through a control line. The determination circuit 541 includes a change condition storage (not shown) that stores the change condition in advance, and a comparator (not shown) that compares the input control command with the change condition. Based on the operation permission signal output from the control circuit 512, the determination circuit 541 inputs the control command output from the data buffer 511 to the comparator, and the change stored in advance in the change condition storage unit Compare with conditions. Subsequently, the determination circuit 541 outputs a control signal (hereinafter referred to as “determination result signal”) for notifying the determination result of whether or not the input control command is a control command satisfying the change condition.

  The change condition is basically arbitrary as long as it is agreed with the post-stage control unit 180 in advance. For example, in this embodiment, whether or not the type of control command output from the buffer unit 510 corresponds to a predetermined type of control command is set as a change condition. The type of the predetermined control command may be one type or a plurality of types, and the type itself is arbitrary.

  The change condition storage unit is configured by a register or the like, and stores a bit pattern of a predetermined control command. In this embodiment, the control command is composed of 1-byte “MODE” information and 1-byte “DATA” information as will be described later. However, the change condition is output from the main CPU 110a, for example. Only the “MODE” information of the control command may be used.

  The comparator is composed of an equal comparator, a magnitude comparator or the like that can compare the number of bits equal to or greater than that of the change condition storage device, and is connected to the data buffer 511 by a data line. The comparator is connected to the determination circuit 542 through a control line. Then, the comparator receives the control command output from the data buffer 511 based on the operation permission signal output from the control circuit 512.

  The comparator compares the input control command with the change condition, and if they match, determines a determination result signal indicating that the control command output from the buffer means 510 is a control command satisfying the change condition. Output to the circuit 542. On the other hand, if the two do not match, the comparator outputs a determination result signal indicating that the control command output from the buffer means 510 is not a control command satisfying the change condition to the determination circuit 542.

  Note that the determination target of the determination circuit 541 may not be the control command itself output from the buffer unit 510. For example, the input side of the determination circuit 541 can be connected to the output side of the generation circuit 521 of the generation unit 520, and the error check value of the control command output from the buffer unit 510 can be determined. At this time, for example, a bit pattern of an error check value generated from a predetermined control command may be stored in the change condition storage. The change condition storage unit may simply store a predetermined value. Even in such a case, the determination circuit 541 can determine whether or not the type of the control command output from the buffer unit 510 is a predetermined type of control command.

  On the other hand, the determination circuit 542 determines the retroactive number according to the HW parameter set from the main CPU 110a and the determination result of the determination circuit 541, and the error check value according to the determined retroactive number executes the test value addition process. This is a circuit for setting the generation means 520 so as to be output to the addition means 530 described later.

  The input side of the decision circuit 542 is connected to the main CPU 110a via a bus, and data transmission / reception is controlled with the main CPU 110a by an input / output control method corresponding to the CPU interface method. Then, the decision circuit 542 takes in the HW parameter output from the main CPU 110a from the data bus during the HW parameter setting process. Further, the input side of the decision circuit 542 is connected to the determination circuit 541 through a control line, and data transmission / reception is controlled between the determination circuit 541 and the input / output control method corresponding to the synchronous interface method. Then, the determination circuit 542 receives the determination result signal output from the determination circuit 541.

  Further, the output side of the decision circuit 542 is connected to the generation unit 520 through a control line, and data transmission / reception is also controlled between the generation unit 520 and the generation unit 520 using a synchronous interface method. Then, the determination circuit 542 determines the retroactive number according to the HW parameter output from the main CPU 110 a and the determination result signal output from the determination circuit 541, and generates an error check value according to the determined retroactive number from the generation unit 520. A control signal for outputting is output.

  Specifically, the determination circuit 542 is preliminarily provided with a data table in which the correspondence between the HW parameter and the retroactive number is known, and the determination circuit 542 can determine the retroactive number based on the captured HW parameter. Further, the determination circuit 542 is provided with a retroactive number storage area (N) for storing a value of N indicating the current retroactive number. In the HW parameter setting process, the determination circuit 542 stores the value of N indicating the retroactive number corresponding to the HW parameter set from the main CPU 110a as a default value in the retroactive number storage area (N).

  In the present embodiment, the error check value is stored as a specific mode for outputting the error check value of the control command N times before indicated by the retroactive number to the adding means 530 that executes the check value adding process. The storage circuit 522 of the generating means 520 is provided with a plurality of storage circuits (storage circuit 1 to storage circuit N in FIG. 5). The determination circuit 542 is provided with a data table in which the correspondence between the value of N and the plurality of storage circuits (storage circuit 1 to storage circuit N in FIG. 5) of the generation unit 520 is known.

  Then, the determination circuit 542 uses any one of the plurality of storage circuits as the storage circuit 522 based on the value stored in the retroactive number storage area (N) during the retroactive number setting process during the boot process. It is determined whether the error check value should be output from the storage circuit 522. Then, the determination circuit 542 outputs a control signal (hereinafter referred to as “connection switching signal”) that enables only the connection with the storage circuit 522 to the input selection circuit 524 of the generation unit 520. In the retroactive number storage area (N), when the retroactive number is changed as will be described later, the value of N indicating the retroactive number after the change (hereinafter, the value of the retroactive number after the change is “N ′”). Is stored). By determining the value of the retroactive number storage area (N), the determination circuit 542 can grasp the storage circuit 522 that is currently operating effectively in the generation unit 520 and outputs the storage circuit 522 from the generation unit 520 to the addition unit 530. It is possible to grasp the error check value to be performed.

  In addition, the determination circuit 542 is provided with a generation number storage area (P) for storing the value of the generation number P of control commands up to the present, similarly to the main RAM 110c. When the determination circuit 542 detects that the determination result signal is output from the determination circuit 541, the determination circuit 542 adds 1 to the value of the generated number storage area (P) and updates it. As a result, the decision circuit 542 causes the control command output from the buffer means 510 corresponding to the output of the determination result signal to be Pth after the main control unit 110 is initialized and the error check value to be added is cleared. It can be grasped that the control command (P) is generated at the same time.

  It should be noted that the value of the generated number storage area (P) provided in the main RAM 110 c and the value of the generated number storage area (P) provided in the determination circuit 542 are the same value, and the control command output from the buffer means 510. (P) is the same as the control command (P) actually output from the main CPU 110a.

  In the present embodiment, as described above, the main CPU 110a determines whether or not the unique information needs to be set in the storage circuit 522 of the generation unit 520, but the determination circuit 542 may determine it. For example, the determination circuit 542 determines whether the value of the generated number storage area (P) is P = 1. If P = 1, the control command output from the buffer unit 510 is stored in the storage circuit 522. After the error check value is cleared, it is determined that the control command is first generated by the main CPU 110a, and this is notified to the buffer means 510. Then, the buffer unit 510 may output a control signal for requesting the main CPU 110a to output the unique information and output the unique information stored in the main ROM 110b.

  Further, the determination circuit 542 changes the retroactive number in accordance with the retroactive number change protocol negotiated with the subsequent control unit 180 in advance in the retroactive number setting process after the boot process. Specifically, the determination circuit 542 confirms the determination result signal output from the determination circuit 541 and grasps whether or not the control command output from the buffer unit 510 is a control command that satisfies the change condition. Then, if the control command output from the buffer means 510 is a control command that satisfies the change condition, the decision circuit 542 determines a predetermined number in order to change from the current retroactive number to a new retroactive number at a predetermined change timing. The value of N indicating the retroactive number is changed according to the change method. That is, the change protocol includes at least a change condition for determining whether or not the retroactive number should be changed, a method for setting the retroactive number change timing, and a retroactive number change method.

  In the present embodiment, as described above, the change condition is whether or not the type of the control command output from the buffer unit 510 corresponds to a predetermined type of control command.

  The method of changing the retroactive number is basically arbitrary as long as it is agreed with the post-stage control unit 180 in advance. For example, the operation result obtained by performing various arithmetic operations and logical operations determined in advance on the current retroactive number value is used as the value of N ′ indicating the retroactive number after the change, or a random number generation prepared in advance The circuit can be operated, and the obtained random number value can be set to a value of N ′ indicating the retroactive number after the change. However, when using a random number generation circuit, it is necessary to notify the subsequent stage control unit 180 of the obtained random number value.

  In addition, the method for setting the retroactive number change timing is basically arbitrary as long as it is agreed with the post-stage control unit 180 in advance, but in this embodiment, the change timing is set as follows. . In other words, when the control command (P) output from the buffer means 510 is a predetermined control command, the determination circuit 542 determines when the generation number P has passed Mo (Mo; non-negative integer) (that is, the generation number). Is changed to the retroactive number in accordance with the above change method, the value of the retroactive number storage area (N) is updated to N ′ and added to the control command (P + Mo) output at that time The error check value is determined as an error check value (P + Mo−N ′) corresponding to the value of N ′ indicating the retroactive number after the change. In the present embodiment, Mo is a fixed value that is negotiated with the subsequent stage control unit 180 in advance.

  The determination circuit 542 is provided with a change timing information storage area (Mi) for storing change timing information Mi indicating the value of the number of generations P when the retroactive number is changed. When the control command (P) output from the buffer means 510 is a control command that satisfies the change condition, the decision circuit 542 adds a predetermined value of Mo to the number P of generated control commands ( P + Mo) is stored in the change timing information storage area (Mi) as change timing information Mi (= P + Mo). That is, the value stored in the change timing information storage area (Mi) is equal to the generation number P of control commands output Mo after a predetermined control command is output.

  Therefore, the determination circuit 542 compares the generated number P of the current control command, that is, the value of the generated number storage area (P) with the value of the change timing information storage area (Mi), so that the change timing is currently set. It is possible to grasp whether or not. The determination circuit 542 is provided with a comparison circuit (not shown) for comparing the value of the generated number storage area (P) and the value of the change timing information storage area (Mi). Note that the decision circuit 542 changes the retroactive number (retroactive number storage area (()) after the value of the generated number storage area (P) matches the value of the change timing information storage area (Mi) and the change timing arrives. After changing the value of N), the change timing information storage area (Mi) is cleared.

  In the present embodiment, there is a control command that further satisfies the change condition between the time when it is determined that the control command output from the buffer means 510 is a control command that satisfies the change condition and the time when the retroactive number is actually changed. It may be output. Therefore, in this embodiment, a plurality of change timing information storage areas (Mi) are provided. i is an identification number for each of the plurality of change timing information storage areas (Mi).

  The decision circuit 542 stores each change timing information Mi in the change timing information storage area (Mi) every time a control command satisfying the change condition is output. The change timing information storage area (Mi) is cleared after changing the retroactive number (after changing the value of the retroactive number storage area (N)). Therefore, the change timing information Mi is stored as many as the number of control commands that satisfy the change condition from the time when the retroactive change timing arrives, and the decision circuit 542 has a maximum of Mo + 1. It is sufficient to secure the change timing information storage area (Mi). If determined in this way, the possible range of the value of i is 1 ≦ i ≦ Mo + 1. In the present embodiment, the smallest value of the change timing information Mi among the plurality of change timing information Mi values is referred to as “Mmin”.

  In this way, the determination circuit 542 determines the retroactive number indicating the error check value to be output from the generation unit 520 to the addition unit 530 in accordance with the HW parameter set from the main CPU 110a and the determination result of the determination circuit 541. To do. Then, the determination circuit 542 outputs the connection switching signal to the input selection circuit 524 so that the error check value indicated by the determined retroactive number is output from the storage circuit 522 of the generation unit 520 to the addition unit 530. Thus, the generation unit 520 can be set according to the determined retroactive number.

  Here, the procedure for adding an error check value will be described with reference to FIG. The error check value adding procedure in the present embodiment is that the control command (P-N) generated N times before the control command (P) written in the buffer means 510 as the main CPU 110a transmits this time. An error check value (PN) is added. FIG. 7 shows an example of control commands (control command (1) to control command (11)) output eleventh after the error check value to be added is cleared.

  In FIG. 7, the default retroactive number corresponding to the HW parameter set in the HW parameter setting process is N = 2. That is, it is assumed that N = 2 is stored in the retroactive number storage area (N). In addition, the value of Mo that is an index of change timing is set to Mo = 4.

  First, when it is time to execute the command transmission process, the main CPU 110a updates the value of the generated number storage area (P) of the main RAM 110c to “P = 1” and reads the unique information stored in the main ROM 110b. The main CPU 110a stores the read unique information in the storage circuits 1 to N as initial check values (1) to (N) so as to correspond to the generation order of the control commands. When P ≦ N, that is, when a control command generated before the Nth time after the error check value stored in the storage circuit 522 is cleared, the control command (P) is transmitted. Initial inspection values (1) to (N) are added. In FIG. 7, N = 2, and two pieces of unique information are stored in the storage circuit 1 and the storage circuit 2 as the initial inspection value (1) and the initial inspection value (2). When P ≦ 2, the initial inspection value (1) and the initial inspection value (2) are added to the control command (1) and the control command (2).

  Subsequently, the main CPU 110 a outputs the control command (1) to the buffer means 510. The buffer unit 510 outputs the control command (1) output from the main CPU 110a to the determination unit 540, the generation unit 520, and the addition unit 530. The determination unit 540 performs retroactive number setting processing. Specifically, the determination circuit 541 inputs the control command (1) output from the buffer unit 510, that is, the control command (1) output from the main CPU 110a, and the determination control command (1) is controlled according to a predetermined control. It is determined whether it is a command, and a determination result signal is output to the decision circuit 542. The same applies to the description of FIG.

  When the determination circuit 542 detects the determination result signal, the determination circuit 542 updates the value of the generated number storage area (P) to “P = 1”, and the control command (1) is a control command having a value of the generated number. (Hereinafter the same in the description of FIG. 7). Then, the determination circuit 542 confirms the determination result signal, and confirms whether the control command (1) is a control command that satisfies the change condition (hereinafter, the same applies in the description of FIG. 7). In FIG. 7, it is assumed that the control command (1) is not a control command that satisfies the change condition. At this time, the change timing information storage area (Mi) remains cleared, and there is no need to set the change timing information Mi. Further, the value of the retroactive number storage area (N) also remains the default “N = 2”. Further, since P ≦ 2, the error check value to be added to the control command (1) is the initial check value (1). The same applies to the control command (2).

  Next, a case where the control command (3) is output from the main CPU 110a will be described. In FIG. 7, since the control command (3) is not a control command that satisfies the change condition, the decision circuit 542 does not set the change timing information Mi. Further, the value of the retroactive number storage area (N) also remains the default “N = 2”. Further, the value (P = 3) of the generated number storage area (P) is larger than the value (N = 2) of the retrospective number storage area (N) (P> N). Therefore, the error check value to be added to the control command (3) is the error check value (PN), that is, the control command (1) (hereinafter the same in the description of FIG. 7).

  Next, a case where the control command (4) is output from the main CPU 110a will be described. In FIG. 7, since the control command (4) is a control command that satisfies the change condition, the decision circuit 542 sets the change timing information Mi as M1. As described above, the change timing information M1 is M1 = P + Mo = 4 + 4 = 8, and the determination circuit 542 stores the value of M1 = 8 in the change timing information storage area (M1). Accordingly, it is understood that the determination circuit 542 has to change the value of the retroactive number storage area (N) at the timing when the value of the generated number storage area (P) becomes P = 8. Further, the determination circuit 542 compares the value (M1 = 8) of the change timing information storage area (Mi) with the value (P = 4) of the generated number storage area (P) (hereinafter the same in the description of FIG. 7). And). In FIG. 7, since the value of the change timing information storage area (M1) does not match the value of the generated number storage area (P), the value of the retrospective number storage area (N) (N = 2) is not the change timing at present. Is maintained. Therefore, the error check value to be added to the control command (4) is the error check value (2) of the control command (2).

  Next, the case where the control command (5) is output from the main CPU 110a will be described. In FIG. 7, since the control command (5) is not a control command that satisfies the change condition, the determination circuit 542 does not newly set the change timing information Mi. Further, since the value (M1 = 8) of the change timing information storage area (Mi) does not match the value (P = 5) of the generated number storage area (P), the value of the retroactive number storage area (N) (N = 2) ) Is maintained, and the error check value to be added to the control command (5) is the error check value (3) of the control command (3).

  Next, the case where the control command (6) is output from the main CPU 110a will be described. In FIG. 7, since the control command (6) is a control command that satisfies the change condition, the decision circuit 542 sets the change timing information Mi as M2. As described above, the change timing information M2 is M2 = P + Mo = 6 + 4 = 10, and the determination circuit 542 stores the value of M2 = 10 in the change timing information storage area (M2). With this, two change timing information of M1 = 8 and M2 = 10 are set in the change timing information storage area (Mi). Then, the decision circuit 542 determines the value (M1 = 8) of the change timing information storage area (M1) having the minimum value Mmin in the change timing information storage area (Mi) and the value of the generated number storage area (P). Compare (P = 6). Since the value of the change timing information storage area (M1) does not match the value of the generated number storage area (P), the value of the retroactive number storage area (N) (N = 2) is maintained instead of the change timing. . Therefore, the error check value to be added to the control command (6) is the error check value (4) of the control command (4). The same applies to the control command (7).

  Next, the case where the control command (8) is output from the main CPU 110a will be described. In FIG. 7, since the control command (8) is not a control command that satisfies the change condition, the determination circuit 542 does not newly set the change timing information Mi. Also, the value (M1 = 8) of the change timing information storage area (M1) having the minimum value Mmin in the change timing information storage area (Mi) is the value (P = 8) of the generated number storage area (P). Since it matches, the current timing is the change timing. The determination circuit 542 changes the value (N = 2) of the retroactive number storage area (N) according to a predetermined change method. In FIG. 7, assuming that N = 2 → N ′ = 3, the determination circuit 542 stores the retroactive number value N ′ = 3 after the change in the retroactive number storage area (N).

Then, the determination circuit 542 confirms the value of the retroactive number storage area (N) (N ′ = 3 after change), and sets the generation unit 520 according to the retroactive number after change. In the present embodiment, the determination circuit 542 outputs a connection switching signal that enables connection with the storage circuit 3 among the plurality of storage circuits provided in the generation unit 520 to the input selection circuit 524 of the generation unit 520. (Hereafter, the same applies in the description of FIG. 7). That is, the determination circuit 542 sets the error check value to be added to the control command (8) as the error check value (5) of the control command (5). Further, the decision circuit 542 clears the value (M1 = 8) of the change timing information storage area (M1) having the minimum value Mmin.
Thereafter, processing similar to the above is performed, and an error check value to be added to the control command output from the buffer means 510 is determined while changing the value of the retroactive number storage area (N).

  The possible range of the retroactive number N is limited by the storage capacity of the storage circuit 522 (and a storage unit 622 to be described later of the post-control unit 180), but is basically arbitrary. If the value of N is large, it becomes more difficult for an unauthorized person to analyze the relationship between a control command and an error check value added to the control command, and illegal acts can be further prevented. However, if the value of N becomes a value far greater than the number of transmissions of the control command while the gaming machine is operating for one day, for example, all error check values added to the control command become unique information, and the confidentiality of the unique information is reduced. There is a risk of damage.

  The generation unit 520 is a circuit that generates an error check value of the control command output from the buffer unit 510 and outputs the generated error check value to the subsequent adding unit 530. In other words, the generation unit 520 plays a role of executing the inspection value generation process. The generation unit 520 includes at least a generation circuit 521, a storage circuit 522, a control circuit 523, and an input selection circuit 524. The generation circuit 521 is a circuit that performs an arithmetic process on the control command output from the buffer means 510 to generate an error check value. The storage circuit 522 is a circuit that stores the error check value generated by the generation circuit 521. The control circuit 523 is a circuit that controls the operation of the generation circuit 521 and the storage circuit 522 based on the operation permission signal output from the buffer unit 510. The input selection circuit 524 is a circuit that selectively switches the connection between the storage circuit 522 and the adding means 530.

  Specifically, the generation circuit 521 operates the control command output from the buffer unit 510 using a preset calculation method for generating an error check value (hereinafter referred to as “generation method”) and performs error checking. This circuit generates a value and outputs it to the storage circuit 522.

  The input side of the generation circuit 521 is connected to the data buffer 511 of the buffer means 510 via a data line, and is connected to the control circuit 523 via a control line. Further, the output side of the generation circuit 521 is connected to a first-stage storage circuit (storage circuit 1 in FIG. 5) among the plurality of storage circuits 1 to N that bear the storage circuit 522 described later by a data line. Then, the control circuit 523 outputs, to the generation circuit 521, an operation permission signal for operating to input a control command and perform arithmetic processing based on the operation permission signal output from the control circuit 512 of the buffer means 510. To do. The generation circuit 521 receives the control command output from the data buffer 511 when the operation permission signal is input from the control circuit 523. Then, the generation circuit 521 generates an error check value by operating the input control command using a preset generation method, and the generated error check value is stored in the first stage storage circuit (the storage circuit 1 in FIG. 5). ).

  The generation method is not particularly limited as long as it is negotiated with the subsequent control unit 180 in advance. As the generation method, for example, a known method such as a checksum method, a CRC method, an odd parity method, an even parity method, a group count check method, a vertical parity method, a horizontal parity method, or a Hamming code method can be used. The generation circuit 521 can be configured to input and calculate the control command output from the buffer unit 510 as it is, or to input and calculate only a part of the control command output from the buffer unit 510. It can also be configured. For example, the control command is composed of 1-byte “MODE” information and 1-byte “DATA” information as will be described later, but only the “MODE” information of the output control command is input. It can be configured to operate.

  The storage circuit 522 is a circuit that stores the error check value output from the generation circuit 521. More specifically, the storage circuit 522 includes N stages of storage circuits 1 to N corresponding to at least the retroactive number N. The storage circuits 1 to N of the storage circuit 522 are connected to each other so as to have a pipeline configuration. That is, the storage circuit 522 has at least the function of an N-stage shift register (FIFO memory) corresponding to the retroactive number N.

  The input side of the first stage storage circuit (storage circuit 1 in FIG. 5) is connected to the generation circuit 521 through a data line. The storage circuits 1 to N are connected to the control circuit 523 through control lines. Then, the control circuit 523 outputs a control signal (hereinafter referred to as “shift processing signal”) for sequentially shifting the data stored in each of the storage circuits 1 to N. When the shift processing signal is input from the control circuit 523, each of the storage circuits 1 to N sequentially shifts the error check value stored therein to the storage circuit at the next stage.

  The output side of each of the storage circuits 1 to N is connected to an input selection circuit 524 configured by a multiplexer or the like via a data line. Then, when the shift processing signal output from the control circuit 523 is input, each of the storage circuits 1 to N sequentially shifts the error check value stored therein to the storage circuit of the next stage, and shifts each error that has been shifted. The inspection values are output to the input selection circuit 524, respectively.

  The input selection circuit 524 is a circuit having a connection switching function so that a specific storage circuit (storage circuit N in FIG. 5) among the plurality of storage circuits 1 to N can be selectively connected as the storage circuit 522. Based on the input of the connection switching signal output from the determination circuit 542 in the retroactive number setting process, the input selection circuit 524 validates only the connection with the storage circuit (storage circuit N in FIG. 5) indicated by the connection switching signal. Set to. The output side of the input selection circuit 524 is connected to the input selection circuit 531 of the adding means 530 through a data line, and the input error check value can be output to the subsequent adding means 530.

  When an error check value is output from each of the storage circuits 1 to N in response to the input of the shift processing signal, the input selection circuit 524 displays the storage circuit 522 whose connection has been enabled by the input of the connection switching signal. Only the error check value output from the specific storage circuit (storage circuit N in FIG. 5) is fetched. Then, the input selection circuit 524 outputs the fetched error check value to the input selection circuit 531 of the adding unit 530 that follows.

  In this way, the storage circuit 522 inputs the error check value generated by the generation circuit 521 to the first stage storage circuit that bears the storage circuit 522, and stores each of the plurality of storage circuits that bear the storage circuit 522. The error check value to be output is output to the input selection circuit 524. However, only the connection between the specific storage circuit (storage circuit N in FIG. 5) and the input selection circuit 524 is validated by the retroactive number setting process of the determination unit 540. As a result, the input selection circuit 524 inputs only the error check value output from the specific storage circuit, and outputs the input error check value to the adding means 530. Therefore, the error check value output from the storage circuit 522 to the adding unit 530 via the input selection circuit 524 is only the error check value corresponding to the retroactive number determined according to the HW parameter or the change protocol.

  That is, the storage circuit 522 stores N control commands from the control command (P) received by the buffer means 510 from the main CPU 110a to the control command (PN) N times before the control command (P). Error check values (error check value (P) to error check value (PN)) corresponding to each can be stored. When the control command (P) is output from the buffer means 510, the storage circuit 522 outputs an error check value (PN) that is an error check value corresponding to the retroactive number N determined by the determining means 540. ) Can be output to the adding means 530.

  The adding unit 530 is a circuit that adds the error check value output from the generating unit 520 to the control command output from the buffer unit 510 and outputs the error check value to the transmitting unit 550. That is, the adding unit 530 plays a role of executing the inspection value adding process. On the input side of the adding means 530, data transmission / reception is controlled between the buffer means 510 and the generating means 520 by a synchronous interface method. On the other hand, data transmission / reception is controlled between the output side of the adding unit 530 and the subsequent transmission unit 550 by the input / output control method corresponding to the CPU interface method as described above. That is, the adding unit 530 has different input / output control methods on its input side and output side, and an input / output control method corresponding to the synchronous interface method in the test value generation unit 500 and the CPU interface method of the transmission unit 550. It plays a role to align.

  The adding unit 530 includes at least an input selection circuit 531 constituted by a multiplexer or the like, and a control circuit 532. The input selection circuit 531 selectively selects the control command output from the buffer means 510 and the error check value output from the generation means 520 so as to be consistent with the predetermined error check value addition procedure. It is a circuit having a connection switching function for capturing. The control circuit 532 is a circuit that controls the operation of the input selection circuit 531 based on the operation permission signal output from the buffer means 510.

  Specifically, the input side of the input selection circuit 531 is connected to the data buffer 511 of the buffer unit 510 by a data line, and is connected to the storage circuit 522 of the generation unit 520 by a data line via the input selection circuit 524. . The input side of the input selection circuit 531 is connected to the control circuit 532 through a control line. The input selection circuit 531 is set in advance so that the connection with the data buffer 511 is valid, and takes in the control command output from the data buffer 511. Then, the control circuit 532 delays a predetermined time based on the operation permission signal output from the control circuit 512 of the buffer means 510, and a control signal for validating the connection with the input selection circuit 524 of the input selection circuit 531. (Hereinafter referred to as “connection switching signal”) is output to the input selection circuit 531. When the connection switching signal is input from the control circuit 532, the input selection circuit 531 takes in the error check value output from the storage circuit 522 via the input selection circuit 531.

  Then, the input selection circuit 531 outputs the control command and the error check value taken into the data bus connected to the transmission unit 550. In addition, the control circuit 532 outputs address data for designating a predetermined storage area of the transmission unit 550 to an address bus connected to the transmission unit 550 and a write signal to the control bus. At this time, the timing at which the control circuit 532 outputs the write signal is based on the operation permission signal output from the control circuit 512 of the buffer means 510 while considering the operation time of the generation means 520 and the transmission unit 550. The timing is set in advance so that the error check value is added in accordance with the error check value addition procedure.

  The transmission unit 550 performs a function of transmitting the control command and the error check value output from the inspection value generation unit 500 to the effect control unit 120, and includes at least a transmission buffer 551 and a transmission circuit 552.

  The transmission buffer 551 is a buffer circuit for temporarily holding data to be transmitted to the effect control unit 120. Specifically, when a write signal for writing the control command output from the test value generation unit 500 to the transmission buffer 551 and address data specifying the transmission buffer 551 are input to the transmission buffer 551, the control is performed. Capture commands via the bus. The transmission buffer 551 receives a write signal for writing the error check value to be added to the control command output from the check value generation unit 500 to the transmission buffer 551 and address data designating the transmission buffer 551. Then, the error check value is taken in via the bus. Then, the transmission buffer 551 immediately transfers the fetched control command and error check value to the transmission circuit 552.

  The transmission circuit 552 transmits data to be transmitted to the effect control unit 120 between the main control unit 110 and the effect control unit 120 and between the effect control unit 120 and the subsequent control unit 180 (such as a serial transmission format or It has a function to convert to a data format compatible with the parallel transmission format. Then, the transmission circuit 552 performs the above conversion processing on the data delivered from the transmission buffer 551 to obtain transmission data, and immediately transmits it to the effect control unit 120.

The operation of each component related to the authentication process of the main control unit 110 configured as described above will be outlined.
When the gaming machine 1 is powered on, a system reset occurs in the main control unit 110, and the main CPU 110a performs a boot process as one of the initialization processes of the main control unit 110. During the boot process, the main CPU 110 a sets an initial value for the inspection value generation unit 500 stored in advance in the main ROM 110 b in the inspection value generation unit 500 as one of the hardware setting items of the main control unit 110.

  At that time, the main CPU 110a performs an HW parameter setting process for setting an HW parameter which is one of initial values related to the inspection value generation unit 500. In the HW parameter setting process, the main CPU 110a takes in the HW parameters from the main ROM 110b and sets them in the determination unit 540 of the inspection value generation unit 500. At this time, the main CPU 110 a outputs a write signal and address data to the determination unit 540.

  Next, the determination unit 540 determines a default retroactive number corresponding to the HW parameter set in the HW parameter setting process as a retroactive number setting process during the boot process, and a connection switching signal corresponding to the determined retroactive number Is output to the generation means 520 of the inspection value generation unit 500. The generation unit 520 sets the connection between the storage circuit 522 and the input selection circuit 524 based on the connection switching signal output from the determination unit 540.

  Thereafter, when the boot process ends, the main CPU 110a performs a process related to the game progress based on the game process program stored in the main ROM 110b. Then, the main CPU 110a performs a command transmission process when it is time to transmit a control command.

  First, the main CPU 110a reads data necessary for configuring a control command from the main ROM 110b, configures a control command (P) to be transmitted this time, and sets it in a transmission data storage area of the main RAM 110c. At this time, if the control command (P) transmitted this time is the control command (1), the initial inspection value is set. The initial test value is set by the main CPU 110a reading the unique information from the main ROM 110b and storing the read unique information in the storage circuit 522 of the generating means 520.

  Then, the main CPU 110a outputs the control command (P) set in the transmission data storage area to the buffer means 510 of the inspection value generation unit 500 at the transmission timing of the control command. At this time, the main CPU 110 a outputs a write signal and address data to the buffer means 510.

  The buffer unit 510 takes the control command (P) and outputs it to the determining unit 540, the generating unit 520, and the adding unit 530 of the inspection value generating unit 500. At this time, the buffer unit 510 outputs an operation permission signal to the determination unit 540, the generation unit 520, and the addition unit 530.

  As the retroactive number setting process after the boot process, the determining unit 540 changes the retroactive number indicating the error check value to be added to the control command based on the input of the operation permission signal output from the buffer unit 510 according to the change protocol. Judge what to do. If the control command (P) output from the buffer unit 510 is a control command that satisfies the change condition, the determining unit 540 determines a new retroactive number and outputs a connection switching signal to the generating unit 520.

  The generation means 520 uses the control command (P) output from the buffer means 510 based on the input of the operation permission signal output from the buffer means 510 as the check value generation processing, and uses the error check value (P). Generate. The generation unit 520 switches the connection between the storage circuit 522 and the input selection circuit 524 based on the connection switching signal output from the determination unit 540. Then, the generation unit 520 stores the generated error check value (P) in the storage circuit 522, and also stores the error check value (PN) stored in the storage circuit 522 in which the connection with the input selection circuit 524 is valid. ) Is output to the adding means 530.

  The adding means 530 takes in the control command (P) output from the buffer means 510 based on the input of the operation permission signal output from the buffer means 510 as the inspection value adding process, and takes the control command (P) taken in. The data is output to the transmission buffer 551 of the transmission unit 550. At this time, the adding unit 530 outputs a write signal and address data to the transmission buffer 551.

  Further, the adding unit 530 switches the connection of its own input selection circuit 531 with a predetermined time delay from the input of the operation permission signal output from the buffer unit 510. Then, the adding unit 530 takes in the error check value (PN) output from the generating unit 520 and outputs the fetched error check value (PN) to the transmission buffer 551. At this time, the adding unit 530 outputs a write signal and address data to the transmission buffer 551.

  When the write signal output from the adding unit 530 is input, the transmission buffer 551 takes in the control command (P) and the error check value (PN) and immediately transfers them to the transmission circuit 552 of the transmission unit 550. The transmission circuit 552 performs the conversion process on the control command (P) and the error check value (PN) delivered from the transmission buffer 551 to obtain transmission data, and immediately transmits it to the effect control unit 120. In this way, a control command with an error check value is transmitted from the transmission unit 550 of the main control unit 110 to the effect control unit 120.

Thereafter, the control command (P) transmitted from the transmission unit 550 constituting the main control unit 110 is received by a reception unit (not shown) constituting the effect control unit 120.
The receiving unit of the effect control unit 120 performs a process corresponding to the conversion process on the transmission data from the main control unit 110 to generate a control command (P) and stores it in its own reception buffer. In addition, the receiving unit outputs a signal indicating that a reception interrupt request for the control command (P) has been requested, or sets a flag indicating that the reception of the control command (P) has been completed. The CPU 120a can detect that the reception of the control command (P) transmitted from the main control unit 110 is completed.

Then, the sub CPU 120a relays and transmits the control command (P) to the succeeding subsequent stage control unit 180 while maintaining the processing content and the reception order of the received control command (P).
Specifically, the sub CPU 120a writes and sets the control command (P) stored in the reception buffer of the reception unit constituting the effect control unit 120 as it is in the transmission data storage area of the sub RAM 120c. Then, the sub CPU 120a sets the control command (P) set in the transmission data storage area to the relay transmission unit (not shown) of the effect control unit 120, and the relay transmission unit sends the control command (P) to the subsequent control unit 180. Send.

  Here, the receiving unit of the effect control unit 120 receives the transmission data from the main control unit 110 and the transmission data from the subsequent control unit 180. When it is necessary to distinguish between the two, the main control unit 110 The receiving unit that receives the transmission data is referred to as a “first receiving unit”, and the receiving unit that receives the transmission data from the subsequent control unit 180 is referred to as a “second receiving unit”. Also, the reception data storage area for storing the data acquired from the first reception unit is referred to as “first reception data storage area”, and the reception data storage area for storing the data acquired from the second reception unit is referred to as “second reception data storage area”. The received data storage area ”.

Thereafter, the control command (P) relay-transmitted from the relay transmission unit that configures the effect control unit 120 is received by the reception unit 600 that configures the subsequent-stage control unit 180.
FIG. 8 shows functional blocks related to authentication processing of the post-stage control unit 180 according to this embodiment.
The post-stage control unit 180 includes at least a reception unit 600, an inspection unit 610, an inspection value generation unit 620, an addition unit 630, and a relay transmission unit 640 as functions related to authentication processing. Further, the check value generation unit 620 determines a generation unit 621 that generates an error check value, a storage unit 622 that stores the generated error check value, and an error check value to be checked by the check unit 610. It has at least a function with the portion 623.

  The receiving unit 600 has a function of performing processing corresponding to the above conversion processing on the transmission data from the effect control unit 120 to obtain a control command (P) and storing it in its own reception buffer. In addition, the receiving unit 600 outputs a signal indicating that a control command (P) reception interrupt request has been made, or sets a flag indicating that the reception of the control command (P) is completed, so that the CPU 180a. However, it has a function that makes it possible to detect that the reception of the control command (P) transmitted from the main control unit 110 has been completed.

  The receiving unit 600 extracts the error check value (PN) added from the received control command (P) with the error check value and outputs the error check value (PN) to the check unit 610. N) has a function of outputting the control command (P) after extraction to the inspection value generation unit 620. Note that specific means for realizing the function of the receiving unit 600 includes a part of the CPU 180a, a part of the ROM 180b, a part of the RAM 180c, and a command receiving input port (not shown) shown in FIG. be able to.

  The check value generation unit 620 has a function of generating an error check value (P) in the generation unit 621 using the control command (P) output from the reception unit 600. The error check value generated by this function is used to verify the validity of the received control command (P). The check value generation unit 620 has a function of storing a plurality of error check values (P) generated by the generation unit 621 in the storage unit 622. Also, the check value generation unit 620 determines an error check value to be checked for the current error check from the plurality of error check values stored in the storage unit 622 in the past by the determination unit 623. The error check value (PN) thus determined is output from the storage unit 622 to the check unit 610.

  The function that the check value generation unit 620 outputs to the check unit 610 the error check values that have been generated and stored in the past (hereinafter referred to as “error check value output function”) is the error check that the main control unit 110 has. This is similar to the value addition function. In addition, the check value generation unit 620 has a plurality of error check value output functions in advance, like the main control unit 110, and, as a specific embodiment thereof, a plurality of retroactive numbers similar to the main control unit 110 are set in advance. It is prepared. The selection information for the error check value output function is also the same as the HW parameter of the main control unit 110. The error check value output function and the selection information thereof of the subsequent control unit 180 are negotiated between the main control unit 110 and the subsequent control unit 180 in advance.

  In particular, the determination unit 623 also changes the retroactive number based on the control command (P) received by the receiving unit 600 and determines the error check value to be output to the checking unit 610. This is the same as the function of changing the retroactive number of the determining means 540. That is, the determination unit 623 determines the type of control command (corresponding to the determination circuit 541 of the main control unit 110), the retroactive number according to the determination result, and stores the error check value indicated by the determined retroactive number. A function of outputting from the unit 622 to the inspection unit 610 (corresponding to the determination circuit 542 of the main control unit 110). In order to realize the function of the determination unit 623, the RAM 180c includes a storage area corresponding to the change condition storage unit of the main control unit 110 and a reception number corresponding to the generated number storage area (P) of the main control unit 110. A storage area (P) is provided. The same applies to the retroactive number storage area (N) and the change timing information storage area (Mi).

  In addition, the function that the generation unit 621 generates an error check value (P) of the control command (P) output from the reception unit 600 by a generation method that is negotiated with the main control unit 110 in advance is also provided. The function is the same as that of the generation unit 520 of the control unit 110.

  The storage unit 622 also stores the error check value (P) generated by the generation unit 621 and outputs the error check value (PN) notified from the determination unit 623 to the check unit 610. The same function as that of the storage circuit 522 of the main control unit 110 is provided. In addition, when the main control unit 110 or the subsequent control unit 180 is initialized and the past error check value stored in the storage unit 622 is cleared, the CPU 180a reads the unique information from the ROM 180b and uses it as an initial check value. The function stored in the storage unit 622 is the same as that of the main control unit 110.

  Note that specific means for realizing the functions of the determination unit 623, the generation unit 621, and the storage unit 622 can be configured from a part of the CPU 180a, a part of the ROM 180b, a part of the RAM 180c, and the like shown in FIG. .

  The checking unit 610 has a function of performing an error checking process for collating the error check value output from the receiving unit 600 with the error check value output from the storage unit 622 of the check value generating unit 620. In the error check process, the error check value output from the receiving unit 600 is compared with the error check value output from the storage unit 622. If both match with the error check value (PN), the check result is If it is determined to be normal and does not match, it is determined that the test result is not normal.

  When the inspection result is determined to be normal, the inspection unit 610 generates the control command (P) to which the currently received error check value (PN) is added and the current error check value (PN) generation source. It is determined that the validity of the N previous control command (PN) is authenticated and the validity of the main control unit 110 can be authenticated. Then, the inspection unit 610 generates authentication result data indicating successful authentication and outputs the generated authentication result data to the adding unit 630. On the other hand, when the inspection result is not determined to be normal, the inspection unit 610 determines that the legitimacy of the main control unit 110 could not be authenticated due to an illegal act or a communication error. Then, the inspection unit 610 generates authentication result data indicating unsuccessful authentication and outputs it to the adding unit 630. The data format of the authentication result data is not particularly limited, but may be a data format having the same data length as the error check value added to the received control command. Further, specific means for realizing the function of the inspection unit 610 can be configured from a part of the CPU 180a, a part of the ROM 180b, a part of the RAM 180c, and the like shown in FIG.

  The adding unit 630 adds the authentication result data output from the checking unit 610 to the control command (P) extracted from the error check value (PN) output from the receiving unit 600, and includes the authentication result data. It has a function of generating a control command (P). The adding unit 630 has a function of outputting the generated control command (P) with authentication result data to the relay transmitting unit 640. Note that specific means for realizing the function of the adding unit 630 can be configured from a part of the CPU 180a, a part of the ROM 180b, a part of the RAM 180c, and the like shown in FIG.

  The relay transmission unit 640 has a function of relaying and transmitting the control command (P) with authentication result data output from the adding unit 630 to the effect control unit 120. The control command (P) with authentication result data transmitted from the relay transmission unit 640 to the effect control unit 120 indicates an effect process having the same content as the control command (P) received by the receiving unit 600. That is, the control command (P) received by the receiving unit 600 is output to the relay transmission unit 640 in a state where the specific processing content and the reception order are maintained, and the relay transmission unit 640 sends the control command (P) to the effect control unit 120. Will be sent. Note that specific means for realizing the function of the relay transmission unit 640 can be configured from a part of the CPU 180a, a part of the ROM 180b, a part of the RAM 180c, and the like shown in FIG.

  When transmitting the generated authentication result data to the effect control unit 120, the latter-stage control unit 180 adds the received authentication command data to the effect control unit 120 and transmits it. That is, the authentication result data is not transmitted by the authentication result data alone, but is transmitted to the effect control unit 120 integrally with the control command which is other transmission data. If the authentication result data and the error check value are in a data format having the same data length, the transmission data transmitted from the main control unit 110 to the subsequent control unit 180 via the effect control unit 120 and the subsequent control unit 180 The transmission data transmitted to the effect control unit 120 can be in a data format having the same data length. By doing so, it is difficult for an unauthorized person to steal transmission data between the post-stage control unit 180 and the production control unit 120 and to illegally analyze the transmission timing of the authentication result data to the production control unit 120. Thus, the security strength of the gaming machine 1 can be improved.

[Explanation of control commands]
Hereinafter, the types of control commands transmitted from the main control unit 110 to the effect control unit 120 of the gaming machine 1 according to the embodiment of the present invention will be described.
FIG. 9 is a diagram showing the types of control commands transmitted from the main control unit 110 to the effect control unit 120 constituting the gaming machine 1 according to the present embodiment. The control command shown in FIG. 9 is an example, and the control command according to the present invention is not limited to this.

  The control command transmitted from the main control unit 110 to the production control unit 120 is composed of 1-byte data, and 1-byte “MODE” information for identifying the control command classification, It consists of 1-byte “DATA” information indicating the detailed control contents of the control command. The “MODE” information and the “DATA” information are stored in advance in the main ROM 110b as described above. In this embodiment, an error check value is added to the control command and transmitted to the effect control unit 120 as a control command with an error check value. In the following description, “transmit a control command” The expression includes transmitting the control command with an error check value.

The “designation designating command” indicates the type of the special symbol that is stopped and displayed. The “MODE” information is set as “E0H”, and the “DATA” information is set according to the special symbol type. ing. Since the special symbol type eventually determines the jackpot type and gaming state, the effect symbol designation command can also be said to indicate the jackpot type and gaming state.
In the effect symbol designation command, when various special symbols are determined and the variation display of the special symbol is started, an effect symbol designation command corresponding to the determined special symbol is transmitted to the effect control unit 120. Specifically, when the lottery result of the jackpot is determined, various special symbols are determined, and the variation display of the special symbols is started, an effect designating command corresponding to the determined special symbol is transmitted to the main RAM 110c. Set in the data storage area. Thereafter, the effect designating command set in the transmission data storage area is transmitted to the effect control unit 120 with the error check value added by the command transmission process. Thereafter, other control commands are similarly transmitted to the effect control unit 120.
The process related to the jackpot lottery related to the production symbol designation command will be described later.

  Here, among the effect designating commands, the “losing effect designating command” set with “DATA” information being “00H” is a control for stopping and displaying the result of the losing when the lottery result is losing. It is a command. That is, it is a control command that is surely transmitted from the main control unit 110 to the effect control unit 120 when the lose design symbol designation command is a loss. Hereinafter, the lose effect designating command is also referred to as a “lose command” as a command for executing a process in case of loss.

The “first special symbol memory designation command” indicates the number of reserved memories stored in the first special symbol reservation number (U1) storage area, and the information of “MODE” is set to “E1H”, “DATA” information is set according to the number of memories.
This first special symbol memory designation command is effect-controlled by the first special symbol memory designation command corresponding to the number of reserved memories when the number of reserved memories stored in the first special symbol reservation number (U1) storage area is switched. Is transmitted to the unit 120. Specifically, when the value stored in the first special symbol hold number (U1) storage area is increased or decreased when determining the result of entering the first start port 14 or the big win lottery result, the reserved memory after the increase or decrease is stored. The first special symbol storage designation command corresponding to the number is set in the transmission data storage area of the main RAM 110c.

The “second special symbol memory designation command” indicates the number of reserved memories stored in the second special symbol reservation number (U2) storage area, and the information of “MODE” is set to “E2H”, “DATA” information is set according to the number of memories.
This second special symbol memory designation command is directed by the second special symbol memory designation command corresponding to the number of reserved memories when the number of reserved memories stored in the second special symbol reservation number (U2) storage area is switched. Is transmitted to the unit 120. Specifically, when the value stored in the second special symbol holding number (U2) storage area is increased or decreased in determining the result of entering the second starting port 15 or the jackpot lottery result, the holding storage after the increase / decrease is performed. The second special symbol storage designation command corresponding to the number is set in the transmission data storage area of the main RAM 110c.
In the present embodiment, the “first special symbol memory designation command” and the “second special symbol memory designation command” are collectively referred to as “special symbol memory designation command”.

The “symbol confirmation command” indicates that the special symbol is stopped and displayed, and “MODE” information is set to “E3H” and “DATA” information is set to “00H”.
This symbol confirmation command is transmitted to the effect control unit 120 when the special symbol is stopped and displayed. Specifically, after determining the jackpot lottery result and the special symbol change time has elapsed, when the special symbol is stopped and displayed on the first special symbol display device 20 or the second special symbol display device 21, the symbol confirmation command Is set in the transmission data storage area of the main RAM 110c.

The “power-on designation command” indicates that the gaming machine 1 is powered on, the “MODE” information is set to “E4H”, and the “DATA” information is set to “00H”. ing.
The power-on designation command is transmitted to the effect control unit 120 when the gaming machine 1 is powered on. When the gaming machine 1 is powered on and the initialization process of the main control unit 110 is performed, if the backup information of the main RAM 110c generated when the power is turned off (hereinafter referred to as “power interruption”) is not valid, The work area in the RAM 110c is cleared and a new work area is set. Thereafter, a power-on designation command is set in the transmission data storage area of the main RAM 110c.
The initialization process related to the power-on designation command and the like will be described later.

The “RAM clear designation command” indicates that the information stored in the main RAM 110c has been cleared. The “MODE” information is set to “E4H” and the “DATA” information is set to “01H”. Has been.
A RAM clear button (not shown) is provided on the back side of the gaming machine 1. When the gaming machine 1 is turned on while pressing the RAM clear button, a system reset occurs in the main control unit 110 and initialization processing is performed. . After the work area of the main RAM 110c is cleared and a new work area is set and a power-on designation command is transmitted, the RAM clear designation command is set in the transmission data storage area of the main RAM 110c.

The “power recovery designation command” indicates that the gaming machine 1 has been powered on and has been restored normally. The “MODE” information is set to “E4H” and is matched according to the gaming state at the time of power interruption. "DATA" information is set.
This power supply restoration designation command is transmitted to the effect control unit 120 when the gaming machine 1 is turned on and normally restored. Specifically, when the gaming machine 1 is turned on and the initialization process is performed, if the backup information of the main RAM 110c generated at the time of power interruption is valid, the power is restored according to the gaming state indicated by the backup information. A designated command is generated, and the generated power supply restoration designation command is set in the transmission data storage area of the main RAM 110c.

  When the power is turned on, at least one of a power-on designation command, a RAM clear designation command, and a power restoration designation command is transmitted from the main control unit 110 to the effect control unit 120. That is, the above-described control command group in which “MODE” information is set to “E4H” is a command for executing a process at power-on. Hereinafter, the control command group in which the “MODE” information is set to “E4H” is also referred to as “power-on command”.

The “demonstration designation command” indicates that the first special symbol display device 20 or the second special symbol display device 21 is not operating, the information of “MODE” is set to “E5H”, and “DATA” Is set to “00H”.
This demonstration designation command is used for effect control when there is no special symbol hold storage in the first special symbol display device 20 or the second special symbol display device 21 and a non-game state in which there is no operation by the player has elapsed for a predetermined time. Is transmitted to the unit 120. Specifically, when the jackpot lottery, the special electric accessory, and the gaming state are controlled, either the first special symbol hold number (U1) storage area or the second special symbol hold number (U2) storage area In addition, when a state in which one or more data is not set continues for a predetermined time, the demo designation command is set in the transmission data storage area of the main RAM 110c.

  The demonstration designation command may be sent immediately when there is no special symbol holding storage of the first special symbol display device 20 or the second special symbol display device 21. In this case, after receiving the demonstration designation command, the effect control unit 120 executes the demonstration effect when no other control command is received for a predetermined time, that is, when the non-game state has elapsed for a predetermined time.

The “variable pattern designation command for the first special symbol” indicates the variation time (variation mode) of the special symbol in the first special symbol display device 20, the information of “MODE” is set as “E6H”, and various “DATA” information is set in accordance with the fluctuation pattern.
The first special symbol variation pattern designation command is a first special symbol variation pattern corresponding to the variation pattern of the special symbol determined when the special symbol variation display of the first special symbol display device 20 is started. A designation command is transmitted to the effect control unit 120. Specifically, the variation pattern for the first special symbol corresponding to the determined variation pattern of the special symbol when the variation pattern of the special symbol is determined and the variation display of the special symbol is started by judging the lottery result of the jackpot The designated command is set in the transmission data storage area of the main RAM 110c.

The “variable pattern designation command for the second special symbol” indicates the variation time (variation mode) of the special symbol in the second special symbol display device 21, and the information of “MODE” is set to “E7H”. “DATA” information is set in accordance with the fluctuation pattern.
The second special symbol variation pattern designation command is a second special symbol variation pattern corresponding to the variation pattern of the special symbol determined when the special symbol variation display of the second special symbol display device 21 is started. A designation command is transmitted to the effect control unit 120. Specifically, the variation pattern for the second special symbol corresponding to the determined variation pattern of the special symbol when the variation pattern of the special symbol is determined and the variation display of the special symbol is started by judging the lottery lottery result The designated command is set in the transmission data storage area of the main RAM 110c.
In the present embodiment, the “first special symbol variation pattern designation command” and the “second special symbol variation pattern designation command” are collectively referred to as a “variation pattern designation command”.

  Here, among the variation pattern designation commands, the control command group in which the information of “DATA” is set to “01H”, “02H”, “03H”, “04H”, “05H” is a control for executing the reach effect. It is a command. Hereinafter, the control command group in which the “MODE” information is set to “E6H” and the “DATA” information is set to “01H” to “05H” is also referred to as “reach command”.

The “big prize opening opening designation command” indicates the number of rounds of jackpots according to various types of jackpots, and “MODE” information is set as “EAH”, and “DATA” is set according to the number of rounds of jackpots. Information is set.
With regard to the special winning opening opening designation command, when the big hit round is started, the big winning opening opening designation command corresponding to the started round number is transmitted to the effect control unit 120. Specifically, when the first big prize opening opening / closing door 16b (or the second big prize opening opening / closing door 17b) is opened in the big hit game process, the big winning opening opening designation command corresponding to the number of rounds to be opened is It is set in the transmission data storage area of the main RAM 110c.
Note that the command group in which the information of “MODE” is set to “EAH” is a command for executing processing corresponding to each round of jackpot. Hereinafter, a command group in which “MODE” information is set to “EAH” is also referred to as a “hit command”.

The “opening designation command” indicates that various jackpots start, “MODE” information is set as “EBH”, and “DATA” information is set according to the jackpot type.
As for this opening designation command, when various jackpots start, an opening designation command corresponding to the type of jackpot is transmitted to the effect control unit 120. Specifically, at the start of the jackpot game process, an opening designation command corresponding to the jackpot type is set in the transmission data storage area of the main RAM 110c.
Note that the command group in which the information of “MODE” is set to “EBH” is a command for starting the big hit state processing. Hereinafter, a command group in which “MODE” information is set to “EBH” is also referred to as a “big hit start command”.

The “ending designation command” indicates that various types of jackpots have ended, “MODE” information is set as “ECH”, and “DATA” information is set according to the jackpot type.
As for this ending designation command, when various jackpots are finished, an ending designation command corresponding to the jackpot type is transmitted to the effect control unit 120. Specifically, at the start of the jackpot game end process, an ending designation command corresponding to the jackpot type is set in the transmission data storage area of the main RAM 110c.
Note that the command group in which the “MODE” information is set to “ECH” is a command for ending the jackpot state process. Hereinafter, a command group in which “MODE” information is set to “ECH” is also referred to as a “hit end command”.

The “gaming state designation command” indicates the contents of the gaming state, the information of “MODE” is set as “EDH”, and the information of “DATA” is set according to the contents of the gaming state.
As for the gaming state designation command, the gaming state designation command is transmitted to the effect control unit 120 at the start and end of the variation of the special symbol. Specifically, when the value of various storage areas storing data indicating the current gaming state, such as the gaming state storage area and the high probability game number counter, changes due to the start and end of the change of the special symbol A gaming state designation command corresponding to the current gaming state is set in the transmission data storage area of the main RAM 110c.

[Control processing of main control unit]
Hereinafter, the control process of the main control unit 110 of the gaming machine 1 according to the embodiment of the present invention will be described. First, main processing of the main control unit 110 will be described.
FIG. 10 is a flowchart showing main processing by the main control unit 110 according to the present embodiment.

  When the gaming machine 1 is powered on and powered by the power supply unit 170, a system reset occurs in the main control unit 110, and the main CPU 110a performs initialization processing (processing from step S1 to step S17 in FIG. 10). ) And random number value update processing (step S20 and step S30 in FIG. 10).

In step S1, the main CPU 110a performs a boot process as a premise of the initialization process of the main control unit 110. In this boot process, the main CPU 110a performs its own self-diagnosis process, initialization of built-in circuits and peripheral circuits, and setting of initial values. Details of the boot process will be described later.
In step S2, the main CPU 110a sets permission to access the main RAM 110c.
In step S3, the main CPU 110a determines whether or not the RAM clear switch is on. If it is determined that the RAM clear switch is on, the main CPU 110a moves the process to step S10 to perform RAM clear. On the other hand, if the RAM clear switch is not determined to be on, the process proceeds to step S4.

In step S4, the main CPU 110a generates a checksum in a predetermined storage area of the main RAM 110c when the power is turned on.
In step S5, the main CPU 110a compares the generated checksum with the checksum in the predetermined storage area of the main RAM 110c generated at the time of power interruption. If they match, it is determined to be normal, and the process proceeds to step S6. If they do not match, it is determined to be an error, and the process proceeds to step S10.

In step S <b> 6, the main CPU 110 a adjusts the start timing of the operation after activation with the peripheral control unit 300 including the effect control unit 120 and the subsequent control unit 180. Specifically, after all of the peripheral control unit 300 and the subsequent stage control unit 180 are activated and become stable, it waits for a certain period of time so that the rendering process and the like can be started at substantially the same timing.
In step S7, the main CPU 110a sets an initial value in the work area of the main RAM 110c that requires an initial value upon recovery from power interruption, and performs a RAM setting process when backup is valid.

In step S8, the main CPU 110a reads the backup information of the main RAM 110c generated at the time of power interruption in order to restore the gaming state at the time of power interruption. Specifically, the game state information is read from the game state storage area of the main RAM 110c that is backed up.
In step S9, the main CPU 110a determines a power restoration designation command based on the read gaming state information, and sets the decided power restoration designation command in the transmission data storage area of the main RAM 110c.

In step S10, the main CPU 110a performs timing adjustment with the peripheral control unit 300 and the subsequent control unit 180 in the same manner as in step S6.
In step S11, the main CPU 110a clears the used area of the main RAM 110c.
In step S12, the main CPU 110a sets initial values in the work area of the main RAM 110c that requires initial values when initializing the gaming machine 1, including setting initial values of various random numbers, and backup is not valid. In this case, the main RAM 110c is set.

In step S13, the main CPU 110a generates a power-on designation command, and sets the generated power-on designation command in the transmission data storage area of the main RAM 110c.
In step S <b> 14, the main CPU 110 a performs a command transmission process for transmitting the control command set in the transmission data storage area to the effect control unit 120. That is, a power-on designation command is transmitted to the effect control unit 120. Note that the command transmission processing in step S14 and step S16 involves retroactive number setting processing, inspection value generation processing, and inspection value addition processing. Further, the command transmission process of step S14 and step S16 involves a process of setting unique information as an initial inspection value in the storage circuit 522. Details of the command transmission process will be described later.

In step S15, the main CPU 110a generates a RAM clear designation command, and sets the generated RAM clear designation command in the transmission data storage area of the main RAM 110c.
In step S16, the main CPU 110a performs a command transmission process for transmitting a control command set in the transmission data storage area of the main RAM 110c to the effect control unit 120. That is, the control command of either the power supply restoration designation command or the RAM clear designation command is transmitted to the effect control unit 120.
In step S <b> 17, the main CPU 110 a sets the interrupt permission and sets the execution period (α, for example, 4 milliseconds) of the timer interrupt program.

  Note that the command transmission processing in step S14 and step S16 may be performed in the timer interrupt processing performed after interrupt permission in step S17. At this time, it is determined in advance that the transmission order of each control command is not changed.

In step S20, the main CPU 110a performs an effect random number update process for updating the reach determination random number value and the special figure variation random value for determining the variation mode (variation time) of the special symbol.
In step S30, the main CPU 110a performs an initial random number value updating process for updating the special symbol determining initial random number value, the big hit symbol initial random number value, the small hit symbol initial random number value, and the normal symbol determining initial random number value. Thereafter, the processes in steps S20 and S30 are repeated until a predetermined interrupt process is performed.

Next, interrupt processing of the main control unit 110 will be described.
FIG. 11 is a flowchart showing interrupt processing by the main control unit 110 according to the present embodiment.
The main CPU 110a executes timer interrupt processing of the main control unit 110 at predetermined intervals (α) based on a clock signal output from a clock pulse generation circuit provided in the main control unit 110.

  First, in step S100, the main CPU 110a saves the information stored in the register of the main CPU 110a to the stack area.

  In step S110, the main CPU 110a updates the special symbol time counter, updates the special game timer counter such as the opening time of the special electric accessory, updates the normal symbol time counter, and updates the normal power release time counter. A time control process for updating various timer counters is performed. Specifically, a process of subtracting 1 from a special symbol time counter, a special game timer counter, a normal symbol time counter, and a general electricity open time counter is performed.

In step S120, the main CPU 110a performs a random number update process for the special symbol determination random number value, the big hit symbol random number value, the small hit symbol random number value, and the normal symbol determination random number value.
Specifically, 1 is added to each random number value and random number counter to be updated. When the added random number counter exceeds the maximum value in the random number range (when the random number counter makes one revolution), the random number counter is returned to 0, and each random number value is newly updated from the initial random number value at that time. .

  In step S130, as in step S30, the main CPU 110a updates the initial random number value for special symbol determination, the initial random number value for jackpot symbol, the initial random number value for small bonus symbol, and the initial random number value for normal symbol determination. Perform numerical value update processing.

  In step S200, the main CPU 110a performs input control processing. In this process, the main CPU 110a includes a general winning opening detection switch 12a, a first large winning opening detection switch 16a, a second large winning opening detection switch 17a, a first starting opening detection switch 14a, a second starting opening detection switch 15a, a gate. An input process for determining whether or not there is an input to each switch of the detection switch 13a is performed.

  Specifically, various detection signals from the general winning opening detecting switch 12a, the first big winning opening detecting switch 16a, the second large winning opening detecting switch 17a, the first starting opening detecting switch 14a, and the second starting opening detecting switch 15a. Is inputted, predetermined data is added to the prize ball counter used for the prize ball provided for each prize opening and updated.

  Further, when a detection signal is input from the first start port detection switch 14a, if the data set in the first special symbol hold number (U1) storage area is less than 4, the first special symbol hold number ( U1) Add 1 to the storage area to obtain special symbol determination random number value, jackpot symbol random number value, small hit symbol random number value, reach determination random value, and special symbol variation random value The random number value is stored in a predetermined storage unit (0th storage unit to 4th storage unit) in the first special symbol random value storage area.

  Similarly, when a detection signal is input from the second start port detection switch 15a, if the data set in the second special symbol hold number (U2) storage area is less than 4, the second special symbol hold number (U2) 1 is added to the storage area, and a special symbol determination random number value, a big hit symbol random number value, a small hit symbol random number value, a reach determination random number value, and a special symbol variation random value are acquired. Various random numbers are stored in a predetermined storage unit (0th storage unit to 4th storage unit) in the second special symbol random number value storage area.

  When a detection signal is input from the gate detection switch 13a, if the data set in the normal symbol hold number (G) storage area is less than 4, the normal symbol hold number (G) storage area is set to 1. It adds, acquires the random number value for normal symbol determination, and memorize | stores the acquired random number value for normal symbol determination in the predetermined memory | storage part (0th memory | storage part-4th memory | storage part) in a normal symbol holding | maintenance storage area.

  Further, when a detection signal from the first grand prize opening detection switch 16a or the second big prize opening detection switch 17a is inputted, the number of game balls won in the first big prize opening 16 or the second big prize opening 17 is counted. 1 is added to the number of entries (C) storage area for the big winning opening to update.

  In step S300, the main CPU 110a, based on the input control process in step S200, performs a special symbol / special electric accessory control process (hereinafter referred to as “a special jackpot lottery, a special electric accessory, and a gaming state control”). Special figure special electricity control process ”). Details of the special figure special electric control process will be described later with reference to FIG.

In step S400, the main CPU 110a performs a normal symbol / ordinary electric accessory control process (hereinafter referred to as a “general-purpose electric power control process”) for performing the normal symbol lottery and the control of the ordinary electric accessory.
Specifically, it is first determined whether or not 1 or more data is set in the normal symbol hold count (G) storage area, and 1 or more data must be set in the normal symbol hold count (G) storage area. If this is the case, the current ordinary power transmission control process is terminated.

If 1 or more data is set in the normal symbol holding number (G) storage area, after subtracting 1 from the value stored in the normal symbol holding number (G) storage area, it is in the normal symbol holding storage area The normal symbol determination random numbers stored in the first storage unit to the fourth storage unit are shifted to the previous storage unit. At this time, the normal symbol determination random number value already written in the 0th storage unit is overwritten and erased.
Then, referring to the hit determination table, a process is performed to determine whether or not the normal symbol determination random number value stored in the 0th storage unit of the normal symbol hold storage area is a random value corresponding to “win”. Thereafter, the normal symbol display device 22 displays the fluctuation of the normal symbol. When the fluctuation time of the normal symbol elapses, the normal symbol corresponding to the result of the normal symbol lottery is stopped and displayed. If the random number for normal symbol determination referred to is “winning”, the start opening / closing solenoid 15c is driven to control the second start opening 15 to the second mode for a predetermined opening time.

  In step S500, the main CPU 110a performs a payout control process. In this payout control process, the main CPU 110 a refers to each prize ball counter, generates payout number designation commands corresponding to various winning ports, and transmits the generated payout number designation commands to the payout control unit 130. To do.

  In step S600, the main CPU 110a, external information data, start opening / closing solenoid data, first big prize opening opening / closing solenoid data, second big prize opening opening / closing solenoid data, special symbol display device data, normal symbol display device data, number of stored Performs data creation for the specified command.

In step S700, the main CPU 110a performs output control processing. In this process, port output processing is performed for outputting signals of the external information data, the start opening / closing solenoid data, the first big prize opening / closing solenoid data, and the second big prize opening / closing solenoid data created in step S600.
Further, the special symbol display device data and the normal symbol display device data created in S600 are used to turn on the LEDs of the first special symbol display device 20, the second special symbol display device 21 and the normal symbol display device 22. Display device output processing is performed.

  In step S710, the main CPU 110a performs a command transmission process for transmitting the control command set in the transmission data storage area of the main RAM 110c to the effect control unit 120. Note that the command transmission process in step S710 also involves a retroactive number setting process, a test value generation process, and a test value addition process, as described above, but details will be described later.

  In step S800, the main CPU 110a restores the information saved in step S100 to the register of the main CPU 110a.

Next, the special figure special electric control process of the main control unit 110 will be described.
FIG. 12 is a flowchart showing a special figure special power control process by the main control unit 110 according to the present embodiment.

  In step S301, the main CPU 110a reads the value of the special figure special electricity processing data. This “Special Figure Special Electric Processing Data” is a value assigned to the address of the storage area in which each subroutine of the special figure special electric control process is stored, and which subroutine is processed by referring to the special figure special electric processing data. You can identify what to do. The special figure special electricity processing data is set as necessary in each subroutine of the special figure special electricity control processing as will be described later, and the subroutine necessary for the game is appropriately processed.

  In step S302, the main CPU 110a refers to the branch address from the read special figure special processing data, and if special figure special electric treatment data = 0, the main CPU 110a moves the processing to the special symbol storage determination process (step S310). If data = 1, the process moves to the special symbol variation process (step S320), and if the special figure special electricity process data = 2, the process moves to the special symbol stop process (step S330), and the special figure special electricity process data = 3. If there is, the process is transferred to the jackpot game process (step S340). If the special figure special electric processing data = 4, the process is transferred to the jackpot game end process (step S350). The processing is moved to processing (step S360).

  In the special symbol memory determination process in step S310, the main CPU 110a performs a jackpot determination process, a special symbol determination process for determining a special symbol to be stopped and displayed, a variation time determination process for determining a variation time of the special symbol, and the like. Here, the specific content of the special symbol memory determination process will be described with reference to FIG.

  FIG. 13 is a flowchart in the special symbol memory determination process by the main control unit 110 according to the present embodiment.

In step S311, the main CPU 110a determines whether one or more data is set in the first special symbol hold count (U1) storage area or the second special symbol hold count (U2) storage area.
If one or more data is not set in any storage area of the first special symbol hold count (U1) storage area or the second special symbol hold count (U2) storage area, the special figure special electricity processing data = 0. The special symbol variation process of this time is terminated while holding.
On the other hand, if one or more data is set in the first special symbol hold count (U1) storage area or the second special symbol hold count (U2) storage area, the process proceeds to step S312.

In step S312, the main CPU 110a performs a jackpot determination process.
Specifically, when one or more data is set in the second special symbol hold count (U2) storage area, 1 is calculated from the value stored in the second special symbol hold count (U2) storage area. After the subtraction, the various random numbers stored in the first to fourth storage units in the second special symbol random number storage area are shifted to the previous storage unit. At this time, various random values already written in the 0th storage unit are overwritten and deleted. Then, referring to the jackpot determination table, whether the special symbol determination random number value stored in the 0th storage unit of the second special symbol random value storage area is a random value corresponding to “big hit” or “small hit” It is determined whether it is a random value corresponding to.

  In addition, when one or more data is not set in the second special symbol hold number (U2) storage area and one or more data is set in the first special symbol hold number (U1) storage area, Various random numbers stored in the first to fourth storage units in the first special symbol random number storage area after subtracting 1 from the value stored in the first special symbol hold number (U1) storage area Is shifted to the previous storage unit. Also at this time, various random numbers already written in the 0th storage unit are overwritten and deleted. Then, referring to the jackpot determination table, whether the special symbol determination random number value stored in the 0th storage unit of the first special symbol random number storage area is a random value corresponding to “big hit” or “small hit” It is determined whether it is a random value corresponding to.

  In the present embodiment, the random number value stored in the second special symbol random value storage area is shifted (digested) with priority over the first special symbol random value storage area. However, the first special symbol storage area or the second special symbol storage area may be shifted in the order of winning in the starting opening, and the first special symbol storage area is given priority over the second special symbol storage area. You may let them.

In step S313, the main CPU 110a performs a special symbol determination process for determining the type of special symbol to be stopped and displayed.
In this special symbol determination process, when it is determined as “big hit” in the jackpot determination process (step S312), the symbol determination table is referred to and stored in the 0th storage unit of the first special symbol random value storage area. The jackpot symbol (special symbol 1 to special symbol 6) is determined based on the random number value for the jackpot symbol. In addition, when it is determined as “small hit” in the jackpot determination process (step S312), the small hit stored in the 0th storage unit of the first special symbol random value storage area with reference to the symbol determination table Based on the symbol random number value, the small hit symbol (special symbol A, special symbol B) is determined. Further, when it is determined as “losing” in the jackpot determination process (step S312), the symbol determining table (special symbol 0) is determined with reference to the symbol determining table.
Then, stop symbol data corresponding to the determined special symbol is stored in the stop symbol data storage area.

In step S314, the main CPU 110a performs special symbol variation time determination processing.
Specifically, referring to the variation pattern determination table, based on the reach determination random value and the special diagram variation random value stored in the 0th storage unit of the first special symbol random value storage area, the special symbol Determine the variation pattern. Thereafter, the variation time of the special symbol corresponding to the determined variation pattern of the special symbol is determined. Then, a process of setting a counter corresponding to the determined variation time of the special symbol in the special symbol time counter is performed.

In step S315, the main CPU 110a sets, in a predetermined processing area, variation display data for causing the first special symbol display device 20 or the second special symbol display device 21 to perform special symbol variation display (LED blinking). . As a result, when the variable display data is set in the predetermined processing area, the LED lighting / extinguishing data is appropriately created in step S600, and the created data is output in step S700. Variation display of the special symbol display device 20 or the second special symbol display device 21 is performed.
Further, the main CPU 110a, when the special symbol variation display is started, the special symbol variation pattern designation command (the first special symbol variation pattern designation command) corresponding to the special symbol variation pattern determined in step S314. Alternatively, the second special symbol variation pattern designation command) is set in the transmission data storage area of the main RAM 110c.

  In step S316, the main CPU 110a sets the special symbol special electricity processing data = 0 to the special symbol special electric treatment data = 1, prepares to move to the special symbol variation processing subroutine, and ends the special symbol memory determination processing.

Again, the description of the special figure special electric control process shown in FIG. 12 will be returned.
In the special symbol variation process of step S320, the main CPU 110a performs a process of determining whether or not the special symbol variation time has elapsed.
Specifically, it is determined whether or not the variation time of the special symbol determined in step S314 has elapsed (special symbol time counter = 0), and if it is determined that the variation time of the special symbol has not elapsed The special symbol variation process is terminated while the special symbol special electricity processing data = 1 is held. Note that the special symbol variation time counter set in step S314 is subtracted in step S110.

If it is determined that the variation time of the special symbol has elapsed, the special symbol determined in step S313 is stopped and displayed on the first special symbol display device 20 or the second special symbol display device 21. Thereby, the special symbol is stopped and displayed on the first special symbol display device 20 or the second special symbol display device 21, and the player is notified of the jackpot determination result.
When the number of high probability games (X)> 0, 1 is subtracted from the high probability game number (X) counter and updated. When the number of high probability games (X) = 0, the high probability game flag is cleared. .
Finally, the special symbol special power processing data = 1 is set to the special symbol special power processing data = 2, preparation is made to move to a special symbol stop processing subroutine, and the special symbol variation processing is terminated.

In the special symbol stop process in step S330, the main CPU 110a performs a process of determining whether the special symbol that is stopped and displayed is a “big hit symbol”, a “small bonus symbol”, or a “losing symbol”. Do.
When it is determined that the game is a jackpot symbol, the data stored in the gaming state storage area is referred to and data indicating the current gaming state is set in the gaming state buffer. Thereafter, the data (high probability game flag) and high probability game count (X) counter stored in the game state storage area (high probability game flag storage area or the like) are cleared. Furthermore, the special figure special power processing data = 2 is set to the special figure special electric processing data = 3, preparation is made to move to the jackpot game processing subroutine, and the special symbol stop processing is ended.

In addition, when it is determined that the small winning symbol, the data stored in the game state storage area is not cleared, and the special figure special electric processing data = 2 to the special figure special electric treatment data = 5 is set. The special symbol stop process is completed by making preparations for transferring to a winning game process subroutine.
On the other hand, if it is determined that the symbol is a lost symbol, the special symbol special electric processing data = 2 is set to special special electric symbol processing data = 0, and the special symbol memory determination processing subroutine is prepared for the special symbol stop processing. finish.

In the jackpot game process of step S340, the main CPU 110a determines which jackpot of the long hit or short hit is executed, and performs a process of controlling the determined jackpot.
Specifically, first, with reference to the special electric accessory operating mode determination table, the jackpot release mode is determined based on the type of jackpot symbol (stop symbol data) determined in step S313.

Next, in order to execute the determined jackpot opening mode, the bonus game opening mode table is referred to, the opening time corresponding to the type of jackpot is set in the special game timer counter, and the first jackpot opening / closing solenoid The drive data of 16c (or the second big prize opening / closing solenoid 17c) is output to open the first big prize opening / closing door 16b (or the second big prize opening / closing door 17b). At this time, 1 is added to the round game count (R) storage area.
When a predetermined number of game balls enter during the opening or when the opening time of the big prize opening has elapsed (the number of the big prize opening (C) = 9 or the special game timer counter = 0), The output of the drive data of the big prize opening / closing solenoid 16c (or the second big prize opening / closing solenoid 17c) is stopped, and the first big prize opening / closing door 16b (or the second big prize opening / closing door 17b) is closed. Thereby, one round game is completed. This round game control is repeated 15 times.

  When the 15 round games are completed (round game count (R) = 15), the data stored in the round game count (R) storage area and the number of winning prize entrance (C) storage areas are cleared, The special figure special electric processing data = 3 is set to the special figure special electric treatment data = 4, preparation is made to move to the big hit game end processing subroutine, and the big hit game processing is ended.

In the jackpot game end process of step S350, the main CPU 110a performs a process of determining a probability game state of either a high probability game state or a low probability game state.
Specifically, with reference to the jackpot game end setting data table, based on the data stored in the game state buffer and the type of jackpot symbol (stop symbol data) determined in step S313, the high probability game Set a flag and set the number of high probability games (X). For example, in the case of the special symbol 1, the high probability game flag is set in the high probability game flag storage area, and the high probability game number (X) counter is set to 10,000 times.
After that, the special symbol special power processing data = 4 is set to the special symbol special power processing data = 0, preparation is made to move to a special symbol memory determination processing subroutine, and the jackpot game end processing is terminated.

In the small hit game process of step S360, the main CPU 110a first refers to the special electric accessory operation mode determination table, and based on the type of small hit symbol (stop symbol data) determined in step S313 above, Determine the opening mode.
Next, in order to execute the determined small winning opening mode, the large winning opening opening mode table is referred to, and the small winning opening time is set in the special game timer counter, and the second large winning port opening / closing solenoid 17c is set. The drive data is output to open the second big prize opening / closing door 17b. At this time, 1 is added to the number-of-releases (K) storage area.
When the small hit opening time elapses (special game timer counter = 0), the output of the drive data of the second big prize opening / closing solenoid 17c is stopped and the second big prize opening opening / closing door 17b is closed. The opening / closing control of the second big prize opening opening / closing door 17b is repeated 15 times.

  Then, the opening / closing control of the second grand prize opening / closing door 17b is performed 15 times, or a predetermined number of game balls enter the second big prize opening 17 (the number of times of opening (K) = 15 or the grand prize opening entrance) Number (C) = 9), in order to end the small hit game, the output of the drive data of the second large winning opening / closing solenoid 17c is stopped, the number of times of opening (K) storage area and the number of winning winning holes (C) Clear the data stored in the storage area, set special figure special electricity processing data = 5 to special figure special electricity treatment data = 0, and prepare to move to a special symbol memory judgment processing subroutine. The winning game process is terminated.

[Control processing related to authentication processing of the main control unit]
Hereinafter, the control process regarding the authentication process of the main control unit 110 of the gaming machine 1 according to the embodiment of the present invention will be described. First, the boot process of the main control unit 110 will be described.
When the gaming machine 1 is powered on, a system reset occurs in the main control unit 110, and the main CPU 110a performs a boot process of the main control unit 110 based on a boot processing program stored in advance in the boot ROM 110d. .
FIG. 14 is a flowchart showing a boot process by the main control unit 110 according to the present embodiment.

In step S51, the main CPU 110a sets the internal state to interrupt prohibition.
In step S52, the main CPU 110a performs a self-diagnosis process for checking whether or not the main CPU 110a itself can operate normally after initialization. As a result of the self-diagnosis process, if the normal operation is possible, the process proceeds to step S53, and if the normal diagnosis is not possible, the subsequent processing is not performed.

  In step S53, the main CPU 110a performs an initial value setting process for a built-in circuit or the like. Specifically, the main CPU 110a sets the stack point designation address in the stack pointer, initializes the internal register, initializes the internal circuit and peripheral circuits of the one-chip microcomputer 110m, and initializes the input / output ports. I do. Then, the main CPU 110a sets various initial values to these built-in circuits that require initial values. At this time, the main CPU 110a performs the same process on each component of the inspection value generation unit 500 to perform an initial value setting process on the inspection value generation unit 500.

  In step S54, the main CPU 110a performs HW parameter setting processing on the inspection value generation unit 500. Specifically, the main CPU 110a outputs a read signal for reading the HW parameter for the inspection value generation unit 500 to the main ROM 110b. Then, the main CPU 110a takes in the HW parameters output from the main ROM 110b by the read signal via the bus.

  Subsequently, the main CPU 110a outputs a write signal for writing the fetched HW parameter to the determination unit 540 of the inspection value generation unit 500. Then, the main CPU 110a sets the HW parameter output from the main CPU 110a by the write signal to the determination circuit 542 of the determination unit 540 via the bus. Note that the HW parameter setting process in step S54 is a special feature of the process of setting the HW parameter in the test value generation unit 500 among the initial value setting processes performed by the main CPU 110a. Therefore, as part of the initial value setting process, It is also possible to configure so as to be performed in step S53.

  In step S55, the inspection value generation unit 500 performs retroactive number setting processing. Specifically, the determination circuit 542 of the determination unit 540 confirms which retroactive number the set HW parameter corresponds to among the retroactive numbers prepared in advance. Then, the determination circuit 542 sets the retroactive number N corresponding to the set HW parameter as a default value in the retroactive number storage area (N). Based on the value set in the retroactive number storage area (N), the decision circuit 542 outputs an error check value from a specific storage circuit among the plurality of storage circuits that bear the storage circuit 522 of the generation unit 520. In this manner, a connection switching signal is output to the input selection circuit 524 of the generation unit 520.

  Accordingly, the generation unit 520 can output an error check value corresponding to the retroactive number stored in the retroactive number storage area (N) to the addition unit 530 during the inspection value generation process. In the check value adding process, an error check value corresponding to the retroactive number can be added to the control command output from the buffer means 510. When this process ends, the boot process ends.

Next, command transmission processing of the main control unit 110 including retroactive number setting processing, inspection value generation processing, and inspection value addition processing will be described.
FIG. 15 is a flowchart showing command transmission processing in the main control unit 110 according to the present embodiment. In each step of FIG. 15, the notation in curly braces {} indicates the generated number storage area (P), change timing information storage area (Mi), and This is to outline the processing to the retroactive number storage area (N).

  After the initialization process including the boot process of the main control unit 110, when the execution timing of the command transmission process is reached, the main CPU 110a checks the control command (P) set in the transmission data storage area of the main RAM 110c. The value is output to the transmission unit 550 via the value generation unit 500 and transmitted to the effect control unit 120.

In step S71, the main CPU 110a adds 1 to the value of the generated number storage area (P) of the main RAM 110c and updates it.
In step S72, the main CPU 110a determines whether or not the control command (P) set in the transmission data storage area corresponds to the control command (1). Specifically, the main CPU 110a refers to the value of the generated number storage area (P) and determines whether P = 1. If P = 1, the process proceeds to step S73, and if P = 1, the process proceeds to step S75.

In step S73, the main CPU 110a reads the unique information stored in the main ROM 110b. At this time, if there are N pieces of unique information, N pieces of unique information are read at a time. Then, the main CPU 110a outputs the read unique information to the inspection value generation unit 500.
In step S74, the inspection value generation unit 500 stores the unique information output from the main CPU 110a in each of the storage circuits 1 to N constituting the storage circuit 522 of the generation unit 520 and sets it as an initial inspection value. Specifically, the buffer unit 510 of the inspection value generation unit 500 takes in the unique information from the main CPU 110a via the bus to the data buffer 511 and outputs it to the generation unit 520. The generation unit 520 stores the unique information output from the data buffer 511 in each of the storage circuits 1 to N that configures its own storage circuit 522.

  In step S75, the main CPU 110a writes the control command (P) set in the transmission data storage area to the buffer means 510 of the inspection value generation unit 500. Specifically, the main CPU 110a outputs a write signal and address data for writing the control command (P) to the buffer means 510, and sends the control command (P) set in the transmission data storage area to the data bus. Output. The control circuit 512 of the buffer unit 510 outputs an operation permission signal to the data buffer 511 of the buffer unit 510 based on the input of the write signal output from the main CPU 110a. The data buffer 511 takes in the control command (P) on the data bus based on the input of the operation permission signal output from the control circuit 512.

  In step S76, the buffer unit 510 outputs the fetched control command (P) to the determination unit 540, the generation unit 520, and the addition unit 530. Specifically, the control circuit 512 of the buffer unit 510 outputs an operation permission signal to the data buffer 511 with a predetermined time delay from the input of the write signal output from the main CPU 110a. The data buffer 511 outputs the fetched control command (P) to the determination unit 540, the generation unit 520, and the addition unit 530 based on the input of the operation permission signal. Subsequently, the control circuit 512 outputs an operation permission signal to these means so that the control command output from the data buffer 511 can be input by the determining means 540, the generating means 520, and the adding means 530. .

  In step S77, the determining means 540 takes in the control command (P) based on the input of the operation permission signal output from the buffer means 510, and the control command (P) is a control that satisfies the predetermined change condition. Determine if it is a command. Specifically, the determination circuit 541 of the determination unit 540 determines whether or not the type of the control command (P) is a predetermined control command type. If the control command (P) is a predetermined control command, the determination circuit 541 sends a determination result signal indicating that the control command output from the buffer means 510 is a control command that satisfies the change condition to the determination circuit 542. Output, and the process proceeds to step S78. On the other hand, if the control command (P) is not a predetermined control command, the determination circuit 541 determines a determination result signal indicating that the control command output from the buffer unit 510 is not a control command that satisfies the change condition. The process proceeds to step S78.

In step S78, the determination circuit 542 updates the value of the generated number storage area (P) provided in the determination circuit 542 by adding 1 in accordance with the input of the determination result signal output from the determination circuit 541. Thereby, the determination circuit 542 can grasp the number P of generated control commands (P) output from the buffer unit 510.
In step S79, the determination circuit 542 is a determination result signal indicating that the determination result signal output from the determination circuit 541 is that the control command (P) output from the buffer unit 510 satisfies the change condition. Check if it exists. If the content of the determination result signal indicates that the control command (P) is a control command that satisfies the change condition, the determination circuit 542 moves the process to step S80. On the other hand, if the content of the determination result signal indicates that the control command (P) is not a control command that satisfies the change condition, the determination circuit 542 moves the process to step S81.

In step S80, when a control command satisfying the change condition is output from the buffer means 510, the decision circuit 542 changes the retroactive number change timing, that is, the value of N stored in the retroactive number storage area (N). Set the timing. Specifically, the decision circuit 542 sets Mo in advance to the value of the current generated number storage area (P) with respect to its own change timing information storage area (Mi) in order to set the change timing information Mi. A value obtained by adding the values (P + Mo) is stored.
In step S81, the determination circuit 542 determines whether or not the present time is the timing for changing the retroactive number. Specifically, the determination circuit 542 compares the minimum value Mmin of the change timing information storage area (Mi) with the value of the current generated number storage area (P). If the two match, the determination circuit 542 determines that the current timing is the change timing, moves to step S82, and if both do not match, the determination circuit 542 determines that the current timing is not the change timing. The process moves to S83.

  In step S82, the determination circuit 542 changes the value of N stored in the retroactive number storage area (N) in order to change the retroactive number. Specifically, the value of N is changed according to a predetermined change method, and N ′, which is the changed value of N, is stored in the retrospective number storage area (N). Then, based on the value of the retroactive number storage area (N) after the change, the determination circuit 542 outputs the error check value from which of the plurality of storage circuits that bear the storage circuit 522 of the generation unit 520. And a connection switching signal that enables only the connection between the storage circuit 522 and the input selection circuit 524 of the generation unit 520 is output to the input selection circuit 524. In the generation unit 520, the connection check signal is input to the input selection circuit 524, so that the error check value stored in the storage circuit 522 according to the retroactive number is output to the addition unit 530.

  In step S83, the generation unit 520 takes in the control command (P) based on the input of the operation permission signal output from the buffer unit 510, and obtains the error check value (P) corresponding to the fetched control command (P). Generate. Specifically, the control circuit 523 of the generation unit 520 outputs an operation permission signal to the generation circuit 521 of the generation unit 520 based on the input of the operation permission signal output from the control circuit 512 of the buffer unit 510. The generation circuit 521 takes in the control command (P) based on the input of the operation permission signal output from the control circuit 523, generates an error check value (P) using the control command (P), and generates the generation unit 520. To the storage circuit 522.

  In step S <b> 84, the generation unit 520 stores the generated error check value (P) in its own storage circuit 522 and outputs the error check value (PN) stored in the past to the addition unit 530. Specifically, the control circuit 523 outputs a shift processing signal to the storage circuit 522 after a predetermined time delay from the input of the operation permission signal output from the control circuit 512. The storage circuit 522 sequentially shifts each error check value stored in each of its storage circuits 1 to N to the next stage based on the input of the shift processing signal output from the control circuit 523. Accordingly, the first stage storage circuit (storage circuit 1 in FIG. 5) of the storage circuit 522 takes in the error check value (P) output from the generation circuit 521. Accordingly, the storage circuit 522 stores the storage circuit 1 to N from the storage circuit (storage circuit N in FIG. 5) that is effectively connected by the connection switching signal output from the determination unit 540. The error check value (PN) stored in the circuit is output to the adding means 530.

  In step S85, the adding means 530 takes in the control command (P) and the error check value (PN) based on the input of the operation permission signal output from the buffer means 510. Then, the adding unit 530 writes the fetched control command (P) and error check value (PN) to the transmission unit 550. Specifically, the input selection circuit 531 of the adding unit 530 receives the control command (P) output from the data buffer 511 of the buffer unit 510 and outputs the acquired control command (P) to the data bus. Further, the control circuit 532 of the adding unit 530 writes a control signal (P) to the transmission buffer 551 of the transmission unit 550 based on the input of the operation permission signal output from the control circuit 512 of the buffer unit 510. And output address data.

  Further, the control circuit 532 outputs a connection switching signal to the input selection circuit 531 after a predetermined time delay from the output of the write signal. The input selection circuit 531 switches the connection source from the data buffer 511 to the storage circuit 522 based on the input of the connection switching signal output from the control circuit 532. Then, the input selection circuit 531 takes in the error check value (PN) from the storage circuit 522 of the generation means 520 via the input selection circuit 524, and outputs the fetched error check value (PN) to the data bus. . Further, when the control circuit 532 outputs the connection switching signal and the error check value (PN) is output from the input selection circuit 531 onto the data bus, the error check value (PN) is sent to the transmission buffer 551. A write signal and address data for writing are immediately output.

  In step S86, the transmission unit 550 immediately transmits the control command (P) and the error check value (P-N) output from the adding unit 530 to the effect control unit 120. Specifically, the transmission buffer 551 of the transmission unit 550 receives the control command (P) on the data bus based on the input of the write signal of the control command (P) output from the adding unit 530, and takes in the control. The command (P) is immediately output to the transmission circuit 552. The transmission buffer 551 takes in the error check value (PN) on the data bus based on the input of the write signal of the error check value (PN) output from the adding means 530, and takes in the error check. The value (P−N) is immediately output to the transmission circuit 552. The transmission circuit 552 immediately transmits the control command (P) and the error check value (PN) output from the transmission buffer 551 to the effect control unit 120 as a series of transmission data. Therefore, the control command (P) is transmitted to the effect control unit 120 as a control command to which the error check value (PN) is added.

  In step S85, when the control circuit 532 outputs the connection switching signal to the input selection circuit 531, the control command (P) output from the input selection circuit 531 is completely written to the transmission buffer 551. After the elapse of the time required until the error check value (PN), the timing is set such that the writing of the error check value (PN) to the transmission buffer 551 is started. As a result, the error check value (PN) is written into the transmission buffer 551 so that the error check value (PN) is written immediately after the control command (P) written in the transmission buffer 551. The timing will be right.

  By setting the error check value write timing as described above, an overrun or underrun of the transmission buffer 551 occurs, and an error check value (P−) to be added to the control command (P) to be transmitted this time. N) can be prevented from being added appropriately. This is because the error check value actually added and transmitted during the error check process in the post-stage control unit 180 is not consistent with the error check value to be added originally. The possibility that the inspection result will not be determined to be normal is suppressed, and the accuracy of the error inspection process is improved.

  Also, by setting the error check value write timing as described above, the error check value (PN) to be added this time is written to the transmission buffer 551 and the control command (P) is sent to the transmission buffer 551. The positional relationship of the write timing on the time axis is clarified, and the error check value (PN) is surely added immediately after the control command (P) and transmitted as one transmission data. As a result, the error check value (PN) is not transmitted to the effect control unit 120 as a single error check value (PN). Therefore, it becomes difficult for an unauthorized person to steal transmission data between the main control unit 110 and the production control unit 120, illegally analyze and reuse the error check value (PN), and the gaming machine 1 Security strength can be improved.

[Control processing of production control unit]
Hereinafter, the control processing of the effect control unit 120 of the gaming machine 1 according to the embodiment of the present invention will be described. First, the main process of the production control unit 120 will be described.
FIG. 16 is a flowchart showing main processing by the effect control unit 120 according to the present embodiment.

  In step S1000, the sub CPU 120a performs an initialization process. In this process, the sub CPU 120a reads the program code related to the main process from the sub ROM 120b in response to power-on. At the same time, the sub CPU 120a initializes a flag and the like stored in the sub RAM 120c, and performs a process of setting a setting value. If this process ends, the process moves to a step S1100.

  In step S1100, the sub CPU 120a performs an effect random number update process. In this process, the sub CPU 120a performs a process of updating the effect random number value, effect design determining random number, effect mode determining random number and the like stored in the sub RAM 120c. Thereafter, the process of step S1100 is repeated until a predetermined interrupt process is performed.

Next, the interruption process of the production control unit 120 will be described.
FIG. 17 is a flowchart showing interrupt processing by the effect control unit 120 according to the present embodiment.
Based on a clock signal output from a clock pulse generation circuit (not shown) provided in the effect control unit 120, the sub CPU 120a performs timer allocation of the effect control unit 120 at predetermined intervals (for example, 2 milliseconds). Execute the included process.

In step S1200, the sub CPU 120a saves the information stored in the register of the sub CPU 120a to the stack area.
In step S1300, the sub CPU 120a performs update processing of various timer counters used in the effect control unit 120.

  In step S1350, the sub CPU 120a performs relay transmission processing. In this process, the sub CPU 120a performs a relay transmission process in which the control command stored in the first received data storage area of the sub RAM 120c is transmitted to the subsequent control unit 180 as it is.

When the first receiving unit of the production control unit 120 receives the control command transmitted from the main control unit 110 and stores it in its own reception buffer, it indicates that there has been a control command reception interrupt request from the main control unit 110. A control command reception interrupt process is generated.
Then, the sub CPU 120a takes in the first reception data storage area of the sub RAM 120c from the reception buffer of the first reception unit and stores it. Then, the sub CPU 120a writes and sets the control command stored in the first reception data storage area as it is in the transmission data storage area of the sub RAM 120c.

  Subsequently, the sub CPU 120a immediately transmits the control command set in the transmission data storage area of the sub RAM 120c as transmission data to the subsequent control unit 180 by the relay transmission unit of the effect control unit 120. When the control command written in the first received data storage area of the sub-RAM 120c is written in the transmission data storage area of the sub-RAM 120c, the order in which these control areas are written and these storage areas are read out. Arrange in advance so that the order matches. This also applies to the case where the control command is relay-transmitted again from the subsequent control unit 180 to the effect control unit 120.

  In step S1500, the sub CPU 120a performs command analysis processing. In this process, the sub CPU 120a performs a process of analyzing the type of the control command stored in the second received data storage area of the sub RAM 120c.

  The control command transmitted from the main control unit 110 is relay-transmitted from the effect control unit 120 to the subsequent stage control unit 180 in step S1350. Then, as will be described later, the control command is relay-transmitted again from the post-stage control unit 180 to the effect control unit 120 in the same transmission order as that transmitted from the effect control unit 120 to the post-control unit 180.

When the second receiving unit of the production control unit 120 receives the control command transmitted from the subsequent control unit 180 and stores it in its own reception buffer, it indicates that there has been a control command reception interrupt request from the subsequent control unit 180. A control command reception interrupt process is generated.
Then, the sub CPU 120a performs an authentication result data analysis process for analyzing the contents of the authentication result data added to the received control command. When the sub CPU 120a confirms that the validity of the control command is authenticated by the post-stage control unit 180 in the authentication result data analysis process, the sub CPU 120a sends the control command from the reception buffer of the second reception unit to the second reception data of the sub RAM 120c. Capture to the storage area for storage. Then, the sub CPU 120a analyzes the type of the control command stored in the second received data storage area, and performs processing according to the type of the control command. Details of the command analysis process will be described later.

In step S <b> 1700, the sub CPU 120 a checks the signal of the effect button detection switch 35 a, and performs effect input control processing related to input from the effect button 35.
In step S1800, the sub CPU 120a performs an effect output control process that is a process for transmitting the control command and various data set in the transmission data storage area of the sub RAM 120c to the lamp control unit 140 and the image control unit 150. Do.
In step S1900, the sub CPU 120a restores the information saved in step S1200 to the register of the sub CPU 120a.

Next, command analysis processing of the effect control unit 120 will be described.
18 and 19 are flowcharts showing command analysis processing by the effect control unit 120 according to the present embodiment. Note that the command analysis process 2 in FIG. 19 is performed subsequent to the command analysis process 1 in FIG.

In step S1501, the sub CPU 120a checks whether or not a control command is stored in the reception buffer of the second reception unit that constitutes the effect control unit 120, and determines whether or not the control command has been received.
If the control command is not stored in the reception buffer of the second reception unit, the sub CPU 120a ends the command analysis process. If the control command is stored in the reception buffer of the second reception unit, the sub CPU 120a moves the process to step S1650.

  In step S1650, the sub CPU 120a performs an authentication result data analysis process on the authentication result data added to the control command stored in the reception buffer of the second reception unit. If the post-control unit 180 confirms that the validity of the control command has been authenticated, the sub CPU 120a takes the received control command into the second received data storage area and moves the process to step S1510. The details of the authentication result data analysis process will be described later.

In step S1510, the sub CPU 120a confirms whether or not the control command stored in the second reception data storage area is a demonstration designation command.
If the control command stored in the second received data storage area is a demo designation command, the sub CPU 120a moves the process to step S1511, and if not, moves the process to step S1520.

In step S1511, the sub CPU 120a performs a demonstration effect pattern determination process for determining a demonstration effect pattern.
Specifically, the demonstration effect pattern is determined, the determined demonstration effect pattern is set in the effect pattern storage area, and information on the determined demonstration effect pattern is transmitted to the image control unit 150 and the lamp control unit 140. An effect pattern designation command based on the demo effect pattern is set in the transmission data storage area of the sub-RAM 120c.

In step S1520, sub CPU 120a checks whether or not the control command stored in the second received data storage area is a special symbol storage designation command.
If the control command stored in the second received data storage area is a special symbol storage designation command, the sub CPU 120a moves the process to step S1521, and moves to step S1530 if it is not a special symbol storage designation command.

  In step S1521, the sub CPU 120a analyzes the special symbol storage designation command to determine the number of display images of special symbols to be displayed on the liquid crystal display device 31 (hereinafter referred to as “special diagram reserved images”). The special symbol display number designation command corresponding to the display number of the special figure reserved images is transmitted to the image control unit 150 and the lamp control unit 140, and a special symbol storage number determination process is performed.

In step S1530, the sub CPU 120a confirms whether or not the control command stored in the second received data storage area is an effect designating command.
If the control command stored in the second received data storage area is an effect designating command, the sub CPU 120a moves the process to step S1531, and moves to step S1540 if it is not an effect designating command.

In step S1531, the sub CPU 120a performs an effect symbol determination process for determining an effect symbol 36 to be stopped and displayed on the liquid crystal display device 31 based on the content of the received effect symbol designation command.
Specifically, the effect designating command is analyzed, the effect symbol data constituting the combination of the effect symbols 36 is determined according to the presence / absence of jackpot and the type of jackpot, and the determined effect symbol data is stored in the effect symbol storage area In addition, in order to transmit the effect symbol data to the image control unit 150 and the lamp control unit 140, a stop symbol designation command indicating the effect symbol data is set in the transmission data storage area of the sub RAM 120c.

  In step S1532, the sub CPU 120a acquires one random number value from the effect mode determination random value updated in step S1100, and based on the acquired effect mode determination random value and the received effect designating command, An effect mode determination process for determining one effect mode from a plurality of effect modes (for example, a normal effect mode and a chance effect mode) is performed. Further, the determined effect mode is set in the effect mode storage area.

In step S1540, the sub CPU 120a checks whether or not the control command stored in the second received data storage area is a variation pattern designation command.
If the control command stored in the second received data storage area is the variation pattern designation command, the sub CPU 120a moves the process to step S1541 and moves the process to step S1550 if it is not the variation pattern designation command.

In step S1541, the sub CPU 120a obtains one random number value from the effect random number value updated in step S1100, and is set in the obtained effect random number value, the received variation pattern designation command, and effect mode storage area. Based on the effect mode being performed, a variation effect pattern determination process for determining one variation effect pattern from a plurality of variation effect patterns is performed.
Specifically, in the normal effect mode, the variation effect pattern determination table is referred to, one change effect pattern is determined based on the acquired effect random number value, and the determined change effect pattern is stored in the effect pattern storage area. At the same time, in order to transmit the determined variation effect pattern information to the image control unit 150 and the lamp control unit 140, an effect pattern designation command based on the determined variation effect pattern is set in the transmission data storage area of the sub RAM 120c.
Thereafter, based on the effect pattern, the liquid crystal display device 31, the audio output device 32, the effect drive device 33, and the effect illumination device 34 are controlled. Note that the variation mode of the effect symbol 36 is determined based on the variation effect pattern determined here.

In step S1550, the sub CPU 120a checks whether or not the control command stored in the second received data storage area is a symbol determination command.
If the control command stored in the second received data storage area is the symbol confirmation command, the sub CPU 120a moves the process to step S1551, and moves to step S1560 if it is not the symbol confirmation command.

  In step S1551, the sub CPU 120a performs an effect symbol stop display process for setting a stop designation command for stopping the effect symbol in the transmission data storage area of the sub RAM 120c in order to stop the effect symbol 36.

In step S1560, the sub CPU 120a determines whether or not the control command stored in the second reception data storage area is a gaming state designation command.
If the control command stored in the second received data storage area is a gaming state designation command, the sub CPU 120a moves the process to step S1561, and if not the gaming command, the sub CPU 120a moves the process to step S1570.

  In step S1561, the sub CPU 120a sets data indicating the gaming state based on the received gaming state designation command in the gaming state storage area in the sub RAM 120c.

In step S1570, the sub CPU 120a checks whether or not the control command stored in the second received data storage area is an opening designation command.
If the control command stored in the second received data storage area is an opening designation command, the sub CPU 120a moves the process to step S1571, and moves to step S1580 if it is not the opening designation command.

In step S1571, the sub CPU 120a performs a hit start effect pattern determination process for determining a hit start effect pattern.
Specifically, the hit start effect pattern is determined based on the opening designation command, the determined hit start effect pattern is set in the effect pattern storage area, and information on the determined hit start effect pattern is transmitted to the image controller 150 and the lamp. In order to transmit to the control unit 140, an effect pattern designation command based on the determined hit start effect pattern is set in the transmission data storage area of the sub RAM 120c.

In step S1580, the sub CPU 120a checks whether or not the control command stored in the second received data storage area is a special winning opening opening designation command.
If the control command stored in the second received data storage area is a big winning opening release designation command, the sub CPU 120a moves the process to step S1581, and if not, moves the processing to step S1590. .

In step S1581, the sub CPU 120a performs a jackpot effect pattern determination process for determining a jackpot effect pattern.
Specifically, the jackpot effect pattern is determined based on the big prize opening opening designation command, the determined jackpot effect pattern is set in the effect pattern storage area, and information on the determined jackpot effect pattern is transmitted to the image controller 150 and the lamp. In order to transmit to the control unit 140, an effect pattern designation command based on the determined jackpot effect pattern is set in the transmission data storage area of the sub RAM 120c.

In step S1590, the sub CPU 120a checks whether or not the control command stored in the second received data storage area is an ending designation command.
If the control command stored in the second received data storage area is an ending designation command, the sub CPU 120a moves the process to step S1591, and ends the command analysis process if it is not an ending designation command.

In step S1591, the sub CPU 120a performs a hit end effect pattern determination process for determining a hit end effect pattern.
Specifically, the winning end effect pattern is determined based on the ending designation command, the determined hit end effect pattern is set in the effect pattern storage area, and information on the determined hit end effect pattern is stored in the image control unit 150 and the lamp. In order to transmit to the control unit 140, an effect pattern designation command based on the determined winning end effect pattern is set in the transmission data storage area of the sub RAM 120c. When this process ends, the command analysis process ends.

Next, the authentication result data analysis process of the production control unit 120 will be described.
FIG. 20 is a flowchart showing authentication result data analysis processing by the effect control unit 120 according to the present embodiment.

In step S1651, the sub CPU 120a determines whether or not authentication result data is added to the control command stored in the reception buffer of the second reception unit constituting the effect control unit 120. If the authentication result data is added, the sub CPU 120a moves the process to step S1652, and if the authentication result data is not added to the control command, the sub CPU 120a ends the authentication result data analysis process.
In step S1652, the sub CPU 120a extracts authentication result data from the control command stored in the reception buffer of the second reception unit, and the process proceeds to step S1653.

In step S1653, the sub CPU 120a determines whether or not the extracted authentication result data indicates that the inspection result of the error inspection process performed by the post-control unit 180 is normal and the main control unit 110 can be authenticated. Determine. Then, the sub CPU 120a determines that the gaming machine 1 is operating normally when the authentication result data is a result indicating a successful authentication. Then, the sub CPU 120a outputs the received control command to the second received data storage area of the sub RAM 120c, and ends the authentication result data analysis process so as to perform processing according to the control command. On the other hand, if the authentication result data is a result indicating that the authentication is unsuccessful, the sub CPU 120a determines that there is a possibility that an illegal act or the like has occurred in the gaming machine 1, and moves the process to step S1654.
In step S1654, when the sub CPU 120a determines that there is a possibility that an illegal act or the like has occurred in the gaming machine 1, the sub CPU 120a outputs a notification signal to notify that fact, and ends the authentication result data analysis processing.

  The sub CPU 120a transmits the generated notification signal to, for example, the lamp control unit 140, the image control unit 150, or a hall computer that manages the gaming machine 1. Based on the received notification signal, the lamp control unit 140, the image control unit 150, and the like perform an effect that notifies that there is a possibility that an illegal act has occurred in the gaming machine 1. This effect is, for example, causing a character that does not normally appear on the liquid crystal display device 31 to appear, or causing a character that normally appears to appear by a method different from normal. In addition, the brightness of the liquid crystal display device 31 may be changed, the color may be changed, or the lamp controller 140 may be controlled to display a predetermined lamp. In any case, when the employee of the game shop passes in front of the gaming machine 1, it is only necessary to notice the state. This effect may be an effect that the customer does not notice the state or an effect that the customer can easily notice. If the production is easily noticed by the customer, fraud can be efficiently suppressed.

  Moreover, you may include the information regarding the gaming state or jackpot type of the gaming machine 1 in the notification signal. Based on these pieces of information, it may be determined whether a fraudulent act is being performed by a hall computer or the like that manages the gaming machine 1. For example, the “high probability gaming state” may be normal even if prize balls are concentrated. Therefore, during the high-probability gaming state, it is preferable to determine whether or not there is a risk of cheating under different conditions from the other states. Moreover, you may make it output the information regarding a gaming state or jackpot type as a separate signal without including it in a notification signal. In this case, the employee determines whether or not there is a risk of fraud based on both the notification signal and the information regarding the gaming state and the jackpot type.

[Control processing of rear-stage control unit]
FIG. 21 is a flowchart showing main processing by the post-stage control unit 180 according to the present embodiment. In each step of FIG. 21, the notation in curly braces {} refers to the received number storage area (P), the change timing information storage area (Mi), and the retroactive number storage area (N) provided in the RAM 180c. This is to outline the process.

  In step S4010, the CPU 180a performs initialization processing. In this process, the CPU 180a reads a program code related to the main process from the ROM 180b in response to power-on. Along with this, the CPU 180a performs processing for initializing flags and the like stored in the RAM 180c and setting the set values. In step S4010, processing for setting an error check value output function corresponding to the error check value addition function of the main control unit 110 to the check value generation unit 620 is performed. If this process ends, the process moves to a step S4020.

In step S4020, CPU 180a determines whether or not a control command transmitted from main control unit 110 via effect control unit 120 has been received.
When the receiving unit 600 of the post-stage control unit 180 receives the control command transmitted from the effect control unit 120 and stores it in its own reception buffer, it indicates that there has been a control command reception interrupt request from the effect control unit 120. A signal is output to generate a control command reception interrupt process.
In step S4020, the CPU 180a waits until the reception interrupt request signal from the reception unit 600 is input. When the signal from the reception unit 600 is input, the CPU 180a stores the control command stored in the reception buffer. Error check processing is performed on Specifically, it is the process of the next step S4030 to step S4190.

In step S4030, when a signal indicating that a control command reception interrupt request has been made is output from the reception unit 600, the CPU 180a updates the reception number storage area (P) of the RAM 180c by adding 1.
In step S4040, the CPU 180a determines whether or not the control command (P) stored in the reception buffer of the reception unit 600 corresponds to the control command (1). Specifically, the CPU 180a refers to the value of the received number storage area (P) and determines whether P = 1. If P = 1, the process proceeds to step S4050, and if P = 1, the process proceeds to step S4070.

In step S4050, the CPU 180a reads unique information stored in the ROM 180b. At this time, if there are N pieces of unique information, N pieces of unique information are read at a time. Then, the CPU 180a outputs the read unique information to the inspection value generation unit 620.
In step S4060, the CPU 180a stores the unique information output to the inspection value generation unit 620 in the storage unit 622 in the inspection value generation unit 620 and sets it as an initial inspection value.

In step S4070, the CPU 180a extracts the error check value (PN) added to the control command (P) from the control command (P) stored in the reception buffer of the reception unit 600.
In step S4080, the CPU 180a outputs the extracted error check value (PN) to the check unit 610, and outputs the control command (P) after extracting the error check value (PN) to the check value generation unit 620. The data is output to the generation unit 621, the determination unit 623, and the addition unit 630.

In step S4090, the CPU 180a determines in the determination unit 623 whether or not the control command (P) is a control command that satisfies a predetermined change condition. Specifically, the CPU 180a determines whether or not the type of the control command (P) is a predetermined type of control command.
In step S4100, if the control command (P) is a predetermined control command, the CPU 180a determines that the extracted control command (P) is a control command that satisfies the change condition, and moves the process to step S4110. On the other hand, if the control command (P) is not a predetermined control command, the CPU 180a determines that the extracted control command (P) is not a control command that satisfies the change condition, and moves the process to step S4120.

If CPU 180a determines in step S4110 that a control command satisfying the change condition has been received, CPU 180a determines the timing for changing the retroactive number, that is, the timing for changing the value of N stored in the retroactive number storage area (N). Set at 623. Specifically, the CPU 180a adds the predetermined value of Mo to the value of the current generated number storage area (P) to the change timing information storage area (Mi) in order to set the change timing information Mi. The obtained value (P + Mo) is stored.
In step S4120, the CPU 180a determines in the determination unit 623 whether or not the present time is the timing for changing the retroactive number. Specifically, the CPU 180a compares the minimum value Mmin of the change timing information storage area (Mi) with the value of the current reception number storage area (P). If they match, the CPU 180a determines that the current timing is the change timing, and moves to step S4130. If they do not match, the CPU 180a determines that the current timing is not the current timing, and proceeds to step S4140. Move processing.

  In step S4130, the CPU 180a changes the value of N stored in the retroactive number storage area (N) in the determination unit 623 to change the retroactive number. Specifically, the CPU 180a changes the value of N according to a predetermined change method, and stores N ′, which is the changed value of N, in the retroactive number storage area (N). Then, the CPU 180a notifies the storage unit 622 of the error check value based on the value of the retroactive number storage area (N) after the change so that the error check value is output from the storage unit 622 to the check unit 610.

In step S4140, the CPU 180a causes the generation unit 621 to generate the error check value (P) of the control command (P) output from the reception unit 600 using a generation method previously determined with the main control unit 110. Generate.
In step S4150, the CPU 180a stores the generated error check value (P) in the storage unit 622, and among the error check values stored in the past, the error check value notified from the determination unit 623 (P−). N) is output to the inspection unit 610.

  In step S4160, the CPU 180a compares the error check value (PN) output from the receiving unit 600 with the error check value (PN) output from the storage unit 622 and compares them. To do. The CPU 180a determines that the inspection result of the error check is normal when both match with the error check value (PN). On the other hand, if the two do not match, the CPU 180a determines that the inspection result is not normal.

  In step S4170, CPU 180a determines whether or not the inspection result is normal in inspection unit 610. When it is determined that the inspection result is normal, the CPU 180a generates the control command (P) to which the currently received error check value (PN) is added and the current error check value (PN). Since the validity of the original N previous control commands (PN) has been authenticated, it is determined that the validity of the main control unit 110 has been authenticated, and the process proceeds to step S4180. On the other hand, if it is determined that the inspection result is not normal, the CPU 180a determines that the validity of the main control unit 110 could not be authenticated, and moves the process to step S4190.

In step S4180, the CPU 180a generates authentication result data indicating successful authentication in the inspection unit 610, outputs the generated authentication result data to the adding unit 630, and shifts the processing to step S4200.
In step S4190, the CPU 180a generates authentication result data indicating unsuccessful authentication in the inspection unit 610, outputs the generated authentication result data to the adding unit 630, and shifts the processing to step S4200.

In step S4200, the CPU 180a adds the authentication result data output from the inspection unit 610 to the control command (P) output from the receiving unit 600, and adds a control command with authentication result data. (P) is output to the relay transmission unit 640, and the process proceeds to step S4210.
In step S4210, CPU 180a immediately transmits control command (P) with authentication result data as transmission data to effect control unit 120 at relay transmission unit 640. Thereafter, the processes after step S4020 are repeated until a predetermined interrupt process is performed.

  The authentication process in the case where the rear stage control unit 180 is provided subsequent to the other control units of the peripheral control unit 300 is the same as the authentication process in the case where the rear stage control unit 180 is provided subsequent to the effect control unit 120. Since the procedure is almost the same, the description is omitted.

  As described above, in the present embodiment, as a security function, the validity of the main control unit 110 is authenticated by checking the validity of the control command output from the main control unit 110. The main control unit 110 generates and stores an error check value for the control command. The main control unit 110 adds the error check value of the control command generated before (past) to the control command to be transmitted this time, and transmits the control command to the subsequent control unit 180 via the effect control unit 120. On the other hand, the post-stage control unit 180 generates and stores an error check value for the received control command. Then, the post-stage control unit 180 performs error checking by comparing the error check value added to the control command received this time with the error check value of the control command generated before (past) the control command received this time. .

  Normally, an error check value such as a checksum is added to the control command of the generation source and used for a communication error check. In contrast, in the present embodiment, as described above, the error check value of the control command generated in the past is added to the control command to be transmitted this time. By using such a new and simple method that has not been used in the past, even if an unauthorized person steals a control command and an error check value, the relationship between the control command and the error check value cannot be easily known. it can. Therefore, according to this embodiment, fraud can be prevented and the security strength of the gaming machine 1 can be improved.

  In addition, the error check value of the control command generated in the past by the main control unit 110 is added to the control command to be transmitted this time and transmitted, and the subsequent control unit 180 performs the error check process of the control command to receive this time In addition to authenticating the validity of the control command, it is also possible to authenticate the validity of the control command generated in the past, that is, the control command from which the error check value added this time is generated. That is, it is possible to authenticate the continuity of the control command, and it becomes easier to detect fraud, and the security strength of the gaming machine 1 can be improved.

  In the present embodiment, the error check value is set to a value unique to the gaming machine 1 by adding unique information unique to the gaming machine 1 to the control command transmitted when P ≦ N. Can do. As a result, even if an unauthorized person who does not know the specific information steals a part of the control command, the error check value cannot be analyzed, and the security strength of the gaming machine 1 can be further improved.

  In this embodiment, an error check value that is normally used for communication error check is used as a check value for detecting fraud. In this way, by using an error check value conventionally used for communication error check, it is possible to detect fraud without separately providing test value generation means for detecting fraud. Can be improved. That is, in a situation where the resources of the main control unit of the gaming machine are limited, an increase in processing load on the main control unit 110 can be suppressed while improving the security strength.

  In the present embodiment, the test value generation unit 500 added as a specific aspect of the security function added to the main control unit 110 is configured with a wired logic control type hardware, and includes the main CPU 110a, the transmission unit 550, and the like. It is provided between. At this time, the input / output control method between the inspection value generation unit 500 and the main CPU 110a and the input / output control method between the inspection value generation unit 500 and the transmission unit 550 are each a CPU interface method. The input / output control method between each means and each circuit in the test value generation unit 500 is a synchronous interface method. Therefore, in this embodiment, the test value generation unit 500 that does not increase the processing load and code size of the main CPU 110a is added while maintaining the input / output control method between the main CPU and the transmission unit of the existing gaming machine. Can do. Therefore, according to the present embodiment, while the gaming machine 1 has the security function, the processing load and code size of the CPU of the main control unit 110, which increase by having the security function, can be suppressed to the maximum. At the same time, according to the present embodiment, a security function having such a feature can be added to an existing gaming machine relatively easily.

  Further, in the present embodiment, a plurality of error check value addition functions are prepared in advance by the check value generation unit 500 having a plurality of retroactive numbers. Based on which retroactive number the error check value is added to, the value of the HW parameter stored in a specific storage area of the main ROM 110b that is not accessed except when the initial value is set during the boot process of the main control unit 110 Is determined on the basis of Therefore, even if an unauthorized person steals transmission data between the main control unit 110 and the production control unit 120 and transmission data between the production control unit 120 and the subsequent control unit 180, what the error check value is? It is difficult to analyze whether or not an error check value is added based on the number of retroactive items. Therefore, the confidentiality of the error check value addition function of the gaming machine 1 can be ensured, and the security strength of the gaming machine 1 can be improved.

  In the present embodiment, the error check value addition function is changed by changing the retroactive number provided in the check value generation unit 500 based on the control command to be transmitted even during the game process after the boot process. Therefore, even if an unauthorized person steals a plurality of control commands and error check values, it becomes more difficult to analyze the correspondence between the control commands and error check values. Therefore, the confidentiality of the error check value adding function of the gaming machine 1 can be further improved, and the security strength of the gaming machine 1 can be further improved.

In the present embodiment, whether the type of the control command to be transmitted corresponds to the type of the predetermined control command as a condition for the check value generation unit 500 to change the retroactive number, that is, a condition for changing the error check value addition function. The condition was whether or not.
Here, when the predetermined control command is a jackpot command, the jackpot command has randomness in the generation timing and is continuously transmitted in each round of jackpot. Therefore, in the inspection value generation unit 500, the retroactive number is changed a plurality of times during a certain period in the big hit state. Therefore, even if an unauthorized person steals a control command and an error check value and diverts them, it is possible to detect fraud more easily.

  In addition, when the predetermined control command is a reach command, the reach command has randomness in generation timing and is generated more frequently than the jackpot command. Therefore, in the inspection value generation unit 500, the retrospective number change timing on the time axis is distributed. Therefore, even if an unauthorized person steals multiple control commands and error check values, it becomes more difficult to analyze the change in the correspondence between the control commands and error check values, and the confidentiality of the error check value addition function is further improved. Can be made.

  In addition, when the predetermined control command is an opening designation command or an ending designation command, the opening designation command or the ending designation command is a control command transmitted at the start or end of the jackpot state, and the occurrence timing is random. And has a low frequency of occurrence. Therefore, in the inspection value generation unit 500, the retroactive number change timing also occurs randomly and with a low frequency. Therefore, it becomes more difficult for an unauthorized person to specify the change timing of the retroactive number, and the secrecy of the error check value addition function can be further improved. Further, when the predetermined control commands are both the opening designation command and the ending designation command, the inspection value generation unit 500 changes the retroactive number a plurality of times during a certain period before and after the jackpot state. Therefore, even when an unauthorized person steals a control command and an error check value and diverts them, it is possible to further detect fraud.

  In addition, when the predetermined control command is a demonstration designation command, the demonstration designation command is a control command that is transmitted to display a demonstration display when a state in which there is no special symbol hold number storage continues for a predetermined period of time, Has randomness in generation timing. Therefore, in the inspection value generation unit 500, the retrospective number change timing on the time axis is distributed. Therefore, even if an unauthorized person steals multiple control commands and error check values, it becomes more difficult to analyze the change in the correspondence between the control commands and error check values, and the confidentiality of the error check value addition function is further improved. Can be made.

  In addition, when the predetermined control command is a lose command (lost design symbol designating command), “lost” is most frequently generated as a lottery result at the time of the lottery, and thus the frequency of the lost command being transmitted is high. Therefore, the inspection value generation unit 500 also increases the frequency of the retroactive number change timing. In other words, in the check value generation unit 500, the retroactive number is changed frequently, the correspondence between the control command and the error check value itself is complicated and it becomes more difficult to analyze, and the secrecy of the error check value addition function is further improved. Can be made.

  Further, in the present embodiment, the timing for changing the retroactive number of error check values is the output timing of the control command output after Mo from the output timing of the control command to be determined whether to change the retroactive number. Yes. That is, in this embodiment, the timing when the retroactive number change condition is satisfied and the actual change timing are distributed. Therefore, even if an unauthorized person steals a plurality of control commands and error check values, it becomes more difficult to analyze the correspondence between the control commands and error check values. Therefore, the confidentiality of the error check value adding function of the gaming machine 1 can be further improved, and the security strength of the gaming machine 1 can be further improved.

  In this embodiment, a plurality of types of error check value addition functions and HW parameters as selection information thereof are prepared in advance, but only specific HW parameters are implemented. Therefore, it is not necessary to newly provide a program associated with the HW parameter selection process in the boot process, and the code size of the program is not increased. Even if a gaming machine manufacturer wants to adopt only a specific error check value addition function, only the HW parameter corresponding to the desired error check value addition function needs to be implemented. Can respond flexibly. Therefore, even diverse security functions can be added relatively easily, and a highly versatile security function can be provided. In addition, by changing the HW parameters used for design / verification work during the development stage of the gaming machine 1 and the HW parameters that are actually mounted before the gaming machine 1 is shipped, which HW parameters are finally adopted. It is possible to limit the number of persons who can know whether this has been done, and to further improve the confidentiality of the error check value addition function.

  In the present embodiment, the authentication function for the main control unit 110 is provided in the rear control unit 180 that is independent from the peripheral control unit 300 that performs processing related to normal game progression. Therefore, for example, when the rear stage control unit 180 is provided subsequent to the production control unit 120, the production control unit 120 executes the authentication process only when authentication result data is received from the rear stage control unit 180. It is. That is, the processing load of the CPU of the effect control unit 120 increases only when the authentication result data is received by performing the authentication process, and thus the rate of increase in the processing load of the effect control unit 120 can be suppressed. it can. Further, it is only necessary to add a program code related to the authentication result data analysis process to the program executed by the effect control unit 120. Therefore, since it is not necessary to perform new timing design over the entire program executed by the effect control unit 120, the mounting and verification work when adding the authentication function can be performed more easily and with less work man-hours.

  Further, in the present embodiment, since the post-stage control unit 180 is provided subsequent to the effect control unit 120, processing between the main CPU 110a configuring the main control unit 110 and the sub CPU 120a configuring the effect control unit 120 is performed. Differences in capacity and differences in storage capacity between the main ROM 110b and main RAM 110c constituting the main control unit 110 and the sub ROM 120b and sub RAM 120c constituting the effect control unit 120 can be absorbed by the subsequent control unit 180. . Thereby, even when there is a difference in processing capacity and storage capacity between the main control unit 110 and the effect control unit 120, the security strength between the main control unit 110 and the effect control unit 120 can be maintained. This also applies to the case where the rear stage control unit 180 is provided following another control unit of the peripheral control unit 300.

  In this embodiment, the data buffer 511 of the buffer unit 510 and the generation circuit 521 of the generation unit 520 are connected, and the storage circuit 522 is provided on the output side of the generation circuit 521. Therefore, the object to be stored in the storage circuit 522 is the error check value generated by the generation circuit 521. However, the present invention is not limited to this, and the object stored in the storage circuit 522 may be a control command. Specifically, as illustrated in FIG. 22, the storage circuit 522 is provided on the input side of the generation circuit 521, and the input selection circuit 524 is provided between the storage circuit 522 and the generation circuit 521. Similarly to FIG. 5, the input selection circuit 524 receives a connection switching signal that validates only the connection with the specific storage circuit (storage circuit N in FIG. 22) output from the determination circuit 542.

  With this configuration, only the control command stored in the connection source storage circuit (storage circuit N in FIG. 22) that has been validated by the connection switching signal is input to the generation circuit 521. In the latter stage control unit 180, the object stored in the storage unit 622 may be an error check value or a control command. In addition, the storage target in the main control unit 110 and the storage target in the subsequent control unit 180 may be different.

  In the present embodiment, the HW parameter is defined as selection information for determining the default retroactive number, but the present invention is not limited to this. For example, as shown in FIG. 23, the HW parameter can be used as selection information for determining a default change condition. At this time, in the determination circuit 542, a plurality of change conditions corresponding to the HW parameters are prepared in advance, and a default value of the retroactive number is prepared. Then, the determination circuit 542 may set the change condition corresponding to the HW parameter set by the main CPU 110a in the change condition storage unit 541a of the determination circuit 541 in the HW parameter setting process during the boot process.

  When the control command output from the buffer means 510 satisfies the change condition, the comparator 541b constituting the determination circuit 541 outputs a determination result signal indicating that the control command is a control command satisfying the change condition. , It does not have to be output every time. That is, even if the control command output from the buffer means 510 is a control command that satisfies the change condition, the comparator 541b does not change the retroactive number in the decision circuit 542, and the unauthorized person sets the retroactive number changing condition. It becomes more difficult to analyze. Further, the comparator 541b may not output the determination result signal itself every time the control command output from the buffer unit 510 is input. In this case, the control circuit 512 of the buffer means 510 and the determination circuit 542 are connected by a control line, and an operation permission signal is output from the control circuit 512 to the determination circuit 542. The determination circuit 542 may update the value of the generated number storage area (P) based on the input of the operation permission signal and perform the retroactive number setting process.

  The HW parameter can be defined as selection information for determining a change method and a change timing setting method. For example, when the change method is determined by the HW parameter, the determination circuit 542 prepares a plurality of change methods for defining a predetermined change order of the retroactive number and associates it with the HW parameter. Then, the determination circuit 542 may set a change method corresponding to the HW parameter set from the main CPU 110a in the HW parameter setting process during the boot process, and change the retroactive number according to the set change method.

  Further, the HW parameter is not limited to being defined as selection information for determining only one component of the change protocol, such as determining only the default retroactive number. For example, the HW parameter can be defined as selection information for determining both the default retroactive number and the default change condition. In other words, in the present invention, the HW parameter is not limited to the selection information for determining the retroactive number used in the generation unit 520, but the change protocol related to the retroactive number such as the change condition, the change timing setting method, and the change method. It can be defined as selection information for determination. That is, the HW parameter is selection information for the error check value addition function in which the retroactive number and its change protocol are implemented.

  As described above, in the present invention, the error check value addition function is based on the value of the HW parameter stored in the specific storage area of the main ROM 110b that is not accessed except when the initial value is set during the boot process of the main control unit 110. Determined. Therefore, even if an unauthorized person steals transmission data between the main control unit 110 and the production control unit 120 and transmission data between the production control unit 120 and the post-stage control unit 180, how the game machine 1 is handled. It is difficult to analyze whether the error check value addition function is installed, the secrecy of the error check value addition function is further improved, and the security strength of the gaming machine 1 can be further improved.

  Further, in the present embodiment, when P ≦ N, the main control unit 110 adds an initial inspection value to the control command (P) and transmits the control command (P), and the subsequent control unit 180 transmits a corresponding initial inspection value. However, the present invention is not limited to this, and the post-stage control unit 180 does not perform error check processing when P ≦ N, and does not perform error check until P> N. Processing may be performed.

  In the present embodiment, the latter control unit 180 is the determination unit 623 having the same function as the function of changing the retroactive number of the main control unit 110, but the present invention is not limited to this. That is, in the present invention, the post-stage control unit 180 outputs only the error check value based on the specific retroactive number determined by the determination unit 623 based on the received control command to the check unit 610 to perform error check processing. It is not limited to that. For example, the post-stage control unit 180 may perform error check processing by checking the error check value added to the received control command with all the error check values stored in the storage unit 622. In this case, if the subsequent control unit 180 matches one of the error check values in the storage unit 622, the check result is normal and the correctness of the received control command and the correctness of the main control unit 110 are authenticated. That's fine.

  In the present embodiment, the initial inspection value used in the case of P ≦ N is the unique information stored in advance in the main ROM 110b, but the present invention is not limited to this. For example, the main control unit 110 is provided with time measuring means, or using the time measuring means provided in the main control unit 110 in advance, the elapsed time from the power-on to the transmission timing of the control command is acquired as time-lapse information and acquired. Time information may be used as an initial inspection value. Since the value of the acquired time-lapse information is a fluctuation value having randomness, it is difficult to reuse the initial inspection value generated by using this, and the security strength of the gaming machine 1 is further improved. Can do. At this time, the post-stage control unit 180 may not perform the error check process when P ≦ N as described above.

  At this time, if N ≧ 2 is determined in advance, the subsequent control unit 180 determines whether or not the temporal information transmitted continuously as the initial inspection value has continuity in time series, that is, continuously. The error check process may be performed by confirming whether or not the value of the time-dependent information transmitted in this way increases according to the transmission order. The time information may be an absolute time acquired by using a time measuring means as a real time clock circuit or the like, or may be a relative time counted from the reset time. In any case, the time-lapse information changes to various values as the timing of acquisition is irregular, so that it can be regarded as information inherent to the gaming machine 1 substantially. Further, when N ≧ 2, the time information may be obtained from the time measuring means for each control command transmission timing, or a plurality of time information acquired at the transmission timing of the first generated control command may be used. It may be used as an initial check value for a control command. In addition, for example, the initial inspection value added to the control command generated first uses the identification number (ID) of the main CPU 110a which is a fixed value, and the subsequent initial inspection value uses time-lapse information which is a variation value. It is also possible to combine fixed values and variable values.

  In addition, as an initial check value used when P ≦ N, for example, an HW parameter that is selection information of an error check value addition function of the main control unit 110 may be used. That is, the determination unit 540 constituting the inspection value generation unit 500 of the main control unit 110 stores the HW parameter set in its determination circuit 542 during the boot process even after the HW parameter setting process. Then, the determination circuit 542 determines whether it is necessary to set unique information in the storage circuit 522. If the value of the generated number storage area (P) is P = 1, the determination circuit 542 first outputs the control command output from the buffer means 510 after the error check value stored in the storage circuit 522 is cleared. It is determined that the control command is generated by the main CPU 110a. In this case, the determination circuit 542 may notify the buffer unit 510 to request that the specific information be output and set the HW parameter stored in the storage circuit 522 to be used as the initial inspection value. .

  The content and mounting method of the HW parameter can be determined by the game machine manufacturer's own judgment, so that the HW parameter is highly confidential and can be regarded as information inherent to the gaming machine 1 substantially. Note that the post-stage control unit 180 may not perform the error check process when P ≦ N as described above. By doing so, the post-control unit 180 is set by the main control unit 110 even if the selection information of the error check value addition function corresponding to the HW parameter is not negotiated with the main control unit 110 in advance. An error check value output function corresponding to the error check value addition function can be selected. Therefore, even if an unauthorized person analyzes the post-control unit 180 itself, it is specified whether the error check process is performed using the error check value output by any of the plurality of error check value output functions. Therefore, the confidentiality of the output function can be ensured, and the security strength of the gaming machine 1 can be further improved.

  Further, in the present embodiment, the input / output control method between each means or each circuit in the test value generation unit 500 is a synchronous interface method. Then, data transmission / reception between each means and each circuit in the inspection value generation unit 500 is performed in synchronization with the clock signal output from the clock pulse generation circuit of the main control unit 110. However, the present invention is not limited to this, and data transmission / reception between each means and each circuit in the test value generation unit 500 may be performed asynchronously with respect to the clock signal. Even in this case, in the test value generation unit 500, if an enable signal or the like is output to the connection destination of the data to be output, the connection destination captures the output data based on the input of the enable signal or the like. This is different from the CPU interface method.

  In this embodiment, the timing for writing the error check value to the transmission buffer 551 of the transmission unit 550 is controlled by adjusting the output timing of the connection switching signal output from the control circuit 532 of the adding unit 530. However, the present invention is not limited to this, and the control circuit 512 of the buffer means 510 can be controlled by adjusting the output timing of the operation permission signal output to the control circuit 532. In addition, the control circuit 523 of the generation unit 520 can also perform control by adjusting the output timing of the operation permission signal output to the generation circuit 521. This is because the output timing of the connection switching signal output from the control circuit 532 is based on the input of the operation permission signal output from the control circuit 512. This is because the timing at which the error check value is input to the input selection circuit 531 to which the connection switching signal is input is based on the input of the operation permission signal output from the control circuit 523.

  Note that the output timing of the operation permission signal output from the control circuit 523 is also based on the input of the operation permission signal output from the control circuit 512, and the output timing of the operation permission signal output from the control circuit 512 is the main timing. This is based on the input of a write signal to the buffer means 510 output by the CPU 110a. The write signal output from the main CPU 110a is specified in advance by the execution timing of the command transmission process originally defined in the existing game processing program.

  As described above, in the present invention, the timing at which the test value generation unit 500 writes the error test value to the transmission unit 550 is uniquely determined based on the execution timing of the command transmission process defined by the existing game processing program. Well, timing design is relatively easy. Therefore, according to the present invention, a security function can be added to an existing gaming machine relatively easily, and a relatively large margin can be secured in the design of the write timing of the error check value. It is easy to ensure the accuracy of processing.

  In the present embodiment, the effect control unit 120 relays the control command transmitted from the main control unit 110 to the subsequent control unit 180, and analyzes the command for the control command relayed again from the subsequent control unit 180. Although processing is performed and processing according to the control command is performed, the present invention is not limited to this. For example, the effect control unit 120 performs command analysis processing on the control command transmitted from the main control unit 110 and relays the control command to the subsequent control unit 180 while performing processing according to the control command. Also good. The post-stage control unit 180 performs error check processing on the received control command to generate authentication result data, adds it to the received control command, and transmits it to the production control unit 120. At this time, the production control unit 120 The control command transmitted from the post-stage control unit 180 may be discarded after extracting the authentication result data. By configuring in this way, the production control unit 120 considers that at least the gaming machine 1 has not detected an illegal act or the like until the authentication result data is transmitted from the post-stage control unit 180, and the main control unit 110 A normal game process is executed based on the transmitted control command, and even if an unexpected situation such as a failure occurs in the subsequent control unit 180, the game process is not directly affected.

  In the present embodiment, the post-control unit 180 adds the authentication result data to the control command and transmits the result to the effect control unit 120 as a control command with authentication result data. However, the present invention is not limited to this. The control command and the authentication result data may be transmitted separately. In this case, the effect control unit 120 may determine whether or not the authentication result data has been received, and perform authentication result data analysis processing when the authentication result data is received. Note that dummy data may be added to each of the control command and the authentication result data so that the data length is the same. By doing so, it becomes difficult for an unauthorized person to distinguish between the control command and the authentication result data, and the security strength of the gaming machine 1 can be improved.

  In the present embodiment, the latter control unit 180 generates the authentication result data and transmits it to the effect control unit 120 regardless of whether the authentication is successful or unsuccessful. However, the present invention is not limited to this. For example, the post-stage control unit 180 may generate authentication result data only when authentication is unsuccessful, or may output a signal indicating unsuccessful authentication and transmit it to the effect control unit 120. The effect control unit 120 may determine whether or not a signal indicating authentication result data or authentication failure has been received and output a notification signal when received.

  In this embodiment, the inspection value generation unit 500 has a circuit configuration separate from the one-chip microcomputer 110m. However, the present invention is not limited to this, and the inspection value generation unit 500 is a circuit integrated with the one-chip microcomputer 110m. It is good also as a structure, and it is good also as a circuit structure integrated with the transmission part 550. Furthermore, in the present invention, all of the inspection value generation unit 500, the one-chip microcomputer 110m, and the transmission unit 550 may be integrated into a circuit configuration.

In the present embodiment, the rear stage control unit 180 is configured to include a CPU, a ROM, a RAM, and the like. However, the same function may be configured to be realized as an integrated circuit such as an LSI.
Moreover, in this embodiment, although the example which applies this invention to a pachinko game machine was shown, it is not limited to this, This invention is a ball game machine other than pachinko game machines, such as a sparrow ball game machine and an arrangement ball. It can also be applied to other gaming machines such as slot machines such as slot machines. Even in these gaming machines, the same effects as in the present embodiment can be obtained by configuring in the same manner as in the present embodiment. Moreover, this embodiment can divert each other's technology as long as there is no particular contradiction or problem in its purpose and configuration.

1 gaming machine 110 main control unit 110a main CPU
110b Main ROM
110c Main RAM
110d Boot ROM
110m One-chip microcomputer 120 Production control unit 120a Sub CPU
120b Sub ROM
120c sub RAM
180 Rear stage control unit 180a CPU
180b ROM
180c RAM
300 Peripheral Control Unit 500 Test Value Generation Unit 510 Buffer Unit 520 Generation Unit 521 Generation Circuit 522 Storage Circuit 530 Addition Unit 540 Determination Unit 541 Determination Circuit 542 Determination Circuit 550 Transmission Unit 600 Reception Unit 610 Inspection Unit 620 Test Value Generation Unit 621 Generation Unit 622 storage unit 623 determination unit 630 addition unit 640 relay transmission unit

Claims (8)

A gaming machine including a main control unit that outputs a control command, a peripheral control unit that performs processing based on the control command, and a rear-stage control unit that is provided subsequent to the peripheral control unit,
The main control unit,
In accordance with a predetermined control program stored in the storage unit, an operation according to predetermined game information is performed to generate the control command and output a first transmission instruction for transmitting the control command, and the generated control command An arithmetic processing unit that outputs a predetermined output control method,
An error check value that is provided subsequent to the arithmetic processing unit and is added to the control command output by the arithmetic processing unit based on the first transmission instruction to inspect the validity of the control command. A first transmission instruction for generating and transmitting the control command to which the error check value is added is output, and the control command to which the error check value is added is output by the predetermined output control method . An inspection value generation unit;
Provided so as to follow the first check value generation unit, based on the second transmission instruction, the control commands that the error check value is added via the peripheral controller to the subsequent stage controller A first transmitter for transmitting;
With
The latter stage control unit
A second check value generator for generating an error check value for verification corresponding to the error check value generated by the first check value generator;
The error check value transmitted by the first transmitter is compared with the error check value generated by the second check value generator to check the validity of the control command transmitted by the first transmitter. An inspection unit for generating the result information of the inspection;
A second transmission unit for transmitting the result information to the peripheral control unit;
With
The peripheral control unit
A processing unit that performs processing based on the control command output from the main control unit and performs processing according to the result information transmitted by the second transmission unit;
The first inspection value generation unit
Buffer means for inputting a control command output by the arithmetic processing unit and outputting the input control command at a timing based on the first transmission instruction defined by the control program ;
The control command output by the buffer means is input, and the control output by the buffer means among a plurality of error check values corresponding to the plurality of control commands output by the arithmetic processing unit in the past from the input control command. The error check value to be added to the command is determined to be the error check value corresponding to the control command output by the arithmetic processing unit N (N is a positive integer) before the input control command, and the determined addition Determining means for outputting information on the N previous control commands used for generating an error check value to be performed according to the timing;
The control command output by the buffer means and the information about the N previous control commands output by the determination means are input, the input control command is stored, and the arithmetic processing is performed in the past from the input control command. Storage means for outputting, according to the timing, a control command indicated by information on the N previous control commands among the plurality of control commands output and stored in advance by the unit;
Enter the output control commands by said storing means, error checking value corresponding to the control command input generated by calculating the control command by a predetermined calculation method, the timing the generated error check value Generating means for outputting according to
The control command output by the buffer means and the error check value output by the generating means are input, the error check value input is added to the input control command, and the second transmission instruction is set at the timing. in response to output to the first transmission portion, an adding means for the control commands said error Ri test values are added to output to the first transmission unit in accordance with prior Symbol timing at the predetermined output control method,
Have
The determining means holds in advance a plurality of values of the N when determining the error check value to be added,
The storage unit has a storage area that is accessible when the gaming machine is activated and stores initial setting information of the gaming machine. The initial setting information includes a plurality of N values corresponding to each of the plurality of N values. Including selection information for
The arithmetic processing unit sets specific selection information of the selection information to the determining means when the gaming machine is activated,
The determining means includes
When starting the gaming machine, the specific N value corresponding to the specific selection information set is set to the default N value when determining the error check value to be added,
When the control command output by the buffer means is input after the gaming machine is activated, the set value of N is changed based on the input control command . The determination unit inputs the control command outputted by the pre-Symbol buffer means, when the control command entered by executing the determination of whether a predetermined condition is satisfied the control command, the condition is satisfied 2. The gaming machine according to claim 1 , wherein the value of N when determining the error check value to be added is changed to one of the plurality of values of N held in advance . The time when the determining means changes the value of N when determining the error check value to be added is when a control command that satisfies the condition is actually input to the determining means, or from the control command The gaming machine according to claim 2 , wherein a control command output later by the arithmetic processing unit is input to the determining means. 4. The gaming machine according to claim 2 , wherein the condition is that a type of the control command that is the object of the determination is a predetermined type of control command. 5. The main control unit further includes a unique information storage unit for storing unique information that indicates the game machine-specific information, prior Symbol rated paid unit, by the operation processing unit from the past control command outputted by said buffer means If the output control command is not stored, claim 1, wherein the unique information unique information stored in the storage unit as the error check value corresponding to the control command, and outputs it to the adding means The gaming machine according to any one of 1 to 4 . Said buffer means, a control command input, said predetermined output control method said determining means at the output control method that is different from the outputs the storage means, and to said adding means,
It said determining means, information about the control command of the N-th previous outputs in the same output control method and Kide force control system before the buffer means used,
The storage means outputs the stored control command in the same output control method as the output control method used by the buffer means,
It said generating means, the generated error check value, the gaming machine according to any of claims 1 to 5, wherein the outputs of the same output control method as before Kide force control method in which the buffer means used. The connection between the arithmetic processing unit and the first inspection value generation unit and the connection between the first inspection value generation unit and the first transmission unit are connected by a bus of the same standard,
It said predetermined output control method, the gaming machine according to any one of claims 1 to 6, characterized in that a scheme negotiated on the basis of the standard. The peripheral control unit
A first receiver for receiving a control command to which the error check value transmitted by the first transmitter is added;
A relay transmission unit that relays the control command to which the error check value received by the first reception unit is added to the subsequent control unit;
With
The latter stage control unit
A second receiving unit that receives the control command to which the error check value is relayed and transmitted by the relay transmitting unit;
With
The check unit performs the check using the error check value added to the control command received by the second receiving unit, and generates the result information,
The second transmission unit relays and transmits the control command received by the second reception unit to the peripheral control unit, and transmits the result information to the peripheral control unit. 8. The gaming machine according to any one of 7 .

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