JP5407653B2 - Liquid crystal display device and common electrode voltage setting method thereof - Google Patents

Description

  The present invention relates to a liquid crystal display device and a common electrode voltage setting method thereof, and more particularly to a third drive method active matrix liquid crystal display device having advantages of an analog drive method and a digital drive method and a common electrode voltage setting method thereof.

  In recent years, a liquid crystal display device of LCOS (Liquid Crystal on Silicon) type is often used as a central part for projecting images in projector devices and projection televisions. This LCOS type liquid crystal display device has a structure in which a transparent electrode, a liquid crystal layer, a reflective electrode arranged in a matrix, a liquid crystal driving element in which a liquid crystal driving circuit is formed on a silicon substrate, and the like overlap. It is widely used for liquid crystal projectors and projection televisions in home, office, and industrial information display terminals.

  In a conventional liquid crystal display device, pixels are arranged in a matrix at each intersection of a plurality of data lines (column signal lines) and a plurality of gate lines (row scanning lines). As shown in FIG. 11, each pixel includes a pixel selection transistor Q, a signal holding capacitor Cs, and a reflective electrode PE. The pixel selection transistor Q has a gate connected to a gate line (row scanning line) G and a drain connected to a data line (column signal line) D. Further, as shown in FIG. 11, the liquid crystal element LC has a configuration in which a liquid crystal display (liquid crystal layer) LCM is sandwiched between a reflective electrode (pixel drive electrode) PE and a counter electrode (common electrode) CE facing each other. Has been.

  In the liquid crystal element LC, the fixed voltage Vcom is applied to the common electrode CE, and various voltages according to the video signal are supplied to the reflective electrode (pixel drive electrode) PE, thereby controlling the light modulation rate of the liquid crystal display LCM. Display as video. Normally, the liquid crystal element LC can be stabilized for a long time by AC driving, so that the reflection electrode (pixel driving electrode) PE receives light according to the video signal with respect to the fixed voltage Vcom of the common electrode CE. AC driving is performed by alternately applying positive and negative voltages that have the same modulation rate.

  In some cases, there is an application example where the voltage of the counter electrode is switched according to the timing of driving with the positive and negative voltages for the purpose of reducing the dynamic range of the video signal, but the basic idea is the same It is.

  In the conventional liquid crystal display device, the video signal is normally written to each pixel once per frame, and the video signal on the positive side and the negative side is signaled alternately with respect to the common electrode CE every frame. After writing into the storage capacitor Cs, the storage voltage is applied to the reflective electrode (pixel drive electrode) PE to drive the liquid crystal element LC with alternating current. In this case, there is an example of double speed driving in which the liquid crystal is AC driven at a frequency twice as high as the writing frequency, but the frequency is about 60 Hz to 120 Hz, and is not a high frequency in any case.

  On the other hand, if the liquid crystal element is driven with alternating current at a higher frequency so that the direct current component between the reflective electrode (pixel drive electrode) PE and the common electrode CE can be reduced to zero, it is possible to improve reliability such as prevention of burn-in. Connection and image display quality are also improved.

  Until now, prevention of deterioration of written signals such as countermeasures against feedthrough caused by parasitic capacitance of the pixel selection transistor (for example, refer to Patent Document 1) and countermeasures for leakage of a storage capacitor (for example, refer to Patent Document 2). A method is disclosed. However, it seems that efforts to drive alternating current at higher frequencies have not been studied much.

  For each of a plurality of pixels connected to the same scanning line, the storage capacitor of each pixel is alternately connected to the storage capacitor line corresponding to the scanning line and another storage capacitor line corresponding to the adjacent scanning line. The compensation voltage for compensating the direct current component between the pixel drive electrode and the counter electrode is inverted for each storage capacitor line, so that the image quality deterioration caused by the potential fluctuation of the common electrode line or the common electrode is reduced. A liquid crystal display device that prevents generation thereof has been conventionally known (see, for example, Patent Document 3).

JP 2006-10897 A JP 2002-250938 A JP 2004-354742 A

  As described above, it is desirable to drive the liquid crystal element with an alternating current at a high frequency as a means for improving reliability such as prevention of burn-in of the liquid crystal element, but it is positive with respect to the counter electrode voltage due to restrictions such as writing time to the pixel. It is difficult to alternately write video signals on the negative side and the negative side at high speed, and conventionally, the frequency of AC drive is only performed at a frame rate or about twice that frequency.

  Further, in the liquid crystal display device described in Patent Document 3, the polarity of the compensation voltage can be reversed only for each frame, and the image signal voltage has two types of voltages, positive and negative, with respect to the common electrode voltage Vcom. is necessary.

  There are mainly two methods for driving the liquid crystal element: an analog driving method using amplitude modulation and a digital driving method using pulse width modulation. The analog drive method has the advantage of being excellent in continuous tone expression, but there are problems in terms of long-term reliability of the liquid crystal element because high-precision electrical adjustment is necessary and high-frequency drive of the liquid crystal element is difficult. Have. On the other hand, the digital drive method has advantages such as easier electrical adjustment compared to the analog method and improved long-term reliability of the liquid crystal element for high-frequency drive, Inferior in key expression.

  Therefore, a third driving method that combines the advantages of the analog driving method and the digital driving method, which enables both continuous gradation expression by amplitude modulation and long-term reliability by high-frequency driving of liquid crystal elements, is desired. ing. In this third driving method, it is difficult to obtain the maximum contrast because the center potential of the common electrode voltage caused by the DC offset of the liquid crystal element and the inversion center potentials of the positive and negative polarity ramp signals do not match. It becomes.

  The present invention has been made in view of the above points. The liquid crystal element is AC-driven at a high frequency that is twice or more the frame rate, and the center of the common electrode voltage caused by the DC offset of the liquid crystal element in the third driving method. An object of the present invention is to provide a liquid crystal display device capable of obtaining a maximum contrast by correcting a mismatch between the potential and the inversion center potentials of the positive and negative polarity ramp signals, and a common electrode voltage setting method thereof. .

In order to achieve the above object, the liquid crystal display device of the present invention is provided at an intersection where a plurality of data lines and a plurality of gate lines intersect each other, each of which includes two data lines.
A liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel drive electrode and a common electrode, and a positive video signal supplied via one of a pair of two data lines are sampled and held for a certain period. A first sampling and holding means; a second sampling and holding means for sampling and holding a negative video signal supplied via the other of the pair of two data lines; and a first sampling. And switching means for switching the positive video signal voltage held in the holding means and the negative video signal voltage held in the second sampling and holding means at a predetermined cycle shorter than the vertical scanning period and applying them to the pixel drive electrodes. A plurality of pixels each comprising:
A ramp signal that generates a positive polarity ramp signal and a negative polarity ramp signal that change continuously in one horizontal scanning period from one of the minimum value and the maximum value and whose level change directions are opposite to each other. The generation means, the value of each pixel of one line of the digital video signal, and the counter value that monotonously changes from the minimum gradation value to the maximum gradation value within one horizontal scanning period are compared in units of pixels. The potentials of the positive polarity ramp signal and the negative polarity ramp signal at the time of coincidence are output as a positive polarity video signal and a negative polarity video signal to a set of data lines connected to the pixel whose comparison result matches, respectively, The first and second sampling and holding means perform sampling and holding for each line of the digital video signal, and the switch for the common electrodes of the liquid crystal elements in the plurality of pixels. The first voltage is generated and applied during the application period of the pixel drive electrode voltage of the positive video signal voltage by the scanning means, and the second voltage is generated during the application period of the pixel drive electrode voltage of the negative video signal voltage. Common electrode voltage generating means to be applied, the common electrode voltage generating means,
Select the video data of the gradation when the potential of the positive polarity ramp signal output to the desired pixel by the DA conversion means becomes equal to the potential of the negative polarity ramp signal, and select the selected video data. After detecting the DC potential of the common electrode where the light from multiple pixels obtained at the time of input as a digital video signal has at least the minimum illuminance, the positive ramp signal and the negative polarity signal with respect to the potential related to the DC potential A third voltage that decreases stepwise from a lower value by an intermediate value between the maximum and minimum values of the ramp signal, and a fourth voltage that stepwise increases from a higher value by an intermediate value step by step. Measures the illuminance of light from multiple pixels when the maximum gradation image data and the minimum gradation image data are sequentially input while being alternately applied to the common electrode of the liquid crystal element as a square wave with a predetermined period. You This is repeated until the maximum value of the positive polarity ramp signal and the negative polarity ramp signal is changed step by step by a constant voltage until the allowable maximum value is reached. The third voltage and the fourth voltage when the ratio between the first measured illuminance and the second measured illuminance at the time of inputting the video data of the minimum gradation becomes the maximum are the first voltage and the second voltage. It is characterized by being preset.

  Further, in the liquid crystal display device of the present invention, the common electrode voltage generation unit includes the first DC potential of the common electrode when the light from the plurality of pixels has the lowest illuminance as the potential related to the DC potential, An average value with the second DC potential of the common electrode at the second lowest illuminance is used.

In order to achieve the above object, a common electrode voltage setting method for a liquid crystal display device according to the present invention includes a plurality of data lines each including two data lines and a plurality of gate lines intersecting each other. Each of the plurality of pixels provided at the intersection is supplied via a liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel drive electrode and a common electrode, and one of a pair of two data lines. A first sampling and holding means for sampling a positive video signal and holding it for a certain period, and a negative video signal supplied via the other of the two data lines in a set, and holding for a certain period The second sampling and holding unit, the positive video signal voltage held in the first sampling and holding unit, and the negative video signal voltage held in the second sampling and holding unit are shorter than the vertical scanning period. Comprising a switching means for applying to the pixel driving electrode is switched at a predetermined period, respectively,
A ramp signal that generates a positive polarity ramp signal and a negative polarity ramp signal that change continuously in one horizontal scanning period from one of the minimum value and the maximum value and whose level change directions are opposite to each other. The generation means, the value of each pixel of one line of the digital video signal, and the counter value that monotonously changes from the minimum gradation value to the maximum gradation value within one horizontal scanning period are compared in units of pixels. The potentials of the positive polarity ramp signal and the negative polarity ramp signal at the time of coincidence are output as a positive polarity video signal and a negative polarity video signal to a set of data lines connected to the pixel whose comparison result matches, respectively, The first and second sampling and holding means are sampled and held for each line of the digital video signal, and the DA conversion means is used to share the liquid crystal elements in a plurality of pixels of the liquid crystal display device. A method for setting a common electrode voltage applied to the electrodes,
A first step of selecting video data of a gradation when the potential of the positive polarity ramp signal output to a desired pixel by the DA conversion means is equal to the potential of the negative polarity ramp signal; A second step of detecting a DC potential of the common electrode at which light from a plurality of pixels obtained in a state where the video data selected in step 1 is inputted as a digital video signal, and a second step; A first voltage that decreases stepwise from a lower value by an intermediate value between the maximum value and the minimum value of the positive polarity ramp signal and the negative polarity ramp signal with respect to the potential related to the detected DC potential; The image data of the maximum gradation and the minimum floor are applied while alternately switching the second voltage, which is gradually increased from the higher value by the intermediate value, stepwise to the common electrode of the liquid crystal element as a square wave of a predetermined period. A third step of measuring the illuminance of light from a plurality of pixels when the video data are sequentially input, and the maximum values of the positive polarity ramp signal and the negative polarity ramp signal are increased by a constant voltage to increase the first to Repeating the third step is measured at the third step after the fourth step that repeats until the maximum value reaches the allowable maximum value and after the repetition of the first to third steps according to the fourth step. The first voltage and the second voltage when the ratio of the first measured illuminance at the time of video data input of the maximum gradation obtained and the second measured illuminance at the time of input of video data of the minimum gradation is maximized. And a fifth step of setting the voltage as a high level and a low level of a common electrode voltage which is a square wave having a predetermined period.

  Furthermore, in order to achieve the above object, the common electrode voltage setting method for a liquid crystal display device according to the present invention is characterized in that the third step outputs a plurality of pixels as potentials related to the DC potential detected in the second step. An average value of the first DC potential of the common electrode when the light has the lowest illuminance and the second DC potential of the common electrode when the light is the second lowest is used.

  According to the present invention, the liquid crystal element is AC-driven at a high frequency that is twice or more the frame rate, and is common due to the DC offset of the liquid crystal element in the third drive system having the advantages of the analog drive system and the digital drive system. The maximum contrast can be obtained by correcting the mismatch between the center potential of the electrode voltage and the inverted center potential of the positive and negative ramp signals.

It is a block diagram of one embodiment of the liquid crystal display device of the present invention. FIG. 2 is an equivalent circuit diagram of an example of the pixel in FIG. 1. 3 is a timing chart for explaining the operation of FIG. 2. It is explanatory drawing of an example of a positive video signal and a negative video signal. 2 is a timing chart for explaining the operation of FIG. 1. It is a conceptual diagram of DC balance when paying attention only to the input signal level. It is a conceptual diagram which shows the case where DC balance collapse | crumbles by DC offset of a liquid crystal display device. It is a system block diagram of one Embodiment of the center electric potential adjustment system of the reference lamp voltage used by this invention. It is a figure explaining the flowchart for operation | movement description of FIG. 8, and the definition of a lamp voltage. It is a figure explaining the detection method of the inversion center potential in consideration of DC offset of the liquid crystal display device by the center potential adjustment system of FIG. It is a block diagram of an example of the liquid crystal element in the conventional liquid crystal display device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a configuration diagram of an embodiment of a liquid crystal display device according to the present invention. As shown in the figure, the liquid crystal display device 100 of the present embodiment includes shift register circuits 101a and 101b, a one-line latch circuit 102, a comparator 103, a gradation counter 104, an analog switch 105, and a horizontal direction. M, n pixels in the vertical direction, timing generator 107, polarity switching control circuit 108, vertical shift register and level shifter 109, inverter INV, and two AND circuits It is composed of n sets of AND circuits each including AND-1 and AND-2. Further, the liquid crystal display device 100 includes a ramp signal generator 110 and a common electrode voltage generation circuit 111.

  The horizontal driver circuit including the shift register circuits 101 a and 101 b, the one-line latch circuit 102, the comparator 103, and the gray scale counter 104 constitutes a data line driving circuit together with the analog switch 105. Note that the comparator 103 is shown as one block in FIG. 1 for simplicity of illustration, but is actually provided for each pixel column.

  The analog switch 105 shown in FIG. 1 has a configuration in which a pair of sampling analog switches for positive polarity and negative polarity are arranged for each pixel column. The pixel 106 shown in FIG. 1 includes m sets of data lines (D1 + and D1-,..., Dm + and Dm-) and n gate lines (G1,..., Gn). ). Each of these n · m pixels 106 is configured as shown in FIG. 2, for example.

  FIG. 2 shows an equivalent circuit diagram of an example of one pixel in the liquid crystal display device according to the present invention. In the figure, a pixel 106 includes pixel selection transistors Q1 and Q2 for writing positive and negative pixel signals, and two independent holding capacitors C1 and C2 for holding image signal voltages of respective polarities in parallel. And a liquid crystal element LC having the same configuration as that of the liquid crystal element shown in FIG. 11, which includes a reflective electrode (hereinafter referred to as a pixel drive electrode) PE and the like.

  The transistors Q3 and Q4 constitute an impedance conversion source follower circuit. The transistor Q5 whose drain is connected to the source of the transistor Q3 and the transistor Q6 whose drain is connected to the source of the transistor Q4 are switching transistors. The sources of the transistors Q5 and Q6 are connected to the pixel drive electrode PE of the liquid crystal element LC. The transistor Q9 is a constant current load transistor that forms a source follower buffer. The transistor Q9 is arranged at the subsequent stage of the polarity switching switching transistors Q5 and Q6, that is, at the node of the pixel drive electrode PE, and has both positive and negative polarity source follower circuits. Functions in common as a load.

  The pixel portion data line is composed of a pair of positive data line D + and negative data line D- for each pixel, and video signals having different polarities sampled by a data line driving circuit (not shown) are provided. Supplied. The drain terminals of the pixel selection transistors Q1 and Q2 are respectively connected to the positive polarity data line Di + (any one of D1 + to Dm + in FIG. 1) and the negative polarity data line Di− (D1 to Dm− in FIG. 1). Any one) is connected, and each gate terminal is connected to the row scanning line Gj (corresponding to any one of the gate lines G1 to Gn in FIG. 1) for the same row.

  Further, a transistor Q10 is provided as a switching means for inspection between the pixel drive electrode PE and the positive video signal writing data line Di +. In each of the transistors Q10 in the pixel circuit in the same row, a gate that is a readout control terminal is commonly connected to a selection line RD of the readout switch. The selection control signal applied to the gate of the transistor Q10 through the selection line RD controls the transistors Q10 in all the pixel rows to be turned off in the normal image display mode (pixel writing mode), and the pixel inspection mode (pixel reading). Mode), the transistors Q10 in the pixel rows to be inspected are sequentially turned on. Here, the pixel inspection mode is a mode in which pixel values are read out to the data line pixel by pixel from a pixel portion in which a plurality of pixels are arranged in a matrix, and the presence or absence of defects is inspected pixel by pixel. Accordingly, in the pixel inspection mode, the video signal for writing is not input to the data line, and the pixel portion is set to the reading mode.

  The row selection means in such a pixel inspection mode is realized with the same configuration as that of the vertical driving circuit formed of a shift register, similarly to the writing of the video signal. It is also possible to share the shift register of the vertical driving circuit for signal writing with the row selection means in the pixel inspection mode.

  Returning to FIG. The pixels 106 are provided in n rows in the vertical direction and m columns in the horizontal direction. A gate line G1 and a read switch selection line RD1 are commonly connected to the m pixels 106 in the first row. A gate line Gn and a read switch selection line RDn are commonly connected to the m pixels 106 in the n-th row. Similarly, in each of the m pixels 106 in each row i, the gate line Gi and the read switch selection line RDi are commonly connected to each pixel row.

  The AND circuit 1-1 performs an AND operation on the selection control signal from the control terminal WT / RD and the vertical direction drive signal from the output terminal of the first row of the vertical shift register and level shifter 109, and outputs it to the gate line G1. To do. The AND circuit 1-2 logically ANDs the signal obtained by logically inverting the selection control signal from the control terminal WT / RD with the inverter INV and the vertical driving signal from the output terminal of the first row of the vertical shift register and level shifter 109. Calculate and output to the selection line RD1 of the read switch.

  The AND circuit n-1 performs a logical product operation on the selection control signal from the control terminal WT / RD and the vertical driving signal from the output terminal of the nth row of the vertical shift register and level shifter 109, and outputs the result to the gate line Gn. To do. The AND circuit n-2 ANDs the signal obtained by logically inverting the selection control signal from the control terminal WT / RD with the inverter INV and the vertical driving signal from the output terminal of the nth row of the vertical shift register and level shifter 109. Calculate and output to the selection line RDn of the read switch.

  Similarly, each pixel circuit in the other pixel row i performs a logical product operation on the selection control signal and the vertical direction drive signal from the i-th row output terminal of the vertical shift register and level shifter 109 and outputs the result to the gate line Gi. An AND circuit, a signal obtained by logically inverting the selection control signal by the inverter INV, and a vertical direction driving signal from the output terminal of the i-th row of the vertical shift register and level shifter 109 are subjected to a logical product operation to select a selection line for the switch It is connected to an AND circuit that outputs to RDi. These selection lines RD1 to RDi are connected to the gate of the transistor Q10 shown in FIG. 2 in the pixels 106 in the same pixel row.

  The control terminal WT / RD is supplied with a high-level selection control signal in the normal image display mode (pixel writing mode) and supplied with a low-level selection control signal in the pixel inspection mode (pixel readout mode). The A normal image display mode (pixel writing mode) is provided by the gate function of AND gates (AND1-1, AND1-2,..., ANDn-1, ANDn-2) configured in each output stage of the vertical shift register and level shifter 109. ) Sometimes selection pulses are sequentially output to the gate lines G1,.

  On the other hand, in the pixel inspection mode (pixel readout mode), the readout switch selection line RD1,... By the gate function of the AND gates (AND1-1, AND1-2,..., ANDn-1, ANDn-2). .., Selection pulses are sequentially output to RDn. Thus, the mode can be switched by sharing the vertical shift register and the level shifter 109 by the selection control signal input via the control terminal WT / RD.

  In the pixel inspection mode, the transistor Q10 shown in FIG. 2 in the pixel 106 in the selected pixel row is turned on by a selection pulse applied to the gate through the selection line RD of the readout switch. As a result, the pixel drive electrode PE and the data line become conductive, and the pixel drive electrode voltage is output to the data line. At this time, when the buffer amplifier (load element) of the pixel circuit in the selected row in the pixel inspection mode is activated and one of the polarity switching control switches Q5 and Q6 is turned on, the pixel drive electrode is set to buffer output during that period. It is possible to read the driving voltage applied to the pixel driving electrode to the signal line side as a voltage output.

  The pixel drive electrode voltage read to the data line side is supplied to the video data common input terminal (Ref_Ramp (+) in the example of FIG. 1) via the analog switch 105 by driving the horizontal driver circuit of FIG. Output as a series signal. By detecting this time series signal, inspection of the pixel circuit (detection of pixel defects) can be performed.

  In the conventional active matrix liquid crystal display device, the pixel is driven by the voltage held in the form of the charge held in the holding capacitor, so the pixel readout inspection is a highly accurate detection that detects a minute current change during charge movement. Whereas an amplifier or the like is required, in the combination of the pixel circuit according to the present embodiment and its inspection / reading means, the voltage of the pixel drive electrode, that is, the voltage of the pixel drive electrode driven with a low output impedance by the buffer amplifier output itself Therefore, pixel defect detection and pixel characteristic detection can be performed more easily.

  Next, an outline of the AC drive control of the pixel 106 will be described with reference to the timing chart of FIG. 3A shows the vertical synchronization signal VD, and FIG. 3B shows a load characteristic control signal of the wiring B applied to the gate of the transistor Q7 in the pixel 106 of FIG. 3C shows the gate control signal of the wiring S + applied to the gate of the switching transistor Q5 that transfers the positive drive voltage in the pixel 106, and FIG. 3D shows the negative electrode in the pixel 106. 4 shows each signal waveform of a gate control signal of the wiring S− applied to the gate of the switching transistor Q6 that transfers the active drive voltage.

  FIG. 4 shows the relationship from the black level to the white level of the positive video signal I and the negative video signal II written to the pixel. The positive video signal I has a black level when the level is minimum and a white level when the level is maximum, whereas the negative video signal II has a white level when the level is minimum and a black level when the level is maximum. The inversion center of the positive video signal I and the negative video signal II is indicated by III.

  In FIG. 4, the positive polarity video signal I indicates the black level when the level is minimum and the white level when the level is maximum, and the negative polarity video signal II indicates the white level when the level is minimum and the black level when the level is maximum. However, in the pixel circuit of the liquid crystal display device of the present invention, the positive video signal I is a white level when the level is minimum, a black level when the level is maximum, and the negative video signal II is black when the level is minimum. The level may be a white level at the maximum.

  2, the positive polarity side switching transistor Q5 is turned on while the gate control signal of the wiring S + shown in FIG. 3C is at a high level, and the load characteristic control signal supplied to the wiring B during this period is shown in FIG. As shown in FIG. 5B, when the level is high, the source follower buffer circuit becomes active, and the pixel drive electrode PE node is charged to the positive video signal level. When the potential of the pixel drive electrode PE is fully charged, the load characteristic control signal of the wiring B is set to a low level, and at that time, the gate control signal of the wiring S + is also switched to a low level. The drive electrode PE is in a floating state, and a positive drive voltage is held in the liquid crystal capacitor.

  On the other hand, when the gate control signal of the wiring S− shown in FIG. 3D is at a high level, the negative polarity side switching transistor Q6 is turned on, and the load characteristic control signal supplied to the wiring B during this period is shown in FIG. ), The source follower buffer circuit becomes active and the pixel drive electrode PE node is charged to the negative video signal level. When the potential of the pixel drive electrode PE is fully charged, the load characteristic control signal of the wiring B is set to the low level, and the gate control signal of the wiring S- is also switched to the low level at that time. The drive electrode PE is in a floating state, and the negative drive voltage is held in the liquid crystal capacitor.

  Hereinafter, in synchronism with the switching in which the switching transistors Q5 and Q6 are alternately turned on, the operation for intermittently activating the constant current load transistor Q7 is repeated, whereby the pixel drive electrode PE of the liquid crystal element has positive polarity. A drive voltage VPE converted into an alternating current with each negative video signal is applied as shown in FIG.

  In the present embodiment, the held charge is not directly transferred to the pixel driver, but is supplied with a voltage via the source follower buffer circuit. There is no problem of sum, and driving without voltage level attenuation can be realized even if polarity switching is performed many times.

  Further, Vcom shown in FIG. 3F represents a voltage applied to the common electrode CE formed on the counter substrate of the liquid crystal display device. The substantial AC drive voltage of the liquid crystal display LCM is a difference voltage between the applied voltage Vcom of the common electrode CE and the applied voltage of the pixel drive electrode PE. In the present embodiment, as shown in FIG. 3F, the common electrode voltage generation circuit 111 inverts the reference level substantially equal to the inversion reference level Vc of the pixel drive electrode potential in synchronization with the pixel polarity switching. A symmetric square wave is generated as a common electrode voltage Vcom and applied to the common electrode CE. As a result, the absolute value of the potential difference between the applied voltage Vcom of the common electrode CE and the applied voltage of the pixel drive electrode PE is always the same, and the liquid crystal display LCM has an AC voltage having no DC component as shown in FIG. VLC is applied.

  As described above, in the present embodiment, the amplitude of the drive voltage on the pixel (PE) side can be reduced to about ½ or less by switching the voltage applied to the common electrode CE in a phase opposite to that of the pixel drive electrode PE. As a result, the required breakdown voltage of the transistors constituting the pixel circuit and the peripheral scanning circuit is greatly reduced, the application of a special high breakdown voltage structure and process is not required, and a normal logic process can be applied, thereby reducing the manufacturing cost. . Further, in this embodiment mode, a driver unit such as a pixel circuit can be configured with a low withstand voltage and small transistor as described above, so that a higher pixel density liquid crystal display device can be realized, and the per unit channel width can be reduced by reducing the transistor withstand voltage. Therefore, it is possible to employ a transistor having a high driving capability, and thus it is possible to easily cope with a high-speed driving operation.

  In the present embodiment, the gate control signal supplied alternately to the wirings S + and S− is a liquid crystal drive signal that inverts the positive polarity and the negative polarity to the pixel driving portion with the switching transistors Q5 and Q6 alternately turned on. Can be given. In the conventional active matrix liquid crystal display device, the polarity inversion can be realized only in the vertical scanning period, whereas in the present embodiment, the pixel circuit itself has a polarity inversion function, which can be controlled at high speed. Therefore, AC driving at a high frequency without restriction of the vertical scanning frequency is possible.

  Returning again to FIG. The polarity switching control circuit 108 shown in FIG. 1 is based on the timing signal from the timing generator 107, the positive polarity gate control signal for the wiring S +, the negative polarity gate control signal for the wiring S-, and the wiring B. Each of the load characteristic control signals is output. In the normal image display mode (pixel writing mode), a high-level selection control signal is supplied, and in the pixel inspection mode (pixel readout mode), a low-level selection control signal is supplied. Therefore, a normal image display mode (pixel) is realized by the gate function of the AND gates (AND1-1, AND1-2,..., ANDn-1, ANDn-2) configured in each output stage of the vertical shift register and the level shifter 109. In the writing mode), gate signals are sequentially output to the gate lines G1 to Gn in one horizontal scanning cycle, and the gate lines G1 to Gn are sequentially selected in one horizontal scanning cycle.

  Next, the operation in the normal image display mode (pixel writing mode) of FIG. 1 will be described with reference to the timing chart of FIG. In FIG. 1, pixel data (DATA) of N bits (N is a natural number of 2 or more) shown in FIG. 5B, which is synchronized with the horizontal synchronizing signal HD shown in FIG. The digital video signal is input to the shift register circuits 101a and 101b through a correction gradation adding unit 113, which will be described later, and sequentially developed as data for one line. When the development for one line is completed, the one-line latch circuit 102 is obtained. Is latched on.

  Of the pixel data (DATA) shown in FIG. 5 (B), horizontal even-numbered column pixel data DATA (even) shown every other white background is supplied to the shift register circuit 101a, and the remaining hatched portions. Every other odd-numbered pixel data DATA (odd) in the horizontal direction is supplied to the shift register circuit 101b. This is because it is easy to cope with high-speed operation on a high-resolution panel.

  The one-line latch circuit 102 is a one-line period of the same line composed of odd-numbered column pixel data DATA (odd) output from the shift register circuit 101a and even-numbered column pixel data DATA (even) output from the shift register circuit 101b. After the pixel data DATA is held as schematically shown in FIG. 5D, it is supplied to the first data input section of the comparator 103 of each pixel column.

  The gradation counter 104 counts the clock Count-CK shown in FIG. 5E, and as shown in FIG. 5F, a plurality of gradation values are sequentially obtained from the minimum value to the maximum value within the horizontal scanning period. The changing reference gradation data C-out is output every horizontal scanning period, and supplied to the second data input unit of the comparator 103 of each pixel column. The comparator 103 compares the value of the input pixel data DATA of the first data input unit with the value of the input reference gradation data C-out (gradation value) of the second data input unit, and the two values match. A coincidence pulse is generated and output at the same timing.

  Of the two sampling analog switches for positive polarity and negative polarity constituting the analog switch 105, the sampling analog switch for positive polarity is connected to the common wiring on the input side from the ramp signal generator 110 for positive polarity. A reference lamp voltage Ref_Ramp (+) which is a ramp signal is applied. On the other hand, in the negative polarity sampling analog switch, a reference ramp voltage Ref_Ramp (−), which is a negative polarity ramp signal, is applied from the ramp signal generator 110 to the input side common wiring. The reference lamp voltages Ref_Ramp (+) and Ref_Ramp (-) correspond to the positive video signal I and the negative video signal II shown in FIG.

  Of the reference ramp voltages Ref_Ramp (+) and Ref_Ramp (−), Ref_Ramp (+) increases in the level from the black level to the white level in the horizontal scanning period as shown in FIG. It is a periodic sweep signal that changes to. On the other hand, the reference ramp voltage Ref_Ramp (−) is a periodic sweep signal that changes in a direction in which the level decreases from the black level of the video to the white level in the horizontal scanning period as shown in FIG. . Therefore, the reference lamp voltages Ref_Ramp (+) and Ref_Ramp (−) have an inversion relationship with respect to a predetermined reference potential.

  The analog switch 105 receives the SW-Start signal shown in FIG. 5 (G), turns on at the same time at the start of the horizontal scanning period, and then turns off when the coincidence pulse is received from the comparator 103. Open / close controlled.

  In the timing chart of FIG. 5, as an example, the opening / closing timing of the analog switch 105 of the pixel column corresponding to the pixel data DATA of the gradation level k is illustrated as a waveform SPk shown in FIG. As a result, the reference ramp voltage Ref_Ramp (+) at the time when the pair of sampling analog switches for positive polarity and negative polarity constituting the analog switch 105 of the pixel column are simultaneously turned off in response to the coincidence pulse. And Ref_Ramp (−) corresponding levels (points P and Q in FIGS. 5I and 5J) are simultaneously sampled and output to the pixel data lines D (+) and D (−) of the pixel column. Is done. The reference ramp voltage levels at points P and Q in FIGS. 5I and 5J are analog voltages obtained by digital-analog conversion of the pixel data DATA at the gradation level k.

  The analog switch 105 is forcibly turned on at the beginning of each horizontal scanning period, but the timing when it is turned off, that is, the timing at which the reference ramp voltage is sampled and held depends on the pattern to be displayed at that time. Each pixel is different, and may be all at the same time or different. The turn-off order is not fixed, and the turn-off order varies depending on the pattern. The liquid crystal display device 100 according to the present embodiment has a feature that the linearity is good by the operation of the DA conversion method using the ramp signal.

  Incidentally, as described in conjunction with FIGS. 5I and 5J, the reference lamp voltages Ref_Ramp (+) and Ref_Ramp (−) have an inversion relationship with respect to a predetermined reference potential. FIG. 6 is a conceptual diagram of DC balance when attention is paid only to the input signal level. The positive reference lamp voltage Ref_Ramp (+) is a waveform in which the potential increases from the black level to the white level as time passes, as indicated by IV in FIG. Further, the negative reference lamp voltage Ref_Ramp (−) is a waveform in which the potential decreases from the black level to the white level as time passes, as indicated by V in FIG. These two reference lamp voltages Ref_Ramp (+) and Ref_Ramp (-) have their center potentials equal to the center potential of the common electrode voltage indicated by Vce (cen) in FIGS. 6 (a) and 6 (b). The reversal relationship is made.

  Thus, as shown in FIGS. 6A and 6B, the absolute value of the potential ΔVk (+) with respect to the common electrode voltage Vce (+) of the reference lamp voltage Ref_Ramp (+) and the reference lamp voltage Ref_Ramp (−) Is equal to the absolute value of the potential ΔVk (−) with respect to the common electrode voltage Vce (−).

  In FIGS. 6A and 6B, the positive pixel voltage obtained by DA conversion using the reference ramp voltage Ref_Ramp (+) when video data of an arbitrary gradation k is input is represented by Vk (+), If the negative pixel voltage obtained by DA conversion using the reference ramp voltage Ref_Ramp (−) is Vk (−), the influence of the input / output characteristics of the transistors Q3 and Q4 in the pixel circuit shown in FIG. In response, the output voltage of the pixel rises by the threshold voltage Vth of the transistors Q3 and Q4 with respect to the input pixel voltage.

  Therefore, as shown in FIG. 9B to be described later, when the maximum value of the reference lamp voltages Ref_Ramp (+) and Ref_Ramp (−) is VH and the minimum value is VL, FIGS. As shown, the maximum and minimum values increase by Vth. The maximum output voltage of both Vk (+) and Vk (−) is the power supply voltage VDD of the liquid crystal panel.

  When the drive voltage of the liquid crystal element LC is actually set optimally, the symmetry of the drive signal is achieved at the input signal level. However, it is known that in the reflective liquid crystal element formed from the pixel drive electrode PE, the common electrode CE, the liquid crystal material, and the alignment film, a DC offset is generated due to the liquid crystal element LC being made of a different substrate material. (For example, Minhua etal, “Reflective Nematic LC Devices for LCOS Applications”, SID2000_IBM publication).

  For this reason, as shown in FIG. 7, the inversion relationship of the reference lamp voltages Ref_Ramp (+) and Ref_Ramp (−) with respect to a predetermined reference potential is broken. That is, the positive reference lamp voltage Ref_Ramp (+) is indicated by VI in FIG. 7 (a), and the negative reference lamp voltage Ref_Ramp (−) is indicated by VII in FIG. 7 (b). These center potentials may become inconsistent with the center potential Vce (cen) of the common electrode voltage due to the DC offset, and the symmetry of both may be lost.

  As a result, as shown in FIGS. 7A and 7B, the potential ΔVk with respect to the common electrode voltage Vce (+) of the reference ramp voltage Ref_Ramp (+) obtained by DA conversion when video data of an arbitrary gradation k is input. The absolute value of (+) does not match the absolute value of the potential ΔVk (−) with respect to the common electrode voltage Vce (−) of the reference lamp voltage Ref_Ramp (−). As a result, a DC component is applied to the liquid crystal layer LCM, and the long-term reliability is lowered due to image sticking or deterioration of the liquid crystal material. In addition, since the DC offset is individually stored in the liquid crystal element LC in the manufacturing process of the liquid crystal display device, the DC offset amount has a different value for each liquid crystal element LC.

  Therefore, in this embodiment, in order to reduce or eliminate the influence of the DC offset, an inversion center potential adjustment system for the reference ramp voltages Ref_Ramp (+) and Ref_Ramp (-) is provided to adjust the inversion center potential. It is something that can be done.

  Next, the operation of this embodiment will be described with reference to FIGS. FIG. 8 is a system configuration diagram of an embodiment of a reference lamp voltage center potential adjustment system, and FIG. 9A is a flowchart for explaining the operation of FIG.

  In FIG. 8, the reference lamp voltage center potential adjustment system 150 includes a reference lamp voltage generation circuit 151, a common electrode voltage generation circuit 111, a center potential detection circuit 153, a light source 154, a polarization beam splitter 155, a projection. A lens 156, an illuminance meter 157, and a data processing personal computer (hereinafter referred to as a personal computer) 158 are connected to the liquid crystal display device 100 shown in FIG.

  The reference ramp voltage generation circuit 151 is a circuit that generates the above-described reference ramp voltages Ref_Ramp (+) and Ref_Ramp (−). The ramp signal generator 110 shown in FIG. 1 can be used, or the ramp signal generator. 110 may be provided separately. The common electrode voltage generation circuit 111 is the common electrode voltage generation circuit 111 shown in FIG.

  The center potential detection circuit 153 includes a variable resistor VR and a selector SEL. The selector SEL selects and outputs the variable voltage from the variable resistor VR when detecting the center potential of the reference lamp voltage, and selects and outputs the common electrode voltage Vcom from the common electrode voltage generation circuit 111 in the normal image display mode. To do.

  In the liquid crystal display device 100, the reference lamp voltages Ref_Ramp (+) and Ref_Ramp (-) from the reference lamp voltage generation circuit 151 are input to the reference lamp voltage input terminal, and the voltage from the center potential detection circuit 153 is received. Then, it is inputted to the common electrode CE of the liquid crystal elements LC in all the pixels 106 through the common electrode voltage input terminal (ITO terminal).

  The light source 154 emits, for example, linearly polarized light having an arbitrary wavelength. The polarization beam splitter 154 reflects the light from the light source 154 and enters each pixel 106 of the liquid crystal display device 100, and transmits the reflected light reflected by rotating the polarization plane in each pixel 106. The projection lens 156 projects the reflected light transmitted through the polarization beam splitter 155 onto the illuminometer 157. The illuminometer 157 measures the illuminance of the incident light from the projection lens 156, and the data processing personal computer 158 performs predetermined data processing described later based on the illuminance measurement result of the illuminometer 157.

  Next, the operation of the reference lamp voltage center potential adjustment system 150 will be described with reference to the flowchart of FIG.

First, as shown in FIG. 9B, the maximum value of the reference lamp voltage Ref_Ramp (+) indicating the white level and the minimum value of the reference lamp voltage Ref_Ramp (-) are set to VH, and the reference lamp voltage Ref_Ramp (+) indicating the black level. ) And the maximum value of the reference lamp voltage Ref_Ramp (-) as VL,
VH = VL = GND + ((VDD−GND) / 10) (1)
Is input from the reference ramp voltage generation circuit 151 to the reference ramp voltage input terminal of the liquid crystal display device 100 (step S1).

  Subsequently, after the above VH is increased by (VDD−GND) / 100 (step S2), video data of the minimum gradation (k = 0) (hereinafter also referred to as “gradation data”) is displayed on the liquid crystal display. Input to the video data input terminal of the apparatus 100 (step S3). Subsequently, the potential Vk (+) of the positive reference lamp voltage Ref_Ramp (+) obtained by DA-converting the video data of gradation k at a desired pixel in the liquid crystal display device 100, and the negative reference lamp The gradation k of the video data input to the liquid crystal display device 100 is incremented by “1” until the potential Vk (−) of the voltage Ref_Ramp (−) becomes equal (steps S4 and S5).

  Thus, as shown in FIG. 10, the potential Vk (+) of the positive reference lamp voltage Ref_Ramp (+) indicated by VIII and the potential Vk (−) of the negative reference lamp voltage Ref_Ramp (−) indicated by IX Select the video data of the gradation when.

  Subsequently, while inputting the video data of the selected gradation to the liquid crystal display device 100, in the following steps, the illuminance meter 157 measures the illuminance while changing the DC voltage Vcedc of the common electrode, and the common electrode having the minimum illuminance is obtained. DC voltage Vcedc is detected.

  That is, first, the variable resistor VR is changed, the DC voltage Vcedc of the common electrode from the variable resistor VR selected by the selector SEL is set to GND, and the common electrode voltage input terminal (ITO terminal) of the liquid crystal display device 100 is set. Supply (step S6). Subsequently, the variable resistance VR is varied to increase the DC voltage Vcedc of the common electrode by (VDD−GND) / 100 and supply it to the common electrode voltage input terminal of the liquid crystal display device 100 (step S7). The reflected light from the light source 154 reflected by each pixel 106 of the liquid crystal display device 100 at this time passes through the polarization beam splitter 155 and is irradiated onto the illuminance meter 157 by the projection lens 156 to measure the illuminance, and the measurement The result is output to a file in the data processing personal computer 158 (step S8).

The data processing personal computer 158 indicates that the illuminance result of the illuminometer 157 is as follows: Vcedc = VDD + LCVth (2)
Is satisfied (step S9). Here, as shown in FIG. 9B, VDD in the formula (2) is a power supply voltage (element power supply voltage) of the liquid crystal panel, and LCVth is a threshold voltage (black voltage) of the liquid crystal element. Equation (2) indicates that the DC voltage Vcedc of the common electrode is the minimum illuminance. If the equation (2) is not satisfied, the DC voltage Vcedc of the common electrode is increased by (VDD−GND) / 100 until satisfied, and determination is performed (steps S6 to S9).

  The DC voltage Vcedc of the common electrode that can obtain the minimum illuminance detected in this way is the center potential Vce (cen) of the square-wave common electrode voltage Vcom in consideration of the DC offset generated due to the factor of the liquid crystal element LC. It is clear that Strictly speaking, however, the liquid crystal element LC has a minimum in the state where the minimum illuminance is obtained with the minimum liquid crystal drive voltage and in the state where the liquid crystal drive voltage is slightly applied (the liquid crystal drive voltage in this state is LCVth). There are two types of illuminance.

Therefore, next, the center potential detection circuit 153 uses Vce (cen) as an average value of Vcedc at the lowest illuminance and Vcedc at the second lowest illuminance, and using the average value, Vce (cen) +) = Vce (cen) − (VH−VL) / 2 (3a)
Vce (−) = Vce (cen) + (VH−VL) / 2 (3b)
Vce (+) and Vce (−) represented by the above are alternately input to the common electrode voltage input terminal of the liquid crystal display device 100 at a predetermined cycle which is the polarity switching cycle of the video data (step S10).

Subsequently, the center potential detection circuit 153 has the following formula: Vce (+) = Vce (+) − (VDD−GND) / 100 (4a)
Vce (-) = Vce (-) + (VDD-GND) / 100 (4b)
Vce (+) and Vce (−) represented by the above are alternately input to the common electrode voltage input terminal of the liquid crystal display device 100 at the predetermined period (step S11). The Vce (+) and Vce (−) on the right side of the equations (4a) and (4b) are initially the common electrode voltages calculated using the average value Vce (cen) according to the equations (3a) and (3b). Vce (+) and Vce (-). However, the Vce (+) and Vce (−) on the right side of the expressions (4a) and (4b) are Vce (+) calculated in the immediately preceding step S11 when NO is determined in step S13. , Vce (−).

  Then, a symmetric square wave having a predetermined period in which Vce (+) calculated by the equation (4a) is at a low level and Vce (−) calculated by the equation (4b) is at a high level is input to the common electrode. First, the video data of the minimum gradation is input to the video data input terminal of the liquid crystal display device 100 in the state, the illuminance of the reflected light from the liquid crystal display device 100 at that time is measured by the illuminometer 157, and the measurement result is obtained. The data is output to the data processing personal computer 158. Subsequently, the video data of the maximum gradation is input to the video data input terminal of the liquid crystal display device 100 in the above state, and the illuminance of the reflected light from the liquid crystal display device 100 at that time is measured by the illuminometer 157, The measurement result is output to the data processing personal computer 158 (step S12).

Subsequently, in the data processing personal computer 158, the common electrode voltage Vce (−) is expressed by the following formula: Vce (−) = VDD + LCVth (5)
Is satisfied (step S13).

  When the liquid crystal display device 100 is a device using the liquid crystal element LC having the minimum illuminance in a state where the liquid crystal driving voltage is slightly applied (the liquid crystal driving voltage in this state is LCVth), In order to obtain the minimum illuminance when the value VH (= VDD−Vth) is set, Vce (−) needs to be a voltage LCVth slightly higher than VH. The determination using the equation (5) in step S13 determines whether this condition is satisfied. The voltage LCVth can be determined in advance in consideration of the physical characteristics of the liquid crystal display device to be adjusted.

  If the expression (5) is not satisfied, the processes in steps S11 to S13 are repeated until the expression is satisfied. That is, the center potential detection circuit 153 gradually decreases the common electrode voltage Vce (+) when positive-polarity video data is input by a potential expressed by (VDD−GND) / 100, and when negative-polarity video data is input. The common electrode voltage Vce (−) is increased stepwise by the potential represented by (VDD−GND) / 100. Then, the center potential detection circuit 153 receives the changed common electrode voltage in the liquid crystal display device 100, and the liquid crystal at the time of input of the minimum gradation video data and the input of the maximum gradation video data. The measurement of the illuminance of the reflected light from the display device 100 is repeated.

  If it is determined in step S13 that the negative common electrode voltage Vce (−) is equal to (VDD + LCVth), the data processing personal computer 158 then determines that the maximum value VH of the reference ramp voltage is equal to (VDD−Vth). Whether or not (step S14). This is because the maximum value VH of the reference ramp voltage is influenced by the input / output characteristics of the transistors Q3 and Q4 as described above, and cannot be larger than (VDD−Vth) due to driving restrictions of the liquid crystal display device 100.

If the maximum value VH of the reference lamp voltage is not equal to the allowable maximum value (VDD−Vth), the process returns to step S2. In this way, until the equation of step S14 is satisfied,
VH ≦ VDD−Vth (6)
In the range, the processes of steps S2 to S13 are repeated.

  When it is determined in step S14 that the maximum value VH of the reference lamp voltage is equal to the allowable maximum value (VDD−Vth), it is expressed by (illuminance at maximum gradation) / (illuminance at minimum gradation). VH, VL, Vce (+), and Vce (−) when the illuminance ratio is maximized are determined as optimum voltages (step S15). The case where the illuminance ratio represented by (illuminance at the maximum gradation) / (illuminance at the minimum gradation) in step S15 is the maximum is the case where the maximum contrast is obtained.

  As described above, according to the adjustment system of the inversion center potential of the reference lamp voltage according to the present embodiment, optimum VH, VL, Vce (+), Vce (− ) Can be determined.

  Further, the center potential detection circuit for detecting the center potential Vce (cen) has only to be a simple configuration using a variable resistor VR capable of variably outputting a DC voltage, as indicated by 153 in FIG. The mounting does not require special parts, so the cost is low. Further, according to the present embodiment, it is possible to establish an adjustment algorithm for VH, VL, Vce (+), and Vce (−) based on the center potential Vce (cen), which is very easy for adjustment. A big merit can be obtained.

  The ramp signal generator 110 shown in FIG. 1 has the reference ramp voltages Ref_Ramp (+) and Ref_Ramp (−) that continuously change in level within one horizontal scanning period from the maximum value VH determined as the optimum voltage in step S15 to the minimum value VL. ) Is input to the reference lamp voltage input terminal of the liquid crystal display device 100. The common electrode voltage generation circuit 111 shown in FIGS. 1 and 8 sets Vce (+) determined as the optimum voltage in step S15 to low level, Vce (−) to high level, and one vertical scanning period. A shorter symmetric square wave having a predetermined period is generated and input to the common electrode voltage input terminal of the liquid crystal display device 100 as the common electrode voltage Vcom.

  Thereby, the center potential Vce (cen) of the common electrode voltage caused by the DC offset of the liquid crystal element LC and the inversion center between the maximum value VH and the minimum value VL of the reference lamp voltages Ref_Ramp (+) and Ref_Ramp (−). The mismatch with the potential is corrected and the maximum contrast can be obtained.

  The present invention is not limited to the above-described embodiment. For example, the circuit of the pixel 106 is not limited to the circuit of FIG. 2, and for example, the transistor Q10 in FIG. A configuration in which the AND circuit and the inverter INV are removed may be used. Further, in the algorithm of the above embodiment, the description has been made so as to correspond to two types of liquid crystal elements in which the relationship between the minimum illuminance and the liquid crystal driving voltage is different, but only one type of liquid crystal elements is supported. It may be an algorithm.

DESCRIPTION OF SYMBOLS 100 Liquid crystal display device 101a, 101b Shift register circuit 102 1 line latch circuit 103 Comparator 104 Gradation counter 105 Analog switch 106 Pixel 107 Timing generator 108 Polarity switching control circuit 109 Vertical shift register / level shifter 110 Lamp signal generator 150 Reference lamp voltage Center potential adjustment system 151 Reference lamp voltage generation circuit 153 Center potential detection circuit 154 Light source 155 Polarizing beam splitter 156 Projection lens 157 Illuminometer 158 Data processing personal computer (personal computer)
D1 + to Dm +, Di +, D1- to Dm-, Di- data line G1 to Gn, Gj gate line B load characteristic control signal line S +, S- gate control signal line PE pixel drive electrode CE common electrode LCM display (liquid crystal) layer)
LC liquid crystal element Q1, Q2 pixel selection transistor Q3, Q4 source follower transistor Q5, Q6 switching transistor Q9 constant current load transistor C1, C2 signal holding capacitance

Claims (4)

It is provided at the intersection where a plurality of sets of data lines and a plurality of gate lines intersect each other, each consisting of two data lines,
A liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel drive electrode and a common electrode;
First sampling and holding means for sampling a positive video signal supplied via one of the two data lines in a set and holding it for a certain period;
A second sampling and holding means for sampling and holding a negative video signal supplied via the other of the two data lines of a set and holding for a certain period;
The pixel having the positive video signal voltage held in the first sampling and holding means and the negative video signal voltage held in the second sampling and holding means are switched at a predetermined cycle shorter than the vertical scanning period. Switching means applied to the drive electrode;
A plurality of pixels each comprising:
A ramp signal that generates a positive polarity ramp signal and a negative polarity ramp signal that change continuously in one horizontal scanning period from one of the minimum value and the maximum value and whose level change directions are opposite to each other. Generating means;
The value of each pixel in one line of the digital video signal is compared with the counter value that changes monotonically from the minimum gradation value to the maximum gradation value within one horizontal scanning period, and the comparison result The potentials of the positive polarity ramp signal and the negative polarity ramp signal at the time of the coincidence are output as a positive polarity video signal and a negative polarity video signal, respectively, to a set of the data lines connected to the pixels having the same polarity. DA converting means for performing sampling and holding in the first and second sampling and holding means of the pixel in units of lines of the digital video signal;
A first voltage is generated and applied to the common electrode of the liquid crystal element in the plurality of pixels during the application period of the positive video signal voltage of the positive video signal voltage by the switching means, and the negative video A common electrode voltage generation unit configured to generate and apply a second voltage during an application period of the pixel drive electrode voltage of a signal voltage, and the common electrode voltage generation unit includes:
The image data of the gradation when the potential of the positive polarity ramp signal output to the desired pixel by the DA conversion means is equal to the potential of the negative polarity ramp signal is selected and selected. After detecting the DC potential of the common electrode at which light from the plurality of pixels obtained with the video data input as the digital video signal has at least the minimum illuminance, the positive electrode with respect to the potential related to the DC potential A third voltage that decreases stepwise from a lower value by an intermediate value between the maximum value and the minimum value of the sex ramp signal and the negative polarity ramp signal, and a fixed value from the higher value by the intermediate value. The fourth voltage, which is increased stepwise, is alternately switched and applied to the common electrode of the liquid crystal element as a square wave of the predetermined period, and the maximum gradation image data and the minimum gradation image data. Measuring the illuminance of light from the plurality of pixels when sequentially inputting the maximum allowable value by changing the maximum value of the positive polarity ramp signal and the negative polarity ramp signal step by step by a constant voltage. When the ratio of the first measured illuminance at the time of inputting the maximum gradation video data and the second measured illuminance at the time of inputting the minimum gradation video data is maximized. 3. A liquid crystal display device, wherein the third voltage and the fourth voltage are preset as the first voltage and the second voltage.   The common electrode voltage generating means is configured to use a first DC potential of the common electrode when the light from the plurality of pixels has the lowest illuminance and a second illuminance as the potential related to the DC potential. The liquid crystal display device according to claim 1, wherein an average value of the common electrode and the second DC potential is used. Each of a plurality of pixels provided at an intersection where a plurality of sets of data lines and a plurality of gate lines intersect each other with a set of two data lines,
A liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel drive electrode and a common electrode;
First sampling and holding means for sampling a positive video signal supplied via one of the two data lines in a set and holding it for a certain period;
A second sampling and holding means for sampling and holding a negative video signal supplied via the other of the two data lines of a set and holding for a certain period;
The pixel having the positive video signal voltage held in the first sampling and holding means and the negative video signal voltage held in the second sampling and holding means are switched at a predetermined cycle shorter than the vertical scanning period. Switching means applied to the drive electrode;
Each with
A ramp signal that generates a positive polarity ramp signal and a negative polarity ramp signal that change continuously in one horizontal scanning period from one of the minimum value and the maximum value and whose level change directions are opposite to each other. Generating means;
The value of each pixel in one line of the digital video signal is compared with the counter value that changes monotonically from the minimum gradation value to the maximum gradation value within one horizontal scanning period, and the comparison result The potentials of the positive polarity ramp signal and the negative polarity ramp signal at the time of the coincidence are output as a positive polarity video signal and a negative polarity video signal, respectively, to a set of the data lines connected to the pixels having the same polarity. The first and second sampling and holding means of the pixel sample and hold the DA in a unit of line of the digital video signal. A method of setting a common electrode voltage applied to a common electrode of a liquid crystal element,
A first selection of video data of a gradation when the potential of the positive polarity ramp signal output to the desired pixel by the DA conversion means is equal to the potential of the negative polarity ramp signal. Steps,
A second step of detecting a DC potential of the common electrode at which light from the plurality of pixels obtained in a state in which the video data selected in the first step is input as the digital video signal;
Step by step from a value lower than an intermediate value between the maximum value and the minimum value of the positive polarity ramp signal and the negative polarity ramp signal with respect to the potential related to the DC potential detected in the second step. A first voltage to be lowered and a second voltage to be increased stepwise from the higher value by the intermediate value are alternately switched and applied to the common electrode of the liquid crystal element as the square wave of the predetermined period. A third step of measuring the illuminance of light from the plurality of pixels when the maximum gradation image data and the minimum gradation image data are sequentially input in a state where
A fourth step of repeating the first to third steps by raising the maximum value of the positive polarity ramp signal and the negative polarity ramp signal by a constant voltage until the maximum value reaches an allowable maximum value. When,
After the repetition of the first to third steps in the fourth step, the first measured illuminance and the minimum gradation when video data of the maximum gradation obtained by the third step is input. The first voltage and the second voltage when the ratio to the second measured illuminance at the time of video data input is maximized are the low level of the common electrode voltage that is a square wave of the predetermined period. A fifth step of setting as a high level;
A method for setting a common electrode voltage for a liquid crystal display device.   In the third step, as the potential related to the DC potential detected in the second step, the first DC potential of the common electrode when the light from the plurality of pixels is the lowest illuminance, and the second 4. The common electrode voltage setting method for a liquid crystal display device according to claim 3, wherein an average value with the second DC potential of the common electrode at low illuminance is used.

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