JP5402964B2 - Mutual monitoring system, management device and system - Google Patents

Description

  The present invention relates to a mutual monitoring system, and more particularly to a mutual monitoring system that monitors the mutual operation between a plurality of systems that operate based on clock signals.

  The present invention also relates to a management apparatus that monitors the operation of a system that operates in accordance with a certain clock signal and a system that operates in accordance with another clock signal, housed in one housing. .

  The present invention also relates to a system in which operations are mutually monitored among a plurality of systems which are arranged so as to be communicable with each other via a data bus or a network and which operate based on clock signals.

  Conventionally, as this type of mutual monitoring system, for example, as described in Patent Document 1 (Japanese Patent Application Laid-Open No. 8-305664), a pair of CPUs (central control units) each operating based on a specific clock signal having substantially the same period. It is known that an arithmetic processing unit) always monitors to execute loop processing with the same loop time that is mutually common.

  However, such a mutual monitoring system has a problem in that monitoring cannot be performed unless the CPUs are operating normally, and monitoring cannot always be performed, and the configuration for monitoring becomes complicated.

JP-A-8-305664

  SUMMARY OF THE INVENTION An object of the present invention is to provide a mutual monitoring system capable of constantly monitoring operations with a simple configuration among a plurality of systems that operate based on clock signals.

  Another object of the present invention is to operate each other with a simple configuration between a system operating based on a certain clock signal and a system operating based on another clock signal housed in one housing. It is to provide a management device capable of constantly monitoring the above.

  Another object of the present invention is to constantly operate each other with a simple configuration between a plurality of systems that are arranged to be communicable with each other via a data bus or a network and that operate based on clock signals. It is to provide a system that can be monitored.

In order to solve the above problems, the mutual monitoring system of the present invention is:
When a natural number from 1 to n (n is a natural number of 2 or more) is represented by i,
I-th power supply for supplying power,
An i-th clock signal generation unit that generates an i-th clock signal using power from the i-th power source, and an i-th operation unit that operates based on the i-th clock signal generated by the i-th clock signal generation unit. ,
The j-th clock signal other than the i-th clock signal from the first clock signal to the n-th clock signal (j is a natural number other than i among the natural numbers from 1 to n) is monitored. An i-th abnormality detecting unit for detecting an abnormality of the j-th clock signal based on the clock pattern of the j-th clock signal ,
The j-th operation unit for the natural number j variably sets the clock pattern of the j-th clock signal so as to represent the operation content of the j-th operation unit,
The i-th abnormality detection unit monitors the j-th clock signal variably set by the j-th operation unit .

In the mutual monitoring system of the present invention, for each natural number i, the i-th clock signal generator generates the i-th clock signal using the power from the i-th power supply. The i-th abnormality detection unit monitors a j-th clock signal other than the i-th clock signal from the first clock signal to the n-th clock signal, and detects an abnormality of the j-th clock signal. Thereby, between a plurality of systems that operate based on the clock signal, for example, a system that includes the i-th clock signal generation unit and the i-th operation unit, and a system that includes the j-th clock signal generation unit and the j-th operation unit, It is possible to constantly monitor each other's operation. The i-th abnormality detection unit that detects an abnormality of the clock signal (j-th clock signal) can be configured by a simple electronic circuit without using a CPU (Central Processing Unit) or software. Therefore, according to the mutual monitoring system of the present invention, the operations can be constantly monitored with a simple configuration.
In the mutual monitoring system, the i-th abnormality detection unit detects the abnormality based on the clock pattern of the j-th clock signal. Therefore, the i-th abnormality detection unit can be configured by a simple electronic circuit without using a CPU (Central Processing Unit) or software.
In this mutual monitoring system, the j-th operation unit for the natural number j variably sets the clock pattern of the j-th clock signal so as to represent the operation content of the j-th operation unit. The i-th abnormality detection unit monitors the j-th clock signal variably set by the j-th operation unit. Therefore, the i-th abnormality detection unit can detect the operation content of the j-th operation unit based on the clock pattern of the j-th clock signal. For example, if the operation content of the j-th operation unit is abnormal, the i-th abnormality detection unit can detect an abnormality related to the operation content of the j-th operation unit.

In the mutual monitoring system of one embodiment, the i-th abnormality detection unit is configured to perform the operation based on the clock pattern of the j-th clock signal varied by the j-th operation unit when the j-th operation unit is operating. While detecting an abnormality related to the operation content of the j-th operation unit, when the j-th operation unit is inactive, based on the clock pattern of the fixed j-th clock signal that is not changed by the j-th operation unit An abnormality of the j-th clock signal generation unit that should generate the j-th clock signal is detected.

In the mutual monitoring system of this one embodiment, the i-th abnormality detection unit includes the j-th system including the j-th operation unit and the j-th clock signal generation unit regardless of whether the j-th operation unit operates or not. Abnormalities can be detected.

  In the mutual monitoring system according to an embodiment, the i-th abnormality detection unit detects the abnormality based on non-occurrence of the j-th clock signal or missing pulses.

  In the mutual monitoring system according to the embodiment, the i-th abnormality detection unit detects the abnormality based on the absence of the j-th clock signal or the lack of a pulse. Therefore, the i-th abnormality detection unit can be configured by a simple electronic circuit without using a CPU (Central Processing Unit) or software.

  This is particularly beneficial when the j-th operation unit includes a j-th central processing unit operated by software. That is, when the j-th operation unit includes the j-th central processing unit that is operated by software, various complicated operations are usually executed. Therefore, it is desired to detect the operation content of the j-th operation unit. This is because there is a strong need.

In the mutual monitoring system of one embodiment,
N is a natural number of 3 or more,
The i-th abnormality detection unit monitors some or all of the j-th clock signals other than the i-th clock signal among the first to n-th clock signals.

  In the mutual monitoring system of this one embodiment, the operation can be constantly monitored between three or more systems each operating based on a clock signal.

  In the mutual monitoring system according to an embodiment, the i-th abnormality detection unit constantly monitors the j-th clock signal.

  In the mutual monitoring system of this one embodiment, the i-th abnormality detection unit constantly monitors the j-th clock signal. Therefore, it is possible to notify the user of the occurrence of abnormality in real time.

  In the mutual monitoring system of one embodiment, the i-th abnormality detection unit periodically monitors the j-th clock signal for each predetermined period.

  In the mutual monitoring system of this embodiment, the i-th abnormality detecting unit periodically monitors the j-th clock signal for a predetermined period. Therefore, power saving can be achieved as compared with the case of constant monitoring.

In the mutual monitoring system of one embodiment,
For each natural number i, the i-th operation unit includes an i-th central processing unit operated by software,
The i-th abnormality detection unit monitors the j-th clock signal when the i-th central processing unit is inactive or not in operation.

  “Operation” by software includes various operations such as an operation for controlling a device based on a signal from a sensor and a recovery process for removing an abnormality and restoring it to a normal state.

  In the mutual monitoring system of this embodiment, for each natural number i, the i-th operation unit includes an i-th central processing unit operated by software. Therefore, the i-th operation unit can execute various complicated operations. In addition, the i-th abnormality detection unit monitors the j-th clock signal when the i central processing unit is inactive or not. Therefore, it is possible to notify the user of the occurrence of abnormality in real time.

  In the mutual monitoring system of one embodiment, the i-th abnormality detection unit outputs a j-th clock abnormality signal indicating that the abnormality has occurred in the j-th clock signal when detecting an abnormality of the j-th clock signal. It is characterized by doing.

  In the mutual monitoring system of this one embodiment, when the i th abnormality detection unit detects an abnormality of the j th clock signal, the i th clock abnormality signal indicating that the abnormality has occurred in the j th clock signal. Output. Therefore, it is possible to notify the user of the occurrence of abnormality. In addition, based on the j-th clock abnormality signal, a recovery process for removing the abnormality and restoring the normal state can be performed on the system including the j-th clock signal generation unit and the j-th operation unit.

  In the mutual monitoring system of one embodiment, when the i-th abnormality detection unit outputs the j-th clock abnormality signal, the i-th operation unit includes a j-th clock signal generation unit that should generate the j-th clock signal. It is characterized in that the control for temporarily stopping and restarting is executed.

  The abnormality of the j-th clock signal may occur based on a factor of only the j-th clock signal generation unit. Here, in the mutual monitoring system according to the embodiment, when the i-th abnormality detection unit outputs the j-th clock abnormality signal, the i-th operation unit generates the j-th clock signal. Control is performed to stop and restart the signal generator. Therefore, there is a possibility that the abnormality can be removed and recovered without temporarily stopping the j-th operation unit.

  In the mutual monitoring system of one embodiment, the i-th operation unit restarts the j-th clock signal generation unit, and when the i-th abnormality detection unit further outputs the j-th clock abnormality signal, Control is performed to temporarily stop and restart the j-th operation unit that operates based on the j-th clock signal.

  After the j-th clock signal generator is restarted, when the i-th abnormality detection unit further outputs the j-th clock abnormality signal, the j-th operation unit, not the j-th clock signal generation unit, is abnormal. This is likely to be a factor. Here, in the mutual monitoring system of this one embodiment, when the i-th operation unit restarts the j-th clock signal generation unit and further detects an abnormality in the j-th clock signal, Control for temporarily stopping and restarting the j-th operation unit that operates based on the clock signal is executed. Therefore, there is a possibility that the abnormal factor related to the j-th operation unit can be removed and recovered.

  In the mutual monitoring system of one embodiment, the i-th power supply, the i-th clock signal generation unit, the i-th operation unit, and the i-th abnormality detection unit for all the natural numbers i from 1 to n are: It is mounted on a common substrate.

  According to the mutual monitoring system of this embodiment, the mutual monitoring system can be constructed with one board.

  The mutual monitoring system of one embodiment is characterized in that some or all of the i-th power sources for all the natural numbers i from 1 to n are common.

  In the mutual monitoring system of this embodiment, since some of the i-th power sources for all the natural numbers i from 1 to n are common, power sources are individually supplied for all the natural numbers i. The number of power supplies can be reduced as compared with the case where is provided.

The management device of this invention is
In one case,
Based on a first power supply for supplying power, a first clock signal generator for generating a first clock signal using power from the first power supply, and a first clock signal generated by the first clock signal generator A first operating part that operates;
Based on a second power supply for supplying power, a second clock signal generator for generating a second clock signal using the power from the second power supply, and a second clock signal generated by the second clock signal generator A second operating part that operates;
A first abnormality detection unit that monitors the second clock signal and detects an abnormality of the second clock signal based on a clock pattern of the second clock signal;
A second abnormality detector that monitors the first clock signal and detects an abnormality of the first clock signal based on a clock pattern of the first clock signal ;
The first operation unit variably sets the clock pattern of the first clock signal so as to represent the operation content of the first operation unit,
The second operation unit variably sets the clock pattern of the second clock signal so as to represent the operation content of the second operation unit,
The first abnormality detection unit monitors the second clock signal variably set by the second operation unit,
The second abnormality detection unit monitors the first clock signal variably set by the first operation unit .

In the management device of the present invention, the first clock signal generation unit and the second clock signal generation unit generate the first clock signal and the second clock signal, respectively, using the power from the first power source and the second power source, respectively. The first abnormality detection unit monitors the second clock signal and detects an abnormality of the second clock signal. The second abnormality detection unit monitors the first clock signal and detects an abnormality of the first clock signal. Thereby, it is possible to constantly monitor the mutual operation between the system including the first clock signal generation unit and the first operation unit and the system including the second clock signal generation unit and the second operation unit. The first abnormality detection unit and the second abnormality detection unit can be configured by a simple electronic circuit without using a CPU (Central Processing Unit) or software. Therefore, according to the management device of the present invention, it is possible to constantly monitor the mutual operation with a simple configuration.
In this management device, the first abnormality detection unit detects an abnormality of the second clock signal based on the clock pattern of the second clock signal, and the second abnormality detection unit detects the first clock signal. The abnormality of the first clock signal is detected based on the clock pattern. Therefore, the first abnormality detection unit and the second abnormality detection unit can be configured by a simple electronic circuit without using a CPU (Central Processing Unit) or software.
In the management apparatus, the first operation unit variably sets the clock pattern of the first clock signal so as to represent the operation content of the first operation unit, and the second operation unit includes: The clock pattern of the second clock signal is variably set so as to represent the operation content of the second operation unit. The first abnormality detection unit monitors the second clock signal variably set by the second operation unit, and the second abnormality detection unit is variably set by the first operation unit. The set first clock signal is monitored. Therefore, the first abnormality detection unit can detect the operation content of the second operation unit based on the clock pattern of the second clock signal, and the second abnormality detection unit can detect the first clock. The operation content of the first operation unit can be detected based on the clock pattern of the signal. For example, if the operation content of the second operation unit is abnormal, the first abnormality detection unit can detect an abnormality related to the operation content of the second operation unit. If the operation content of the first operation unit is abnormal, the second abnormality detection unit can detect an abnormality related to the operation content of the first operation unit.
In addition, since the management apparatus accommodates the mutual monitoring system in one housing, the mutual monitoring system can be easily installed at various locations by transporting and moving the management apparatus.

The system of this invention
When a natural number from 1 to n (n is a natural number greater than or equal to 2) is represented by i, the i-th power source that supplies power, and the i-th clock signal is generated using the power from the i-th power source. an i-clock signal generation unit, and an i-th operation unit that operates based on the i-th clock signal generated by the i-th clock signal generation unit,
The j-th clock signal other than the i-th clock signal from the first clock signal to the n-th clock signal (j is a natural number other than i among the natural numbers from 1 to n) is monitored. An i-th abnormality detecting unit for detecting an abnormality of the j-th clock signal based on the clock pattern of the j-th clock signal,
The j-th operation unit for the natural number j variably sets the clock pattern of the j-th clock signal so as to represent the operation content of the j-th operation unit,
The i-th abnormality detection unit monitors the j-th clock signal variably set by the j-th operation unit,
Some or all of the i-th operation unit and the i-th abnormality detection unit for all the natural numbers i from 1 to n are distributed in a communicable manner via a data bus or a network. It is characterized by being.

In the system of the present invention, for each natural number i, the i-th clock signal generator generates the i-th clock signal using the power from the i-th power supply. The i-th abnormality detection unit monitors a j-th clock signal other than the i-th clock signal from the first clock signal to the n-th clock signal, and detects an abnormality of the j-th clock signal. Thereby, between a plurality of systems that operate based on the clock signal, for example, a system that includes the i-th clock signal generation unit and the i-th operation unit, and a system that includes the j-th clock signal generation unit and the j-th operation unit, It is possible to constantly monitor each other's operation. The i-th abnormality detection unit that detects an abnormality of the clock signal (j-th clock signal) can be configured by a simple electronic circuit without using a CPU (Central Processing Unit) or software. Therefore, according to the system of the present invention, the operations can be constantly monitored with a simple configuration.
In this management apparatus, the i-th abnormality detection unit detects the abnormality based on the clock pattern of the j-th clock signal. Therefore, the i-th abnormality detection unit can be configured by a simple electronic circuit without using a CPU (Central Processing Unit) or software.
In this management apparatus, the j-th operation unit for the natural number j variably sets the clock pattern of the j-th clock signal so as to represent the operation content of the j-th operation unit. The i-th abnormality detection unit monitors the j-th clock signal variably set by the j-th operation unit. Therefore, the i-th abnormality detection unit can detect the operation content of the j-th operation unit based on the clock pattern of the j-th clock signal. For example, if the operation content of the j-th operation unit is abnormal, the i-th abnormality detection unit can detect an abnormality related to the operation content of the j-th operation unit.
Further, in the system of the present invention, some or all of the i-th operation unit and the i-th abnormality detection unit for all the natural numbers i from 1 to n communicate with each other via a data bus or a network. Since it is distributed as possible, it can be adapted to a service-oriented architecture (SOA).

  In this specification, service-oriented architecture (SOA) refers to the concept of constructing the entire system by regarding the function of software corresponding to one process in business as a service and linking that service on the network. Means.

  As is clear from the above, according to the mutual monitoring system of the present invention, it is possible to constantly monitor the mutual operation with a simple configuration between a plurality of systems that operate based on the clock signal.

  Further, according to the management device of the present invention, a simple configuration between a system operating based on a certain clock signal and a system operating based on another clock signal accommodated in one housing is possible. It is possible to constantly monitor each other's operation.

  In addition, according to the system of the present invention, a plurality of systems that are arranged so as to be communicable with each other via a data bus or a network and that operate based on clock signals can operate with a simple configuration. Can be monitored at any time.

It is a figure which shows the structure of the mutual monitoring system of one Embodiment of this invention. It is a figure which shows the structure of the mutual monitoring system of another embodiment of this invention. It is a figure which shows the structure of the mutual monitoring system of another embodiment of this invention. FIG. 4A is a diagram illustrating a fixed clock pattern with a duty ratio of 50% and the contents represented by the pattern. FIG. 4B is a diagram illustrating a variable clock pattern with a duty ratio of 90% and the contents represented by the pattern. FIG. 4C is a diagram illustrating a variable clock pattern with a duty ratio of 10% and the contents represented by the pattern. FIG. 4D is a diagram illustrating a non-clock generation pattern and contents represented by the pattern. It is a figure which illustrates the circuit contained in the 1st abnormality detection part in FIG. It is a figure which illustrates the circuit contained in the 1st operation | movement part in FIG. It is a figure which illustrates the flow of a process by the 1st recovery process part in FIG. It is a figure which shows the structure of 1 board mutual monitoring system of one Embodiment which mounted the mutual monitoring system of FIG. 1 on one board | substrate. It is a figure which shows the structure of the management apparatus of one Embodiment which accommodated the mutual monitoring system of FIG. 3 in one housing | casing. It is a figure which shows the structure of the system of one Embodiment which applied the mutual monitoring system of FIG. 3 to the SOA world.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 shows a configuration of a mutual monitoring system (the whole is denoted by reference numeral Y1) according to an embodiment of the present invention.

  This mutual monitoring system Y1 is roughly divided into two systems, a first system G1 and a second system G2. The first system G1 includes a first power supply W1, a first clock signal generation unit CG1, a first operation unit M1, and a first abnormality detection unit D1. The second system G2 includes a second power supply W2, a second clock signal generation unit CG2, a second operation unit M2, and a second abnormality detection unit D2.

  In the first system G1, the first power supply W1 constantly supplies power. The first clock signal generator CG1 includes a commercially available crystal oscillator, and generates a periodic first clock signal CL1 using power from the first power supply W1. Since the first power supply W1 constantly supplies power, the first clock signal generator CG1 generates the first clock signal CL1 unless there is any abnormality. The first operation unit M1 operates based on the first clock signal CL1. The first abnormality detection unit D1 constantly monitors the second clock signal CL2 using the power from the first power supply W1, and indicates whether or not an abnormality has occurred in the second clock signal CL2. AS2 is output.

  In the second system G2, the second power source W2 always supplies power. The second clock signal generator CG2 includes a commercially available crystal oscillator, and generates a periodic second clock signal CL2 using power from the second power supply W2. Since the second power source W2 constantly supplies power, the second clock signal generator CG2 generates the second clock signal CL2 unless there is any abnormality. The second operation unit M2 operates based on the second clock signal CL2. The second abnormality detection unit D2 constantly monitors the first clock signal CL1 using the power from the second power supply W2, and indicates whether or not an abnormality has occurred in the first clock signal CL1. AS1 is output.

  In this example, each of the first clock signal CL1 and the second clock signal CL2 is a rectangular wave that repeats a high (H) level and a low (L) level at a duty ratio of 50% as shown in FIG. It is assumed that it is a fixed clock (for example, 10 MHz). “Fixed clock” means a clock signal having a constant frequency.

  In this example, the first abnormality detection unit D1 shown in FIG. 1 includes a buffer amplifier 11, a smoothing circuit 12, and a differential amplifier 13 as components, as shown in FIG. The buffer amplifier 11 amplifies the second clock signal CL2 while maintaining its waveform, and also functions as a buffer, so that the operation of the subsequent smoothing circuit 12 is performed with respect to the second clock signal generator CG2 of the second system G2. To prevent influence. The smoothing circuit 12 includes an integrating circuit composed of a resistance element R and a capacitance element C, smoothes the second clock signal CL2 from the buffer amplifier 11, and has a DC level (DC () corresponding to the duty ratio of the second clock signal CL2. DC) voltage Vs2 is obtained. The differential amplifier 13 compares the DC voltage Vs2 from the smoothing circuit 12 with the reference voltage Vref, and determines whether the DC voltage Vs2 is at a high (H) level or a low (L) level with respect to the reference voltage Vref. A signal representing is output. Here, the reference voltage Vref is created by dividing the voltage of the power from the first power supply W1 by a series resistor, and is set between the DC voltage Vs2 and the ground potential GND (= 0). That is, Vs2> Vref> 0 is set. With this configuration, the first abnormality detection unit D1 has a case where a fixed clock (second clock signal CL2) with a duty ratio of 50% shown in FIG. The case where the fixed clock shown in () is not generated (abnormal) is identified. The first abnormality detection unit D1 outputs a signal of logical value 0 representing normality as the second clock monitoring signal AS2 during the period in which the second clock signal CL2 is normally generated, and the second clock signal CL2 is not generated In this period, a signal of a logical value 1 (second clock abnormality signal) representing abnormality is output as the second clock monitoring signal AS2. In addition, as the above-described buffer amplifier 11 and differential amplifier 13 of the first abnormality detection unit D1, commercially available operational amplifiers (op-amps) can be used.

  The second abnormality detection unit D2 also includes the same components as those in the first abnormality detection unit D1. Accordingly, the second abnormality detection unit D2 also has the fixed clock shown in FIG. 4D when the fixed clock (first clock signal CL1) shown in FIG. The case of occurrence (abnormal case) is identified. While the first clock signal CL1 is normally generated, the second abnormality detection unit D2 outputs a signal having a logical value 0 representing normality as the first clock monitoring signal AS1, while the first clock signal CL1 is not During the generation period, a signal having a logical value of 1 (first clock abnormality signal) indicating abnormality is output as the first clock monitoring signal AS1.

  In this example, as shown in FIG. 6, the first operation unit M1 shown in FIG. 1 includes a frequency dividing circuit 16, an LED (light emitting diode) driving circuit 17, and an LED lamp 18 as components. Contains. The frequency dividing circuit 16 divides the first clock signal CL1 to generate a fixed clock signal CLL1 of 1 Hz in this example. The LED drive circuit 17 uses the fixed clock signal CLL1 from the frequency divider circuit 16 according to the signal during the period of receiving the signal of the logical value 1 representing the abnormality as the second clock monitoring signal AS2. The drive current If1 is supplied to the. This causes the LED lamp 18 to blink at a frequency of 1 Hz. On the other hand, the LED drive circuit 17 keeps the LED lamp 18 off during a period of receiving a signal of logical value 0 representing normality as the second clock monitoring signal AS2. In this way, the first operation unit M1 notifies the user that an abnormality has occurred in the second system G2. Note that a commercially available frequency divider is used as the frequency divider circuit 16 of the first operation unit M1, a commercially available LED drive IC (integrated circuit) is used as the LED drive circuit, and a commercially available LED element is used as the LED lamp 18. be able to.

  Although not shown for simplicity, the second operation unit M2 also includes a frequency dividing circuit 16, an LED drive circuit 17, and an LED lamp 18, similarly to the first operation unit M1. Therefore, the LED lamp 18 blinks at a frequency of 1 Hz during a period in which the second operation unit M2 receives a signal having a logical value 1 representing an abnormality as the first clock monitoring signal AS1. On the other hand, the LED lamp 18 remains off during the period in which the second operation unit M2 receives a signal of logical value 0 representing normality as the second clock monitoring signal AS2. In this way, the second operation unit M2 notifies the user that an abnormality has occurred in the first system G1.

  In this example, it is assumed that the first operating unit M1 and the second operating unit M2 operate by constantly receiving power from the first power source W1 and the second power source W2, respectively.

  The mutual monitoring system Y1 operates as follows as a whole. That is, the first abnormality detection unit D1 constantly monitors the second clock signal CL2 using the power from the first power supply W1. On the other hand, the second abnormality detection unit D2 constantly monitors the first clock signal CL1 using the power from the second power supply W2. Thereby, it is possible to constantly monitor the operation between the first system G1 and the second system G2. As described above, both the first abnormality detection unit D1 and the second abnormality detection unit D2 can be configured by a simple electronic circuit without using a CPU or software. Therefore, according to this mutual monitoring system Y1, it is possible to constantly monitor the mutual operation with a simple configuration.

  In this example, when the second clock signal CL2 is not generated in the second system G2 and an abnormality occurs, the first abnormality detection unit D1 in the first system G1 serves as the second clock monitoring signal AS2. A signal having a logical value 1 representing abnormality is output, and the first operating unit M1 causes the LED lamp 18 to blink at a frequency of 1 Hz. On the other hand, if the first clock signal CL1 is not generated in the first system G1 and an abnormality occurs, the second abnormality detection unit D2 in the second system G2 represents the abnormality as the first clock monitoring signal AS1. A signal of value 1 is output, and the second operation unit M2 causes the LED lamp 18 to blink at a frequency of 1 Hz. Therefore, the user can easily recognize in real time that an abnormality has occurred in the second system G2 due to the blinking of the LED lamp 18 of the first operation unit M1 of the first system G1, and the second system G2 It can be easily recognized in real time that an abnormality has occurred in the first system G1 by the blinking of the LED lamp 18 of the second operation unit M2.

  Each of the first abnormality detection unit D1 and the second abnormality detection unit D2 includes a latch circuit (not shown). When an abnormality such as a missing single pulse occurs in the second clock signal CL2 and the first clock signal CL1, for example, the first abnormality detection unit D1 and the second abnormality detection unit D2 are each at least performed by the latch circuit. The logical values of the second clock monitoring signal AS2 and the first clock monitoring signal AS1 are maintained at 1 for only 1 second. Therefore, even if an abnormality such as a single missing pulse occurs, the user can easily recognize that the abnormality has occurred by the blinking of the LED lamp 18.

  In the above example, the first abnormality detection unit D1 constantly monitors the second clock signal CL2, and the second abnormality detection unit D2 constantly monitors the first clock signal CL1. However, the timer for setting the period may be provided so that the first abnormality detection unit D1 may periodically monitor the second clock signal CL2 for each predetermined period, and the second abnormality detection unit D2 may monitor the first clock signal CL1. You may monitor regularly for every predetermined period. Thereby, power saving can be achieved compared with the case of always monitoring.

  The first operation unit M1 and the second operation unit M2 are power sources other than the first power source W1 and the second power source W2, respectively, for example, power sources that supply / non-supply power according to the on / off of the start switch. It may be operated by receiving power supply from “start-up power supply”.

  Further, the first operation unit M1 and the second operation unit M2 are not limited to the circuit shown in FIG. 6 and include, for example, a piezoelectric buzzer, and an abnormality occurs to the user due to an alarm sound generated by the piezoelectric buzzer. It may be configured to notify that.

  Further, the first operation unit M1 and the second operation unit M2 are not limited to the circuit shown in FIG. 6 and include a CPU that operates by software, and various devices, for example, devices based on signals from sensors. You may perform the operation | movement to control, the recovery process which removes abnormality, and restores to a normal state.

(Second Embodiment)
FIG. 2 shows the configuration of a mutual monitoring system (indicated by the symbol Y2) of another embodiment of the present invention. For simplicity, elements corresponding to those in FIG. 1 are denoted by the same reference numerals (the same applies hereinafter).

  This mutual monitoring system Y2 is roughly divided into a total of four systems: a first system G1, a second system G2, a third system G3, and a fourth system G4. The first system G1 includes a first power supply W1, a first clock signal generation unit CG1, a first operation unit M1, and a first abnormality detection unit D1, as in FIG. The second system G2 includes a second power supply W2, a second clock signal generation unit CG2, a second operation unit M2, and a second abnormality detection unit D2. The third system G3 includes a third power supply W3, a third clock signal generation unit CG3, a third operation unit M3, and a third abnormality detection unit D3. The fourth system G4 includes a fourth power supply W4, a fourth clock signal generation unit CG4, a fourth operation unit M4, and a fourth abnormality detection unit D4.

  The third power source W3 of the third system G3 and the fourth power source W4 of the fourth system G4 are respectively the same as the first power source W1 of the first system G1 and the second power source W2 of the second system G2. Is always supplied. The third clock signal generation unit CG3 of the third system G3 and the fourth clock signal generation unit CG4 of the fourth system G4 use the power from the third power supply W3 and the fourth power supply W4, respectively. A clock signal CL3 and a fourth clock signal CL4 are generated.

  In this example, the first abnormality detection unit D1 of the first system G1 includes three sets of the circuit shown in FIG. By these three sets of circuits, the second clock signal CL2 from the second clock signal generator CG2 of the second system G2, and the third clock signal from the third clock signal generator CG3 of the third system G3, respectively. CL3 and the fourth clock signal CL4 from the fourth clock signal generator CG4 of the fourth system G4 are constantly monitored. The first abnormality detection unit D1 includes a second clock monitoring signal AS2 and a third clock monitoring signal that indicate whether an abnormality has occurred in the second clock signal CL2, the third clock signal CL3, and the fourth clock signal CL4, respectively. AS3 and the fourth clock monitoring signal AS4 are output.

  Further, the first operation unit M1 of the first system G1 includes three sets of the circuit shown in FIG. Each of these three sets of circuits receives a logical value 1 signal representing an abnormality as the third clock monitoring signal AS3 while receiving a logical value 1 signal representing the abnormality as the second clock monitoring signal AS2. During the period, during the period in which the signal of logical value 1 representing abnormality is received as the fourth clock monitoring signal AS4, the LED lamp 18 is blinked at a frequency of 1 Hz.

  Further, the second abnormality detection unit D2 of the second system G2 includes three sets of the circuits shown in FIG. 5, similarly to the first abnormality detection unit D1 of the first system G1. By these three sets of circuits, the first clock signal CL1 from the first clock signal generator CG1 of the first system G1 and the third clock signal from the third clock signal generator CG3 of the third system G3, respectively. CL3 and the fourth clock signal CL4 from the fourth clock signal generator CG4 of the fourth system G4 are constantly monitored. The second abnormality detection unit D2 includes a first clock monitoring signal AS1 and a third clock monitoring signal that indicate whether or not an abnormality has occurred in the first clock signal CL1, the third clock signal CL3, and the fourth clock signal CL4, respectively. AS3 and the fourth clock monitoring signal AS4 are output.

  Further, the second operation unit M2 of the second system G2 includes three sets of the circuit shown in FIG. Each of these three sets of circuits receives a logical value 1 signal representing an abnormality as the third clock monitoring signal AS3, while receiving a logical value 1 signal representing the abnormality as the first clock monitoring signal AS1. During the period, during the period in which the signal of logical value 1 representing abnormality is received as the fourth clock monitoring signal AS4, the LED lamp 18 is blinked at a frequency of 1 Hz.

  Further, the third abnormality detection unit D3 of the third system G3 includes two sets of the circuits shown in FIG. By these two sets of circuits, the second clock signal CL2 from the second clock signal generator CG2 of the second system G2 and the fourth clock signal from the fourth clock signal generator CG4 of the fourth system G4, respectively. CL4 is constantly monitored. Then, the third abnormality detection unit D3 outputs a second clock monitoring signal AS2 and a fourth clock monitoring signal AS4 that indicate whether or not an abnormality has occurred in the second clock signal CL2 and the fourth clock signal CL4, respectively.

  Further, the third operation unit M3 of the third system G3 includes two sets of the circuit shown in FIG. By these two sets of circuits, a logical value 1 signal indicating abnormality is received as the fourth clock monitoring signal AS4 during a period of receiving a logical value 1 signal indicating abnormality as the second clock monitoring signal AS2. During the period, the LED lamp 18 is blinked at a frequency of 1 Hz.

  Further, the fourth abnormality detection unit D4 of the fourth system G4 includes one set of the circuits shown in FIG. The third clock signal CL3 from the third clock signal generator CG3 of the third system G3 is constantly monitored by the one set of circuits. Then, the fourth abnormality detection unit D4 outputs a third clock monitoring signal AS3 indicating whether or not an abnormality has occurred in the third clock signal CL3.

  The fourth operating unit M4 of the fourth system G4 includes one set of the circuit shown in FIG. The LED lamp 18 blinks at a frequency of 1 Hz during a period in which the set of circuits receives a signal of logical value 1 representing an abnormality as the third clock monitoring signal AS3.

  Thus, in this mutual monitoring system Y2, there are three or more systems (in this example, the first system G1, the second system G2, the third system G3, and the fourth system G4). The operation can be monitored constantly. In addition, the first abnormality detection unit D1, the second abnormality detection unit D2, the third abnormality detection unit D3, and the fourth abnormality detection unit D4 can all be configured by a simple electronic circuit without using a CPU or software. Therefore, according to this mutual monitoring system Y2, it is possible to constantly monitor the mutual operation with a simple configuration.

  In the above example, the third abnormality detection unit D3 monitors only two clock signals, the second clock signal CL2 and the fourth clock signal CL4, and the fourth abnormality detection unit D4 monitors only the third clock signal CL3. It was supposed to be monitored. However, when a natural number from 1 to n (n is a natural number greater than or equal to 2; in this example, n = 4) is represented by i, the i-th abnormality detection unit starts from the first clock signal to the n-th clock. All the j-th clock signals other than the i-th clock signal among the signals (j is a natural number other than i among the natural numbers from 1 to n) may be monitored.

  The first operating unit M1, the second operating unit M2, the third operating unit M3, and the fourth operating unit M4 are power sources other than the first power source W1, the second power source W2, the third power source W3, and the fourth power source W4, respectively. For example, you may operate | move by receiving electric power supply from the starting power supply which supplies / does not supply electric power according to ON / OFF of the starting switch.

  Further, the first operation unit M1, the second operation unit M2, the third operation unit M3, and the fourth operation unit M4 are not limited to the circuit shown in FIG. You may be comprised so that it may alert | report.

  Further, the first operation unit M1, the second operation unit M2, the third operation unit M3, and the fourth operation unit M4 are not limited to the circuit shown in FIG. 6, and include various CPUs that operate by software. An operation, for example, an operation for controlling the device based on a signal from the sensor, a recovery process for removing the abnormality and restoring the normal state, or the like may be performed.

  Also, some or all of the i-th power supplies (in the above example, the first power supply W1, the second power supply W2, the third power supply W3, and the fourth power supply W4) for all natural numbers i from 1 to n are , May be common. In that case, the number of power supplies can be reduced as compared with the case where power supplies are provided individually.

(Third embodiment)
FIG. 3 shows the configuration of a mutual monitoring system (indicated by the symbol Y3) of still another embodiment of the present invention.

  This mutual monitoring system Y3 is roughly divided into two systems, a first system G1 and a second system G2, similar to the mutual monitoring system Y1 of FIG. The first system G1 includes a first power supply W1, a first clock signal generation unit CG1, a first operation unit M1, a first activation power supply U1, and a first abnormality detection unit D1. The second system G2 includes a second power supply W2, a second clock signal generation unit CG2, a second operation unit M2, a second activation power supply U2, and a second abnormality detection unit D2.

  In the first system G1, the first power supply W1 constantly supplies power. The first start-up power supply U1 supplies / not supplies power according to on / off of a start switch (not shown).

  The first clock signal generator CG1 includes a commercially available crystal oscillator, and generates a periodic first clock signal CL1 using power from the first power supply W1. Since the first power supply W1 constantly supplies power, the first clock signal generator CG1 generates the first clock signal CL1 unless there is any abnormality. The clock pattern of the first clock signal CL1 is variably set by a first control signal CM1 output from the first CPU 15 during a period in which a later-described first CPU 15 included in the first operation unit M1 is operating. During the period in which the first CPU 15 is operating, the first clock signal generator CG1 outputs the first clock signal CL1 ′ set variably.

  In this example, the first operation unit M1 includes a first abnormality notification unit 10 that operates by always receiving power from the first power supply W1, and a first CPU 15 that operates by receiving power supply from the first activation power supply U1. It is out.

  The first abnormality notification unit 10 is composed of a set of circuits shown in FIG. 6, and the LED lamp 18 is turned on at a frequency of 1 Hz during a period in which a signal of logical value 1 representing abnormality is received as the second clock monitoring signal AS2. Blink. On the other hand, the first abnormality notification unit 10 keeps the LED lamp 18 off during a period of receiving a signal of logical value 0 representing normality as the second clock monitoring signal AS2.

  During a period when the activation switch is turned on by the user and the first activation power supply U1 supplies power, the first CPU 15 functions as a first clock pattern generation unit M11 and a first restoration processing unit M12 by software. That is, the first CPU 15 operates as the first clock pattern generation unit M11 and receives the first clock signal CL1 from the first clock signal generation unit CG1. Then, the first control signal CM1 is output to the first clock signal generation unit CG1, and the clock pattern of the first clock signal CL1 is variably set so as to represent the operation content of the first operation unit M1. As a result, as described above, the first clock signal generator CG1 outputs the variably set first clock signal CL1 ′. The operation of the first CPU 15 as the first restoration processing unit M12 will be described later. The first CPU 15 does not operate during a period when the start switch is turned off by the user and the first start power supply U1 is not supplying power.

  In this example, when the first CPU 15 included in the first operation unit M1 detects the normality of the first system G1, the first clock signal CL1 ′ has a duty ratio of 90% shown in FIG. Variable clock. When the first CPU 15 detects an abnormality of the first system G1, a variable clock having a duty ratio of 10% shown in FIG. During the period in which the first startup power supply U1 is not supplying power, the first CPU 15 is inactive, and the first clock signal CL1 ′ is a fixed clock (first clock having a duty ratio of 50% shown in FIG. 4A). Clock signal CL1).

  The first abnormality detection unit D1 is composed of a set of circuits shown in FIG. 5, and constantly monitors the second clock signal CL2 ′ using the power from the first power supply W1 to detect the second clock signal CL2 ′. Detect anomalies. Then, the first abnormality detection unit D1 outputs a second clock monitoring signal AS2 indicating whether or not an abnormality has occurred in the second clock signal CL2 ′.

  Specifically, in this example, the smoothing circuit 12 in FIG. 5 smoothes the second clock signal CL2 ′ from the buffer amplifier 11, and a DC voltage having a level corresponding to the duty ratio of the second clock signal CL2 ′. Get. The DC voltage when the second clock signal CL2 ′ is a variable clock with a duty ratio of 90% shown in FIG. The DC voltage when the second clock signal CL2 ′ is a fixed clock (first clock signal CL1) having a duty ratio of 50% shown in FIG. Further, the DC voltage when the second clock signal CL2 ′ is a variable clock having a duty ratio of 10% shown in FIG. These DC voltages have a relationship of Vs3> Vs2> Vs1. In this example, it is assumed that the reference voltage Vref is set to Vs3> Vs2> Vref> Vs1> 0. With this configuration, the first abnormality detection unit D1 has the duty ratio 50 shown in FIG. 4A in a state where the variable clock having the duty ratio of 90% shown in FIG. 4B or the first activation power supply U1 is not supplying power. % Fixed clock (second clock signal CL2) is generated (normal) and a variable clock with a duty ratio of 10% shown in FIG. 4C is generated or fixed clock shown in FIG. Is identified as a non-occurrence (abnormal case). The first abnormality detection unit D1 outputs a signal of logical value 0 representing normality as the second clock monitoring signal AS2 during the period in which the second clock signal CL2 ′ is normally generated, and the second clock signal CL2 ′ During an abnormal period, a signal having a logical value 1 representing abnormality is output as the second clock monitoring signal AS2. In this way, the first abnormality detection unit D1 of the first system G1 detects whether the operation content of the second operation unit M2 is normal or abnormal based on the clock pattern of the second clock signal CL2 ′. To do.

  Since the first abnormality detection unit D1 detects an abnormality based on the clock pattern of the second clock signal CL2 ′, the first abnormality detection unit D1 does not use a CPU (Central Processing Unit) or software, and does not use the circuit shown in FIG. It can be constituted by a simple electronic circuit.

  The second system G2 is configured substantially in the same manner as the first system G1.

  That is, in the second system G2, the second power source W2 always supplies power. The second start-up power supply U2 supplies / not supplies power according to on / off of a start switch (not shown).

  The second clock signal generator CG2 includes a commercially available crystal oscillator, and generates a periodic second clock signal CL2 using power from the second power supply W2. Since the second power source W2 constantly supplies power, the second clock signal generator CG2 generates the second clock signal CL2 unless there is any abnormality. The clock pattern of the second clock signal CL2 is variably set by a second control signal CM2 output from the second CPU 25 during a period in which a later-described second CPU 25 included in the second operation unit M2 is operating. During the period when the second CPU 25 is operating, the second clock signal generator CG2 outputs the second clock signal CL2 ′ set variably.

  In this example, the second operating unit M2 includes a second abnormality notifying unit 20 that operates by always receiving power from the second power source W2, and a second CPU 25 that operates by receiving power from the second activation power source U2. It is out.

  The second abnormality notification unit 20 includes the set of circuits shown in FIG. 6 similarly to the first abnormality notification unit 10, and a period during which a signal of logical value 1 representing abnormality is received as the second clock monitoring signal AS1. The LED lamp 18 is blinked at a frequency of 1 Hz. On the other hand, the second abnormality notification unit 20 keeps the LED lamp 18 off during a period in which a signal having a logical value of 0 representing normality is received as the second clock monitoring signal AS1.

  During the period when the activation switch is turned on by the user and the second activation power supply U2 supplies power, the second CPU 25 functions as a second clock pattern generation unit M21 and a second recovery processing unit M22 by software. That is, the second CPU 25 operates as the second clock pattern generation unit M21 and receives the second clock signal CL2 from the second clock signal generation unit CG2. Then, the second control signal CM2 is output to the second clock signal generation unit CG2, and the clock pattern of the second clock signal CL2 is variably set so as to represent the operation content of the second operation unit M2. As a result, as described above, the second clock signal generation unit CG2 outputs the second clock signal CL2 ′ set variably. The operation of the second CPU 25 as the second recovery processing unit M22 will be described later. The second CPU 25 does not operate during a period when the start switch is turned off by the user and the second start-up power supply U2 does not supply power.

  In this example, when the second CPU 25 included in the second operation unit M2 detects the normality of the second system G2, the second clock signal CL2 ′ has a duty ratio of 90% shown in FIG. Variable clock. When the second CPU 25 detects an abnormality in the second system G2, a variable clock having a duty ratio of 10% shown in FIG. During the period when the second startup power supply U2 is not supplying power, the second CPU 25 is inactive, and the second clock signal CL2 ′ is a fixed clock (second clock) having a duty ratio of 50% shown in FIG. Clock signal CL2).

  Similarly to the first abnormality detection unit D1, the second abnormality detection unit D2 is composed of a set of circuits shown in FIG. 5, and constantly monitors the first clock signal CL1 ′ using the power from the second power supply W2. Thus, the abnormality of the first clock signal CL1 ′ is detected. Then, the second abnormality detection unit D2 outputs a first clock monitoring signal AS1 indicating whether or not an abnormality has occurred in the first clock signal CL1 ′. The second abnormality detection unit D2 outputs a signal of logical value 0 representing normality as the first clock monitoring signal AS1 during the period when the first clock signal CL1 ′ is normally generated, and the first clock signal CL1 ′ During an abnormal period, a signal having a logical value 1 representing an abnormality is output as the first clock monitoring signal AS1.

  Since the second abnormality detection unit D2 detects an abnormality based on the clock pattern of the first clock signal CL1 ′, the second abnormality detection unit D2 does not use a CPU (Central Processing Unit) or software, and does not use the circuit shown in FIG. It can be constituted by a simple electronic circuit.

  The mutual monitoring system Y3 operates as follows as a whole.

  First, the first CPU 15 of the first operating unit M1 and the second CPU 25 of the second operating unit M2 do not operate during a period when the first startup power source U1 and the second startup power source U2 are not supplying power. In this case, the mutual monitoring system Y3 operates in the same manner as the mutual monitoring system Y1 in FIG.

  That is, in this case, the first abnormality detection unit D1 uses the power from the first power supply W1 to generate the second clock signal CL2 ′ (in this case, the duty ratio shown in FIG. 4A if normal). A 50% fixed clock (second clock signal CL2) is constantly monitored. On the other hand, the second abnormality detection unit D2 uses the power from the second power supply W2 to fix the first clock signal CL1 ′ (in this case, a duty ratio of 50% shown in FIG. 4A if normal). The clock (first clock signal CL1) is constantly monitored. Thereby, it is possible to constantly monitor the operation between the first system G1 and the second system G2.

  Further, an abnormality occurs in the second system G2 during the period in which the first startup power supply U1 and the second startup power supply U2 are not supplying power, and the second clock signal CL2 ′ (second clock signal CL2) is not generated. In this case, in the first system G1, the first abnormality detection unit D1 outputs a signal having a logical value 1 representing an abnormality as the second clock monitoring signal AS2, and the first abnormality notification unit 10 of the first operation unit M1. Flashes the LED lamp 18 at a frequency of 1 Hz. On the other hand, when an abnormality occurs in the first system G1 and the first clock signal CL1 ′ (first clock signal CL1) is not generated, the second abnormality detection unit D2 in the second system G2 detects the first clock. A signal of logical value 1 representing abnormality is output as the monitoring signal AS1, and the second abnormality notification unit 20 of the second operation unit M2 blinks the LED lamp 18 at a frequency of 1 Hz. Therefore, the user can easily recognize in real time that an abnormality has occurred in the second system G2 due to the blinking of the LED lamp 18 of the first operation unit M1 of the first system G1, and the second system G2 It can be easily recognized in real time that an abnormality has occurred in the first system G1 by the blinking of the LED lamp 18 of the second operation unit M2.

  Next, the first CPU 15 of the first operation unit M1 and the second CPU 25 of the second operation unit M2 operate during a period in which the first activation power supply U1 and the second activation power supply U2 supply power. In this case, if normal, the first clock signal CL1 ′ and the second clock signal CL2 ′ are both variable clocks having a duty ratio of 90% shown in FIG. The first abnormality detection unit D1 constantly monitors the second clock signal CL2 ′ using the power from the first power supply W1. On the other hand, the second abnormality detection unit D2 constantly monitors the first clock signal CL1 ′ using the power from the second power supply W2. Thereby, it is possible to constantly monitor the operation between the first system G1 and the second system G2.

  Further, an abnormality occurs in the second system G2 during the period in which the first start-up power supply U1 and the second start-up power supply U2 supply power, and the second clock signal CL2 ′ has a duty ratio of 10 shown in FIG. % Variable clock or non-occurrence, in the first system G1, the first abnormality detection unit D1 outputs a signal of logical value 1 representing abnormality as the second clock monitoring signal AS2, and the first operation unit M1 The first abnormality notification unit 10 causes the LED lamp 18 to blink at a frequency of 1 Hz. On the other hand, when an abnormality occurs in the first system G1 and the first clock signal CL1 ′ becomes a variable clock having a duty ratio of 10% shown in FIG. 4C or is not generated, the second system G2 The abnormality detection unit D2 outputs a signal having a logical value 1 representing the abnormality as the first clock monitoring signal AS1, and the second abnormality notification unit 20 of the second operation unit M2 blinks the LED lamp 18 at a frequency of 1 Hz. Therefore, the user can easily recognize in real time that an abnormality has occurred in the second system G2 due to the blinking of the LED lamp 18 of the first operation unit M1 of the first system G1, and the second system G2 It can be easily recognized in real time that an abnormality has occurred in the first system G1 by the blinking of the LED lamp 18 of the second operation unit M2.

  In particular, in the mutual monitoring system Y3, the first abnormality detection unit D1 and the second abnormality notification unit 20 are respectively connected to the second clock signal CL2 ′ and the first clock signal regardless of whether the first CPU 15 and the second CPU 25 operate or not. CL1 'is constantly monitored. Therefore, it is possible to notify the user of the occurrence of abnormality in real time.

  There may be a period in which one of the first startup power supply U1 and the second startup power supply U2 supplies power and the other does not supply power. For example, it is assumed that the first startup power supply U1 supplies power and the first CPU 15 is operating, but the second startup power supply U2 does not supply power and the second CPU 25 is stopped. In this case, the first abnormality detection unit D1 constantly monitors the second clock signal CL2 using the power from the first power supply W1. On the other hand, the second abnormality detection unit D2 constantly monitors the first clock signal CL1 ′ using the power from the second power supply W2. Conversely, if the first startup power supply U1 is not supplying power and the first CPU 15 is stopped, but the second startup power supply U2 is supplying power and the second CPU 25 is operating, the first abnormality is detected. The unit D1 constantly monitors the second clock signal CL2 ′ using the power from the first power supply W1. On the other hand, the second abnormality detection unit D2 constantly monitors the first clock signal CL1 using the power from the second power supply W2. Therefore, also in these cases, it is possible to notify the user of the occurrence of abnormality in real time.

  In this example, the first CPU 15 and the second CPU 25 use software to perform various operations such as an operation for controlling various devices based on signals from sensors, a recovery process for removing abnormalities and restoring a normal state, and the like. Can be executed.

  FIG. 7 shows that the first CPU 15 in FIG. 3 works as the first recovery processing unit M12 during the period when the first startup power supply U1 and the second startup power supply U2 supply power, and the second system G2 The process flow when performing a recovery process is illustrated.

  First, in step S1 in FIG. 7, the first CPU 15 is referred to as a signal of logical value 1 (hereinafter referred to as “second clock abnormality signal”) in which the first abnormality detection unit D1 indicates abnormality as the second clock monitoring signal AS2. ) Until it occurs.

  When the first abnormality detection unit D1 monitors the second clock signal CL2 ′ and outputs the second clock abnormality signal (YES in step S1), the first CPU 15 temporarily stops the second clock signal generation unit CG2 and restarts it. Start (step S2). This is because the abnormality of the second clock signal CL2 ′ may occur based on the factor of only the second clock signal generator CG2. Accordingly, there is a possibility that the abnormality can be removed and restored to the normal state by temporarily stopping the second CPU 25 by this step S2.

  After restarting the second clock signal generator CG2 in step S2, in step S3, the first CPU 15 checks again whether or not the first abnormality detector D1 has generated the second clock abnormality signal. Here, when the first abnormality detection unit D1 does not generate the second clock abnormality signal (NO in Step S1), that is, when the abnormality can be removed and restored to the normal state by Step S2, Step S7 described later is performed. Proceed to

  On the other hand, when the first abnormality detection unit D1 further outputs the second clock abnormality signal (YES in step S3), there is a high possibility that the second operation unit M2 (particularly, the second CPU 25) is an abnormality factor. Therefore, in step S4, the first CPU 15 temporarily stops and restarts the second CPU 25. Thereby, there is a possibility that the abnormal factor related to the second CPU 25 of the second operation unit M2 can be removed and recovered.

  After the second CPU 25 is restarted in step S4, in step S5, the first CPU 15 checks again whether or not the first abnormality detection unit D1 has generated the second clock abnormality signal. Here, when the first abnormality detection unit D1 does not generate the second clock abnormality signal (NO in step S5), that is, when the abnormality is removed and recovered by step S4, the process proceeds to step S7 described later.

  On the other hand, when the first abnormality detection unit D1 further outputs the second clock abnormality signal (YES in step S5), the first CPU 15 transmits a warning to the second operation unit M2 in this example in step S6. Alternatively, the second CPU 25 of the second operation unit M2 is stopped.

  Here, the “warning” to the second operation unit M2 means, for example, that the initial screen of the display unit (not shown) of the second operation unit M2 is “the computer has been restarted because an error has occurred, but the error has been removed. Not to display ". Instead, the reason for stopping the second CPU 25 of the second operation unit M2 is for safety.

  Thereafter, in step S7, the processing progress from step S1 to step S6 is recorded and stored in a storage device (not shown). And it returns to step S1 and continues monitoring.

  In the above example, the first abnormality detection unit D1 and the second abnormality detection unit D2 monitor the abnormality of the second clock signal CL2 ′ and the first clock signal CL1 ′ by the circuits shown in FIG. However, it is not limited to this. For example, the first abnormality detection unit D1 includes a counter that counts the duty ratio of the second clock signal CL2 ′ and a decoder that decodes the output of the counter instead of the circuit shown in FIG. Even if information identifying whether the clock pattern of the clock signal CL2 'corresponds to any one of the clock patterns shown in FIGS. 4A, 4B, 4C, and 4D is output. Good (this output is called "second clock identification signal AS2 '"). The second abnormality detection unit D2 is configured in the same manner, and the clock pattern of the first clock signal CL1 ′ is the same as that of the clock pattern of FIGS. 4 (A), 4 (B), 4 (C), and 4 (D). Information for identifying which of them may be output (this output is referred to as “first clock identification signal AS1 ′”).

  In that case, the first CPU 15 of the first operation unit M1 can execute a more appropriate restoration process for the second system G2 based on the second clock identification signal AS2 ′. Similarly, the second CPU 25 of the second operation unit M2 can execute more appropriate restoration processing for the first system G1 based on the first clock identification signal AS1 ′.

  For example, it is assumed that the first abnormality detection unit D1 outputs information indicating that the clock pattern of the second clock signal CL2 ′ is the pattern of FIG. 4C as the second clock identification signal AS2 ′. In this case, as shown in the right half of FIG. 4C, “clock generation unit: normal, operation unit: abnormal”, that is, the operation of the second clock signal generation unit CG2 is normal, and the second operation unit M2 (In particular, the operation of the second CPU 25) is likely to be abnormal. Therefore, when the information indicating that the clock pattern of the second clock signal CL2 'is the pattern of FIG. 4C is received as the second clock identification signal AS2', the first CPU 15 of the first operation unit M1 receives the information shown in FIG. After step S1 in the process flow, steps S2 and S3 may be omitted, and the second CPU 25 may be temporarily stopped and restarted immediately as in step S4. As a result, there is a possibility that an abnormal factor related to the second CPU 25 of the second operation unit M2 can be quickly removed and recovered.

  The processing by the second CPU 25 as the second recovery processing unit M22 is performed in the same manner as the processing by the first CPU 15 as the first recovery processing unit M12.

  In the above example, the first abnormality detection unit D1 constantly monitors the second clock signal CL2 ′, and the second abnormality detection unit D2 constantly monitors the first clock signal CL1 ′. However, the timer for setting the period may be provided so that the first abnormality detection unit D1 may periodically monitor the second clock signal CL2 ′ for each predetermined period, and the second abnormality detection unit D2 may monitor the first clock signal CL1. 'May be monitored periodically for a predetermined period. Thereby, power saving can be achieved compared with the case of always monitoring.

(Fourth embodiment)
FIG. 8 shows the configuration of a one-board mutual monitoring system (the whole is denoted by reference numeral Y4) according to another embodiment of the present invention.

  This mutual monitoring system Y4 generally corresponds to a system in which the mutual monitoring system Y1 of FIG. The first power supply W1 and the second power supply W2 in FIG.

  The common power supply 41 is common to the first system G1 and the second system G2. The common power supply 41 constantly supplies power to the first clock signal generation unit CG1, the first operation unit M1, and the first abnormality detection unit D1 of the first system G1, and the second clock of the second system G2. Electric power is constantly supplied to the signal generator CG2, the second operating unit M2, and the second abnormality detector D2. In this case, the number of power supplies can be reduced as compared with the case where the first system G1 and the second system G2 are individually provided with power supplies.

  In the mutual monitoring system Y4, the first abnormality detection unit D1 constantly monitors the second clock signal CL2 using the power from the common power supply 41. On the other hand, the second abnormality detection unit D2 constantly monitors the first clock signal CL1 using the power from the common power supply 41. Thereby, it is possible to constantly monitor the mutual operation between the first system G1 and the second system G2. As described above, both the first abnormality detection unit D1 and the second abnormality detection unit D2 can be configured by a simple electronic circuit without using a CPU or software. Therefore, according to this mutual monitoring system Y4, it is possible to constantly monitor the mutual operation with a simple configuration. In particular, according to the mutual monitoring system Y4, the mutual monitoring system can be constructed with one board.

(Fifth embodiment)
FIG. 9 shows the configuration of a management apparatus (the whole is denoted by reference numeral Y5) according to another embodiment of the present invention.

  This management device Y5 generally corresponds to the one in which the mutual monitoring system Y3 of FIG. The first power supply W1, the second power supply W2, the first start-up power supply U1, and the second start-up power supply U2 in FIG. 3 are replaced with a common power supply unit 51.

  The power supply unit 51 has a common steady power supply 52 that constantly supplies power regardless of whether the start switch 54 provided on the casing 50 is on or off, and supplies or does not supply power according to whether the start switch 54 is on or off. The common starting power supply 53 is included.

  The common steady power supply 52 constantly supplies power to the first clock signal generation unit CG1 of the first system G1, the first abnormality notification unit 10 and the first abnormality detection unit D1 of the first operation unit M1, and the first Power is always supplied to the second clock signal generation unit CG2 of the second system G2, the first abnormality notification unit 20 and the second abnormality detection unit D2 of the second operation unit M2.

  The common activation power supply 53 supplies / not supplies power to the first CPU 15 of the first operation unit M1 and supplies / non-supplys power to the second CPU 25 of the second operation unit M2 in accordance with on / off of the activation switch 54. To do.

  In the management device Y5, the first CPU 15 of the first operation unit M1 and the second CPU 25 of the second operation unit M2 do not operate during the period when the common activation power supply 53 is not supplying power. In this case, the first abnormality detection unit D1 substantially monitors the second clock signal CL2 at all times using the power from the common stationary power supply 52. On the other hand, the second abnormality detection unit D2 substantially monitors the first clock signal CL1 at all times using the power from the common stationary power supply 52. Thereby, it is possible to constantly monitor the operation between the first system G1 and the second system G2. Therefore, it is possible to constantly monitor the mutual operation with a simple configuration.

  Further, during the period in which the common activation power supply 53 supplies power, the first CPU 15 of the first operation unit M1 and the second CPU 25 of the second operation unit M2 further operate. In this case, the first abnormality detection unit D1 constantly monitors the second clock signal CL2 ′ using the power from the common stationary power supply 52. On the other hand, the second abnormality detection unit D2 constantly monitors the first clock signal CL1 ′ using the power from the common stationary power supply 52. Thereby, it is possible to constantly monitor the operation between the first system G1 and the second system G2. In addition, the first CPU 15 and the second CPU 25 use software to perform various operations such as an operation for controlling various devices based on signals from sensors, a recovery process for removing abnormalities and restoring a normal state, and the like. can do.

  Since the management device Y5 accommodates the mutual monitoring system in one casing 50, the mutual monitoring system can be easily installed at various places by transporting and moving the management device Y5.

  In the housing 50, the first clock signal generation unit CG1, the first operation unit M1, and the first abnormality detection unit D1 of the first system G1 are mounted on the first substrate 56, and the second system G2 The second clock signal generation unit CG2, the second operation unit M2, and the second abnormality detection unit D2 may be mounted on the second substrate 57. In this case, for example, the first board 56 constitutes a motherboard for a computer, and the second board 57 constitutes a RAS (Reliability Availability and Serviceability) board. May be. In this case, since the present invention enables mutual monitoring between the mother board and the RAS board, not only the failure on the mother board side can be detected by the RAS board, but also the failure on the RAS board side can be detected by the mother board.

  Further, by connecting a plurality of the management devices Y5 as described above so that they can communicate with each other via a network, the abnormality information can be shared between the management devices.

(Sixth embodiment)
FIG. 10 shows the configuration of a system according to another embodiment of the present invention (the whole is denoted by reference numeral Y6).

  This system Y6 includes a plurality of systems G1, G2, which are arranged so as to be communicable with each other via a network 110 (or an enterprise service bus (ESB) as a data bus) 110 such as the Internet or a local area network. G3,... Constantly monitor each other's operations. This is compatible with Service Oriented Architecture (SOA). SOA refers to the concept of constructing the entire system by regarding the function of software corresponding to one process in business as a service and linking the service on the network 110.

  In this example, the controller 101 included in the first system G1 includes the first power supply W1, the first activation power supply U1, the first clock signal generation unit CG1, the first operation unit M1, and the first operation shown in FIG. An abnormality detection unit D1 is included. The controller 102 included in the second system G2 includes a second power supply W2, a second activation power supply U2, a second clock signal generation unit CG2, a second operation unit M2, and a second abnormality detection unit D2. Similarly, the controller 103 included in the third system G3 also includes a third power supply W3, a third activation power supply U3, a third clock signal generation unit CG3, a third operation unit M3, and a third abnormality corresponding to a natural number i = 3. The detection part D3 is included. In this example, the first operation unit M1 and the first abnormality detection unit D1 included in the controller 101, the second operation unit M2 and the second abnormality detection unit D2 included in the controller 102, and the controller 103 The third operation unit M3 and the third abnormality detection unit D3 can communicate with each other via the network 110.

  The first operation unit M1 included in the controller 101 collects information from the sensor SS1 and the device ME1, processes the information as necessary, and flows information A ′ on the network 110. Similarly, the second operation unit M2 included in the controller 102 collects information from the sensor SS2 and the device ME2, processes the information as necessary, and flows information B ′ on the network 110. The third operation unit M3 included in the controller 103 collects information from the sensor SS3 and the device ME3, processes the information as necessary, and flows information C ′ on the network 110. Based on these pieces of information A ′, B ′, and C ′, the customer 9 can receive various services A, B, and C.

  The first abnormality detection unit D1 included in the controller 101 is a clock generated by the second clock signal generation unit CG2 and the third clock signal generation unit CG3 included in the controllers 102 and 103 via the network 110, respectively. Detect signal anomalies. The second abnormality detection unit D2 included in the controller 102 receives clock signals generated by the first clock signal generation unit CG1 and the third clock signal generation unit CG3 included in the controllers 101 and 103 via the network 110, respectively. Detect anomalies. Similarly, the third abnormality detection unit D3 included in the controller 103 generates the first clock signal generation unit CG1 and the second clock signal generation unit CG2 included in the controllers 101 and 102 via the network 110, respectively. Detect clock signal anomalies. Therefore, these controllers 101, 102, and 103 can constantly monitor the operation of each other via the network 110. According to the system Y6, the operations can be constantly monitored with a simple configuration.

CG1 1st clock signal generation part CG2 2nd clock signal generation part CG3 3rd clock signal generation part CG4 4th clock signal generation part D1 1st abnormality detection part D2 2nd abnormality detection part D3 3rd abnormality detection part D4 4th abnormality Detection unit G1 1st system G2 2nd system G3 3rd system G4 4th system M1 1st operation part M2 2nd operation part M3 3rd operation part M4 4th operation part U1 1st starting power supply U2 2nd Start-up power supply W1 1st power supply W2 2nd power supply W3 3rd power supply W4 4th power supply 10 1st abnormality notification part 20 2nd abnormality notification part 15 1st CPU
25 Second CPU
41 Common power supply 51 Power supply unit

Claims (14)

When a natural number from 1 to n (n is a natural number of 2 or more) is represented by i,
I-th power supply for supplying power,
An i-th clock signal generation unit that generates an i-th clock signal using power from the i-th power source, and an i-th operation unit that operates based on the i-th clock signal generated by the i-th clock signal generation unit. ,
The j-th clock signal other than the i-th clock signal from the first clock signal to the n-th clock signal (j is a natural number other than i among the natural numbers from 1 to n) is monitored. An i-th abnormality detecting unit for detecting an abnormality of the j-th clock signal based on the clock pattern of the j-th clock signal ,
The j-th operation unit for the natural number j variably sets the clock pattern of the j-th clock signal so as to represent the operation content of the j-th operation unit,
The mutual monitoring system, wherein the i-th abnormality detecting unit monitors the j-th clock signal variably set by the j-th operating unit . The mutual monitoring system according to claim 1,
The i-th abnormality detection unit relates to the operation content of the j-th operation unit based on a clock pattern of the j-th clock signal varied by the j-th operation unit when the j-th operation unit is operating. While detecting an abnormality, when the j-th operation unit is inactive, the j-th clock signal should be generated based on the clock pattern of the fixed j-th clock signal that is not changed by the j-th operation unit A mutual monitoring system for detecting an abnormality in a j-th clock signal generation unit. The mutual monitoring system according to claim 1 or 2,
The mutual monitoring system, wherein the i-th abnormality detecting unit detects the abnormality based on non-occurrence of the j-th clock signal or missing pulse. The mutual monitoring system according to claim 1,
N is a natural number of 3 or more,
The i-th abnormality detection unit monitors some or all of the j-th clock signals other than the i-th clock signal among the first to n-th clock signals. In the mutual monitoring system according to any one of claims 1 to 4 ,
The i-th abnormality detection unit constantly monitors the j-th clock signal. In the mutual monitoring system according to any one of claims 1 to 4 ,
The i-th abnormality detection unit periodically monitors the j-th clock signal every predetermined period. In the mutual monitoring system according to any one of claims 1 to 4 ,
For each natural number i, the i-th operation unit includes an i-th central processing unit operated by software,
The i-th abnormality detection unit monitors the j-th clock signal when the i-th central processing unit is not operating or regardless of operation non-operation. In the mutual monitoring system according to any one of claims 1 to 7 ,
The i-th abnormality detection unit outputs a j-th clock abnormality signal indicating that the abnormality has occurred in the j-th clock signal when detecting an abnormality of the j-th clock signal. . The mutual monitoring system according to claim 8 , wherein
When the i-th abnormality detection unit outputs the j-th clock abnormality signal, the i-th operation unit performs control to temporarily stop and restart the j-th clock signal generation unit that should generate the j-th clock signal. A mutual monitoring system characterized by executing. The mutual monitoring system according to claim 9 , wherein
The i-th operation unit operates based on the j-th clock signal when the i-th abnormality detection unit further outputs the j-th clock abnormality signal after restarting the j-th clock signal generation unit. A mutual monitoring system, wherein control for temporarily stopping and restarting the j-th operation unit is executed. The mutual monitoring system according to any one of claims 1 to 10 ,
The i-th power supply, the i-th clock signal generation unit, the i-th operation unit, and the i-th abnormality detection unit for all the natural numbers i from 1 to n are mounted on a common substrate. Mutual monitoring system characterized by The mutual monitoring system according to any one of claims 1 to 11 ,
A mutual monitoring system, wherein some or all of the i-th power supplies for all the natural numbers i from 1 to n are common. In one case,
Based on a first power supply for supplying power, a first clock signal generator for generating a first clock signal using power from the first power supply, and a first clock signal generated by the first clock signal generator A first operating part that operates;
Based on a second power supply for supplying power, a second clock signal generator for generating a second clock signal using the power from the second power supply, and a second clock signal generated by the second clock signal generator A second operating part that operates;
A first abnormality detection unit that monitors the second clock signal and detects an abnormality of the second clock signal based on a clock pattern of the second clock signal;
A second abnormality detector that monitors the first clock signal and detects an abnormality of the first clock signal based on a clock pattern of the first clock signal ;
The first operation unit variably sets the clock pattern of the first clock signal so as to represent the operation content of the first operation unit,
The second operation unit variably sets the clock pattern of the second clock signal so as to represent the operation content of the second operation unit,
The first abnormality detection unit monitors the second clock signal variably set by the second operation unit,
The second abnormality detection unit monitors the first clock signal variably set by the first operation unit . When a natural number from 1 to n (n is a natural number greater than or equal to 2) is represented by i, the i-th power source that supplies power, and the i-th clock signal is generated using the power from the i-th power source. an i-clock signal generation unit, and an i-th operation unit that operates based on the i-th clock signal generated by the i-th clock signal generation unit,
The j-th clock signal other than the i-th clock signal from the first clock signal to the n-th clock signal (j is a natural number other than i among the natural numbers from 1 to n) is monitored. An i-th abnormality detecting unit for detecting an abnormality of the j-th clock signal based on the clock pattern of the j-th clock signal,
The j-th operation unit for the natural number j variably sets the clock pattern of the j-th clock signal so as to represent the operation content of the j-th operation unit,
The i-th abnormality detection unit monitors the j-th clock signal variably set by the j-th operation unit,
Some or all of the i-th operation unit and the i-th abnormality detection unit for all the natural numbers i from 1 to n are distributed in a communicable manner via a data bus or a network. A system characterized by that.

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