JP3879523B2 - Microcomputer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microcomputer, and more particularly to a technique for reducing power consumption in a microcomputer.
[0002]
[Prior art]
In general, in a microcomputer (hereinafter referred to as a microcomputer) mounted on an electronic control device, a clock signal supplied to a peripheral circuit, a control signal for controlling on / off of a control target, and the like having an arbitrary cycle and duty ratio. A program is often set to repeatedly output a pulse signal.
[0003]
For example, in an electronic control device mounted on a vehicle, the microcomputer may have to repeatedly output the pulse signal when the engine is stopped when the battery is not charged.
For this reason, there is a demand for a microcomputer to output a pulse signal having an arbitrary cycle and duty ratio with less power consumption (current consumption).
[0004]
Therefore, the present inventor considered the configurations and methods of [Conventional Example 1] to [Conventional Example 3] below before reaching the present invention.
[Conventional example 1]
First, the microcomputer 101 of Conventional Example 1 shown in FIG. 5A includes a CPU 103 in addition to a CPU 103 (that is, a central processing unit including an instruction decoding unit and an arithmetic unit) that operates according to a program, and an I / O port 105. Is provided with an intermittent operation control unit 107 that performs control for intermittent operation.
[0005]
In the microcomputer 101, the CPU 103 executes a predetermined operation stop command to stop its own operation (that is, the program execution operation that is the original operation of the microcomputer) and to the intermittent operation control unit 107. When the request is issued, the intermittent operation control unit 107 starts counting the timer time set in advance by the CPU 103, and when the timer time has elapsed, the CPU 103 wakes up from the stopped state to the operating state.
[0006]
Therefore, in the microcomputer 101, when the CPU 103 determines that it is not necessary to operate, it executes the operation stop command, stops its own operation, and outputs an operation request to the intermittent operation control unit 107. As shown in the upper part of FIG. 5B, the CPU 103 stops the operation, and then the timer time counted by the intermittent operation control unit 107 (“ The intermittent operation repeats the operation and the non-operation (operation stop), such as restarting the operation when the interval of the intermittent operation ") elapses, and stopping the operation again when it is determined that it is not necessary to operate. Will be done.
[0007]
Therefore, when the microcomputer 101 repeatedly outputs a pulse signal having a certain cycle and duty ratio from the output terminal (output port) P with low power consumption, as shown in FIG. The function may be used to cause the CPU 103 to operate intermittently and to invert the output level of the output terminal P every time the CPU 103 restarts the operation.
[0008]
That is, as shown in FIG. 5B, when the CPU 103 is intermittently operating, the temporary operation time of the CPU 103 is Ta, and the CPU 103 non-operation time determined by the timer time (“intermittent” in FIG. 5B). Assuming that the operation interval “) is Tb, the output level of the output terminal P is inverted every“ Ta + Tb ”. Therefore, by alternately changing Tb between Tb1 and Tb2 by software, the cycle T becomes“ 2 × A pulse signal of “Ta + Tb1 + Tb2” and a duty ratio D of “100 × (Ta + Tb1) / T” percent is output from the output terminal P.
[0009]
In FIG. 5B, the output start level (initial output level) of the pulse signal from the output terminal P is high (Hi), and the output level of the output terminal P is high during the period “Ta + Tb1”. The case where it becomes a level is illustrated.
According to the microcomputer 101 of the conventional example 1, since the CPU 103 having particularly high power consumption among the components of the microcomputer is operated not intermittently but intermittently. The power consumption can be suppressed to a low level, and thus the power consumption in the electronic control device on which the microcomputer 101 is mounted can be suppressed. In the microcomputer 101, when the CPU 103 continues to operate, the CPU 103 controls the output level of the output terminal P according to the program.
[0010]
[Conventional example 2]
Next, FIG. 6A is a configuration diagram illustrating the microcomputer 201 of the second conventional example. In FIG. 6A, the same components as those of the microcomputer 101 in FIG. 5A are denoted by the same reference numerals, and detailed description thereof is omitted.
[0011]
As shown in FIG. 6A, the microcomputer 201 of the conventional example 2 is different from the microcomputer 101 of the conventional example 1 in that the output change function unit 203 for inverting the output level of the output terminal P while the operation of the CPU 103 is stopped. We have added.
When the output change function unit 203 receives a timing start command from the CPU 103, the output change function unit 203 starts counting the waiting time set in advance by the CPU 103, and outputs the output from the output terminal P when the waiting time has elapsed. Invert the level.
[0012]
Therefore, when the microcomputer 201 repeatedly outputs a pulse signal having a certain cycle and duty ratio from the output terminal P with low power consumption, the intermittent operation function described above is used as shown in FIG. The CPU 103 is intermittently operated, and every time the CPU 103 restarts the operation, the output level of the output terminal P is set to one level (in this example, high level), and the output change function is immediately before the operation is stopped. What is necessary is just to perform the setting of the waiting time Tw and the timing start command for reversing the output level of the output terminal P to the unit 203 while the operation of the CPU 103 is stopped.
[0013]
That is, in this way, as shown in FIG. 6B, the temporary operation time of the CPU 103 when the CPU 103 is operating intermittently is Ta, and the non-operation time of the CPU 103 (“ When the interval of the intermittent operation ") is Tb, a pulse signal having a period T of" Ta + Tb "and a duty ratio D of" 100 × (Ta + Tw) / T "percent is output from the output terminal P. Note that the timing start command to the output change function unit 203 may be issued every time the CPU 103 restarts the operation. In this case, the waiting time to be measured by the output change function unit 203 is shown in FIG. The time may be set longer by Ta than Tw.
[0014]
And since this CPU 201 also operates CPU103 intermittently, power consumption can be restrained small. In this microcomputer 201 as well, when the CPU 103 continues to operate, the CPU 103 controls the output level of the output terminal P according to the program.
[0015]
[Conventional Example 3]
Next, FIG. 7A is a configuration diagram showing the microcomputer 301 of the conventional example 3. In FIG. 7A, the same components as those of the microcomputer 101 in FIG. 5A are denoted by the same reference numerals, and detailed description thereof is omitted.
[0016]
As shown in FIG. 7A, the microcomputer 301 of the conventional example 3 includes a frequency control unit 303 instead of the intermittent operation control unit 107 as compared with the microcomputer 101 of the conventional example 1. Then, the frequency control unit 303 generates a clock having a frequency designated by the CPU 103 and outputs the clock as an operation clock for the CPU 103. That is, the microcomputer 301 can change the operation speed of the CPU 103.
[0017]
When the microcomputer 301 repeatedly outputs a pulse signal having a certain cycle and duty ratio from the output terminal P with low power consumption, the CPU 103 receives a signal from the frequency control unit 303 as shown in FIG. Set the frequency of the output operation clock to a frequency (eg, several MHz) lower than the frequency during normal operation (eg, several tens of MHz) and operate at a low speed to reduce power consumption. The output level of P may be controlled.
[0018]
[Problems to be solved by the invention]
However, first, in the microcomputer 301 of the conventional example 3, since the CPU 103 always operates, it is difficult to significantly reduce power consumption.
Further, since the microcomputers 101 and 201 of the conventional examples 1 and 2 can provide a time during which the operation of the CPU 103 stops, the pulse signal output from the output terminal P is advantageous over the microcomputer 301 of the conventional example 3. Since it is necessary to wake up the CPU 103 at least once during one cycle, there is a limit to further reducing power consumption.
[0019]
In the microcomputer 101 of the conventional example 1, it is necessary to wake up the CPU 103 twice per cycle of the pulse signal, whereas according to the microcomputer 201 of the conventional example 2, the CPU 103 is turned off per cycle of the pulse signal. This is advantageous because it only needs to be woken up once. However, even in the microcomputer 201 of Conventional Example 2, it is necessary to wake up the CPU 103 once for each period of the pulse signal, and therefore the effect is reduced when the period of the pulse signal is short.
[0020]
The present invention has been made in view of these problems, and an object thereof is to provide a microcomputer capable of outputting a pulse signal having an arbitrary period and duty ratio with less power consumption.
[0021]
[Means for Solving the Problems and Effects of the Invention]
  The microcomputer according to claim 1, which has been made to achieve the above object, includes a CPU that operates according to a program and a main clock that generates a main clock for operating the CPU (that is, an operation clock of the CPU). Generating means. In this microcomputer, the CPU can change between the operation state and the stop state. When the CPU is stopped, the main clockOperation of generating meansAlso stop.
[0022]
  In addition, this microcomputer can output any signal when the CPU stops operating.ForAs a meansProvided separately from the main clock generation means,Sub clock whose frequency is lower than that of the main clockSubclock generation means that always generates and the subclockArbitrary signal output means for receiving and operatingAndI have. And when the arbitrary signal output means receives the output start command from the CPU, the arbitrary signal output means outputs the pulse signal having the cycle and duty ratio set by the CPU until the output stop command is received from the CPU.Even if has stopped workingOutput from a specific output terminal of the microcomputer.
[0023]
Therefore, according to this microcomputer, it is possible to repeatedly output a pulse signal having an arbitrary cycle and duty ratio from the output terminal of the microcomputer while the operation of the CPU is stopped. Ratio pulse signals can be output with less power consumption. That is, before the CPU stops its own operation, the period and duty ratio of the pulse signal desired to be output from the specific output terminal are set in the arbitrary signal output means, and the output start command is sent to the arbitrary signal output means. After that, even if the CPU has stopped operating, the pulse signal having the cycle and duty ratio set by the CPU is output by the arbitrary signal output means operating at the low-speed subclock. It is because it is repeatedly output from.
[0024]
Further, according to this microcomputer, even when the CPU is operating, the pulse signal having a desired cycle and duty ratio can be output from the specific output terminal by the arbitrary signal output means. The processing load can also be reduced. That is, it is not necessary to control the output of the pulse signal by software.
[0025]
  FurtherAnd claims1The microcomputer described in,UpAn intermittent operation control means is provided that operates in response to the low-speed sub-clock and performs control for intermittently operating the CPU.
  In this microcomputer, “the CPU outputs an operation request to the intermittent operation control means when stopping the operation, and when the intermittent operation control means receives the operation request from the CPU, the operation of the main clock generation means is stopped. At the same time, start measuring the preset time and restart the operation of the main clock generation means after the set time has elapsed.,Wake up the CPU from the stopped state to the operating stateRUN signal for output to wake up the CPUIs performed, the intermittent operation of the CPU as shown in the upper part of FIG. 3 is performed.Further, the RUN signal is continuously output until the intermittent operation control means next stops the operation of the main clock generating means.Note that the period indicated as “intermittent operation interval (intermittent time)” in FIG. 3 is a period in which the CPU is stopped, and the program execution operation, which is a substantial operation of the microcomputer, is stopped. It is a period.
[0026]
  Such claims1According to the microcomputer, when the operation of the CPU is stopped, the high-frequency main clock that is the operation clock of the CPUOf the main clock generation means for generatingTherefore, a pulse signal having an arbitrary cycle and duty ratio can be output with much less power consumption.
[0027]
  By the way, claims1In the microcomputer, the set time that is measured by the intermittent operation control means may be a fixed value.2If it is configured to be set by the CPU (in other words, by a program) as described in the above, it is very advantageous to obtain high versatility.
[0028]
  Next, the claim3In the microcomputer described in claim 1,, 2In this microcomputer, the arbitrary signal output means receives the output start command from the CPU and starts the pulse signal output operation. In other words, the level of the output terminal when no pulse signal is output is set by the CPU (in other words, by the program).
[0029]
  Such claims3According to this microcomputer, the output start level of the pulse signal can be arbitrarily set to either the high level or the low level, and versatility can be improved.
  Claims4In the microcomputer according to claim 1,3In the microcomputer, the output terminal from which the arbitrary signal output means outputs a pulse signal is set by the CPU (in other words, by a program) to one of a plurality of terminals of the microcomputer. This microcomputer is convenient because the pulse signal output terminal can be arbitrarily selected from a plurality of terminals. For example, at the time of pattern design of a printed wiring board on which the microcomputer is mounted, the path of the pulse signal wiring pattern can be easily changed.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a single chip microcomputer according to an embodiment to which the present invention is applied will be described with reference to the drawings.
First, FIG. 1 is a block diagram showing the configuration of the microcomputer 1 of the present embodiment.
[0031]
As shown in FIG. 1, the microcomputer 1 of the present embodiment temporarily stores, as basic components, a CPU 3 that operates according to a program, a ROM 5 that stores programs and fixed data in advance, and a calculation result by the CPU 3. RAM 6 and an I / O port 7 for inputting / outputting signals from / to the outside via a terminal of the microcomputer 1.
[0032]
Furthermore, the microcomputer 1 cooperates with the oscillation element 8 provided outside the microcomputer 1 to generate a main clock (several MHz to several tens of MHz in the present embodiment) that is an operation clock of the CPU 3, and A main clock generation unit 13 including an oscillation control unit 11 that controls the main oscillation circuit 9 and an intermittent operation control that performs control for operating the CPU 3 intermittently (intermittent operation) in cooperation with the oscillation control unit 11. When receiving an output start command from the CPU 15 and the CPU 3, the pulse signal having the cycle and duty ratio set by the CPU 3 is input to the above I until the output stop command is received from the CPU 3 regardless of the operation state of the CPU 3. An arbitrary signal output control unit 17 that outputs from the output terminal of the microcomputer 1 via the / O port 7 and provided outside the microcomputer 1 In cooperation with the vibration element 18 and a sub-oscillation circuit 19 for generating a sub-clock (several tens KHz in this embodiment) lower frequency than the main clock.
[0033]
  In the microcomputer 1 of the present embodiment, each of the oscillation control unit 11, the intermittent operation control unit 15, and the arbitrary signal output control unit 17 operates in response to a subclock constantly generated by the sub oscillation circuit 19. To do.
  In the present embodiment, the main oscillation circuit 9 corresponds to the main clock generation unit, the oscillation control unit 11 and the intermittent operation control unit 15 correspond to the intermittent operation control unit, and the arbitrary signal output control unit 17 Corresponds to arbitrary signal output means. The sub oscillation circuit 19 corresponds to sub clock generation means.
[0034]
Here, the CPU 3 can stop its own operation by executing a specific operation stop command in the same manner as the CPU 103 of the conventional example 1 described above. The CPU 3 outputs an operation request to the intermittent operation control unit 15 when the operation is stopped by itself (that is, when the operation stop command is executed). Further, the CPU 3 outputs each of an output start command and an output stop command to the arbitrary signal output control unit 17 by executing a predetermined command.
[0035]
On the other hand, the intermittent operation control unit 15 includes a register 15a in which a timer time (corresponding to a set time) to be measured is set (written) by the CPU 3.
The intermittent operation control unit 15 normally gives an operation instruction to the oscillation control unit 11 of the main clock generation unit 13 to cause the oscillation control unit 11 to operate the main oscillation circuit 9. When an operation request is received (that is, when the CPU 3 stops operation), a stop instruction is output to the oscillation control unit 11 to stop the operation of the main oscillation circuit 9 from the oscillation control unit 11, and the CPU 3 performs the above operation in advance. The timer time set in the register 15a is started to be counted. When the timer time has elapsed, an operation instruction is output to the oscillation control unit 11 again, and the oscillation control unit 11 resumes the operation of the main oscillation circuit 9. .
[0036]
The oscillation control unit 11 of the main clock generation unit 13 switches between operation and non-operation of the main oscillation circuit 9 according to the operation instruction and stop instruction from the intermittent operation control unit 15. When the operation of the main oscillation circuit 9 is started in response to an operation instruction from the control unit 15, when a predetermined oscillation stabilization wait time that is considered that the frequency of the main clock is stabilized from that time point, A RUN signal for raising the CPU 3 from the stopped state to the operating state is output.
[0037]
The oscillation stabilization wait time is provided to wake up the CPU 3 after the main clock frequency is reliably stabilized, and is counted based on the number of sub-clocks. The oscillation control unit 11 includes a register 11a in which the oscillation stabilization waiting time is set (written) by the CPU 3. In the present embodiment, the oscillation control unit 11 uses the RUN signal until the next stop instruction is received from the intermittent operation control unit 15 (that is, the operation of the CPU 3 stops and the operation of the main oscillation circuit 9 is performed next). It will continue to output until it is stopped.
[0038]
In the microcomputer 1 including the oscillation control unit 11 and the intermittent operation control unit 15, the CPU 3 sets the timer time in advance in the register 15 a of the intermittent operation control unit 15 and there is no processing to be executed. If it is determined that the operation can be stopped, the above operation stop command is executed, the operation is stopped, and an operation request is output to the intermittent operation control unit 15. And the intermittent operation | movement (operation | movement which repeats operation | movement and non-operation | movement) of CPU3 as shown in the upper stage of FIG. 4 will be implement | achieved.
[0039]
That is, when the CPU 3 determines that the operation may be stopped and stops its own operation and outputs an operation request to the intermittent operation control unit 15, the intermittent operation control unit 15 instructs the oscillation control unit 11 to stop. Is output to stop the operation of the main oscillation circuit 9, and the timer time (set time) set in the register 15a is started. When the timer time elapses, the oscillation control unit 11 is instructed to operate again. Then, the operation of the main oscillation circuit 9 is resumed. Then, when the above-described oscillation stabilization wait time elapses from that point, the RUN signal is output from the oscillation control unit 11 to the CPU 3 and the CPU 3 wakes up from the stop state to the operation state. By being repeated, the intermittent operation of the CPU 3 is performed.
[0040]
Next, the arbitrary signal output control unit 17 will be described.
As shown in FIG. 2, the arbitrary signal output control unit 17 includes a storage unit 17a in which the cycle of the pulse signal to be output is written by the CPU 3, a storage unit 17b in which the duty ratio of the pulse signal to be output is written by the CPU 3, An output indicating a storage unit 17c in which the output start level of the pulse signal is written by the CPU 3, and an output terminal (hereinafter referred to as a pulse signal output target terminal) from which the pulse signal is to be output among the plurality of output terminals P1 to Pn of the microcomputer 1 A storage unit 17d in which terminal information is written by the CPU 3 is provided.
[0041]
Then, as shown in the lower part of FIG. 4, the arbitrary signal output control unit 17 receives the pulse signal output target terminal (corresponding to the output terminal information written in the storage unit 17 d until receiving the output start command from the CPU 3 ( Here, the output level of P1 among P1 to Pn) is set to a level opposite to the output start level written in the storage unit 17c (here, it is assumed to be a low level). When an output start command is received from the CPU 3, the output of the pulse signal from the pulse signal output target terminal P1 is started.
[0042]
Here, in this example, since the output start level written in the storage unit 17c is a high level, the arbitrary signal output control unit 17 receives the output start command from the CPU 3 and outputs the pulse signal output target terminal P1. After the level is changed from the low level to the high level, until the output stop command from the CPU 3 is received, the pulses of the cycle and duty ratio written in each of the storage units 17a and 17b from the pulse signal output target terminal P1 Output the signal repeatedly. And the arbitrary signal output control part 17 will hold | maintain the level of the pulse signal output object terminal P1, if the output stop command from CPU3 is received. The arbitrary signal output control unit 17 can also stop the level of the pulse signal output target terminal P1 at a level designated by the CPU 3 when receiving an output stop command.
[0043]
The high level time Th in one cycle of the pulse signal is “T × D, where T is the period written in the storage unit 17 a and D [%] is the duty ratio written in the storage unit 17 b. / 100 ".
According to the microcomputer 1 of the present embodiment as described above, as illustrated in FIG. 4, a pulse signal having an arbitrary cycle and duty ratio is repeatedly output from the pulse signal output target terminal while the operation of the CPU 3 is stopped. As a result, a pulse signal having an arbitrary period and duty ratio can be output with less power consumption.
[0044]
Specifically, as shown in FIG. 4, before the CPU 3 outputs an operation request to the intermittent operation control unit 15 and stops its operation, the period T of the pulse signal to be output from the pulse signal output target terminal P1 If the duty ratio D and the output start level are written in the storage units 17a to 17c of the arbitrary signal output control unit 17 and an output start command is output to the arbitrary signal output control unit 17 (that is, for the output start command) After that, even if the CPU 3 stops operating, the arbitrary signal output control unit 17 causes the pulse signal having the cycle T and the duty ratio D set by the CPU 3 to be output from the pulse signal output target terminal P1. This is because it is output repeatedly. When it is desired to stop the output of the pulse signal, an output stop command may be executed to the arbitrary signal output control unit 17 when the CPU 3 is operating and an output stop command is executed.
[0045]
According to the microcomputer 1 of this embodiment, for example, a clock signal to a peripheral circuit, a control signal for controlling on / off of a control target, and the like can be output with very little power consumption. become able to.
Moreover, according to the microcomputer 1 of the present embodiment, when the operation of the CPU 3 is stopped, the main clock that is the operation clock of the CPU 3 is also stopped, so that the number of pulse signals having an arbitrary period and duty ratio is further reduced. It can be output with power consumption.
[0046]
Further, according to the microcomputer 1, even when the CPU 3 is operating, the arbitrary signal output control unit 17 can output a pulse signal having a desired cycle and duty ratio from the pulse signal output target terminal. It is also possible to reduce the processing load during operation. This is because the output control of the pulse signal by software becomes unnecessary.
[0047]
Furthermore, according to the microcomputer 1 of this embodiment, the output start level of the pulse signal can be arbitrarily set to either a high level or a low level by a program, and the pulse signal output target terminal is also a plurality of terminals. Since it can select arbitrarily from the inside, very high versatility is acquired.
[0048]
As mentioned above, although one Embodiment of this invention was described, it cannot be overemphasized that this invention can take a various form.
For example, the timer time counted by the intermittent operation control unit 15 is not set (programmable) by the CPU 3 but may be a fixed value. However, it is more versatile and advantageous to adopt the configuration of the above embodiment in which the timer time can be arbitrarily set.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a microcomputer according to an embodiment.
FIG. 2 is a block diagram illustrating an arbitrary signal output control unit in the microcomputer of the embodiment.
FIG. 3 is a time chart showing an intermittent operation of a CPU in the microcomputer of the embodiment.
FIG. 4 is a time chart showing the operation of the microcomputer according to the embodiment.
FIG. 5 is an explanatory diagram for explaining a conventional example 1;
FIG. 6 is an explanatory diagram for explaining a second conventional example.
FIG. 7 is an explanatory diagram for explaining a conventional example 3;
[Explanation of symbols]
1 ... Microcomputer (microcomputer) 3 ... CPU 5 ... ROM
6 ... RAM 7 ... I / O port 8,18 ... oscillating element
9 ... Main oscillation circuit 11 ... Oscillation controller 13 ... Main clock generator
15: Intermittent operation control section 11a, 15a ... Register
17 ... Arbitrary signal output control unit 19 ... Sub oscillation circuit P1-Pn ... Output terminal

Claims (4)

A CPU that operates according to a program;
Main clock generating means for generating a main clock for operating the CPU;
The CPU is capable of transitioning between an operating state and a stopped state, and also stops the operation of the main clock generating means while the CPU is stopped.
A sub clock generating means that is provided separately from the main clock generating means, and that constantly generates a sub clock having a frequency lower than that of the main clock;
When receiving an output start command from the CPU, the CPU operates in response to the sub clock and outputs a pulse signal having a cycle and duty ratio set by the CPU until receiving an output stop command from the CPU. Even if the operation has stopped, arbitrary signal output means for outputting from a specific output terminal of the microcomputer ,
Operates by receiving a pre-Symbol subclock, and a intermittent operation control means for performing control for intermittently operating said CPU,
When the CPU stops the operation, it outputs an operation request to the intermittent operation control means. When the intermittent operation control means receives the operation request, it stops the operation of the main clock generation means, and in advance and starts counting the set time that is set, after a lapse of the set time, the main clock generating means restarts the operation of, and outputs a RUN signal to wake up the CPU from the stopped state to the operating state By waking up the CPU, intermittent operation of the CPU is implemented ,
Further, the RUN signal is continuously output until the intermittent operation control means next stops the operation of the main clock generation means ,
A microcomputer characterized by. The microcomputer according to claim 1 ,
The intermittent operation control means includes
The set time is configured to be set by the CPU;
A microcomputer characterized by. The microcomputer according to claim 1 or 2 ,
The arbitrary signal output means includes
An initial output level of the pulse signal when the output operation of the pulse signal is started in response to an output start command from the CPU is configured to be set by the CPU.
A microcomputer characterized by. The microcomputer according to any one of claims 1 to 3 ,
The output terminal from which the arbitrary signal output means outputs the pulse signal is set by the CPU to any one of a plurality of terminals of the microcomputer,
A microcomputer characterized by.

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