JP5398000B2 - Inrush current prevention circuit - Google Patents

Description

  The present invention relates to an inrush current prevention circuit.

  In order to stably supply energy from the power supply to the main circuit at the subsequent stage, a bypass capacitor may be provided between the power supply and the main circuit. The inrush current prevention circuit prevents a large current (inrush current) from flowing through the bypass capacitor when the power is turned on. Examples of conventional inrush current prevention circuits include those described in Patent Documents 1 and 2 described below.

FIG. 3 is a diagram showing a power supply device incorporating a conventional inrush current prevention circuit, which is disclosed in Patent Document 1. In FIG.
The power supply device shown in FIG. 3 charges the energy from the power supply to the capacitor C1 whose one electrode is connected to the power supply terminal T1, and supplies the energy charged in the capacitor C1 to the supply destination via the transformer 3. .

The inrush current prevention circuit incorporated in the power supply device prevents inrush current from flowing through the capacitor C1, and includes resistors R1, R2, and R3, an N-channel FET Q1, and a capacitor C2. .
One end of the resistor R1 and the drain of the FET Q1 are connected to the other electrode of the capacitor C1. The other end of the resistor R1 and the source of the FET Q1 are connected to the power supply terminal T2.

  The gate of the FET Q1 is connected to one end of the resistor R2, one end of the resistor R3, and one electrode of the capacitor C2. The other end of the resistor R2 is connected to the power supply terminal T1. The other end of the resistor R3 and the other electrode of the capacitor C2 are connected to the power supply terminal T2.

  When power is supplied to the power terminals T1 and T2, charging of the capacitor C1 and the capacitor C2 is started. Immediately after the power is turned on, the FET Q1 is off and the charging current of the capacitor C1 flows through the resistor R1, and the current value is limited by the resistance value of the resistor R1. When the charging voltage of the capacitor C2 exceeds the threshold value of the FET Q1, the FET Q1 is turned on and both ends of the resistor R1 are short-circuited. After the charging of the capacitor C1 is completed by making the time constant of the capacitor C2 determined by the capacitances of the resistors R2, R3, and C2 larger than the time constant of the capacitor C1 determined by the capacitances of the resistors R1 and C1, the FET Q1 Can be turned on.

FIG. 4 is a diagram showing a starting circuit in which a conventional inrush current prevention circuit is incorporated, and is shown in Patent Document 2. In FIG.
The inrush current prevention circuit is a circuit for preventing an inrush current from flowing through the capacitor C0 having one electrode connected to the positive electrode of the power supply V0. The resistors R0, R1, R2, a Zener diode D0, and an N-channel type An FET Q0 and an NPN transistor Q1 are provided.

One end of the resistor R1, one end of the resistor R2, and the drain of the FET Q0 are connected to the other electrode of the capacitor C0. The other end of the resistor R1 and the source of the FET Q0 are connected to the negative electrode of the power source V0.
The other end of the resistor R2 is connected to the base of the NPN transistor Q1. The collector of the NPN transistor Q1 and the gate of the FET Q0 are connected to the positive electrode of the power source V0 via the resistor R0. The emitter of the NPN transistor Q1 is connected to the negative electrode of the power supply V0.

  In such an inrush current prevention circuit, when the power supply V0 is turned on, charging of the capacitor C0 is started. When the power source V0 is turned on, the NPN transistor Q1 is turned on, so that the FET Q0 is turned off and the current flowing through the capacitor C0 is limited by the resistor R1. When the voltage between both electrodes of the capacitor C0 increases, the NPN transistor Q1 is turned off. As a result, the FET Q0 is driven by the power source V0 to turn on, and both ends of the resistor R1 are short-circuited. Further, when the NPN transistor Q1 is turned off, the base potential of the NPN transistor Q2 in the startup delay unit rises, and the startup delay unit is activated to supply energy to the on / off time ratio control circuit of the energy supply destination. .

JP-A-9-233678 Japanese Utility Model Publication No. 7-29607

  In the inrush current prevention circuit of FIG. A shown in Patent Document 1, there is no means for detecting the charging voltage of the capacitor C1, and switching of the switching element 4 cannot be started in accordance with the charging voltage of the capacitor C1.

  In the inrush current prevention circuit of FIG. B shown in Patent Document 2, the charging voltage of the capacitor C0 is detected by the transistor Q1, and when the transistor Q1 is turned off, the FET Q0 is turned on and the operation of the on / off time ratio control circuit 20 is performed. Has started. However, if the transistor Q1 is set to be turned off when the charging voltage of the capacitor C0 becomes sufficiently high in order to prevent an instantaneous inrush current from flowing when the FET Q0 is turned on, the charging voltage of the capacitor C0 is reduced. Even if the ON / OFF time ratio control circuit 20 rises to a voltage that can be driven stably, the ON / OFF time ratio control circuit 20 cannot be driven. That is, there is a problem in that the driving start of the on / off time ratio control circuit 20 is delayed.

  The present invention has been made in view of the current situation as described above, and can reliably prevent an inrush current from flowing into the bypass capacitor, and at the latter stage when the charging voltage of the bypass capacitor reaches a predetermined value. An object of the present invention is to realize an inrush current prevention circuit capable of starting the operation of the main circuit.

In order to achieve the above object, an inrush current prevention circuit according to the present invention comprises:
A bypass capacitor that stores energy supplied from the power supply, and is connected in parallel to the bypass capacitor, operates when the input control signal is at the first logic level, and stores energy stored in the bypass capacitor. An inrush current preventing circuit that suppresses an inrush current flowing in the bypass capacitor when the power is turned on.
Resistor means connected to the bypass capacitor and flowing while suppressing the charging current of the bypass capacitor and generating a conversion signal corresponding to the charging current;
Charging state detection means for outputting the control signal that transitions from the second logic level to the first logic level from an output terminal when it is detected that the charging current has become a predetermined value or less based on the conversion signal When,
An integration circuit for generating an integrated signal obtained by integrating the control signal;
A control electrode connected to the output terminal of the integration circuit; a first conduction electrode connected to one end of the resistance means; and a second conduction electrode connected to the other end of the resistance means; A transistor for turning on and off between the first conductive electrode and the second conductive electrode based on a signal;
The transistor includes a first conductive electrode and a second conductive electrode when the integration signal is changed to a predetermined value due to the control signal transitioning to the first logic level. Turn on,
It is characterized by that.

  According to the present invention, it is possible to reliably prevent an excessive inrush current from flowing into the bypass capacitor, and to start the operation of the main circuit at the subsequent stage when the energy of the bypass capacitor reaches a predetermined value.

It is a circuit diagram which shows the inrush current prevention circuit which concerns on embodiment of this invention. It is a wave form diagram for demonstrating operation | movement of the inrush current prevention circuit of FIG. It is a figure which shows the power supply device with which the conventional inrush current prevention circuit was integrated. It is a figure which shows the starting circuit in which the conventional inrush current prevention circuit was integrated.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a circuit diagram showing an inrush current prevention circuit 10 according to an embodiment of the present invention.
The inrush current prevention circuit 10 is a circuit that prevents an inrush current from flowing through the bypass capacitor 20 when the DC power supply 1 is turned on.

  The bypass capacitor 20 is provided to charge energy supplied from the DC power supply 1 and supply the energy to the main circuit 30 at the subsequent stage. One electrode of the bypass capacitor 20 and one power supply terminal 30a of the main circuit 30 are connected to the positive electrode of the DC power supply 1 via the switch SW. The other power supply terminal 30 b of the main circuit 30 is connected to the other electrode of the bypass capacitor 20.

The inrush current prevention circuit 10 includes a resistor 11, a resistor 12, and an N-channel FET 13. One end of the resistor 11 and the drain of the FET 13 are connected to the other electrode of the bypass capacitor 20.
The other end of the resistor 11 is connected to one end of the resistor 12, and the other end of the resistor 12 is connected to the ground together with the source of the FET 13. That is, a series circuit of resistors 11 and 12 is connected to the other electrode of the bypass capacitor 20, and a drain and a source of the FET 13 are connected in parallel to the series circuit.

A connection point between the resistor 11 and the resistor 12 is connected to one input terminal (−) of the comparator 14. A reference voltage Vref is input to the other input terminal (+) of the comparator 14.
The output terminal of the comparator 14 is connected to the control signal input terminal 30 c of the main circuit 30 and one end of the resistor 15. The main circuit 30 starts operating when the level of the control signal input terminal 30c transitions to a high level.

  The other end of the resistor 15 is connected to one electrode of the capacitor 16 and the gate of the FET 13. The capacitor 16 constitutes an integration circuit together with the resistor 15, and the other electrode of the capacitor 16 is connected to the ground.

Next, the operation of the inrush current prevention circuit 10 when the power is turned on will be described.
FIG. 2 is a waveform diagram for explaining the operation of the inrush current prevention circuit 10.
The DC power source 1 is turned on by turning on the switch SW. The DC power source 1 generates a DC voltage V1, and the bypass capacitor 20 starts charging.

  Immediately after the DC power supply 1 is turned on, the FET 13 is turned off, and the charging current Ic of the bypass capacitor 20 flows through the resistor 11 and the resistor 12 connected in series, and the charging current of the bypass capacitor 20 by the resistor 11 and the resistor 12. Ic is limited, and an excessive inrush current is prevented from flowing. The charging current Ic of the bypass capacitor 20 is V1 / (R11 + R12) immediately after the DC power supply 1 is turned on as shown in FIG. 2 when the resistance value of the resistor 11 is R11 and the resistance value of the resistor 12 is R12. Then it decreases. On the other hand, the charging voltage Vc of the bypass capacitor 20 is 0 immediately after the DC power supply 1 is turned on, but increases so as to approach the voltage V1 as time passes.

The resistor 12 converts the charging current of the bypass capacitor 20 into a voltage signal and inputs the voltage signal to the comparator 14.
The output signal of the comparator 14 transitions from a low level to a high level when the voltage signal input from the resistor 12 becomes equal to or lower than the reference voltage Vref. The output signal of the comparator 14 indicates the charged state of the bypass capacitor 20 and indicates that a predetermined amount of energy is accumulated in the bypass capacitor 20 when the level is high.

  The output signal of the comparator 14 is given as a control signal to the control signal input terminal 30c of the main circuit 30 and one end of the resistor 15. The main circuit 30 starts its operation when a high level signal is input to the control signal input terminal 30c.

  The integrating circuit composed of the resistor 15 and the capacitor 16 forms an integrated signal obtained by integrating the output signal of the comparator 14 and applies it to the gate of the FET 13 from the connection point between the resistor 15 and the capacitor 16. The integration signal output from the integration circuit becomes a high level with a delay with respect to the output signal of the comparator 14 that has transitioned to a high level, and the change in the level is gradual.

  Accordingly, the FET 13 is turned on with a delay after the level of the output signal of the comparator 14 changes to a high level. By turning on the FET 13, both ends of the series circuit of the resistor 11 and the resistor 12 are short-circuited, and even when the main circuit 30 is operating, the bypass capacitor 20 is charged without loss.

As described above, the inrush current prevention circuit 10 of the present embodiment has the following effects.
(1) When the DC power supply 1 is turned on, the FET 13 is turned off, and the charging current of the bypass capacitor 20 flows through the resistor 11 and the resistor 12. Therefore, it is possible to prevent an excessive inrush current from flowing.

  (2) Since the comparator 14 is provided and when the charge amount of the bypass capacitor 20 reaches a predetermined amount, the output signal of the comparator 14 transitions from a low level to a high level, and the main circuit 30 starts operating. The operation of the main circuit 30 can be started earlier.

  (3) Since the power supply terminals 30a and 30b of the main circuit 30 are connected to both electrodes of the bypass capacitor 20 without using a resistor or the like, energy can be supplied from the bypass capacitor 20 to the main circuit 30 that has started operation without loss.

  (4) Since an integrating circuit including the resistor 15 and the capacitor 16 is provided and the FET 13 is turned on after the output signal of the comparator 14 has transitioned to a high level, the charging voltage of the bypass capacitor 20 is reliably increased. Since the FET 13 is turned on after that, the voltage applied between the drain and source of the FET 13 can be set sufficiently small when the FET 13 is turned on. Therefore, a relatively small FET 13 can be used, and the cost can be reduced.

  (5) Since the output signal of the integrating circuit composed of the resistor 15 and the capacitor 16 gently changes from a low level to a high level, the FET 13 does not instantly change from an off state to an on state. Thereby, it is possible to reduce the peak value of the current flowing through the FET 13 until the FET 13 is completely turned on.

In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible.
For example, when the voltage generated by the DC power supply 1 is low, the resistors 11 and 12 may be configured by one resistor element.
It is also possible to configure the FET 13 with a bipolar transistor.

DESCRIPTION OF SYMBOLS 1 ... DC power supply 10 ... Inrush current prevention circuit 11, 12, 15 ... Resistance 13 ... FET
14 ... Comparator 16 ... Capacitor 20 ... Bypass capacitor 30 ... Main circuit

Claims (6)

A bypass capacitor that stores energy supplied from the power supply, and is connected in parallel to the bypass capacitor, operates when the input control signal is at the first logic level, and stores energy stored in the bypass capacitor. An inrush current preventing circuit that suppresses an inrush current flowing in the bypass capacitor when the power is turned on.
Resistor means connected to the bypass capacitor and flowing while suppressing the charging current of the bypass capacitor and generating a conversion signal corresponding to the charging current;
Charging state detection means for outputting the control signal that transitions from the second logic level to the first logic level from an output terminal when it is detected that the charging current has become a predetermined value or less based on the conversion signal When,
An integration circuit for generating an integrated signal obtained by integrating the control signal;
A control electrode connected to the output terminal of the integration circuit; a first conduction electrode connected to one end of the resistance means; and a second conduction electrode connected to the other end of the resistance means; A transistor for turning on and off between the first conductive electrode and the second conductive electrode based on a signal;
The transistor includes a first conductive electrode and a second conductive electrode when the integration signal is changed to a predetermined value due to the control signal transitioning to the first logic level. Turn on,
An inrush current prevention circuit.   The inrush current prevention circuit according to claim 1, wherein the main circuit is connected between both electrodes of the bypass capacitor and receives energy from the bypass capacitor.   The charge state detection means includes a comparator that compares a voltage of the conversion signal with a reference voltage and detects that the charge current has become a predetermined value or less based on a comparison result. The inrush current prevention circuit according to 1 or 2. The integration circuit includes a resistance element having one end connected to the output terminal of the charging state detection unit, and a capacitance element connected between the other end of the resistance element and a fixed potential.
4. The inrush current prevention circuit according to claim 1, wherein a control electrode of the transistor is connected to a connection point between the resistance element and the capacitance element. 5.   The transistor is a field effect transistor having a gate connected to an output terminal of the integrating circuit, a drain connected to one end of the resistance means, and a source connected to the other end of the resistance means. Item 5. The inrush current prevention circuit according to any one of Items 1 to 4.   The transistor is a bipolar transistor having a base connected to an output terminal of the integrating circuit, an emitter connected to one end of the resistance means, and a collector connected to the other end of the resistance means. The inrush current prevention circuit according to any one of 1 to 4.

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