JP5391720B2 - Compound semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a compound semiconductor device and a manufacturing method thereof.

  In recent years, application of high electron mobility transistors (HEMTs) mainly composed of compound semiconductor devices, particularly GaN-based compound semiconductors, to high-power high-frequency devices has been studied. In addition, it is important that a HEMT (hereinafter also referred to as a GaN-based HEMT) using a GaN-based compound semiconductor as a main material is operable at a high current and in a high temperature environment.

  FIG. 1 is a cross-sectional view showing the structure of a conventional GaN-based HEMT. In this GaN-based HEMT, a GaN layer 102, an AlGaN layer 103, and an n-type n-GaN layer 104 are formed in this order on a substrate 101. A gate electrode 107 g is formed on the n-GaN layer 104. Openings are formed at two locations across the gate electrode 107g of the n-GaN layer 104, a source electrode 107s is formed on one side, and a drain electrode 107d is formed on the other side. The source electrode 107s is composed of a Ti film 105s and an Al film 106s, and the drain electrode 107d is composed of a Ti film 105d and an Al film 106d. An Au film 109 is formed on the source electrode 107s and the drain electrode 107d. A Si nitride film 108 is formed between the source electrode 107s and the gate electrode 107g and between the drain electrode 107d and the gate electrode 107g.

  The GaN-based HEMT having such a structure can be operated during a large current operation and in a high temperature environment. However, with miniaturization, it may not be able to withstand long-term use. Such a problem also exists in compound semiconductor devices other than GaN-based HEMTs.

Japanese Patent Laid-Open No. 10-12862 JP 2003-209246 A Japanese Patent Laid-Open No. 7-13005 JP-A-10-104985

  An object of the present invention is to provide a compound semiconductor device capable of stable operation over a long period of time and a manufacturing method thereof.

In one aspect of the compound semiconductor device, a substrate, an electron transit layer formed above the substrate, an electron supply layer formed above the electron transit layer, a source electrode formed above the electron supply layer, A drain electrode and a gate electrode are provided. The contact resistance between the back surface of the source electrode and the GaN-based compound semiconductor decreases as the distance from the gate electrode decreases, and the contact resistance between the back surface of the drain electrode and the GaN-based compound semiconductor separates from the gate electrode. It is so low. The resistance between the source electrode and the electron supply layer decreases as the distance from the gate electrode decreases, and the resistance between the drain electrode and the electron supply layer decreases as the distance from the gate electrode increases. It has become.

In one aspect of the method for manufacturing a compound semiconductor device, an electron transit layer is formed above the substrate, and an electron supply layer is formed above the electron transit layer. In addition, a source electrode, a drain electrode, and a gate electrode are formed above the electron supply layer. The contact resistance with the GaN-based compound semiconductor on the back surface of the source electrode decreases as the distance from the gate electrode decreases, and the contact resistance with the GaN-based compound semiconductor on the back surface of the drain electrode decreases with distance from the gate electrode. To do. The resistance between the source electrode and the electron supply layer is lowered as the distance from the gate electrode is decreased, and the resistance between the drain electrode and the electron supply layer is decreased as the distance from the gate electrode is increased.

  According to the above-described compound semiconductor device or the like, since the resistance between the source and drain electrodes and the electron supply layer is appropriately defined, damage is unlikely to occur and the device can operate stably over a long period of time.

It is sectional drawing which shows the structure of the conventional GaN-type HEMT. It is a figure which shows the problem of the conventional GaN-type HEMT. It is a figure which shows the GaN-type HEMT (semiconductor device) which concerns on a 1st reference example . It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on a 1st reference example in order of a process. FIG. 4B is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT in the order of steps following FIG. 4A. FIG. 4B is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT in the order of steps following FIG. 4B. FIG. 4D is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT in the order of steps subsequent to FIG. 4C. It is a figure which shows the modification of a 1st reference example . It is a figure which shows GaN-type HEMT which concerns on a 2nd reference example . It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on a 2nd reference example to process order. It is sectional drawing which shows the method of manufacturing GaN-type HEMT in order of a process following FIG. 7A. It is a figure which shows GaN-type HEMT which concerns on a 3rd reference example . It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on a 3rd reference example to process order. FIG. 9B is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT in the order of steps following FIG. 9A. It is a figure which shows GaN-type HEMT which concerns on a 4th reference example . It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on a 4th reference example to process order. FIG. 11B is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT in the order of steps following FIG. 11A. It is a figure which shows GaN-type HEMT which concerns on 1st Embodiment. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 1st Embodiment to process order. It is a figure which shows the modification of 1st Embodiment. It is sectional drawing which shows GaN-type HEMT which concerns on 2nd Embodiment. FIG. 6 is a layout diagram showing a GaN-based HEMT according to a second embodiment. It is a figure which shows the source electrode 7s in 2nd Embodiment. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 2nd Embodiment in process order. It is sectional drawing which shows GaN-type HEMT concerning the 5th reference example . It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on a 5th reference example to process order.

  As a result of studying the lifetime in the conventional GaN-based HEMT, the inventor of the present application has found that the current density locally increases in the source electrode 107s and the drain electrode 107d, which are ohmic electrodes, with miniaturization. . That is, as shown in FIG. 2A, in both the drain electrode 107d and the source electrode 107s, current flows only in a region close to the gate electrode 107g, and the current path 110 is concentrated there. . This is due to the following reason. The resistance in the vicinity of the drain electrode 107d is illustrated in FIG.

That is, a resistance value R _Al when flowing in the Al film 106d in the horizontal direction, a resistance value R _C when flowing in the AlGaN layer 103 in the vertical direction, and a two-dimensional electron gas layer (2DEG) of the GaN layer 102 in the horizontal direction. There is a resistance value R _2DEG when flowing. In addition, although resistance exists also in Ti film | membrane 105d, since it is negligibly low compared with another part, it is abbreviate | omitting in FIG.2 (b). The extreme paths include a path 111 that flows laterally in the Al film 106d, flows in the AlGaN layer 103 in the vertical direction, and reaches the lower part of the gate electrode 107g of the GaN layer 102, and the AlGaN layer 103 in the vertical direction. And a path 112 that flows laterally through 2DEG below the Al film 106d of the GaN layer 102 and reaches the gate electrode 107g below the GaN layer 102. When these are compared, since the resistance value R _Al is significantly lower than the resistance value R _2DEG , most of the current flows through the path 111. In this way, a region where the current density becomes extremely high is generated. When such a region occurs, electromigration occurs in the vicinity due to the effect of the high current density itself and the temperature rise associated with the high current density, damage to the Al film 106d and the like occurs, and the resistance value increases. It will rise. For example, when the Al films 106d and 106s are in contact with the Au film 109, purple plague that is a high-resistance material is generated, and the drain electrode 107d and the source electrode 107s are deteriorated.

  Based on such knowledge, the present inventor has conceived the following various embodiments in order to alleviate the concentration of current density.

(First reference example )
First, a first reference example will be described. FIG. 3 is a diagram showing a GaN-based HEMT (semiconductor device) according to a first reference example .

In the first reference example , as shown in FIG. 3A, an i-GaN layer 2, an AlGaN layer 3, and an n-GaN layer 4 are arranged in this order on a substrate 1 such as a semi-insulating SiC substrate. It is formed with. The i-GaN layer 2a is a GaN layer that is not intentionally doped with impurities, and has a thickness of about 3 μm. The surface layer portion of the i-GaN layer 2a functions as an electron transit layer, and the lower portion functions as a buffer layer. The buffer layer prevents the propagation of lattice defects existing on the surface of the substrate 1 to the electron transit layer. The AlGaN layer 3 includes an i-AlGaN layer and an n-AlGaN layer formed thereon. The i-AlGaN layer is an Al _0.25 Ga _0.75 N layer that is not intentionally doped with impurities, and its thickness is about 5 nm. The n-AlGaN layer is an n-type Al _0.25 Ga _0.75 N layer doped with Si at a concentration of about 5 × 10 ¹⁸ cm ⁻³ and has a thickness of about 30 nm. The n-AlGaN layer functions as an electron supply layer. The n-GaN layer 4 is an n-type GaN layer doped with Si at a concentration of about 2 × 10 ¹⁸ cm ⁻³ and has a thickness of about 10 nm. The ratio of Al and Ga in each AlGaN layer is not particularly limited.

A gate electrode 7 g is formed on the n-GaN layer 4. Openings 4 s and 4 d exposing the AlGaN layer 3 are formed at two locations sandwiching the gate electrode 7 g in plan view of the n-GaN layer 4. Si injection regions 11as, 11bs, 11cs, 11ds, 11es, 11fs, 11gs, 11hs, and 11is are formed in this order from the side away from the gate electrode 7g in the portion exposed from the opening 4s of the AlGaN layer 3. In these Si implantation regions, Si is implanted separately from the above-mentioned Si of about 5 × 10 ¹⁸ cm ⁻³ , and is located away from the gate electrode 7g as shown in FIG. The Si doping amount is higher. Similarly, Si implantation regions 11ad, 11bd, 11cd, 11dd, 11ed, 11fd, 11gd, 11hd, and 11id are formed in order from the side away from the gate electrode 7g in the portion exposed from the opening 4d of the AlGaN layer 3. ing. In these Si implantation regions, Si is implanted separately from the above-mentioned Si of about 5 × 10 ¹⁸ cm ⁻³ , and the Si doping amount increases as the distance from the gate electrode 7 g increases. . The Si doping amount of the Si implantation regions 11as and 11ad with the highest Si doping amount is, for example, about 4 × 10 ²⁰ cm ⁻³ , and the Si doping amount of the Si implantation regions 11is and 11id with the lowest Si doping amount is, for example, 1 × 10 ²⁰ cm ^-3 or so.

  A source electrode 7s is formed in the opening 4s, and a drain electrode 7d is formed in the opening 4d. The source electrode 7s includes a Ti film 5s formed on the Si implantation region and an Al film 6s formed thereon. The drain electrode 7d includes a Ti film 5d formed on the Si implantation region and an Al film 6d formed thereon. The thickness of the Ti films 5s and 5d is about 30 nm, and the thickness of the Al films 6s and 6d is about 300 nm. Further, an Au film 9 is formed on the Al films 6s and 6d.

  A silicon nitride film 8 that covers the n-GaN layer 4 and the like is formed around the gate electrode 7g, the source electrode 7s, and the drain electrode 7d. The thickness of the silicon nitride film 8 is about 5 nm to 500 nm (for example, 500 nm).

In the first reference example configured as described above, the resistance of the region in contact with the source electrode 7s and the drain electrode 7d of the AlGaN layer 3 becomes lower as the distance from the gate electrode 7g increases. For this reason, the current flowing in the source and drain electrodes 7d does not concentrate on the gate electrode 7g side but also flows in a portion separated from the gate electrode 7g. As a result, since the concentration of the current density is relaxed, it is possible to suppress the electromigration and the like accompanying the influence of the large current density itself and the influence of high temperature.

Next, a method for manufacturing the GaN-based HEMT according to the first reference example will be described. 4A to 4D are cross-sectional views illustrating a method of manufacturing the GaN-based HEMT according to the first reference example in the order of steps.

  First, as shown in FIG. 4A (a), an i-GaN layer 2 and an AlGaN layer are formed on a substrate 1 such as a semi-insulating SiC substrate by, for example, a metal organic vapor phase epitaxy (MOVPE) method. Layer 3 and n-GaN layer 4 are formed in this order.

Next, as shown in FIG. 4A (b), an opening 71s that opens a region for forming the opening 4s and an opening 71d that opens a region for forming the opening 4d are provided on the n-GaN layer 4. The resist pattern 71 thus formed is formed. Thereafter, using the resist pattern 71 as a mask, dry etching using an inert gas and a chlorine-based gas such as Cl ₂ gas is performed on the n-GaN layer 4, thereby opening the opening 4 s and the n-GaN layer 4. 4d is formed. In addition, regarding the depth of the openings 4s and 4d, a part of the n-GaN layer 4 may be left, or a part of the AlGaN layer 3 may be removed. That is, the depths of the openings 4 s and 4 d do not need to match the thickness of the n-GaN layer 4.

  Subsequently, as shown in FIG. 4A (c), the resist pattern 71 is removed, and an opening 72as for opening a region for forming the Si implantation region 11as and a region for forming the Si implantation region 11ad are opened over the entire surface. A resist pattern 72a provided with an opening 72ad is formed.

Next, by implanting Si using the resist pattern 72a as a mask, Si implanted regions 11as and 11ad are formed as shown in FIG. 4A (d). The implantation energy at this time is about 1 keV to 150 keV (for example, 60 keV). Further, the doping amount is, for example, 0.375 × 10 ²⁰ cm ⁻³ .

  Thereafter, as shown in FIG. 4B (e), the resist pattern 72a is removed, and an opening 72bs that opens a region for forming the Si implantation regions 11as and 11bs and a region for forming the Si implantation regions 11ad and 11bd are formed on the entire surface. A resist pattern 72b provided with an opening 72bd is formed.

Subsequently, Si implantation is performed using the resist pattern 72b as a mask, thereby forming Si implanted regions 11bs and 11bd as shown in FIG. 4B (f). The implantation energy at this time is about 1 keV to 150 keV (for example, 60 keV). Further, the doping amount is, for example, 0.375 × 10 ²⁰ cm ⁻³ . As a result, the total doping amount of the Si implantation regions 11as and 11ad is 0.75 × 10 ²⁰ cm ⁻³ .

Thereafter, by removing the resist pattern, forming a new resist pattern, and implanting silicon, Si implantation regions 11cs to 11hs and 11cd to 11hd are formed as shown in FIG. 4B (g). The implantation energy at this time is about 1 keV to 150 keV (for example, 60 keV). Further, the doping amount is, for example, 0.375 × 10 ²⁰ cm ⁻³ . As a result, the total amount of doping in the Si implantation regions 11as and 11ad becomes 3.0 × 10 ²⁰ cm ⁻³ in a total of eight implantations. Further, a resist pattern 72i provided with an opening 72is that opens a region for forming the Si implantation regions 11as to 11is and an opening 72id that opens a region for forming the Si implantation regions 11ad to 11id is formed on the entire surface.

Next, Si implantation is performed using the resist pattern 72i as a mask, thereby forming Si implantation regions 11is and 11id as shown in FIG. 4B (h). The implantation energy at this time is about 1 keV to 150 keV (for example, 60 keV). The dope amount is, for example, 1.0 × 10 ²⁰ cm ⁻³ . As a result, the total amount of doping in the Si implantation regions 11as and 11ad is 4.0 × 10 ²⁰ cm ⁻³ . Further, the doping amount of the Si implantation regions 11is and 11id is 1.0 × 10 ²⁰ cm ⁻³ . In the Si implantation region located between them, the doping amount is higher as it is closer to the Si implantation regions 11as and 11ad, and the doping amount is lower as it is closer to the Si implantation regions 11is and 11id.

  Thereafter, as shown in FIG. 4C (i), the resist pattern 72i is removed. Subsequently, heat treatment is performed at about 500 ° C. to 1500 ° C. (for example, 1000 ° C.) in a nitrogen atmosphere.

  Next, as shown in FIG. 4C (j), a lower resist pattern in which an opening 73s that opens a region for forming the source electrode 7s and an opening 73d that opens a region for forming the drain electrode 7d are provided on the entire surface. 73 is formed. Further, on the lower resist pattern 73, an upper resist pattern 74 provided with an opening 74s that opens a region for forming the source electrode 7s and an opening 74d that opens a region for forming the drain electrode 7d is formed. Then, by using the multilayer resist pattern of the lower layer resist pattern 73 and the upper layer resist pattern 74 as a mask, Ti and Al are deposited, so that the source electrode 7s including the Ti film 5s and the Al film 6s, and the Ti film 5d and A drain electrode 7d having an Al film 6d is formed.

  Next, as shown in FIG. 4C (k), the lower layer resist pattern 73 and the upper layer resist pattern 74 are removed, and a silicon nitride film 8 is formed on the entire surface.

  Thereafter, as shown in FIG. 4C (l), an opening 8g for a gate electrode is formed in the silicon nitride film 8, and a gate electrode 7g is formed inside the opening 8g.

  Subsequently, as shown in FIG. 4D (m), a resist pattern 75 provided with an opening 75s that matches the source electrode 7s and an opening 75d that matches the drain electrode 7d is formed on the entire surface. Then, using the resist pattern 75 as a mask, openings 8s and 8d are formed in the silicon nitride film 8 by dry etching.

  Next, as shown in FIG. 4D (n), the resist pattern 75 is removed, and a resist pattern 76 in which an opening 76s that matches the source electrode 7s and an opening 76d that matches the drain electrode 7d is provided on the entire surface. Newly formed. Thereafter, an Au film 9 is formed on the Al films 7s and 7d by sputtering. The thickness of the Au film is, for example, 200 nm.

  Then, as shown in FIG. 4D (o), the resist pattern 76 is removed. Thereafter, a protective film, wiring, and the like are formed to complete a GaN-based HEMT (semiconductor device).

In the first reference example , the Si doping amount on the surface of the AlGaN layer 3 is changed in nine steps, but this change does not have to be stepwise, and may be continuous as described later. Good. Moreover, when changing in steps, the number of steps is not limited to nine, and may be, for example, 20 as shown in FIG.

(Second reference example )
Next, a second reference example will be described. FIG. 6 is a diagram showing a GaN-based HEMT according to a second reference example .

In the second reference example , as shown in FIG. 6A, Si implantation regions 21as, 21bs, and 21cs are formed in the portion exposed from the opening 4s of the AlGaN layer 3 in order from the side away from the gate electrode 7g. Has been. In these Si implantation regions, Si is implanted separately from the above-mentioned Si of about 5 × 10 ¹⁸ cm ⁻³ , and is located away from the gate electrode 7g as shown in FIG. 6B. The Si doping amount is higher. Similarly, Si implantation regions 21ad, 21bd, and 21cd are formed in the portion exposed from the opening 4d of the AlGaN layer 3 in order from the side away from the gate electrode 7g. In these Si implantation regions, Si is implanted separately from the above-mentioned Si of about 5 × 10 ¹⁸ cm ⁻³ , and the Si doping amount increases as the distance from the gate electrode 7 g increases. .

Other configurations are the same as those of the first reference example .

According to such a second reference example , the same effect as that of the first reference example can be obtained. Further, as described later, it can be manufactured with fewer steps than the first reference example .

Next, a method for manufacturing a GaN-based HEMT according to the second reference example will be described. 7A to 7B are cross-sectional views showing a method of manufacturing a GaN-based HEMT according to a second reference example in the order of steps.

First, similarly to the first reference example , the processes up to the formation of the openings 4s and 4d are performed. Next, as shown in FIG. 7A (a), a resist in which an opening 77as that opens a region for forming the Si implantation region 21as and an opening 77ad that opens a region for forming the Si implantation region 21ad are provided on the entire surface. A pattern 77a is formed.

Thereafter, Si implantation is performed using the resist pattern 77a as a mask, thereby forming Si implanted regions 21as and 21ad as shown in FIG. 7A (b). The implantation energy at this time is about 1 keV to 150 keV (for example, 60 keV). The dope amount is set to 1.5 × 10 ²⁰ cm ⁻³ , for example.

  Subsequently, as shown in FIG. 7A (c), the resist pattern 77a is removed, and openings 77bs that open regions for forming the Si implantation regions 21as and 21bs and Si implantation regions 21ad and 21bd are formed on the entire surface. A resist pattern 77b provided with an opening 77bd that opens the region is formed.

Next, Si implantation regions 21bs and 21bd are formed by implanting Si using the resist pattern 77b as a mask. The implantation energy at this time is about 1 keV to 150 keV (for example, 60 keV). The dope amount is set to 1.5 × 10 ²⁰ cm ⁻³ , for example. As a result, the total doping amount of the Si implantation regions 21as and 21ad is 3.0 × 10 ²⁰ cm ⁻³ .

  Thereafter, as shown in FIG. 7A (d), the resist pattern 77b is removed, and openings 77cs that open regions for forming Si implantation regions 21as to 21cs and regions for forming Si implantation regions 21ad to 21cd are formed on the entire surface. A resist pattern 77c provided with an opening 77cd is formed.

Subsequently, Si implantation regions 21cs and 21cd are formed by implanting Si using the resist pattern 77c as a mask. The implantation energy at this time is about 1 keV to 150 keV (for example, 60 keV). The dope amount is, for example, 1.0 × 10 ²⁰ cm ⁻³ . As a result, the total amount of doping in the Si implantation regions 11as and 11ad is 4.0 × 10 ²⁰ cm ⁻³ . Further, the doping amount of the Si implantation regions 21cs and 21cd is 1.0 × 10 ²⁰ cm ⁻³ . The total doping amount of the Si implantation regions 21bs and 21bd located between them is 2.5 × 10 ²⁰ cm ^{−3 in} total.

Next, as shown in FIG. 7B (e), the resist pattern 77c is removed, and the processes from the heat treatment in the nitrogen atmosphere to the formation of the silicon nitride film 8 are performed as in the first reference example .

  Thereafter, as shown in FIG. 7B (f), an opening 8g is formed, and a gate electrode 7g is formed.

  Subsequently, as shown in FIG. 7B (g), an Au film 9 is formed. Thereafter, a protective film, wiring, and the like are formed to complete a GaN-based HEMT (semiconductor device).

In such methods, because the number of injections of Si is less than the first reference example, it can be produced easily in fewer steps than the first embodiment.

(Third reference example )
Next, a third reference example will be described. FIG. 8 is a diagram showing a GaN-based HEMT according to a third reference example .

In the third reference example , as shown in FIG. 8A, a Si diffusion region 32s extending in a direction away from the gate electrode 7g is formed in a region below the source electrode 7s of the AlGaN layer 3 and the GaN layer 4. Yes. Further, a Si diffusion region 32d extending in a direction away from the gate electrode 7g is formed in a region below the drain electrode 7d of the AlGaN layer 3 and the GaN layer 4. On the surface of the Si diffusion region 32s, as shown in FIG. 8B, the Si doping amount increases continuously as the distance from the gate electrode 7g increases.

Other configurations are the same as those of the first reference example .

According to such a third reference example , the same effects as those of the first and second reference examples can be obtained. Further, as will be described later, it can be manufactured with fewer steps than the first and second reference examples .

Next, a method for manufacturing a GaN-based HEMT according to the third reference example will be described. 9A to 9B are cross-sectional views showing a method of manufacturing a GaN-based HEMT according to a third reference example in the order of steps.

First, similarly to the first reference example , the processes up to the formation of the n-GaN layer 4 are performed. Next, as shown in FIG. 9A (a), an opening 78s that opens a region for forming the opening 4s, an opening 78d that opens a region for forming the opening 4d, and the gate electrode 7g are formed over the entire surface. A resist pattern 78 is formed, which is provided with an opening 78e that opens a region separated from the region where the film is to be formed. Thereafter, using the resist pattern 78 as a mask, dry etching using an inert gas and a chlorine-based gas such as Cl ₂ gas is performed on the n-GaN layer 4, thereby opening the opening 4 s and the n-GaN layer 4. 4d and the opening 4e are formed.

  Next, as shown in FIG. 9A (b), the resist pattern 78 is removed, and a resist pattern 79 provided with an opening 79e that opens the opening 4e is formed on the entire surface.

  Thereafter, Si implantation is performed using the resist pattern 79 as a mask, thereby forming Si implanted regions 31s and 31d as shown in FIG. 9A (c). The implantation energy at this time is about 1 keV to 150 keV (for example, 40 keV).

  Subsequently, as shown in FIG. 9A (d), the resist pattern 79 is removed. Next, heat treatment is performed at about 500 ° C. to 1500 ° C. (for example, 1200 ° C.) in a nitrogen atmosphere to diffuse silicon in the Si implantation regions 31 s and 31 d, thereby forming Si diffusion regions 32 s and 32 d. The heat treatment time is, for example, several minutes.

Next, as shown in FIG. 9B (e), similarly to the first reference example , the processing from the formation of the source electrode 7s and the drain electrode 7d to the formation of the silicon nitride film 8 is performed.

  Thereafter, as shown in FIG. 9B (f), an opening 8g is formed, and a gate electrode 7g is formed.

  Subsequently, as shown in FIG. 9B (g), an Au film 9 is formed. Thereafter, a protective film, wiring, and the like are formed to complete a GaN-based HEMT (semiconductor device).

In such methods, because the number of injections of Si is less than the first and second reference example, it can be produced easily in fewer steps than the first and second reference example.

(Fourth reference example )
Next, a fourth reference example will be described. FIG. 10 is a diagram showing a GaN-based HEMT according to a fourth reference example .

In the fourth reference example , as shown in FIG. 10A, the B implantation regions 41as, 41bs, 41cs, 41ds, 41es, and the like are sequentially formed in the portion exposed from the opening 4s of the AlGaN layer 3 from the gate electrode 7g side. 41fs, 41gs, 41hs, and 41is are formed. In these B implantation regions, B is implanted separately from the Si of about 5 × 10 ¹⁸ cm ⁻³ , and as shown in FIG. 10B, the closer to the gate electrode 7g, The amount of B dope is high. Similarly, B injection regions 41ad, 41bd, 41cd, 41dd, 41ed, 41fd, 41gd, 41hd, and 41id are formed in this order from the gate electrode 7g side in the portion exposed from the opening 4d of the AlGaN layer 3. In these B implantation regions, B is implanted separately from the above Si of about 5 × 10 ¹⁸ cm ^−3, and the closer to the gate electrode 7g, the higher the B doping amount.

Other configurations are the same as those of the first reference example .

In the fourth reference example configured as described above, B in the B implantation region inactivates Si that has been implanted into the AlGaN layer 3. Therefore, the resistance of the region of the AlGaN layer 3 in contact with the source electrode 7s and the drain electrode 7d increases as it approaches the gate electrode 7g. For this reason, the current flowing in the source and drain electrodes 7d does not concentrate on the gate electrode 7g side, but also flows away from the gate electrode 7g, as in the first reference example . As a result, since the concentration of the current density is relaxed, it is possible to suppress the electromigration and the like accompanying the influence of the large current density itself and the influence of high temperature.

Next, a method for manufacturing a GaN-based HEMT according to the fourth reference example will be described. 11A to 11B are cross-sectional views showing a method of manufacturing a GaN-based HEMT according to a fourth reference example in the order of steps.

First, similarly to the first reference example , the processes up to the formation of the openings 4s and 4d are performed. Next, as shown in FIG. 11A (a), a resist in which an opening 80as that opens a region for forming the B implantation region 41as and an opening 80ad that opens a region for forming the B implantation region 41ad are provided on the entire surface. A pattern 80a is formed.

Thereafter, B is implanted using the resist pattern 80a as a mask, thereby forming B implantation regions 41as and 41ad as shown in FIG. 11A (b). The implantation energy at this time is about 1 keV to 150 keV (for example, 20 keV). The doping amount is, for example, about 1.2 × 10 ¹⁸ cm ⁻³ .

Subsequently, by removing the resist pattern, forming a new resist pattern, and implanting silicon, B implantation regions 41bs to 41hs and 41bd to 41hd are formed as shown in FIG. 11A (c). The implantation energy at this time is about 1 keV to 150 keV (for example, 20 keV). Further, the doping amount is, for example, about 1.2 × 10 ²⁰ cm ⁻³ . As a result, the doping amount of the B implantation regions 41as and 41ad is about 9.9 × 10 ¹⁸ cm ⁻³ in total by eight implantations. Further, a resist pattern 80i provided with an opening 80is that opens a region for forming the B implantation regions 41as to 41is and an opening 80id that opens a region for forming the B implantation regions 41ad to 41id is formed on the entire surface.

Subsequently, B implantation regions 41is and 41id are formed by implanting B using the resist pattern 80i as a mask. The implantation energy at this time is about 1 keV to 150 keV (for example, 20 keV). The dope amount is set to 1.0 × 10 ¹⁶ cm ⁻³ , for example. As a result, the total doping amount of the B implantation regions 41as and 41ad is 1.0 × 10 ¹⁹ cm ⁻³ . The doping amount of the B implantation regions 41is and 41id is 1.0 × 10 ¹⁶ cm ⁻³ . In the B implantation region located between these regions, the closer to the B implantation regions 41as and 41ad, the higher the doping amount, and the closer to the B implantation regions 41is and 41id, the lower the doping amount.

Next, as shown in FIG. 11B (e), the resist pattern 80i is removed, and processing from the formation of the source electrode 7s and the drain electrode 7d to the formation of the silicon nitride film 8 is performed in the same manner as in the first reference example. .

  Thereafter, as shown in FIG. 11B (f), an opening 8g is formed, and a gate electrode 7g is formed.

  Subsequently, as shown in FIG. 11B (g), an Au film 9 is formed. Thereafter, a protective film, wiring, and the like are formed to complete a GaN-based HEMT (semiconductor device).

In the fourth reference example , the B doping amount on the surface of the AlGaN layer 3 is changed in nine steps, but this change is not necessarily stepwise and may be continuous. Moreover, when changing in steps, the number of steps is not limited to nine, and may be, for example, 20 or 3 steps.

(First Embodiment)
Next, a first embodiment will be described. FIG. 12 is a diagram showing a GaN-based HEMT according to the first embodiment.

In the first embodiment, as shown in FIG. 12A, local Si or B implantation into the AlGaN layer 3 as in the first to fourth reference examples is not performed. On the other hand, the configurations of the source electrode 7s and the drain electrode 7d are different from the first to fourth reference examples .

That is, for the drain electrode 7d, as shown in FIG. 12B, a Mo film 52d having a thickness of about 300 nm is formed on a Ti film 51d having a thickness of about 30 nm. Further, the Mo film 52d is not only in contact with the Ti film 51d, but is also in contact with the AlGaN layer 3 on the gate electrode 7g side from the Ti film 51d. The length L _{Ti of the} portion where the Ti film 51d is in contact with the AlGaN layer 3 in the direction connecting the gate electrode 7g and the drain electrode 7d is about 1 μm to 2000 μm (for example, 40 μm), and the Mo film 52d is the AlGaN layer 3. The length L _{Mo of the} portion in contact with the substrate is about 0.01 μm to 20 μm (for example, 0.4 μm). The dimensions in the direction perpendicular to the length direction are common between the Ti film 51d and the Mo film 52d. Therefore, the ratio of the contact area between the Ti film 51d and the Mo film 52d with the AlGaN layer 3 is 100: 1.

Also for the source electrode 7s, a Mo film 52s having a thickness of about 300 nm is formed on a Ti film 51s having a thickness of about 30 nm. The Mo film 52s not only contacts the Ti film 51s but also contacts the AlGaN layer 3 on the gate electrode 7g side of the Ti film 51s. The length L _{Ti of the} portion where the Ti film 51s is in contact with the AlGaN layer 3 in the direction connecting the gate electrode 7g and the source electrode 7s is about 1 μm to 2000 μm (for example, 40 μm), and the Mo film 52s is the AlGaN layer 3. The length L _{Mo of the} portion in contact with the substrate is about 0.01 μm to 20 μm (for example, 0.4 μm). The dimensions in the direction perpendicular to the length direction are common between the Ti film 51s and the Mo film 52s. Therefore, the contact area of the Ti film 51s and the Mo film 52s with the AlGaN layer 3 is 100: 1.

Other configurations are the same as those of the first reference example .

In the first embodiment configured as described above, the contact resistance of the Ti films 51s and 51d to the AlGaN layer 3 is about 10 ⁻⁵ Ω · cm ² , and the contact resistance of the Mo films 52s and 52d to the AlGaN layer 3 is It is about 10 ⁻⁴ Ω · cm ² . Further, as described above, the contact area ratio is 100: 1. For this reason, when two current paths similar to those shown in FIG. 1B are compared, the total resistance values are equal between the two paths. This is also clear from the simulation results shown in FIG. Note that the horizontal axis of FIG. 12C indicates the ratio of the contact area between the Mo films 52 s and 52 d and the AlGaN layer 3 to the contact area between the Ti films 51 s and 51 d and the AlGaN layer 3. The vertical axis indicates the ratio of the resistance value of the path corresponding to the path 111 to the resistance value of the path corresponding to the path 112.

Next, a method for manufacturing the GaN-based HEMT according to the first embodiment will be described. FIG. 13 is a cross-sectional view showing a method of manufacturing the GaN-based HEMT according to the first embodiment in the order of steps.

First, similarly to the first reference example , the processes up to the formation of the openings 4s and 4d are performed. Next, as shown in FIG. 13A, a lower resist pattern in which an opening 81s that opens a region for forming the Ti film 51s and an opening 81d that opens a region for forming the Ti film 51d are provided on the entire surface. 81 is formed. Further, on the lower resist pattern 81, an upper resist pattern 82 provided with an opening 82s that opens a region for forming the Ti film 51s and an opening 82d that opens a region for forming the Ti film 51d is formed. Then, Ti films 51s and 51d are formed by performing Ti deposition using the multilayer resist pattern of the lower layer resist pattern 81 and the upper layer resist pattern 82 as a mask.

  Next, as shown in FIG. 13B, the lower resist pattern 81 and the upper resist pattern 82 are removed. Thereafter, a lower resist pattern 83 provided with an opening 83s that opens a region for forming the Mo film 52s and an opening 83d that opens a region for forming the Mo film 52d is formed on the entire surface. Further, on the lower resist pattern 83, an upper resist pattern 84 provided with an opening 84s that opens a region for forming the Mo film 52s and an opening 84d that opens a region for forming the Mo film 52d is formed. Then, using the multilayer resist pattern of the lower layer resist pattern 83 and the upper layer resist pattern 84 as a mask, Mo is deposited to form Mo films 52s and 52d. In this way, the source electrode 7s and the drain electrode 7d are formed.

Subsequently, as shown in FIG. 13C, the lower layer resist pattern 83 and the upper layer resist pattern 84 are removed. Next, heat treatment is performed at about 400 ° C. to 1000 ° C. (for example, 600 ° C.) in a nitrogen atmosphere. Then, similarly to the first reference example , the processes from the formation of the silicon nitride film 8 to the formation of the gate electrode 7g are performed.

  Subsequently, an Au film 9 is formed as shown in FIG. Thereafter, a protective film, wiring, and the like are formed to complete a GaN-based HEMT (semiconductor device).

In the first embodiment, two types of metals (Ti and Mo) are used so that the contact resistance of the source electrodes 7s and 7d is increased on the gate electrode 7g side. A body (metal, alloy, compound, etc.) may be used. That is, the material is not limited as long as the contact resistance decreases as the distance from the gate electrode increases. For example, as shown in FIG. 14, conductive members 53ad, 53bd, 53cd, and 53dd having a contact resistance lower than that of the Mo film 52d may be provided side by side in a direction away from the gate electrode 7g. In this case, the contact resistance of the conductive member 53ad is the lowest, and the contact resistance of the conductive member 53dd is the highest. Further, the contact resistance of the conductive member 53bd is the second lowest, and the contact resistance of the conductive member 53dd is the second highest. As materials for such ohmic electrodes (source electrode 7s and drain electrode 7d), Mo, Ti, Pt, Ir, W, Ni, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta , Si, TaN, TiN, Si ₃ N ₄ , Ru, ITO (indium tin oxide), NiO, IrO, SrRuO, CoSi ₂ , WSi ₂ , NiSi, MoSi ₂ , TiSi ₂ , Al—Si alloy, Al—Si alloy Al-Cu alloy and Al-Si-Cu alloy.

(Second Embodiment)
Next, a second embodiment will be described. 15A is a sectional view showing a GaN-based HEMT according to the second embodiment, FIG. 15B is a layout diagram showing a GaN-based HEMT according to the second embodiment.

As shown in FIGS. 15A and 15B, in the second embodiment, the first embodiment has a multi-finger gate structure. That is, the planar shape of the gate electrode 7g, the source electrode 7s, and the drain electrode 7d is comb-shaped, and the source electrode 7s and the drain electrode 7d are alternately arranged. A gate electrode 7g is disposed between them.

  Further, the source electrode 7s and the drain electrode 7d are shared by the two HEMTs. As shown in FIG. 16, for example, when the source electrode 7s is divided into two, the Ti film 51s and the Mo film 52s are in contact with the AlGaN layer 3. The area is 100: 1. Similarly, when the drain electrode 7d is divided into two, the contact area of the Ti film 51d and the Mo film 52d with the AlGaN layer 3 is 100: 1.

  By adopting such a multi-finger gate structure, the output can be improved. The active region 10 includes the GaN layer 2, the AlGaN layer 3, and the like, and the periphery of the active region 10 is set as an inactive region by ion implantation or mesa etching.

Next, a method for manufacturing the GaN-based HEMT according to the second embodiment will be described. FIG. 17 is a cross-sectional view showing a method of manufacturing the GaN-based HEMT according to the second embodiment in the order of steps. Although FIG. 17 illustrates the vicinity of the source electrode 7s, parallel processing is performed also in the vicinity of the drain electrode 7d.

First, similarly to the first embodiment, processing up to the formation of the openings 4s and 4d is performed. Next, as shown in FIG. 17A, a lower resist pattern 85 in which an opening 85s that opens a region for forming the Ti film 51s and an opening that opens a region for forming the Ti film 51d are provided on the entire surface. Form. Further, on the lower resist pattern 85, an upper resist pattern 86 provided with an opening 86s that opens a region for forming the Ti film 51s and an opening that opens a region for forming the Ti film 51d is formed. At this time, in this embodiment, Ti films 51 s and 51 d are formed by performing Ti deposition using the multilayer resist pattern of the lower resist pattern 85 and the upper resist pattern 86 as a mask. At this time, in the present embodiment, spaces in which the Mo films 52s and 52d enter are provided on both sides of the Ti films 51s and 51d.

  Next, as shown in FIG. 17B, the lower layer resist pattern 85 and the upper layer resist pattern 86 are removed. Thereafter, a lower resist pattern 87 is formed on the entire surface, which is provided with an opening 87s that opens a region for forming the Mo film 52s and an opening that opens a region for forming the Mo film 52d. Further, on the lower resist pattern 87, an upper resist pattern 88 provided with an opening 88s for opening a region for forming the Mo film 52s and an opening for opening a region for forming the Mo film 52d is formed. Then, using the multilayer resist pattern of the lower layer resist pattern 87 and the upper layer resist pattern 88 as a mask, Mo is deposited to form Mo films 52s and 52d. At this time, in this embodiment, the Mo films 52s and 52d are brought into contact with the AlGaN layer 3 from both sides of the Ti films 51s and 51d. In this way, the source electrode 7s and the drain electrode 7d are formed.

Subsequently, as shown in FIG. 17C, the lower layer resist pattern 87 and the upper layer resist pattern 88 are removed. Next, heat treatment is performed at about 400 ° C. to 1000 ° C. (for example, 600 ° C.) in a nitrogen atmosphere. Then, similarly to the first reference example , the processes from the formation of the silicon nitride film 8 to the formation of the Au film 9 are performed. Thereafter, a protective film, wiring, and the like are formed to complete a GaN-based HEMT (semiconductor device).

Such a multi-finger gate structure can also be realized in the first to fourth reference examples .

( Fifth reference example )
Next, a fifth reference example will be described. FIG. 18 is a cross-sectional view showing a GaN-based HEMT according to a fifth reference example .

Also in the fifth reference example , a multi-finger gate structure is adopted as in the second embodiment. The structures of the source electrode 7s and the drain electrode 7d are the same as those in the first to fourth reference examples . That is, the source electrode 7s includes the Ti film 5s and the Al film 6s, and the drain electrode 7d includes the Ti film 5d and the Al film 6d. Further, an In diffusion region 62 is formed on the surface of the AlGaN layer 3 immediately below the source electrode 7s and the drain electrode 7d, and the In concentration decreases as it approaches the gate electrode 7g.

Other configurations are the same as those of the second embodiment.

In the fifth reference example configured as described above, In in the In diffusion region 62 reduces the contact resistance. The effect of reducing the contact resistance is higher in the region where the In concentration is higher. That is, when the source electrode 7s and the drain electrode 7d shared by two HEMTs are divided into two, the In concentration increases and the contact resistance decreases as the distance from the gate electrode 7g increases. For this reason, the same effect as the first reference example can be obtained. Further, as will be described later, it can also be easily manufactured with fewer steps.

Next, a method for manufacturing a GaN-based HEMT according to the fifth reference example will be described. FIG. 19 is a cross-sectional view showing a method of manufacturing a GaN-based HEMT according to a fifth reference example in the order of steps. Although FIG. 19 shows the vicinity of the source electrode 7s, parallel processing is also performed on the vicinity of the drain electrode 7d.

First, similarly to the second embodiment, the processes up to the formation of the openings 4s and 4d are performed. Next, as shown in FIG. 19A, a lower resist pattern 89 provided with an opening 89a that opens a region for forming the In diffusion region 62 is formed on the entire surface. Further, an upper layer resist pattern 90 provided with an opening 90 a that opens a region for forming the In diffusion region 62 is formed on the lower layer resist pattern 89. Then, using the multilayer resist pattern of the lower layer resist pattern 89 and the upper layer resist pattern 90 as a mask, the In film 61 is formed in the central portion of the region where the source electrode 7s is to be formed.

  Thereafter, as shown in FIG. 19B, the lower layer resist pattern 89 and the upper layer resist pattern 90 are removed. Subsequently, heat treatment is performed at about 400 ° C. to 1000 ° C. (for example, 600 ° C.) in a nitrogen atmosphere. As a result, In constituting the In film 61 is thermally diffused into the AlGaN layer 3, and an In diffusion region 62 in which In is mixed with the AlGaN layer 3 is formed. The In concentration in the In diffusion region 62 is higher just below the center of the In film 61, and is lower as it is farther away from here.

  Next, as shown in FIG. 19B, a lower layer provided with an opening 91s that opens a region for forming the source electrode 7s and an opening that opens a region for forming the drain electrode 7d on the entire surface. A resist pattern 91 is formed. Further, on the lower resist pattern 91, an upper resist pattern 92 provided with an opening 92s for opening a region for forming the source electrode 7s and an opening for opening a region for forming the drain electrode 7d is formed. Then, by using the multilayer resist pattern of the lower layer resist pattern 91 and the upper layer resist pattern 92 as a mask, Ti and Al are deposited, so that the source electrode 7s including the Ti film 5s and the Al film 6s, and the Ti film 5d and A drain electrode 7d having an Al film 6d is formed.

  Thereafter, as shown in FIG. 19C, processing from the removal of the lower resist pattern 91 and the upper resist pattern 92 to the formation of the Au film 9 is performed. Thereafter, a protective film, wiring, and the like are formed to complete a GaN-based HEMT (semiconductor device).

Although multi-finger gate structure as in the second embodiment, even the fifth reference example is employed, the first embodiment may be in the first to fourth reference example similar layout.

In any of the embodiments and reference examples , as the substrate 1, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon substrate, a GaN substrate, a GaAs substrate, or the like may be used. The substrate 1 may be conductive, semi-insulating, or insulating.

  Further, the structures of the gate electrode 7g, the source electrode 7s, and the drain electrode 7d are not limited to those of the above-described embodiment. Moreover, these formation methods are not limited to the lift-off method.

  Further, instead of the silicon nitride film 8, another insulating film may be used. In addition, the insulating film such as the silicon nitride film 8 may be etched by wet etching or ion milling.

  Furthermore, a resistor, a capacitor, and the like may be mounted to form a monolithic microwave integrated circuit (MMIC).

1: Substrate 2: i-GaN layer 3: AlGaN layer 4: n-GaN layer 5s, 5d: Ti film 6s, 6d: Al film 7s: source electrode 7d: drain electrode 7g: gate electrode 11as to 11is, 11ad to 11id : Si implantation region 21as to 21cs, 21ad to 21cd: Si implantation region 31s, 31d: Si implantation region 32s, 32d: Si diffusion region 41as to 41is, 41ad to 41id: B implantation region 51s, 51d: Ti film 52s, 52d: Mo film 53ad to 53dd: Conductive member 61: In film 62: In diffusion region

Claims (4)

A substrate,
An electron transit layer formed above the substrate;
An electron supply layer formed above the electron transit layer;
A source electrode, a drain electrode and a gate electrode formed above the electron supply layer;
Have
The contact resistance with the GaN-based compound semiconductor on the back surface of the source electrode is low as it is separated from the gate electrode,
The contact resistance with the GaN-based compound semiconductor on the back surface of the drain electrode is lower as it is separated from the gate electrode,
The resistance between the source electrode and the electron supply layer is so low that it is separated from the gate electrode,
The compound semiconductor device according to claim 1, wherein a resistance between the drain electrode and the electron supply layer decreases as the distance from the gate electrode increases. The source electrode and the drain electrode are respectively in contact with the electron supply layer.
A first metal film having a first value of contact resistance with the electron supply layer;
A second metal film having a second value lower than the first value in contact resistance with the electron supply layer;
Have
2. The compound semiconductor device according to claim 1, wherein the first metal film is located closer to the gate electrode than the second metal film . Forming an electron transit layer above the substrate;
Forming an electron supply layer above the electron transit layer;
Forming a source electrode, a drain electrode and a gate electrode above the electron supply layer;
Have
The contact resistance with the GaN-based compound semiconductor on the back surface of the source electrode is lowered as the distance from the gate electrode increases.
The contact resistance with the GaN-based compound semiconductor on the back surface of the drain electrode is lowered as the distance from the gate electrode increases.
The resistance between the source electrode and the electron supply layer is lowered as the distance from the gate electrode increases.
A method of manufacturing a compound semiconductor device, wherein a resistance between the drain electrode and the electron supply layer is lowered as the distance from the gate electrode increases. Each of the source electrode and the drain electrode in contact with the electron supply layer,
A first metal film having a first value of contact resistance with the electron supply layer;
A second metal film having a second value lower than the first value in contact resistance with the electron supply layer;
Include
The method of manufacturing a compound semiconductor device according to claim 3, wherein the first metal film is positioned closer to the gate electrode than the second metal film.

Images