JP5390967B2 - Processor system and control method thereof - Google Patents

Description

  The present invention relates to a processor system and a control method thereof, and more particularly to a technique for controlling the power of a processor system including a plurality of CPUs.

  In order to improve the performance of a processor system, a multi-CPU system incorporating a plurality of CPUs is known (Patent Document 1).

  On the other hand, with the diversification and complexity of memory control requirements in processor systems, the circuit scale of memory controllers that control memory is increasing (Patent Document 2). In a single-CPU processor system, a configuration is known in which a clock supplied to the memory controller is controlled in order to suppress power consumption of the memory controller (Patent Document 3).

Japanese Patent Laid-Open No. 6-231088 JP-A-2-280259 JP 2003-308246 A

  However, in a multi-CPU processor system, a certain CPU does not use a memory controller, but other CPUs may use a memory controller. For this reason, when the conventional power consumption suppression method is applied to a multi-CPU processor system as it is, the clock supplied to the memory controller is controlled by controlling only one CPU. Therefore, when the other CPU wants to use the memory controller, a situation in which it cannot be used may occur.

  SUMMARY An advantage of some aspects of the invention is that it provides a technique for suppressing power consumption of a memory controller, which can be applied to a multi-CPU processor system.

In order to achieve the above object, according to the present invention,
A processor system connected to an external memory,
A main processor;
A communication processor having an internal memory and a communication interface;
Memory control means for controlling whether or not to use the external memory, which is accessible to the main processor and the communication processor in common;
With
The memory control means includes
If there is no access from either the main processor or the communication processor, take a power saving state,
Provided is a processor system which is activated when processing using the communication interface of the communication processor cannot be executed only by using the internal memory, and allows the communication processor to use the external memory. .

  ADVANTAGE OF THE INVENTION According to this invention, the technique which suppresses the power consumption of a memory controller applicable also in the processor system of multi CPU can be provided.

The figure which shows the hardware structural example containing a processor system. The figure which shows the memory map example of a hardware system. The flowchart explaining operation | movement of a communication processor. The flowchart explaining operation | movement of a main processor. The figure which shows the clock input circuit of a memory controller. The figure which shows the operation state of a memory controller. The flowchart explaining operation | movement of a main processor.

<< First Embodiment >>
(Processor system)
A hardware configuration including the processor system according to the first embodiment of the present invention will be described with reference to FIG. 1 in FIG. 1 is a processor system according to the present embodiment. Reference numeral 2 denotes a communication I / F (communication interface). The communication I / F 2 is an interface for performing network communication such as bus communication such as USB, wired network, and wireless network. Reference numeral 3 denotes an external memory. As shown in FIG. 1, the processor system 1 is connected to the communication I / F 2 and the external memory 3.

  Reference numeral 11 in FIG. 1 denotes a communication processor for processing information related to the communication I / F. Reference numeral 12 denotes a main processor (general-purpose processor) that plays a central role in the processing of the processor system 1. Reference numeral 13 denotes a shared register for sharing information between the communication processor 11 and the main processor 12. Reference numeral 14 denotes a memory controller for controlling the external memory. The memory controller 14 is accessible to the main processor 12 and the communication processor 11 in common, and performs memory control for controlling whether or not the external memory 3 can be used. Reference numeral 15 denotes a bus for connecting the communication processor 11, the main processor 12, the shared register 13, and the memory controller 14 in the processor system 1. Reference numeral 16 denotes a bus arbiter that determines which bus use right is given in response to a bus use request from each block in the processor system 1.

  Reference numeral 111 in FIG. 1 denotes a communication CPU (Central Processing Unit) that performs calculation processing in the communication processor 11. Reference numeral 112 denotes a communication CPU cache memory as an internal memory for shortening a calculation processing delay accompanying access from the communication CPU 111 to the external memory 3. 113 is a communication I / F controller for controlling the communication I / F.

  The object of the present invention can also be realized by a computer program or a computer-readable recording medium storing the computer program.

(Memory map)
FIG. 2A is a memory map of the hardware system in the first embodiment. The space from the address 00000000 to the address less than 10000000 is a space allocated for the external memory 3. The space from 10000000 address to less than 10001000 address is a space allocated for the shared register 13. Of these, address 10000010 is a memory controller management / control field.

  FIG. 2B is a diagram showing bit allocation in the memory controller management / control field according to the first embodiment. Bit 0 (301) indicates whether or not the main processor 12 is accessing the memory controller. Bit 1 (302) indicates whether or not the communication processor 11 is accessing the memory controller. Bit 0 (301) and bit 1 (302) are set to a value of 1 when the memory controller is being accessed, and set to a value of 0 when the memory controller is not being accessed.

Bit 2 (303) represents the state of the memory controller 14 (memory controller setting). As will be described later with reference to FIG. 5, when the value “1” is set in the “memory controller setting” bit 303, the memory controller 14 is activated, and when the value 0 is set, the memory controller 14 is in the power saving state. . When at least one of the main processor 12 and the communication processor 11 accesses the memory controller 14, a value 1 is set in the “memory controller setting” bit 303. Bits 3 to 15 (304) are unused areas. As described above, at least the following information is held in the shared register 13.
Setting information (303) indicating an operation mode to be set in the memory controller 14.
Information (301) indicating whether or not the main processor 12 has accessed the memory controller 14.
Information (302) indicating whether or not the communication controller 11 has accessed the memory controller 14.

(Processing of processor system)
The processor system according to the first embodiment operates as follows. When data arrives from the outside to the communication processor 11 via the communication I / F 2, a processing request is sent from the communication I / F controller 113 connected thereto to the communication CPU 111. Processing of the communication processor 11 and the main processor 12 in such a case will be described below.

Processing of communication processor 11 The communication processor 11 operates as shown in FIG. First, in step S401, it is determined whether or not this process can be performed only by the communication CPU cache memory 112 without using the external memory 3. If the process is possible (YES in step S401), the process is executed using the cache memory 112 (S402), and the process ends.

  If the processing is not possible (NO in step S401), the following processing is performed in order to use the external memory 3 through the control of the memory controller 14. First, in order to access the shared register 13, a bus use request is issued to the bus arbiter 16 (S403), and the process waits until an access use permission is obtained from the bus arbiter 16 (S404).

  If the bus access permission is obtained from the bus arbiter 16 (YES in S404), the process proceeds to S405. In S405, the “accessing from communication processor” bit (302) at address 10001010, which is a memory controller management / control field in the area allocated to the shared register 13 in the memory map, is set to 1 (S405).

  Next, it is confirmed whether or not the “accessing from main processor” bit (301) at the address 10001010 is 0 (S406). When the “accessing from the main processor” bit (301) is 0 (YES in S406), this corresponds to a state where the main processor 12 is not accessing the memory controller. That is, since the memory controller 14 is in the power saving state, it is necessary to switch to an accessible startup state. Therefore, in order to access the memory controller 14 from now on, the “memory controller setting” bit 303 at the address 10001010 is set to 1 (S407). Otherwise (NO in S406), this corresponds to a state in which the main processor 12 is accessing the memory controller 14, and S407 is skipped.

  Next, in order to access the memory controller 14, a bus use request is issued to the bus arbiter 16 (S408), and the process waits until access permission is obtained from the bus arbiter 16 (S409). When the bus access permission is obtained from the bus arbiter 16 (YES in S409), the memory access to the external memory 3 is started under the control of the memory controller 14 and the process is executed (S410).

  When this process is completed (S411), the “accessing from communication processor” bit (302) at the address 10001010 is set to 0 (S412). Subsequently, it is confirmed whether or not the “accessing from main processor” bit (301) at address 10001010 is 0 (S413). When the “accessing from the main processor” bit (301) is 0 (YES in S413), this corresponds to the state where the main processor 12 is not accessing the memory controller 14, and therefore the memory controller 14 needs to be put into a power saving state. There is. Therefore, the “memory controller setting” bit 303 at the address 10001010 is set to 0 (S414). Otherwise, this corresponds to a state in which the main processor 12 is accessing the memory controller 14, and S414 is skipped. Then, the process ends.

Main Processor Processing On the other hand, the main processor 12 operates as shown in FIG. First, in order to access the shared register 13, a bus use request is issued to the bus arbiter 16 (S501), and the process waits until an access use permission is obtained from the bus arbiter 16 (S502). If the bus access permission is obtained from the bus arbiter 16 (YES in S502), the process proceeds to S503.

  In S503, the “accessing from main processor” bit (301), which is a memory controller management / control field in the area allocated to the shared register 13 in the memory map, is set to 1.

  Next, it is confirmed whether or not the “accessing from communication processor” bit (302) at the address 10001010 is 0 (S504). In the case of 0 (YES in S504), the communication processor 11 is not accessing the memory controller 14, and the memory controller 14 is in the power saving state. Therefore, in order to enable access to the memory controller 14 from now on, the “memory controller setting” bit 303 at the address 10001010 is set to 1 (S505). Otherwise (NO in S504), this corresponds to a state in which the communication processor 11 is accessing the memory controller 14, and thus S505 is skipped.

  Next, in order to access the memory controller 14, a bus use request is issued to the bus arbiter 16 (S506), and the process waits until an access use permission is obtained from the bus arbiter 16 (S507). When the bus access permission is obtained from the bus arbiter 16, memory access to the external memory 3 is started under the control of the memory controller 14 and processing is executed (S508). When this processing is completed (S509), the “accessing from main processor” bit (301) at the address 10001010 is set to 0 (S510).

  Subsequently, it is confirmed whether or not the “accessing from communication processor” bit (302) at the address 10001010 is 0 (S511). When the “accessing from the communication processor” bit (302) is 0, this corresponds to a state where the communication processor 11 is not accessing the memory controller 14 either. Therefore, in order to put the memory controller 14 in the power saving state, the “memory controller setting” bit 303 at the address 10001010 is set to 0 (S512). Otherwise, this corresponds to the state in which the communication processor 11 is accessing the memory controller 14, so S512 is skipped. Then, the process ends.

("Memory controller setting" bit)
As shown in FIG. 5, the value of the “memory controller setting” bit 303 at the address 10001010 and the clock signal of the processor system are connected to the input of the AND circuit. The output of the AND circuit is connected to the clock input of the memory controller. Therefore, when the “memory controller setting” bit 303 at the address 10001010 becomes 0, the clock input of the memory controller becomes 0. Since the clock input does not change, the memory controller does not operate and enters a power saving state.

  As the communication processor 11 and the main processor 12 operate as described above, as shown in FIG. 6A, the memory controller 14 is turned on only while at least one of the processors is accessing. FIG. 6 is a diagram showing the relationship between the presence / absence of access to the memory controller 14 from the communication processor 11 or the main processor 12 and the operation state of the memory controller 14. Thereby, the power saving of the memory controller 14 is achieved.

  As described above, the memory controller 14 is in a power saving state when there is no access from either the main processor 12 or the communication processor 11. On the other hand, when the processing using the communication I / F 2 of the communication processor 11 cannot be executed only by using the communication CPU cache memory 112, the communication processor 11 is activated, and the communication processor 11 can use the external memory 3. For this reason, according to the present embodiment, in a multi-CPU processor system, the memory controller can be put into a power saving state during a period when each processor is not required, and the power consumption of the memory controller is suppressed as a whole. Is possible.

  The operation mode of the memory controller 14 is controlled via information held in the shared register 13. In particular, in the present embodiment, information (“main controller setting” bit “1”) for setting the activation state when at least one of the main processor 12 and the communication processor 11 accesses the memory controller 14 is set. Is done. For this reason, this embodiment can be easily mounted.

<< Second Embodiment >>
In the first embodiment, while at least one of the communication processor 11 and the main processor 12 is accessing the memory controller 14, the “memory controller setting” bit is set to 1 to operate the memory controller 14. . However, depending on the application, when the use of the external memory 3 by the main processor 12 is completed, it may be desirable to shift the memory controller 14 to the power saving mode regardless of whether there is an access from the communication processor 11. Therefore, in the second embodiment of the present invention, a configuration will be described in which the memory controller 14 is shifted to the power saving mode in accordance with the end of access from the main processor 12.

  The configuration of the hardware system including the processor system according to the present embodiment, the memory map of the hardware system, the bit assignment of the memory controller management / control field, and the operation of the communication processor have been described in the first embodiment. It is the same. That is, the hardware configuration of the processor system 1 is represented by FIG. 1, the memory map and bit allocation are represented by FIGS. 2 (a) and 2 (b), and the operation of the communication processor 11 is represented by the flowchart of FIG. The

  In the processor system according to the second embodiment, the main processor 12 operates as shown in FIG. 7 is the same as S501 to S510 in FIG. 4, and thus description thereof is omitted.

  In the present embodiment, when the processing of S810 ends, the process proceeds to S811 without checking the value of the “accessing from communication processor” bit 302. In S811, the “memory controller setting” bit 303 at the address 10001010 is set to 0 in order to put the memory controller 14 in the power saving state.

  As shown in FIG. 5, the value of the “memory controller setting” bit 303 at the address 10001010 and the clock signal of the processor system are connected to the input of the AND circuit. The output of the AND circuit is connected to the clock input of the memory controller. Therefore, when the “memory controller setting” bit 303 at the address 10001010 becomes 0, the clock input of the memory controller becomes 0. Since the clock input does not change, the memory controller does not operate and enters a power saving state.

  As the communication processor 11 and the main processor 12 operate as described above, as shown in FIG. 6B, the memory controller 14 is turned on when either processor accesses.

  Further, when the processing of the main processor 12 which is the center of the processor system 1 is completed, the processing as the processor system 1 is also ended. Therefore, even if the communication processor 11 is accessing the memory controller 14, the memory controller 14 is turned off if there is no access to the memory controller 14 from the main processor. Thereby, the power saving of the memory controller 14 is achieved.

  The memory controller 14 shifts to the power saving state regardless of the presence or absence of access from the communication processor 11 in response to the use of the external memory 3 by the main processor 12 being completed. Therefore, the present invention can be suitably applied in applications where the processing of the main processor 12 needs to be executed with priority.

<< Other Embodiments >>
In the above configuration, only the communication processor 11 includes the dedicated internal memory (communication CPU cache memory 112), but the main processor may also include the dedicated memory. In this case, when the processing of the main processor 12 cannot be executed only by using the dedicated memory, the memory controller 14 may be activated to enable the main processor 12 to use the external memory 3. According to such a configuration, the memory controller 14 can be activated only when the main processor 12 needs to use the external memory 3, and the power saving effect of the entire system can be effectively enhanced. .

The operation mode of the memory controller 14 may be changed based on information from the communication interface. For example, the following configuration can be adopted.
(Configuration example 1): An event that cannot be processed only by the internal cache is detected using the communication I / F 2 (for example, LAN, WLAN, USB). In this communication I / F2, the memory controller 14 is turned ON when a specific signal / packet / protocol is detected.
(Configuration Example 2): An event that cannot be processed only by the internal cache is detected by hardware such as a bus arbiter 16 or a bus address decoder (not shown). The detection result is directly connected (clock gating) to the clock supply unit of the memory controller 14 and the shared register 13 is also set.
(Configuration example 3): An event that cannot be processed only by the internal cache is detected by software. That is, before turning off the memory controller 14, a specific program (the shared register 13 is set immediately before going to access the external memory 3 out of the cached code) is loaded into the internal cache of the processor. Keep it.

  The above configuration can be applied not only to a combination of a communication processor and a main processor, but also to any configuration as long as the configuration includes a plurality of processors. That is, a processor system connected to an external memory, including a first and second processor, and a memory controller that controls access to the external memory that can be used in common by the first and second processors. It can also be applied to other processor systems. In this case, the memory controller takes an activated state only when there is an access by at least one of the first and second processors, and takes the power saving state in other cases, thereby effectively reducing the power consumption in the multiprocessor system. Can be realized.

Claims (7)

A processor system connected to an external memory,
A main processor;
A communication processor having an internal memory and a communication interface;
Memory control means for controlling whether or not to use the external memory, which is accessible to the main processor and the communication processor in common;
With
The memory control means includes
If there is no access from either the main processor or the communication processor, take a power saving state,
A processor system, wherein when the processing using the communication interface of the communication processor cannot be executed only by using the internal memory, the processor system is activated and the communication processor can use the external memory. Further comprising holding means for holding setting information indicating an operation mode to be set in the memory control means;
2. The processor system according to claim 1, wherein an operation mode of the memory control unit is controlled through information held by the holding unit. The holding means further holds information indicating presence / absence of access to the memory control means from the main processor and information indicating presence / absence of access to the memory control means from the communication processor,
3. The setting information is set to information for setting an activation state when at least one of the main processor and the communication processor accesses the memory control unit. Processor system. The main processor includes a dedicated memory,
The memory control means is activated when the processing of the main processor cannot be executed only by using the dedicated memory, and allows the main processor to use the external memory. 4. The processor system according to any one of 3 above.   5. The memory control unit shifts to a power saving state regardless of whether or not there is an access from the communication processor in response to completion of use of the external memory by the main processor. The processor system according to any one of the above.   2. The processor system according to claim 1, wherein an operation mode of the memory control unit is changed based on information from the communication interface. A method for controlling a processor system connected to an external memory, comprising:
The processor system includes:
A main processor;
A communication processor having an internal memory and a communication interface;
Memory control means for controlling whether or not to use the external memory, which is accessible to the main processor and the communication processor in common;
With
The memory control means includes
If there is no access from either the main processor or the communication processor, take a power saving state,
A control method for a processor system, wherein when a process using a communication interface of the communication processor cannot be executed only by using the internal memory, the communication processor enters an activated state and allows the communication processor to use the external memory.

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